au1550_ac97.c 50 KB

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  1. /*
  2. * au1550_ac97.c -- Sound driver for Alchemy Au1550 MIPS Internet Edge
  3. * Processor.
  4. *
  5. * Copyright 2004 Embedded Edge, LLC
  6. * dan@embeddededge.com
  7. *
  8. * Mostly copied from the au1000.c driver and some from the
  9. * PowerMac dbdma driver.
  10. * We assume the processor can do memory coherent DMA.
  11. *
  12. * Ported to 2.6 by Matt Porter <mporter@kernel.crashing.org>
  13. *
  14. * This program is free software; you can redistribute it and/or modify it
  15. * under the terms of the GNU General Public License as published by the
  16. * Free Software Foundation; either version 2 of the License, or (at your
  17. * option) any later version.
  18. *
  19. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  20. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  21. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  22. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  23. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  24. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  25. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  26. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  28. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29. *
  30. * You should have received a copy of the GNU General Public License along
  31. * with this program; if not, write to the Free Software Foundation, Inc.,
  32. * 675 Mass Ave, Cambridge, MA 02139, USA.
  33. *
  34. */
  35. #undef DEBUG
  36. #include <linux/module.h>
  37. #include <linux/string.h>
  38. #include <linux/ioport.h>
  39. #include <linux/sched.h>
  40. #include <linux/delay.h>
  41. #include <linux/sound.h>
  42. #include <linux/slab.h>
  43. #include <linux/soundcard.h>
  44. #include <linux/init.h>
  45. #include <linux/interrupt.h>
  46. #include <linux/kernel.h>
  47. #include <linux/poll.h>
  48. #include <linux/pci.h>
  49. #include <linux/bitops.h>
  50. #include <linux/spinlock.h>
  51. #include <linux/smp_lock.h>
  52. #include <linux/ac97_codec.h>
  53. #include <linux/mutex.h>
  54. #include <asm/io.h>
  55. #include <asm/uaccess.h>
  56. #include <asm/hardirq.h>
  57. #include <asm/mach-au1x00/au1xxx_psc.h>
  58. #include <asm/mach-au1x00/au1xxx_dbdma.h>
  59. #include <asm/mach-au1x00/au1xxx.h>
  60. #undef OSS_DOCUMENTED_MIXER_SEMANTICS
  61. /* misc stuff */
  62. #define POLL_COUNT 0x50000
  63. #define AC97_EXT_DACS (AC97_EXTID_SDAC | AC97_EXTID_CDAC | AC97_EXTID_LDAC)
  64. /* The number of DBDMA ring descriptors to allocate. No sense making
  65. * this too large....if you can't keep up with a few you aren't likely
  66. * to be able to with lots of them, either.
  67. */
  68. #define NUM_DBDMA_DESCRIPTORS 4
  69. #define err(format, arg...) printk(KERN_ERR format "\n" , ## arg)
  70. /* Boot options
  71. * 0 = no VRA, 1 = use VRA if codec supports it
  72. */
  73. static int vra = 1;
  74. module_param(vra, bool, 0);
  75. MODULE_PARM_DESC(vra, "if 1 use VRA if codec supports it");
  76. static struct au1550_state {
  77. /* soundcore stuff */
  78. int dev_audio;
  79. struct ac97_codec *codec;
  80. unsigned codec_base_caps; /* AC'97 reg 00h, "Reset Register" */
  81. unsigned codec_ext_caps; /* AC'97 reg 28h, "Extended Audio ID" */
  82. int no_vra; /* do not use VRA */
  83. spinlock_t lock;
  84. struct mutex open_mutex;
  85. struct mutex sem;
  86. mode_t open_mode;
  87. wait_queue_head_t open_wait;
  88. struct dmabuf {
  89. u32 dmanr;
  90. unsigned sample_rate;
  91. unsigned src_factor;
  92. unsigned sample_size;
  93. int num_channels;
  94. int dma_bytes_per_sample;
  95. int user_bytes_per_sample;
  96. int cnt_factor;
  97. void *rawbuf;
  98. unsigned buforder;
  99. unsigned numfrag;
  100. unsigned fragshift;
  101. void *nextIn;
  102. void *nextOut;
  103. int count;
  104. unsigned total_bytes;
  105. unsigned error;
  106. wait_queue_head_t wait;
  107. /* redundant, but makes calculations easier */
  108. unsigned fragsize;
  109. unsigned dma_fragsize;
  110. unsigned dmasize;
  111. unsigned dma_qcount;
  112. /* OSS stuff */
  113. unsigned mapped:1;
  114. unsigned ready:1;
  115. unsigned stopped:1;
  116. unsigned ossfragshift;
  117. int ossmaxfrags;
  118. unsigned subdivision;
  119. } dma_dac, dma_adc;
  120. } au1550_state;
  121. static unsigned
  122. ld2(unsigned int x)
  123. {
  124. unsigned r = 0;
  125. if (x >= 0x10000) {
  126. x >>= 16;
  127. r += 16;
  128. }
  129. if (x >= 0x100) {
  130. x >>= 8;
  131. r += 8;
  132. }
  133. if (x >= 0x10) {
  134. x >>= 4;
  135. r += 4;
  136. }
  137. if (x >= 4) {
  138. x >>= 2;
  139. r += 2;
  140. }
  141. if (x >= 2)
  142. r++;
  143. return r;
  144. }
  145. static void
  146. au1550_delay(int msec)
  147. {
  148. unsigned long tmo;
  149. signed long tmo2;
  150. if (in_interrupt())
  151. return;
  152. tmo = jiffies + (msec * HZ) / 1000;
  153. for (;;) {
  154. tmo2 = tmo - jiffies;
  155. if (tmo2 <= 0)
  156. break;
  157. schedule_timeout(tmo2);
  158. }
  159. }
  160. static u16
  161. rdcodec(struct ac97_codec *codec, u8 addr)
  162. {
  163. struct au1550_state *s = (struct au1550_state *)codec->private_data;
  164. unsigned long flags;
  165. u32 cmd, val;
  166. u16 data;
  167. int i;
  168. spin_lock_irqsave(&s->lock, flags);
  169. for (i = 0; i < POLL_COUNT; i++) {
  170. val = au_readl(PSC_AC97STAT);
  171. au_sync();
  172. if (!(val & PSC_AC97STAT_CP))
  173. break;
  174. }
  175. if (i == POLL_COUNT)
  176. err("rdcodec: codec cmd pending expired!");
  177. cmd = (u32)PSC_AC97CDC_INDX(addr);
  178. cmd |= PSC_AC97CDC_RD; /* read command */
  179. au_writel(cmd, PSC_AC97CDC);
  180. au_sync();
  181. /* now wait for the data
  182. */
  183. for (i = 0; i < POLL_COUNT; i++) {
  184. val = au_readl(PSC_AC97STAT);
  185. au_sync();
  186. if (!(val & PSC_AC97STAT_CP))
  187. break;
  188. }
  189. if (i == POLL_COUNT) {
  190. err("rdcodec: read poll expired!");
  191. data = 0;
  192. goto out;
  193. }
  194. /* wait for command done?
  195. */
  196. for (i = 0; i < POLL_COUNT; i++) {
  197. val = au_readl(PSC_AC97EVNT);
  198. au_sync();
  199. if (val & PSC_AC97EVNT_CD)
  200. break;
  201. }
  202. if (i == POLL_COUNT) {
  203. err("rdcodec: read cmdwait expired!");
  204. data = 0;
  205. goto out;
  206. }
  207. data = au_readl(PSC_AC97CDC) & 0xffff;
  208. au_sync();
  209. /* Clear command done event.
  210. */
  211. au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
  212. au_sync();
  213. out:
  214. spin_unlock_irqrestore(&s->lock, flags);
  215. return data;
  216. }
  217. static void
  218. wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
  219. {
  220. struct au1550_state *s = (struct au1550_state *)codec->private_data;
  221. unsigned long flags;
  222. u32 cmd, val;
  223. int i;
  224. spin_lock_irqsave(&s->lock, flags);
  225. for (i = 0; i < POLL_COUNT; i++) {
  226. val = au_readl(PSC_AC97STAT);
  227. au_sync();
  228. if (!(val & PSC_AC97STAT_CP))
  229. break;
  230. }
  231. if (i == POLL_COUNT)
  232. err("wrcodec: codec cmd pending expired!");
  233. cmd = (u32)PSC_AC97CDC_INDX(addr);
  234. cmd |= (u32)data;
  235. au_writel(cmd, PSC_AC97CDC);
  236. au_sync();
  237. for (i = 0; i < POLL_COUNT; i++) {
  238. val = au_readl(PSC_AC97STAT);
  239. au_sync();
  240. if (!(val & PSC_AC97STAT_CP))
  241. break;
  242. }
  243. if (i == POLL_COUNT)
  244. err("wrcodec: codec cmd pending expired!");
  245. for (i = 0; i < POLL_COUNT; i++) {
  246. val = au_readl(PSC_AC97EVNT);
  247. au_sync();
  248. if (val & PSC_AC97EVNT_CD)
  249. break;
  250. }
  251. if (i == POLL_COUNT)
  252. err("wrcodec: read cmdwait expired!");
  253. /* Clear command done event.
  254. */
  255. au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
  256. au_sync();
  257. spin_unlock_irqrestore(&s->lock, flags);
  258. }
  259. static void
  260. waitcodec(struct ac97_codec *codec)
  261. {
  262. u16 temp;
  263. u32 val;
  264. int i;
  265. /* codec_wait is used to wait for a ready state after
  266. * an AC97C_RESET.
  267. */
  268. au1550_delay(10);
  269. /* first poll the CODEC_READY tag bit
  270. */
  271. for (i = 0; i < POLL_COUNT; i++) {
  272. val = au_readl(PSC_AC97STAT);
  273. au_sync();
  274. if (val & PSC_AC97STAT_CR)
  275. break;
  276. }
  277. if (i == POLL_COUNT) {
  278. err("waitcodec: CODEC_READY poll expired!");
  279. return;
  280. }
  281. /* get AC'97 powerdown control/status register
  282. */
  283. temp = rdcodec(codec, AC97_POWER_CONTROL);
  284. /* If anything is powered down, power'em up
  285. */
  286. if (temp & 0x7f00) {
  287. /* Power on
  288. */
  289. wrcodec(codec, AC97_POWER_CONTROL, 0);
  290. au1550_delay(100);
  291. /* Reread
  292. */
  293. temp = rdcodec(codec, AC97_POWER_CONTROL);
  294. }
  295. /* Check if Codec REF,ANL,DAC,ADC ready
  296. */
  297. if ((temp & 0x7f0f) != 0x000f)
  298. err("codec reg 26 status (0x%x) not ready!!", temp);
  299. }
  300. /* stop the ADC before calling */
  301. static void
  302. set_adc_rate(struct au1550_state *s, unsigned rate)
  303. {
  304. struct dmabuf *adc = &s->dma_adc;
  305. struct dmabuf *dac = &s->dma_dac;
  306. unsigned adc_rate, dac_rate;
  307. u16 ac97_extstat;
  308. if (s->no_vra) {
  309. /* calc SRC factor
  310. */
  311. adc->src_factor = ((96000 / rate) + 1) >> 1;
  312. adc->sample_rate = 48000 / adc->src_factor;
  313. return;
  314. }
  315. adc->src_factor = 1;
  316. ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
  317. rate = rate > 48000 ? 48000 : rate;
  318. /* enable VRA
  319. */
  320. wrcodec(s->codec, AC97_EXTENDED_STATUS,
  321. ac97_extstat | AC97_EXTSTAT_VRA);
  322. /* now write the sample rate
  323. */
  324. wrcodec(s->codec, AC97_PCM_LR_ADC_RATE, (u16) rate);
  325. /* read it back for actual supported rate
  326. */
  327. adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
  328. pr_debug("set_adc_rate: set to %d Hz\n", adc_rate);
  329. /* some codec's don't allow unequal DAC and ADC rates, in which case
  330. * writing one rate reg actually changes both.
  331. */
  332. dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
  333. if (dac->num_channels > 2)
  334. wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, dac_rate);
  335. if (dac->num_channels > 4)
  336. wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, dac_rate);
  337. adc->sample_rate = adc_rate;
  338. dac->sample_rate = dac_rate;
  339. }
  340. /* stop the DAC before calling */
  341. static void
  342. set_dac_rate(struct au1550_state *s, unsigned rate)
  343. {
  344. struct dmabuf *dac = &s->dma_dac;
  345. struct dmabuf *adc = &s->dma_adc;
  346. unsigned adc_rate, dac_rate;
  347. u16 ac97_extstat;
  348. if (s->no_vra) {
  349. /* calc SRC factor
  350. */
  351. dac->src_factor = ((96000 / rate) + 1) >> 1;
  352. dac->sample_rate = 48000 / dac->src_factor;
  353. return;
  354. }
  355. dac->src_factor = 1;
  356. ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
  357. rate = rate > 48000 ? 48000 : rate;
  358. /* enable VRA
  359. */
  360. wrcodec(s->codec, AC97_EXTENDED_STATUS,
  361. ac97_extstat | AC97_EXTSTAT_VRA);
  362. /* now write the sample rate
  363. */
  364. wrcodec(s->codec, AC97_PCM_FRONT_DAC_RATE, (u16) rate);
  365. /* I don't support different sample rates for multichannel,
  366. * so make these channels the same.
  367. */
  368. if (dac->num_channels > 2)
  369. wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, (u16) rate);
  370. if (dac->num_channels > 4)
  371. wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, (u16) rate);
  372. /* read it back for actual supported rate
  373. */
  374. dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
  375. pr_debug("set_dac_rate: set to %d Hz\n", dac_rate);
  376. /* some codec's don't allow unequal DAC and ADC rates, in which case
  377. * writing one rate reg actually changes both.
  378. */
  379. adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
  380. dac->sample_rate = dac_rate;
  381. adc->sample_rate = adc_rate;
  382. }
  383. static void
  384. stop_dac(struct au1550_state *s)
  385. {
  386. struct dmabuf *db = &s->dma_dac;
  387. u32 stat;
  388. unsigned long flags;
  389. if (db->stopped)
  390. return;
  391. spin_lock_irqsave(&s->lock, flags);
  392. au_writel(PSC_AC97PCR_TP, PSC_AC97PCR);
  393. au_sync();
  394. /* Wait for Transmit Busy to show disabled.
  395. */
  396. do {
  397. stat = au_readl(PSC_AC97STAT);
  398. au_sync();
  399. } while ((stat & PSC_AC97STAT_TB) != 0);
  400. au1xxx_dbdma_reset(db->dmanr);
  401. db->stopped = 1;
  402. spin_unlock_irqrestore(&s->lock, flags);
  403. }
  404. static void
  405. stop_adc(struct au1550_state *s)
  406. {
  407. struct dmabuf *db = &s->dma_adc;
  408. unsigned long flags;
  409. u32 stat;
  410. if (db->stopped)
  411. return;
  412. spin_lock_irqsave(&s->lock, flags);
  413. au_writel(PSC_AC97PCR_RP, PSC_AC97PCR);
  414. au_sync();
  415. /* Wait for Receive Busy to show disabled.
  416. */
  417. do {
  418. stat = au_readl(PSC_AC97STAT);
  419. au_sync();
  420. } while ((stat & PSC_AC97STAT_RB) != 0);
  421. au1xxx_dbdma_reset(db->dmanr);
  422. db->stopped = 1;
  423. spin_unlock_irqrestore(&s->lock, flags);
  424. }
  425. static void
  426. set_xmit_slots(int num_channels)
  427. {
  428. u32 ac97_config, stat;
  429. ac97_config = au_readl(PSC_AC97CFG);
  430. au_sync();
  431. ac97_config &= ~(PSC_AC97CFG_TXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
  432. au_writel(ac97_config, PSC_AC97CFG);
  433. au_sync();
  434. switch (num_channels) {
  435. case 6: /* stereo with surround and center/LFE,
  436. * slots 3,4,6,7,8,9
  437. */
  438. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(6);
  439. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(9);
  440. case 4: /* stereo with surround, slots 3,4,7,8 */
  441. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(7);
  442. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(8);
  443. case 2: /* stereo, slots 3,4 */
  444. case 1: /* mono */
  445. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(3);
  446. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(4);
  447. }
  448. au_writel(ac97_config, PSC_AC97CFG);
  449. au_sync();
  450. ac97_config |= PSC_AC97CFG_DE_ENABLE;
  451. au_writel(ac97_config, PSC_AC97CFG);
  452. au_sync();
  453. /* Wait for Device ready.
  454. */
  455. do {
  456. stat = au_readl(PSC_AC97STAT);
  457. au_sync();
  458. } while ((stat & PSC_AC97STAT_DR) == 0);
  459. }
  460. static void
  461. set_recv_slots(int num_channels)
  462. {
  463. u32 ac97_config, stat;
  464. ac97_config = au_readl(PSC_AC97CFG);
  465. au_sync();
  466. ac97_config &= ~(PSC_AC97CFG_RXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
  467. au_writel(ac97_config, PSC_AC97CFG);
  468. au_sync();
  469. /* Always enable slots 3 and 4 (stereo). Slot 6 is
  470. * optional Mic ADC, which we don't support yet.
  471. */
  472. ac97_config |= PSC_AC97CFG_RXSLOT_ENA(3);
  473. ac97_config |= PSC_AC97CFG_RXSLOT_ENA(4);
  474. au_writel(ac97_config, PSC_AC97CFG);
  475. au_sync();
  476. ac97_config |= PSC_AC97CFG_DE_ENABLE;
  477. au_writel(ac97_config, PSC_AC97CFG);
  478. au_sync();
  479. /* Wait for Device ready.
  480. */
  481. do {
  482. stat = au_readl(PSC_AC97STAT);
  483. au_sync();
  484. } while ((stat & PSC_AC97STAT_DR) == 0);
  485. }
  486. /* Hold spinlock for both start_dac() and start_adc() calls */
  487. static void
  488. start_dac(struct au1550_state *s)
  489. {
  490. struct dmabuf *db = &s->dma_dac;
  491. if (!db->stopped)
  492. return;
  493. set_xmit_slots(db->num_channels);
  494. au_writel(PSC_AC97PCR_TC, PSC_AC97PCR);
  495. au_sync();
  496. au_writel(PSC_AC97PCR_TS, PSC_AC97PCR);
  497. au_sync();
  498. au1xxx_dbdma_start(db->dmanr);
  499. db->stopped = 0;
  500. }
  501. static void
  502. start_adc(struct au1550_state *s)
  503. {
  504. struct dmabuf *db = &s->dma_adc;
  505. int i;
  506. if (!db->stopped)
  507. return;
  508. /* Put two buffers on the ring to get things started.
  509. */
  510. for (i=0; i<2; i++) {
  511. au1xxx_dbdma_put_dest(db->dmanr, db->nextIn, db->dma_fragsize);
  512. db->nextIn += db->dma_fragsize;
  513. if (db->nextIn >= db->rawbuf + db->dmasize)
  514. db->nextIn -= db->dmasize;
  515. }
  516. set_recv_slots(db->num_channels);
  517. au1xxx_dbdma_start(db->dmanr);
  518. au_writel(PSC_AC97PCR_RC, PSC_AC97PCR);
  519. au_sync();
  520. au_writel(PSC_AC97PCR_RS, PSC_AC97PCR);
  521. au_sync();
  522. db->stopped = 0;
  523. }
  524. static int
  525. prog_dmabuf(struct au1550_state *s, struct dmabuf *db)
  526. {
  527. unsigned user_bytes_per_sec;
  528. unsigned bufs;
  529. unsigned rate = db->sample_rate;
  530. if (!db->rawbuf) {
  531. db->ready = db->mapped = 0;
  532. db->buforder = 5; /* 32 * PAGE_SIZE */
  533. db->rawbuf = kmalloc((PAGE_SIZE << db->buforder), GFP_KERNEL);
  534. if (!db->rawbuf)
  535. return -ENOMEM;
  536. }
  537. db->cnt_factor = 1;
  538. if (db->sample_size == 8)
  539. db->cnt_factor *= 2;
  540. if (db->num_channels == 1)
  541. db->cnt_factor *= 2;
  542. db->cnt_factor *= db->src_factor;
  543. db->count = 0;
  544. db->dma_qcount = 0;
  545. db->nextIn = db->nextOut = db->rawbuf;
  546. db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels;
  547. db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ?
  548. 2 : db->num_channels);
  549. user_bytes_per_sec = rate * db->user_bytes_per_sample;
  550. bufs = PAGE_SIZE << db->buforder;
  551. if (db->ossfragshift) {
  552. if ((1000 << db->ossfragshift) < user_bytes_per_sec)
  553. db->fragshift = ld2(user_bytes_per_sec/1000);
  554. else
  555. db->fragshift = db->ossfragshift;
  556. } else {
  557. db->fragshift = ld2(user_bytes_per_sec / 100 /
  558. (db->subdivision ? db->subdivision : 1));
  559. if (db->fragshift < 3)
  560. db->fragshift = 3;
  561. }
  562. db->fragsize = 1 << db->fragshift;
  563. db->dma_fragsize = db->fragsize * db->cnt_factor;
  564. db->numfrag = bufs / db->dma_fragsize;
  565. while (db->numfrag < 4 && db->fragshift > 3) {
  566. db->fragshift--;
  567. db->fragsize = 1 << db->fragshift;
  568. db->dma_fragsize = db->fragsize * db->cnt_factor;
  569. db->numfrag = bufs / db->dma_fragsize;
  570. }
  571. if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
  572. db->numfrag = db->ossmaxfrags;
  573. db->dmasize = db->dma_fragsize * db->numfrag;
  574. memset(db->rawbuf, 0, bufs);
  575. pr_debug("prog_dmabuf: rate=%d, samplesize=%d, channels=%d\n",
  576. rate, db->sample_size, db->num_channels);
  577. pr_debug("prog_dmabuf: fragsize=%d, cnt_factor=%d, dma_fragsize=%d\n",
  578. db->fragsize, db->cnt_factor, db->dma_fragsize);
  579. pr_debug("prog_dmabuf: numfrag=%d, dmasize=%d\n", db->numfrag, db->dmasize);
  580. db->ready = 1;
  581. return 0;
  582. }
  583. static int
  584. prog_dmabuf_adc(struct au1550_state *s)
  585. {
  586. stop_adc(s);
  587. return prog_dmabuf(s, &s->dma_adc);
  588. }
  589. static int
  590. prog_dmabuf_dac(struct au1550_state *s)
  591. {
  592. stop_dac(s);
  593. return prog_dmabuf(s, &s->dma_dac);
  594. }
  595. static void
  596. dac_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  597. {
  598. struct au1550_state *s = (struct au1550_state *) dev_id;
  599. struct dmabuf *db = &s->dma_dac;
  600. u32 ac97c_stat;
  601. spin_lock(&s->lock);
  602. ac97c_stat = au_readl(PSC_AC97STAT);
  603. if (ac97c_stat & (AC97C_XU | AC97C_XO | AC97C_TE))
  604. pr_debug("AC97C status = 0x%08x\n", ac97c_stat);
  605. db->dma_qcount--;
  606. if (db->count >= db->fragsize) {
  607. if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
  608. db->fragsize) == 0) {
  609. err("qcount < 2 and no ring room!");
  610. }
  611. db->nextOut += db->fragsize;
  612. if (db->nextOut >= db->rawbuf + db->dmasize)
  613. db->nextOut -= db->dmasize;
  614. db->count -= db->fragsize;
  615. db->total_bytes += db->dma_fragsize;
  616. db->dma_qcount++;
  617. }
  618. /* wake up anybody listening */
  619. if (waitqueue_active(&db->wait))
  620. wake_up(&db->wait);
  621. spin_unlock(&s->lock);
  622. }
  623. static void
  624. adc_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  625. {
  626. struct au1550_state *s = (struct au1550_state *)dev_id;
  627. struct dmabuf *dp = &s->dma_adc;
  628. u32 obytes;
  629. char *obuf;
  630. spin_lock(&s->lock);
  631. /* Pull the buffer from the dma queue.
  632. */
  633. au1xxx_dbdma_get_dest(dp->dmanr, (void *)(&obuf), &obytes);
  634. if ((dp->count + obytes) > dp->dmasize) {
  635. /* Overrun. Stop ADC and log the error
  636. */
  637. spin_unlock(&s->lock);
  638. stop_adc(s);
  639. dp->error++;
  640. err("adc overrun");
  641. return;
  642. }
  643. /* Put a new empty buffer on the destination DMA.
  644. */
  645. au1xxx_dbdma_put_dest(dp->dmanr, dp->nextIn, dp->dma_fragsize);
  646. dp->nextIn += dp->dma_fragsize;
  647. if (dp->nextIn >= dp->rawbuf + dp->dmasize)
  648. dp->nextIn -= dp->dmasize;
  649. dp->count += obytes;
  650. dp->total_bytes += obytes;
  651. /* wake up anybody listening
  652. */
  653. if (waitqueue_active(&dp->wait))
  654. wake_up(&dp->wait);
  655. spin_unlock(&s->lock);
  656. }
  657. static loff_t
  658. au1550_llseek(struct file *file, loff_t offset, int origin)
  659. {
  660. return -ESPIPE;
  661. }
  662. static int
  663. au1550_open_mixdev(struct inode *inode, struct file *file)
  664. {
  665. file->private_data = &au1550_state;
  666. return 0;
  667. }
  668. static int
  669. au1550_release_mixdev(struct inode *inode, struct file *file)
  670. {
  671. return 0;
  672. }
  673. static int
  674. mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
  675. unsigned long arg)
  676. {
  677. return codec->mixer_ioctl(codec, cmd, arg);
  678. }
  679. static int
  680. au1550_ioctl_mixdev(struct inode *inode, struct file *file,
  681. unsigned int cmd, unsigned long arg)
  682. {
  683. struct au1550_state *s = (struct au1550_state *)file->private_data;
  684. struct ac97_codec *codec = s->codec;
  685. return mixdev_ioctl(codec, cmd, arg);
  686. }
  687. static /*const */ struct file_operations au1550_mixer_fops = {
  688. owner:THIS_MODULE,
  689. llseek:au1550_llseek,
  690. ioctl:au1550_ioctl_mixdev,
  691. open:au1550_open_mixdev,
  692. release:au1550_release_mixdev,
  693. };
  694. static int
  695. drain_dac(struct au1550_state *s, int nonblock)
  696. {
  697. unsigned long flags;
  698. int count, tmo;
  699. if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
  700. return 0;
  701. for (;;) {
  702. spin_lock_irqsave(&s->lock, flags);
  703. count = s->dma_dac.count;
  704. spin_unlock_irqrestore(&s->lock, flags);
  705. if (count <= s->dma_dac.fragsize)
  706. break;
  707. if (signal_pending(current))
  708. break;
  709. if (nonblock)
  710. return -EBUSY;
  711. tmo = 1000 * count / (s->no_vra ?
  712. 48000 : s->dma_dac.sample_rate);
  713. tmo /= s->dma_dac.dma_bytes_per_sample;
  714. au1550_delay(tmo);
  715. }
  716. if (signal_pending(current))
  717. return -ERESTARTSYS;
  718. return 0;
  719. }
  720. static inline u8 S16_TO_U8(s16 ch)
  721. {
  722. return (u8) (ch >> 8) + 0x80;
  723. }
  724. static inline s16 U8_TO_S16(u8 ch)
  725. {
  726. return (s16) (ch - 0x80) << 8;
  727. }
  728. /*
  729. * Translates user samples to dma buffer suitable for AC'97 DAC data:
  730. * If mono, copy left channel to right channel in dma buffer.
  731. * If 8 bit samples, cvt to 16-bit before writing to dma buffer.
  732. * If interpolating (no VRA), duplicate every audio frame src_factor times.
  733. */
  734. static int
  735. translate_from_user(struct dmabuf *db, char* dmabuf, char* userbuf,
  736. int dmacount)
  737. {
  738. int sample, i;
  739. int interp_bytes_per_sample;
  740. int num_samples;
  741. int mono = (db->num_channels == 1);
  742. char usersample[12];
  743. s16 ch, dmasample[6];
  744. if (db->sample_size == 16 && !mono && db->src_factor == 1) {
  745. /* no translation necessary, just copy
  746. */
  747. if (copy_from_user(dmabuf, userbuf, dmacount))
  748. return -EFAULT;
  749. return dmacount;
  750. }
  751. interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
  752. num_samples = dmacount / interp_bytes_per_sample;
  753. for (sample = 0; sample < num_samples; sample++) {
  754. if (copy_from_user(usersample, userbuf,
  755. db->user_bytes_per_sample)) {
  756. return -EFAULT;
  757. }
  758. for (i = 0; i < db->num_channels; i++) {
  759. if (db->sample_size == 8)
  760. ch = U8_TO_S16(usersample[i]);
  761. else
  762. ch = *((s16 *) (&usersample[i * 2]));
  763. dmasample[i] = ch;
  764. if (mono)
  765. dmasample[i + 1] = ch; /* right channel */
  766. }
  767. /* duplicate every audio frame src_factor times
  768. */
  769. for (i = 0; i < db->src_factor; i++)
  770. memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
  771. userbuf += db->user_bytes_per_sample;
  772. dmabuf += interp_bytes_per_sample;
  773. }
  774. return num_samples * interp_bytes_per_sample;
  775. }
  776. /*
  777. * Translates AC'97 ADC samples to user buffer:
  778. * If mono, send only left channel to user buffer.
  779. * If 8 bit samples, cvt from 16 to 8 bit before writing to user buffer.
  780. * If decimating (no VRA), skip over src_factor audio frames.
  781. */
  782. static int
  783. translate_to_user(struct dmabuf *db, char* userbuf, char* dmabuf,
  784. int dmacount)
  785. {
  786. int sample, i;
  787. int interp_bytes_per_sample;
  788. int num_samples;
  789. int mono = (db->num_channels == 1);
  790. char usersample[12];
  791. if (db->sample_size == 16 && !mono && db->src_factor == 1) {
  792. /* no translation necessary, just copy
  793. */
  794. if (copy_to_user(userbuf, dmabuf, dmacount))
  795. return -EFAULT;
  796. return dmacount;
  797. }
  798. interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
  799. num_samples = dmacount / interp_bytes_per_sample;
  800. for (sample = 0; sample < num_samples; sample++) {
  801. for (i = 0; i < db->num_channels; i++) {
  802. if (db->sample_size == 8)
  803. usersample[i] =
  804. S16_TO_U8(*((s16 *) (&dmabuf[i * 2])));
  805. else
  806. *((s16 *) (&usersample[i * 2])) =
  807. *((s16 *) (&dmabuf[i * 2]));
  808. }
  809. if (copy_to_user(userbuf, usersample,
  810. db->user_bytes_per_sample)) {
  811. return -EFAULT;
  812. }
  813. userbuf += db->user_bytes_per_sample;
  814. dmabuf += interp_bytes_per_sample;
  815. }
  816. return num_samples * interp_bytes_per_sample;
  817. }
  818. /*
  819. * Copy audio data to/from user buffer from/to dma buffer, taking care
  820. * that we wrap when reading/writing the dma buffer. Returns actual byte
  821. * count written to or read from the dma buffer.
  822. */
  823. static int
  824. copy_dmabuf_user(struct dmabuf *db, char* userbuf, int count, int to_user)
  825. {
  826. char *bufptr = to_user ? db->nextOut : db->nextIn;
  827. char *bufend = db->rawbuf + db->dmasize;
  828. int cnt, ret;
  829. if (bufptr + count > bufend) {
  830. int partial = (int) (bufend - bufptr);
  831. if (to_user) {
  832. if ((cnt = translate_to_user(db, userbuf,
  833. bufptr, partial)) < 0)
  834. return cnt;
  835. ret = cnt;
  836. if ((cnt = translate_to_user(db, userbuf + partial,
  837. db->rawbuf,
  838. count - partial)) < 0)
  839. return cnt;
  840. ret += cnt;
  841. } else {
  842. if ((cnt = translate_from_user(db, bufptr, userbuf,
  843. partial)) < 0)
  844. return cnt;
  845. ret = cnt;
  846. if ((cnt = translate_from_user(db, db->rawbuf,
  847. userbuf + partial,
  848. count - partial)) < 0)
  849. return cnt;
  850. ret += cnt;
  851. }
  852. } else {
  853. if (to_user)
  854. ret = translate_to_user(db, userbuf, bufptr, count);
  855. else
  856. ret = translate_from_user(db, bufptr, userbuf, count);
  857. }
  858. return ret;
  859. }
  860. static ssize_t
  861. au1550_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
  862. {
  863. struct au1550_state *s = (struct au1550_state *)file->private_data;
  864. struct dmabuf *db = &s->dma_adc;
  865. DECLARE_WAITQUEUE(wait, current);
  866. ssize_t ret;
  867. unsigned long flags;
  868. int cnt, usercnt, avail;
  869. if (db->mapped)
  870. return -ENXIO;
  871. if (!access_ok(VERIFY_WRITE, buffer, count))
  872. return -EFAULT;
  873. ret = 0;
  874. count *= db->cnt_factor;
  875. mutex_lock(&s->sem);
  876. add_wait_queue(&db->wait, &wait);
  877. while (count > 0) {
  878. /* wait for samples in ADC dma buffer
  879. */
  880. do {
  881. spin_lock_irqsave(&s->lock, flags);
  882. if (db->stopped)
  883. start_adc(s);
  884. avail = db->count;
  885. if (avail <= 0)
  886. __set_current_state(TASK_INTERRUPTIBLE);
  887. spin_unlock_irqrestore(&s->lock, flags);
  888. if (avail <= 0) {
  889. if (file->f_flags & O_NONBLOCK) {
  890. if (!ret)
  891. ret = -EAGAIN;
  892. goto out;
  893. }
  894. mutex_unlock(&s->sem);
  895. schedule();
  896. if (signal_pending(current)) {
  897. if (!ret)
  898. ret = -ERESTARTSYS;
  899. goto out2;
  900. }
  901. mutex_lock(&s->sem);
  902. }
  903. } while (avail <= 0);
  904. /* copy from nextOut to user
  905. */
  906. if ((cnt = copy_dmabuf_user(db, buffer,
  907. count > avail ?
  908. avail : count, 1)) < 0) {
  909. if (!ret)
  910. ret = -EFAULT;
  911. goto out;
  912. }
  913. spin_lock_irqsave(&s->lock, flags);
  914. db->count -= cnt;
  915. db->nextOut += cnt;
  916. if (db->nextOut >= db->rawbuf + db->dmasize)
  917. db->nextOut -= db->dmasize;
  918. spin_unlock_irqrestore(&s->lock, flags);
  919. count -= cnt;
  920. usercnt = cnt / db->cnt_factor;
  921. buffer += usercnt;
  922. ret += usercnt;
  923. } /* while (count > 0) */
  924. out:
  925. mutex_unlock(&s->sem);
  926. out2:
  927. remove_wait_queue(&db->wait, &wait);
  928. set_current_state(TASK_RUNNING);
  929. return ret;
  930. }
  931. static ssize_t
  932. au1550_write(struct file *file, const char *buffer, size_t count, loff_t * ppos)
  933. {
  934. struct au1550_state *s = (struct au1550_state *)file->private_data;
  935. struct dmabuf *db = &s->dma_dac;
  936. DECLARE_WAITQUEUE(wait, current);
  937. ssize_t ret = 0;
  938. unsigned long flags;
  939. int cnt, usercnt, avail;
  940. pr_debug("write: count=%d\n", count);
  941. if (db->mapped)
  942. return -ENXIO;
  943. if (!access_ok(VERIFY_READ, buffer, count))
  944. return -EFAULT;
  945. count *= db->cnt_factor;
  946. mutex_lock(&s->sem);
  947. add_wait_queue(&db->wait, &wait);
  948. while (count > 0) {
  949. /* wait for space in playback buffer
  950. */
  951. do {
  952. spin_lock_irqsave(&s->lock, flags);
  953. avail = (int) db->dmasize - db->count;
  954. if (avail <= 0)
  955. __set_current_state(TASK_INTERRUPTIBLE);
  956. spin_unlock_irqrestore(&s->lock, flags);
  957. if (avail <= 0) {
  958. if (file->f_flags & O_NONBLOCK) {
  959. if (!ret)
  960. ret = -EAGAIN;
  961. goto out;
  962. }
  963. mutex_unlock(&s->sem);
  964. schedule();
  965. if (signal_pending(current)) {
  966. if (!ret)
  967. ret = -ERESTARTSYS;
  968. goto out2;
  969. }
  970. mutex_lock(&s->sem);
  971. }
  972. } while (avail <= 0);
  973. /* copy from user to nextIn
  974. */
  975. if ((cnt = copy_dmabuf_user(db, (char *) buffer,
  976. count > avail ?
  977. avail : count, 0)) < 0) {
  978. if (!ret)
  979. ret = -EFAULT;
  980. goto out;
  981. }
  982. spin_lock_irqsave(&s->lock, flags);
  983. db->count += cnt;
  984. db->nextIn += cnt;
  985. if (db->nextIn >= db->rawbuf + db->dmasize)
  986. db->nextIn -= db->dmasize;
  987. /* If the data is available, we want to keep two buffers
  988. * on the dma queue. If the queue count reaches zero,
  989. * we know the dma has stopped.
  990. */
  991. while ((db->dma_qcount < 2) && (db->count >= db->fragsize)) {
  992. if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
  993. db->fragsize) == 0) {
  994. err("qcount < 2 and no ring room!");
  995. }
  996. db->nextOut += db->fragsize;
  997. if (db->nextOut >= db->rawbuf + db->dmasize)
  998. db->nextOut -= db->dmasize;
  999. db->total_bytes += db->dma_fragsize;
  1000. if (db->dma_qcount == 0)
  1001. start_dac(s);
  1002. db->dma_qcount++;
  1003. }
  1004. spin_unlock_irqrestore(&s->lock, flags);
  1005. count -= cnt;
  1006. usercnt = cnt / db->cnt_factor;
  1007. buffer += usercnt;
  1008. ret += usercnt;
  1009. } /* while (count > 0) */
  1010. out:
  1011. mutex_unlock(&s->sem);
  1012. out2:
  1013. remove_wait_queue(&db->wait, &wait);
  1014. set_current_state(TASK_RUNNING);
  1015. return ret;
  1016. }
  1017. /* No kernel lock - we have our own spinlock */
  1018. static unsigned int
  1019. au1550_poll(struct file *file, struct poll_table_struct *wait)
  1020. {
  1021. struct au1550_state *s = (struct au1550_state *)file->private_data;
  1022. unsigned long flags;
  1023. unsigned int mask = 0;
  1024. if (file->f_mode & FMODE_WRITE) {
  1025. if (!s->dma_dac.ready)
  1026. return 0;
  1027. poll_wait(file, &s->dma_dac.wait, wait);
  1028. }
  1029. if (file->f_mode & FMODE_READ) {
  1030. if (!s->dma_adc.ready)
  1031. return 0;
  1032. poll_wait(file, &s->dma_adc.wait, wait);
  1033. }
  1034. spin_lock_irqsave(&s->lock, flags);
  1035. if (file->f_mode & FMODE_READ) {
  1036. if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
  1037. mask |= POLLIN | POLLRDNORM;
  1038. }
  1039. if (file->f_mode & FMODE_WRITE) {
  1040. if (s->dma_dac.mapped) {
  1041. if (s->dma_dac.count >=
  1042. (signed)s->dma_dac.dma_fragsize)
  1043. mask |= POLLOUT | POLLWRNORM;
  1044. } else {
  1045. if ((signed) s->dma_dac.dmasize >=
  1046. s->dma_dac.count + (signed)s->dma_dac.dma_fragsize)
  1047. mask |= POLLOUT | POLLWRNORM;
  1048. }
  1049. }
  1050. spin_unlock_irqrestore(&s->lock, flags);
  1051. return mask;
  1052. }
  1053. static int
  1054. au1550_mmap(struct file *file, struct vm_area_struct *vma)
  1055. {
  1056. struct au1550_state *s = (struct au1550_state *)file->private_data;
  1057. struct dmabuf *db;
  1058. unsigned long size;
  1059. int ret = 0;
  1060. lock_kernel();
  1061. mutex_lock(&s->sem);
  1062. if (vma->vm_flags & VM_WRITE)
  1063. db = &s->dma_dac;
  1064. else if (vma->vm_flags & VM_READ)
  1065. db = &s->dma_adc;
  1066. else {
  1067. ret = -EINVAL;
  1068. goto out;
  1069. }
  1070. if (vma->vm_pgoff != 0) {
  1071. ret = -EINVAL;
  1072. goto out;
  1073. }
  1074. size = vma->vm_end - vma->vm_start;
  1075. if (size > (PAGE_SIZE << db->buforder)) {
  1076. ret = -EINVAL;
  1077. goto out;
  1078. }
  1079. if (remap_pfn_range(vma, vma->vm_start, page_to_pfn(virt_to_page(db->rawbuf)),
  1080. size, vma->vm_page_prot)) {
  1081. ret = -EAGAIN;
  1082. goto out;
  1083. }
  1084. vma->vm_flags &= ~VM_IO;
  1085. db->mapped = 1;
  1086. out:
  1087. mutex_unlock(&s->sem);
  1088. unlock_kernel();
  1089. return ret;
  1090. }
  1091. #ifdef DEBUG
  1092. static struct ioctl_str_t {
  1093. unsigned int cmd;
  1094. const char *str;
  1095. } ioctl_str[] = {
  1096. {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
  1097. {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
  1098. {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
  1099. {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
  1100. {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
  1101. {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
  1102. {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
  1103. {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
  1104. {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
  1105. {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
  1106. {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
  1107. {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
  1108. {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
  1109. {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
  1110. {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
  1111. {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
  1112. {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
  1113. {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
  1114. {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
  1115. {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
  1116. {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
  1117. {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
  1118. {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
  1119. {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
  1120. {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
  1121. {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
  1122. {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
  1123. {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
  1124. {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
  1125. {OSS_GETVERSION, "OSS_GETVERSION"},
  1126. {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
  1127. {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
  1128. {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
  1129. {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
  1130. };
  1131. #endif
  1132. static int
  1133. dma_count_done(struct dmabuf *db)
  1134. {
  1135. if (db->stopped)
  1136. return 0;
  1137. return db->dma_fragsize - au1xxx_get_dma_residue(db->dmanr);
  1138. }
  1139. static int
  1140. au1550_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
  1141. unsigned long arg)
  1142. {
  1143. struct au1550_state *s = (struct au1550_state *)file->private_data;
  1144. unsigned long flags;
  1145. audio_buf_info abinfo;
  1146. count_info cinfo;
  1147. int count;
  1148. int val, mapped, ret, diff;
  1149. mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
  1150. ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
  1151. #ifdef DEBUG
  1152. for (count=0; count<sizeof(ioctl_str)/sizeof(ioctl_str[0]); count++) {
  1153. if (ioctl_str[count].cmd == cmd)
  1154. break;
  1155. }
  1156. if (count < sizeof(ioctl_str) / sizeof(ioctl_str[0]))
  1157. pr_debug("ioctl %s, arg=0x%lxn", ioctl_str[count].str, arg);
  1158. else
  1159. pr_debug("ioctl 0x%x unknown, arg=0x%lx\n", cmd, arg);
  1160. #endif
  1161. switch (cmd) {
  1162. case OSS_GETVERSION:
  1163. return put_user(SOUND_VERSION, (int *) arg);
  1164. case SNDCTL_DSP_SYNC:
  1165. if (file->f_mode & FMODE_WRITE)
  1166. return drain_dac(s, file->f_flags & O_NONBLOCK);
  1167. return 0;
  1168. case SNDCTL_DSP_SETDUPLEX:
  1169. return 0;
  1170. case SNDCTL_DSP_GETCAPS:
  1171. return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
  1172. DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
  1173. case SNDCTL_DSP_RESET:
  1174. if (file->f_mode & FMODE_WRITE) {
  1175. stop_dac(s);
  1176. synchronize_irq();
  1177. s->dma_dac.count = s->dma_dac.total_bytes = 0;
  1178. s->dma_dac.nextIn = s->dma_dac.nextOut =
  1179. s->dma_dac.rawbuf;
  1180. }
  1181. if (file->f_mode & FMODE_READ) {
  1182. stop_adc(s);
  1183. synchronize_irq();
  1184. s->dma_adc.count = s->dma_adc.total_bytes = 0;
  1185. s->dma_adc.nextIn = s->dma_adc.nextOut =
  1186. s->dma_adc.rawbuf;
  1187. }
  1188. return 0;
  1189. case SNDCTL_DSP_SPEED:
  1190. if (get_user(val, (int *) arg))
  1191. return -EFAULT;
  1192. if (val >= 0) {
  1193. if (file->f_mode & FMODE_READ) {
  1194. stop_adc(s);
  1195. set_adc_rate(s, val);
  1196. }
  1197. if (file->f_mode & FMODE_WRITE) {
  1198. stop_dac(s);
  1199. set_dac_rate(s, val);
  1200. }
  1201. if (s->open_mode & FMODE_READ)
  1202. if ((ret = prog_dmabuf_adc(s)))
  1203. return ret;
  1204. if (s->open_mode & FMODE_WRITE)
  1205. if ((ret = prog_dmabuf_dac(s)))
  1206. return ret;
  1207. }
  1208. return put_user((file->f_mode & FMODE_READ) ?
  1209. s->dma_adc.sample_rate :
  1210. s->dma_dac.sample_rate,
  1211. (int *)arg);
  1212. case SNDCTL_DSP_STEREO:
  1213. if (get_user(val, (int *) arg))
  1214. return -EFAULT;
  1215. if (file->f_mode & FMODE_READ) {
  1216. stop_adc(s);
  1217. s->dma_adc.num_channels = val ? 2 : 1;
  1218. if ((ret = prog_dmabuf_adc(s)))
  1219. return ret;
  1220. }
  1221. if (file->f_mode & FMODE_WRITE) {
  1222. stop_dac(s);
  1223. s->dma_dac.num_channels = val ? 2 : 1;
  1224. if (s->codec_ext_caps & AC97_EXT_DACS) {
  1225. /* disable surround and center/lfe in AC'97
  1226. */
  1227. u16 ext_stat = rdcodec(s->codec,
  1228. AC97_EXTENDED_STATUS);
  1229. wrcodec(s->codec, AC97_EXTENDED_STATUS,
  1230. ext_stat | (AC97_EXTSTAT_PRI |
  1231. AC97_EXTSTAT_PRJ |
  1232. AC97_EXTSTAT_PRK));
  1233. }
  1234. if ((ret = prog_dmabuf_dac(s)))
  1235. return ret;
  1236. }
  1237. return 0;
  1238. case SNDCTL_DSP_CHANNELS:
  1239. if (get_user(val, (int *) arg))
  1240. return -EFAULT;
  1241. if (val != 0) {
  1242. if (file->f_mode & FMODE_READ) {
  1243. if (val < 0 || val > 2)
  1244. return -EINVAL;
  1245. stop_adc(s);
  1246. s->dma_adc.num_channels = val;
  1247. if ((ret = prog_dmabuf_adc(s)))
  1248. return ret;
  1249. }
  1250. if (file->f_mode & FMODE_WRITE) {
  1251. switch (val) {
  1252. case 1:
  1253. case 2:
  1254. break;
  1255. case 3:
  1256. case 5:
  1257. return -EINVAL;
  1258. case 4:
  1259. if (!(s->codec_ext_caps &
  1260. AC97_EXTID_SDAC))
  1261. return -EINVAL;
  1262. break;
  1263. case 6:
  1264. if ((s->codec_ext_caps &
  1265. AC97_EXT_DACS) != AC97_EXT_DACS)
  1266. return -EINVAL;
  1267. break;
  1268. default:
  1269. return -EINVAL;
  1270. }
  1271. stop_dac(s);
  1272. if (val <= 2 &&
  1273. (s->codec_ext_caps & AC97_EXT_DACS)) {
  1274. /* disable surround and center/lfe
  1275. * channels in AC'97
  1276. */
  1277. u16 ext_stat =
  1278. rdcodec(s->codec,
  1279. AC97_EXTENDED_STATUS);
  1280. wrcodec(s->codec,
  1281. AC97_EXTENDED_STATUS,
  1282. ext_stat | (AC97_EXTSTAT_PRI |
  1283. AC97_EXTSTAT_PRJ |
  1284. AC97_EXTSTAT_PRK));
  1285. } else if (val >= 4) {
  1286. /* enable surround, center/lfe
  1287. * channels in AC'97
  1288. */
  1289. u16 ext_stat =
  1290. rdcodec(s->codec,
  1291. AC97_EXTENDED_STATUS);
  1292. ext_stat &= ~AC97_EXTSTAT_PRJ;
  1293. if (val == 6)
  1294. ext_stat &=
  1295. ~(AC97_EXTSTAT_PRI |
  1296. AC97_EXTSTAT_PRK);
  1297. wrcodec(s->codec,
  1298. AC97_EXTENDED_STATUS,
  1299. ext_stat);
  1300. }
  1301. s->dma_dac.num_channels = val;
  1302. if ((ret = prog_dmabuf_dac(s)))
  1303. return ret;
  1304. }
  1305. }
  1306. return put_user(val, (int *) arg);
  1307. case SNDCTL_DSP_GETFMTS: /* Returns a mask */
  1308. return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg);
  1309. case SNDCTL_DSP_SETFMT: /* Selects ONE fmt */
  1310. if (get_user(val, (int *) arg))
  1311. return -EFAULT;
  1312. if (val != AFMT_QUERY) {
  1313. if (file->f_mode & FMODE_READ) {
  1314. stop_adc(s);
  1315. if (val == AFMT_S16_LE)
  1316. s->dma_adc.sample_size = 16;
  1317. else {
  1318. val = AFMT_U8;
  1319. s->dma_adc.sample_size = 8;
  1320. }
  1321. if ((ret = prog_dmabuf_adc(s)))
  1322. return ret;
  1323. }
  1324. if (file->f_mode & FMODE_WRITE) {
  1325. stop_dac(s);
  1326. if (val == AFMT_S16_LE)
  1327. s->dma_dac.sample_size = 16;
  1328. else {
  1329. val = AFMT_U8;
  1330. s->dma_dac.sample_size = 8;
  1331. }
  1332. if ((ret = prog_dmabuf_dac(s)))
  1333. return ret;
  1334. }
  1335. } else {
  1336. if (file->f_mode & FMODE_READ)
  1337. val = (s->dma_adc.sample_size == 16) ?
  1338. AFMT_S16_LE : AFMT_U8;
  1339. else
  1340. val = (s->dma_dac.sample_size == 16) ?
  1341. AFMT_S16_LE : AFMT_U8;
  1342. }
  1343. return put_user(val, (int *) arg);
  1344. case SNDCTL_DSP_POST:
  1345. return 0;
  1346. case SNDCTL_DSP_GETTRIGGER:
  1347. val = 0;
  1348. spin_lock_irqsave(&s->lock, flags);
  1349. if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
  1350. val |= PCM_ENABLE_INPUT;
  1351. if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
  1352. val |= PCM_ENABLE_OUTPUT;
  1353. spin_unlock_irqrestore(&s->lock, flags);
  1354. return put_user(val, (int *) arg);
  1355. case SNDCTL_DSP_SETTRIGGER:
  1356. if (get_user(val, (int *) arg))
  1357. return -EFAULT;
  1358. if (file->f_mode & FMODE_READ) {
  1359. if (val & PCM_ENABLE_INPUT) {
  1360. spin_lock_irqsave(&s->lock, flags);
  1361. start_adc(s);
  1362. spin_unlock_irqrestore(&s->lock, flags);
  1363. } else
  1364. stop_adc(s);
  1365. }
  1366. if (file->f_mode & FMODE_WRITE) {
  1367. if (val & PCM_ENABLE_OUTPUT) {
  1368. spin_lock_irqsave(&s->lock, flags);
  1369. start_dac(s);
  1370. spin_unlock_irqrestore(&s->lock, flags);
  1371. } else
  1372. stop_dac(s);
  1373. }
  1374. return 0;
  1375. case SNDCTL_DSP_GETOSPACE:
  1376. if (!(file->f_mode & FMODE_WRITE))
  1377. return -EINVAL;
  1378. abinfo.fragsize = s->dma_dac.fragsize;
  1379. spin_lock_irqsave(&s->lock, flags);
  1380. count = s->dma_dac.count;
  1381. count -= dma_count_done(&s->dma_dac);
  1382. spin_unlock_irqrestore(&s->lock, flags);
  1383. if (count < 0)
  1384. count = 0;
  1385. abinfo.bytes = (s->dma_dac.dmasize - count) /
  1386. s->dma_dac.cnt_factor;
  1387. abinfo.fragstotal = s->dma_dac.numfrag;
  1388. abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
  1389. pr_debug("ioctl SNDCTL_DSP_GETOSPACE: bytes=%d, fragments=%d\n", abinfo.bytes, abinfo.fragments);
  1390. return copy_to_user((void *) arg, &abinfo,
  1391. sizeof(abinfo)) ? -EFAULT : 0;
  1392. case SNDCTL_DSP_GETISPACE:
  1393. if (!(file->f_mode & FMODE_READ))
  1394. return -EINVAL;
  1395. abinfo.fragsize = s->dma_adc.fragsize;
  1396. spin_lock_irqsave(&s->lock, flags);
  1397. count = s->dma_adc.count;
  1398. count += dma_count_done(&s->dma_adc);
  1399. spin_unlock_irqrestore(&s->lock, flags);
  1400. if (count < 0)
  1401. count = 0;
  1402. abinfo.bytes = count / s->dma_adc.cnt_factor;
  1403. abinfo.fragstotal = s->dma_adc.numfrag;
  1404. abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
  1405. return copy_to_user((void *) arg, &abinfo,
  1406. sizeof(abinfo)) ? -EFAULT : 0;
  1407. case SNDCTL_DSP_NONBLOCK:
  1408. file->f_flags |= O_NONBLOCK;
  1409. return 0;
  1410. case SNDCTL_DSP_GETODELAY:
  1411. if (!(file->f_mode & FMODE_WRITE))
  1412. return -EINVAL;
  1413. spin_lock_irqsave(&s->lock, flags);
  1414. count = s->dma_dac.count;
  1415. count -= dma_count_done(&s->dma_dac);
  1416. spin_unlock_irqrestore(&s->lock, flags);
  1417. if (count < 0)
  1418. count = 0;
  1419. count /= s->dma_dac.cnt_factor;
  1420. return put_user(count, (int *) arg);
  1421. case SNDCTL_DSP_GETIPTR:
  1422. if (!(file->f_mode & FMODE_READ))
  1423. return -EINVAL;
  1424. spin_lock_irqsave(&s->lock, flags);
  1425. cinfo.bytes = s->dma_adc.total_bytes;
  1426. count = s->dma_adc.count;
  1427. if (!s->dma_adc.stopped) {
  1428. diff = dma_count_done(&s->dma_adc);
  1429. count += diff;
  1430. cinfo.bytes += diff;
  1431. cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) + diff -
  1432. virt_to_phys(s->dma_adc.rawbuf);
  1433. } else
  1434. cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) -
  1435. virt_to_phys(s->dma_adc.rawbuf);
  1436. if (s->dma_adc.mapped)
  1437. s->dma_adc.count &= (s->dma_adc.dma_fragsize-1);
  1438. spin_unlock_irqrestore(&s->lock, flags);
  1439. if (count < 0)
  1440. count = 0;
  1441. cinfo.blocks = count >> s->dma_adc.fragshift;
  1442. return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
  1443. case SNDCTL_DSP_GETOPTR:
  1444. if (!(file->f_mode & FMODE_READ))
  1445. return -EINVAL;
  1446. spin_lock_irqsave(&s->lock, flags);
  1447. cinfo.bytes = s->dma_dac.total_bytes;
  1448. count = s->dma_dac.count;
  1449. if (!s->dma_dac.stopped) {
  1450. diff = dma_count_done(&s->dma_dac);
  1451. count -= diff;
  1452. cinfo.bytes += diff;
  1453. cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff -
  1454. virt_to_phys(s->dma_dac.rawbuf);
  1455. } else
  1456. cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) -
  1457. virt_to_phys(s->dma_dac.rawbuf);
  1458. if (s->dma_dac.mapped)
  1459. s->dma_dac.count &= (s->dma_dac.dma_fragsize-1);
  1460. spin_unlock_irqrestore(&s->lock, flags);
  1461. if (count < 0)
  1462. count = 0;
  1463. cinfo.blocks = count >> s->dma_dac.fragshift;
  1464. return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
  1465. case SNDCTL_DSP_GETBLKSIZE:
  1466. if (file->f_mode & FMODE_WRITE)
  1467. return put_user(s->dma_dac.fragsize, (int *) arg);
  1468. else
  1469. return put_user(s->dma_adc.fragsize, (int *) arg);
  1470. case SNDCTL_DSP_SETFRAGMENT:
  1471. if (get_user(val, (int *) arg))
  1472. return -EFAULT;
  1473. if (file->f_mode & FMODE_READ) {
  1474. stop_adc(s);
  1475. s->dma_adc.ossfragshift = val & 0xffff;
  1476. s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
  1477. if (s->dma_adc.ossfragshift < 4)
  1478. s->dma_adc.ossfragshift = 4;
  1479. if (s->dma_adc.ossfragshift > 15)
  1480. s->dma_adc.ossfragshift = 15;
  1481. if (s->dma_adc.ossmaxfrags < 4)
  1482. s->dma_adc.ossmaxfrags = 4;
  1483. if ((ret = prog_dmabuf_adc(s)))
  1484. return ret;
  1485. }
  1486. if (file->f_mode & FMODE_WRITE) {
  1487. stop_dac(s);
  1488. s->dma_dac.ossfragshift = val & 0xffff;
  1489. s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
  1490. if (s->dma_dac.ossfragshift < 4)
  1491. s->dma_dac.ossfragshift = 4;
  1492. if (s->dma_dac.ossfragshift > 15)
  1493. s->dma_dac.ossfragshift = 15;
  1494. if (s->dma_dac.ossmaxfrags < 4)
  1495. s->dma_dac.ossmaxfrags = 4;
  1496. if ((ret = prog_dmabuf_dac(s)))
  1497. return ret;
  1498. }
  1499. return 0;
  1500. case SNDCTL_DSP_SUBDIVIDE:
  1501. if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
  1502. (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
  1503. return -EINVAL;
  1504. if (get_user(val, (int *) arg))
  1505. return -EFAULT;
  1506. if (val != 1 && val != 2 && val != 4)
  1507. return -EINVAL;
  1508. if (file->f_mode & FMODE_READ) {
  1509. stop_adc(s);
  1510. s->dma_adc.subdivision = val;
  1511. if ((ret = prog_dmabuf_adc(s)))
  1512. return ret;
  1513. }
  1514. if (file->f_mode & FMODE_WRITE) {
  1515. stop_dac(s);
  1516. s->dma_dac.subdivision = val;
  1517. if ((ret = prog_dmabuf_dac(s)))
  1518. return ret;
  1519. }
  1520. return 0;
  1521. case SOUND_PCM_READ_RATE:
  1522. return put_user((file->f_mode & FMODE_READ) ?
  1523. s->dma_adc.sample_rate :
  1524. s->dma_dac.sample_rate,
  1525. (int *)arg);
  1526. case SOUND_PCM_READ_CHANNELS:
  1527. if (file->f_mode & FMODE_READ)
  1528. return put_user(s->dma_adc.num_channels, (int *)arg);
  1529. else
  1530. return put_user(s->dma_dac.num_channels, (int *)arg);
  1531. case SOUND_PCM_READ_BITS:
  1532. if (file->f_mode & FMODE_READ)
  1533. return put_user(s->dma_adc.sample_size, (int *)arg);
  1534. else
  1535. return put_user(s->dma_dac.sample_size, (int *)arg);
  1536. case SOUND_PCM_WRITE_FILTER:
  1537. case SNDCTL_DSP_SETSYNCRO:
  1538. case SOUND_PCM_READ_FILTER:
  1539. return -EINVAL;
  1540. }
  1541. return mixdev_ioctl(s->codec, cmd, arg);
  1542. }
  1543. static int
  1544. au1550_open(struct inode *inode, struct file *file)
  1545. {
  1546. int minor = MINOR(inode->i_rdev);
  1547. DECLARE_WAITQUEUE(wait, current);
  1548. struct au1550_state *s = &au1550_state;
  1549. int ret;
  1550. #ifdef DEBUG
  1551. if (file->f_flags & O_NONBLOCK)
  1552. pr_debug("open: non-blocking\n");
  1553. else
  1554. pr_debug("open: blocking\n");
  1555. #endif
  1556. file->private_data = s;
  1557. /* wait for device to become free */
  1558. mutex_lock(&s->open_mutex);
  1559. while (s->open_mode & file->f_mode) {
  1560. if (file->f_flags & O_NONBLOCK) {
  1561. mutex_unlock(&s->open_mutex);
  1562. return -EBUSY;
  1563. }
  1564. add_wait_queue(&s->open_wait, &wait);
  1565. __set_current_state(TASK_INTERRUPTIBLE);
  1566. mutex_unlock(&s->open_mutex);
  1567. schedule();
  1568. remove_wait_queue(&s->open_wait, &wait);
  1569. set_current_state(TASK_RUNNING);
  1570. if (signal_pending(current))
  1571. return -ERESTARTSYS;
  1572. mutex_lock(&s->open_mutex);
  1573. }
  1574. stop_dac(s);
  1575. stop_adc(s);
  1576. if (file->f_mode & FMODE_READ) {
  1577. s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
  1578. s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
  1579. s->dma_adc.num_channels = 1;
  1580. s->dma_adc.sample_size = 8;
  1581. set_adc_rate(s, 8000);
  1582. if ((minor & 0xf) == SND_DEV_DSP16)
  1583. s->dma_adc.sample_size = 16;
  1584. }
  1585. if (file->f_mode & FMODE_WRITE) {
  1586. s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
  1587. s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
  1588. s->dma_dac.num_channels = 1;
  1589. s->dma_dac.sample_size = 8;
  1590. set_dac_rate(s, 8000);
  1591. if ((minor & 0xf) == SND_DEV_DSP16)
  1592. s->dma_dac.sample_size = 16;
  1593. }
  1594. if (file->f_mode & FMODE_READ) {
  1595. if ((ret = prog_dmabuf_adc(s)))
  1596. return ret;
  1597. }
  1598. if (file->f_mode & FMODE_WRITE) {
  1599. if ((ret = prog_dmabuf_dac(s)))
  1600. return ret;
  1601. }
  1602. s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
  1603. mutex_unlock(&s->open_mutex);
  1604. mutex_init(&s->sem);
  1605. return 0;
  1606. }
  1607. static int
  1608. au1550_release(struct inode *inode, struct file *file)
  1609. {
  1610. struct au1550_state *s = (struct au1550_state *)file->private_data;
  1611. lock_kernel();
  1612. if (file->f_mode & FMODE_WRITE) {
  1613. unlock_kernel();
  1614. drain_dac(s, file->f_flags & O_NONBLOCK);
  1615. lock_kernel();
  1616. }
  1617. mutex_lock(&s->open_mutex);
  1618. if (file->f_mode & FMODE_WRITE) {
  1619. stop_dac(s);
  1620. kfree(s->dma_dac.rawbuf);
  1621. s->dma_dac.rawbuf = NULL;
  1622. }
  1623. if (file->f_mode & FMODE_READ) {
  1624. stop_adc(s);
  1625. kfree(s->dma_adc.rawbuf);
  1626. s->dma_adc.rawbuf = NULL;
  1627. }
  1628. s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
  1629. mutex_unlock(&s->open_mutex);
  1630. wake_up(&s->open_wait);
  1631. unlock_kernel();
  1632. return 0;
  1633. }
  1634. static /*const */ struct file_operations au1550_audio_fops = {
  1635. owner: THIS_MODULE,
  1636. llseek: au1550_llseek,
  1637. read: au1550_read,
  1638. write: au1550_write,
  1639. poll: au1550_poll,
  1640. ioctl: au1550_ioctl,
  1641. mmap: au1550_mmap,
  1642. open: au1550_open,
  1643. release: au1550_release,
  1644. };
  1645. MODULE_AUTHOR("Advanced Micro Devices (AMD), dan@embeddededge.com");
  1646. MODULE_DESCRIPTION("Au1550 AC97 Audio Driver");
  1647. MODULE_LICENSE("GPL");
  1648. static int __devinit
  1649. au1550_probe(void)
  1650. {
  1651. struct au1550_state *s = &au1550_state;
  1652. int val;
  1653. memset(s, 0, sizeof(struct au1550_state));
  1654. init_waitqueue_head(&s->dma_adc.wait);
  1655. init_waitqueue_head(&s->dma_dac.wait);
  1656. init_waitqueue_head(&s->open_wait);
  1657. mutex_init(&s->open_mutex);
  1658. spin_lock_init(&s->lock);
  1659. s->codec = ac97_alloc_codec();
  1660. if(s->codec == NULL) {
  1661. err("Out of memory");
  1662. return -1;
  1663. }
  1664. s->codec->private_data = s;
  1665. s->codec->id = 0;
  1666. s->codec->codec_read = rdcodec;
  1667. s->codec->codec_write = wrcodec;
  1668. s->codec->codec_wait = waitcodec;
  1669. if (!request_mem_region(CPHYSADDR(AC97_PSC_SEL),
  1670. 0x30, "Au1550 AC97")) {
  1671. err("AC'97 ports in use");
  1672. }
  1673. /* Allocate the DMA Channels
  1674. */
  1675. if ((s->dma_dac.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_MEM_CHAN,
  1676. DBDMA_AC97_TX_CHAN, dac_dma_interrupt, (void *)s)) == 0) {
  1677. err("Can't get DAC DMA");
  1678. goto err_dma1;
  1679. }
  1680. au1xxx_dbdma_set_devwidth(s->dma_dac.dmanr, 16);
  1681. if (au1xxx_dbdma_ring_alloc(s->dma_dac.dmanr,
  1682. NUM_DBDMA_DESCRIPTORS) == 0) {
  1683. err("Can't get DAC DMA descriptors");
  1684. goto err_dma1;
  1685. }
  1686. if ((s->dma_adc.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_AC97_RX_CHAN,
  1687. DBDMA_MEM_CHAN, adc_dma_interrupt, (void *)s)) == 0) {
  1688. err("Can't get ADC DMA");
  1689. goto err_dma2;
  1690. }
  1691. au1xxx_dbdma_set_devwidth(s->dma_adc.dmanr, 16);
  1692. if (au1xxx_dbdma_ring_alloc(s->dma_adc.dmanr,
  1693. NUM_DBDMA_DESCRIPTORS) == 0) {
  1694. err("Can't get ADC DMA descriptors");
  1695. goto err_dma2;
  1696. }
  1697. pr_info("DAC: DMA%d, ADC: DMA%d", DBDMA_AC97_TX_CHAN, DBDMA_AC97_RX_CHAN);
  1698. /* register devices */
  1699. if ((s->dev_audio = register_sound_dsp(&au1550_audio_fops, -1)) < 0)
  1700. goto err_dev1;
  1701. if ((s->codec->dev_mixer =
  1702. register_sound_mixer(&au1550_mixer_fops, -1)) < 0)
  1703. goto err_dev2;
  1704. /* The GPIO for the appropriate PSC was configured by the
  1705. * board specific start up.
  1706. *
  1707. * configure PSC for AC'97
  1708. */
  1709. au_writel(0, AC97_PSC_CTRL); /* Disable PSC */
  1710. au_sync();
  1711. au_writel((PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE), AC97_PSC_SEL);
  1712. au_sync();
  1713. /* cold reset the AC'97
  1714. */
  1715. au_writel(PSC_AC97RST_RST, PSC_AC97RST);
  1716. au_sync();
  1717. au1550_delay(10);
  1718. au_writel(0, PSC_AC97RST);
  1719. au_sync();
  1720. /* need to delay around 500msec(bleech) to give
  1721. some CODECs enough time to wakeup */
  1722. au1550_delay(500);
  1723. /* warm reset the AC'97 to start the bitclk
  1724. */
  1725. au_writel(PSC_AC97RST_SNC, PSC_AC97RST);
  1726. au_sync();
  1727. udelay(100);
  1728. au_writel(0, PSC_AC97RST);
  1729. au_sync();
  1730. /* Enable PSC
  1731. */
  1732. au_writel(PSC_CTRL_ENABLE, AC97_PSC_CTRL);
  1733. au_sync();
  1734. /* Wait for PSC ready.
  1735. */
  1736. do {
  1737. val = au_readl(PSC_AC97STAT);
  1738. au_sync();
  1739. } while ((val & PSC_AC97STAT_SR) == 0);
  1740. /* Configure AC97 controller.
  1741. * Deep FIFO, 16-bit sample, DMA, make sure DMA matches fifo size.
  1742. */
  1743. val = PSC_AC97CFG_SET_LEN(16);
  1744. val |= PSC_AC97CFG_RT_FIFO8 | PSC_AC97CFG_TT_FIFO8;
  1745. /* Enable device so we can at least
  1746. * talk over the AC-link.
  1747. */
  1748. au_writel(val, PSC_AC97CFG);
  1749. au_writel(PSC_AC97MSK_ALLMASK, PSC_AC97MSK);
  1750. au_sync();
  1751. val |= PSC_AC97CFG_DE_ENABLE;
  1752. au_writel(val, PSC_AC97CFG);
  1753. au_sync();
  1754. /* Wait for Device ready.
  1755. */
  1756. do {
  1757. val = au_readl(PSC_AC97STAT);
  1758. au_sync();
  1759. } while ((val & PSC_AC97STAT_DR) == 0);
  1760. /* codec init */
  1761. if (!ac97_probe_codec(s->codec))
  1762. goto err_dev3;
  1763. s->codec_base_caps = rdcodec(s->codec, AC97_RESET);
  1764. s->codec_ext_caps = rdcodec(s->codec, AC97_EXTENDED_ID);
  1765. pr_info("AC'97 Base/Extended ID = %04x/%04x",
  1766. s->codec_base_caps, s->codec_ext_caps);
  1767. if (!(s->codec_ext_caps & AC97_EXTID_VRA)) {
  1768. /* codec does not support VRA
  1769. */
  1770. s->no_vra = 1;
  1771. } else if (!vra) {
  1772. /* Boot option says disable VRA
  1773. */
  1774. u16 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
  1775. wrcodec(s->codec, AC97_EXTENDED_STATUS,
  1776. ac97_extstat & ~AC97_EXTSTAT_VRA);
  1777. s->no_vra = 1;
  1778. }
  1779. if (s->no_vra)
  1780. pr_info("no VRA, interpolating and decimating");
  1781. /* set mic to be the recording source */
  1782. val = SOUND_MASK_MIC;
  1783. mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC,
  1784. (unsigned long) &val);
  1785. return 0;
  1786. err_dev3:
  1787. unregister_sound_mixer(s->codec->dev_mixer);
  1788. err_dev2:
  1789. unregister_sound_dsp(s->dev_audio);
  1790. err_dev1:
  1791. au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
  1792. err_dma2:
  1793. au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
  1794. err_dma1:
  1795. release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
  1796. ac97_release_codec(s->codec);
  1797. return -1;
  1798. }
  1799. static void __devinit
  1800. au1550_remove(void)
  1801. {
  1802. struct au1550_state *s = &au1550_state;
  1803. if (!s)
  1804. return;
  1805. synchronize_irq();
  1806. au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
  1807. au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
  1808. release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
  1809. unregister_sound_dsp(s->dev_audio);
  1810. unregister_sound_mixer(s->codec->dev_mixer);
  1811. ac97_release_codec(s->codec);
  1812. }
  1813. static int __init
  1814. init_au1550(void)
  1815. {
  1816. return au1550_probe();
  1817. }
  1818. static void __exit
  1819. cleanup_au1550(void)
  1820. {
  1821. au1550_remove();
  1822. }
  1823. module_init(init_au1550);
  1824. module_exit(cleanup_au1550);
  1825. #ifndef MODULE
  1826. static int __init
  1827. au1550_setup(char *options)
  1828. {
  1829. char *this_opt;
  1830. if (!options || !*options)
  1831. return 0;
  1832. while ((this_opt = strsep(&options, ","))) {
  1833. if (!*this_opt)
  1834. continue;
  1835. if (!strncmp(this_opt, "vra", 3)) {
  1836. vra = 1;
  1837. }
  1838. }
  1839. return 1;
  1840. }
  1841. __setup("au1550_audio=", au1550_setup);
  1842. #endif /* MODULE */