asix.c 23 KB

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  1. /*
  2. * ASIX AX8817X based USB 2.0 Ethernet Devices
  3. * Copyright (C) 2003-2005 David Hollis <dhollis@davehollis.com>
  4. * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
  5. * Copyright (c) 2002-2003 TiVo Inc.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. */
  21. // #define DEBUG // error path messages, extra info
  22. // #define VERBOSE // more; success messages
  23. #include <linux/module.h>
  24. #include <linux/kmod.h>
  25. #include <linux/sched.h>
  26. #include <linux/init.h>
  27. #include <linux/netdevice.h>
  28. #include <linux/etherdevice.h>
  29. #include <linux/ethtool.h>
  30. #include <linux/workqueue.h>
  31. #include <linux/mii.h>
  32. #include <linux/usb.h>
  33. #include <linux/crc32.h>
  34. #include "usbnet.h"
  35. /* ASIX AX8817X based USB 2.0 Ethernet Devices */
  36. #define AX_CMD_SET_SW_MII 0x06
  37. #define AX_CMD_READ_MII_REG 0x07
  38. #define AX_CMD_WRITE_MII_REG 0x08
  39. #define AX_CMD_SET_HW_MII 0x0a
  40. #define AX_CMD_READ_EEPROM 0x0b
  41. #define AX_CMD_WRITE_EEPROM 0x0c
  42. #define AX_CMD_WRITE_ENABLE 0x0d
  43. #define AX_CMD_WRITE_DISABLE 0x0e
  44. #define AX_CMD_WRITE_RX_CTL 0x10
  45. #define AX_CMD_READ_IPG012 0x11
  46. #define AX_CMD_WRITE_IPG0 0x12
  47. #define AX_CMD_WRITE_IPG1 0x13
  48. #define AX_CMD_WRITE_IPG2 0x14
  49. #define AX_CMD_WRITE_MULTI_FILTER 0x16
  50. #define AX_CMD_READ_NODE_ID 0x17
  51. #define AX_CMD_READ_PHY_ID 0x19
  52. #define AX_CMD_READ_MEDIUM_STATUS 0x1a
  53. #define AX_CMD_WRITE_MEDIUM_MODE 0x1b
  54. #define AX_CMD_READ_MONITOR_MODE 0x1c
  55. #define AX_CMD_WRITE_MONITOR_MODE 0x1d
  56. #define AX_CMD_WRITE_GPIOS 0x1f
  57. #define AX_CMD_SW_RESET 0x20
  58. #define AX_CMD_SW_PHY_STATUS 0x21
  59. #define AX_CMD_SW_PHY_SELECT 0x22
  60. #define AX88772_CMD_READ_NODE_ID 0x13
  61. #define AX_MONITOR_MODE 0x01
  62. #define AX_MONITOR_LINK 0x02
  63. #define AX_MONITOR_MAGIC 0x04
  64. #define AX_MONITOR_HSFS 0x10
  65. /* AX88172 Medium Status Register values */
  66. #define AX_MEDIUM_FULL_DUPLEX 0x02
  67. #define AX_MEDIUM_TX_ABORT_ALLOW 0x04
  68. #define AX_MEDIUM_FLOW_CONTROL_EN 0x10
  69. #define AX_MCAST_FILTER_SIZE 8
  70. #define AX_MAX_MCAST 64
  71. #define AX_EEPROM_LEN 0x40
  72. #define AX_SWRESET_CLEAR 0x00
  73. #define AX_SWRESET_RR 0x01
  74. #define AX_SWRESET_RT 0x02
  75. #define AX_SWRESET_PRTE 0x04
  76. #define AX_SWRESET_PRL 0x08
  77. #define AX_SWRESET_BZ 0x10
  78. #define AX_SWRESET_IPRL 0x20
  79. #define AX_SWRESET_IPPD 0x40
  80. #define AX88772_IPG0_DEFAULT 0x15
  81. #define AX88772_IPG1_DEFAULT 0x0c
  82. #define AX88772_IPG2_DEFAULT 0x12
  83. #define AX88772_MEDIUM_FULL_DUPLEX 0x0002
  84. #define AX88772_MEDIUM_RESERVED 0x0004
  85. #define AX88772_MEDIUM_RX_FC_ENABLE 0x0010
  86. #define AX88772_MEDIUM_TX_FC_ENABLE 0x0020
  87. #define AX88772_MEDIUM_PAUSE_FORMAT 0x0080
  88. #define AX88772_MEDIUM_RX_ENABLE 0x0100
  89. #define AX88772_MEDIUM_100MB 0x0200
  90. #define AX88772_MEDIUM_DEFAULT \
  91. (AX88772_MEDIUM_FULL_DUPLEX | AX88772_MEDIUM_RX_FC_ENABLE | \
  92. AX88772_MEDIUM_TX_FC_ENABLE | AX88772_MEDIUM_100MB | \
  93. AX88772_MEDIUM_RESERVED | AX88772_MEDIUM_RX_ENABLE )
  94. #define AX_EEPROM_MAGIC 0xdeadbeef
  95. /* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */
  96. struct asix_data {
  97. u8 multi_filter[AX_MCAST_FILTER_SIZE];
  98. };
  99. struct ax88172_int_data {
  100. u16 res1;
  101. u8 link;
  102. u16 res2;
  103. u8 status;
  104. u16 res3;
  105. } __attribute__ ((packed));
  106. static int asix_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
  107. u16 size, void *data)
  108. {
  109. return usb_control_msg(
  110. dev->udev,
  111. usb_rcvctrlpipe(dev->udev, 0),
  112. cmd,
  113. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  114. value,
  115. index,
  116. data,
  117. size,
  118. USB_CTRL_GET_TIMEOUT);
  119. }
  120. static int asix_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
  121. u16 size, void *data)
  122. {
  123. return usb_control_msg(
  124. dev->udev,
  125. usb_sndctrlpipe(dev->udev, 0),
  126. cmd,
  127. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  128. value,
  129. index,
  130. data,
  131. size,
  132. USB_CTRL_SET_TIMEOUT);
  133. }
  134. static void asix_async_cmd_callback(struct urb *urb, struct pt_regs *regs)
  135. {
  136. struct usb_ctrlrequest *req = (struct usb_ctrlrequest *)urb->context;
  137. if (urb->status < 0)
  138. printk(KERN_DEBUG "asix_async_cmd_callback() failed with %d",
  139. urb->status);
  140. kfree(req);
  141. usb_free_urb(urb);
  142. }
  143. static inline int asix_set_sw_mii(struct usbnet *dev)
  144. {
  145. int ret;
  146. ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL);
  147. if (ret < 0)
  148. devdbg(dev, "Failed to enable software MII access");
  149. return ret;
  150. }
  151. static inline int asix_set_hw_mii(struct usbnet *dev)
  152. {
  153. int ret;
  154. ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL);
  155. if (ret < 0)
  156. devdbg(dev, "Failed to enable hardware MII access");
  157. return ret;
  158. }
  159. static inline int asix_get_phyid(struct usbnet *dev)
  160. {
  161. int ret = 0;
  162. void *buf;
  163. buf = kmalloc(2, GFP_KERNEL);
  164. if (!buf)
  165. goto out1;
  166. if ((ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID,
  167. 0, 0, 2, buf)) < 2) {
  168. devdbg(dev, "Error reading PHYID register: %02x", ret);
  169. goto out2;
  170. }
  171. ret = *((u8 *)buf + 1);
  172. out2:
  173. kfree(buf);
  174. out1:
  175. return ret;
  176. }
  177. static int asix_sw_reset(struct usbnet *dev, u8 flags)
  178. {
  179. int ret;
  180. ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL);
  181. if (ret < 0)
  182. devdbg(dev,"Failed to send software reset: %02x", ret);
  183. return ret;
  184. }
  185. static int asix_write_rx_ctl(struct usbnet *dev, u16 mode)
  186. {
  187. int ret;
  188. ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL);
  189. if (ret < 0)
  190. devdbg(dev, "Failed to write RX_CTL mode: %02x", ret);
  191. return ret;
  192. }
  193. static void asix_status(struct usbnet *dev, struct urb *urb)
  194. {
  195. struct ax88172_int_data *event;
  196. int link;
  197. if (urb->actual_length < 8)
  198. return;
  199. event = urb->transfer_buffer;
  200. link = event->link & 0x01;
  201. if (netif_carrier_ok(dev->net) != link) {
  202. if (link) {
  203. netif_carrier_on(dev->net);
  204. usbnet_defer_kevent (dev, EVENT_LINK_RESET );
  205. } else
  206. netif_carrier_off(dev->net);
  207. devdbg(dev, "Link Status is: %d", link);
  208. }
  209. }
  210. static void
  211. asix_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value, u16 index,
  212. u16 size, void *data)
  213. {
  214. struct usb_ctrlrequest *req;
  215. int status;
  216. struct urb *urb;
  217. if ((urb = usb_alloc_urb(0, GFP_ATOMIC)) == NULL) {
  218. devdbg(dev, "Error allocating URB in write_cmd_async!");
  219. return;
  220. }
  221. if ((req = kmalloc(sizeof(struct usb_ctrlrequest), GFP_ATOMIC)) == NULL) {
  222. deverr(dev, "Failed to allocate memory for control request");
  223. usb_free_urb(urb);
  224. return;
  225. }
  226. req->bRequestType = USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE;
  227. req->bRequest = cmd;
  228. req->wValue = cpu_to_le16(value);
  229. req->wIndex = cpu_to_le16(index);
  230. req->wLength = cpu_to_le16(size);
  231. usb_fill_control_urb(urb, dev->udev,
  232. usb_sndctrlpipe(dev->udev, 0),
  233. (void *)req, data, size,
  234. asix_async_cmd_callback, req);
  235. if((status = usb_submit_urb(urb, GFP_ATOMIC)) < 0) {
  236. deverr(dev, "Error submitting the control message: status=%d",
  237. status);
  238. kfree(req);
  239. usb_free_urb(urb);
  240. }
  241. }
  242. static void asix_set_multicast(struct net_device *net)
  243. {
  244. struct usbnet *dev = netdev_priv(net);
  245. struct asix_data *data = (struct asix_data *)&dev->data;
  246. u8 rx_ctl = 0x8c;
  247. if (net->flags & IFF_PROMISC) {
  248. rx_ctl |= 0x01;
  249. } else if (net->flags & IFF_ALLMULTI
  250. || net->mc_count > AX_MAX_MCAST) {
  251. rx_ctl |= 0x02;
  252. } else if (net->mc_count == 0) {
  253. /* just broadcast and directed */
  254. } else {
  255. /* We use the 20 byte dev->data
  256. * for our 8 byte filter buffer
  257. * to avoid allocating memory that
  258. * is tricky to free later */
  259. struct dev_mc_list *mc_list = net->mc_list;
  260. u32 crc_bits;
  261. int i;
  262. memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
  263. /* Build the multicast hash filter. */
  264. for (i = 0; i < net->mc_count; i++) {
  265. crc_bits =
  266. ether_crc(ETH_ALEN,
  267. mc_list->dmi_addr) >> 26;
  268. data->multi_filter[crc_bits >> 3] |=
  269. 1 << (crc_bits & 7);
  270. mc_list = mc_list->next;
  271. }
  272. asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
  273. AX_MCAST_FILTER_SIZE, data->multi_filter);
  274. rx_ctl |= 0x10;
  275. }
  276. asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
  277. }
  278. static int asix_mdio_read(struct net_device *netdev, int phy_id, int loc)
  279. {
  280. struct usbnet *dev = netdev_priv(netdev);
  281. u16 res;
  282. asix_set_sw_mii(dev);
  283. asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id,
  284. (__u16)loc, 2, (u16 *)&res);
  285. asix_set_hw_mii(dev);
  286. return res & 0xffff;
  287. }
  288. /* same as above, but converts resulting value to cpu byte order */
  289. static int asix_mdio_read_le(struct net_device *netdev, int phy_id, int loc)
  290. {
  291. return le16_to_cpu(asix_mdio_read(netdev,phy_id, loc));
  292. }
  293. static void
  294. asix_mdio_write(struct net_device *netdev, int phy_id, int loc, int val)
  295. {
  296. struct usbnet *dev = netdev_priv(netdev);
  297. u16 res = val;
  298. asix_set_sw_mii(dev);
  299. asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id,
  300. (__u16)loc, 2, (u16 *)&res);
  301. asix_set_hw_mii(dev);
  302. }
  303. /* same as above, but converts new value to le16 byte order before writing */
  304. static void
  305. asix_mdio_write_le(struct net_device *netdev, int phy_id, int loc, int val)
  306. {
  307. asix_mdio_write( netdev, phy_id, loc, cpu_to_le16(val) );
  308. }
  309. static int ax88172_link_reset(struct usbnet *dev)
  310. {
  311. u16 lpa;
  312. u16 adv;
  313. u16 res;
  314. u8 mode;
  315. mode = AX_MEDIUM_TX_ABORT_ALLOW | AX_MEDIUM_FLOW_CONTROL_EN;
  316. lpa = asix_mdio_read_le(dev->net, dev->mii.phy_id, MII_LPA);
  317. adv = asix_mdio_read_le(dev->net, dev->mii.phy_id, MII_ADVERTISE);
  318. res = mii_nway_result(lpa|adv);
  319. if (res & LPA_DUPLEX)
  320. mode |= AX_MEDIUM_FULL_DUPLEX;
  321. asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode, 0, 0, NULL);
  322. return 0;
  323. }
  324. static void
  325. asix_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo)
  326. {
  327. struct usbnet *dev = netdev_priv(net);
  328. u8 opt;
  329. if (asix_read_cmd(dev, AX_CMD_READ_MONITOR_MODE, 0, 0, 1, &opt) < 0) {
  330. wolinfo->supported = 0;
  331. wolinfo->wolopts = 0;
  332. return;
  333. }
  334. wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
  335. wolinfo->wolopts = 0;
  336. if (opt & AX_MONITOR_MODE) {
  337. if (opt & AX_MONITOR_LINK)
  338. wolinfo->wolopts |= WAKE_PHY;
  339. if (opt & AX_MONITOR_MAGIC)
  340. wolinfo->wolopts |= WAKE_MAGIC;
  341. }
  342. }
  343. static int
  344. asix_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo)
  345. {
  346. struct usbnet *dev = netdev_priv(net);
  347. u8 opt = 0;
  348. u8 buf[1];
  349. if (wolinfo->wolopts & WAKE_PHY)
  350. opt |= AX_MONITOR_LINK;
  351. if (wolinfo->wolopts & WAKE_MAGIC)
  352. opt |= AX_MONITOR_MAGIC;
  353. if (opt != 0)
  354. opt |= AX_MONITOR_MODE;
  355. if (asix_write_cmd(dev, AX_CMD_WRITE_MONITOR_MODE,
  356. opt, 0, 0, &buf) < 0)
  357. return -EINVAL;
  358. return 0;
  359. }
  360. static int asix_get_eeprom_len(struct net_device *net)
  361. {
  362. return AX_EEPROM_LEN;
  363. }
  364. static int asix_get_eeprom(struct net_device *net,
  365. struct ethtool_eeprom *eeprom, u8 *data)
  366. {
  367. struct usbnet *dev = netdev_priv(net);
  368. u16 *ebuf = (u16 *)data;
  369. int i;
  370. /* Crude hack to ensure that we don't overwrite memory
  371. * if an odd length is supplied
  372. */
  373. if (eeprom->len % 2)
  374. return -EINVAL;
  375. eeprom->magic = AX_EEPROM_MAGIC;
  376. /* ax8817x returns 2 bytes from eeprom on read */
  377. for (i=0; i < eeprom->len / 2; i++) {
  378. if (asix_read_cmd(dev, AX_CMD_READ_EEPROM,
  379. eeprom->offset + i, 0, 2, &ebuf[i]) < 0)
  380. return -EINVAL;
  381. }
  382. return 0;
  383. }
  384. static void asix_get_drvinfo (struct net_device *net,
  385. struct ethtool_drvinfo *info)
  386. {
  387. /* Inherit standard device info */
  388. usbnet_get_drvinfo(net, info);
  389. info->eedump_len = 0x3e;
  390. }
  391. static int asix_get_settings(struct net_device *net, struct ethtool_cmd *cmd)
  392. {
  393. struct usbnet *dev = netdev_priv(net);
  394. return mii_ethtool_gset(&dev->mii,cmd);
  395. }
  396. static int asix_set_settings(struct net_device *net, struct ethtool_cmd *cmd)
  397. {
  398. struct usbnet *dev = netdev_priv(net);
  399. return mii_ethtool_sset(&dev->mii,cmd);
  400. }
  401. /* We need to override some ethtool_ops so we require our
  402. own structure so we don't interfere with other usbnet
  403. devices that may be connected at the same time. */
  404. static struct ethtool_ops ax88172_ethtool_ops = {
  405. .get_drvinfo = asix_get_drvinfo,
  406. .get_link = ethtool_op_get_link,
  407. .get_msglevel = usbnet_get_msglevel,
  408. .set_msglevel = usbnet_set_msglevel,
  409. .get_wol = asix_get_wol,
  410. .set_wol = asix_set_wol,
  411. .get_eeprom_len = asix_get_eeprom_len,
  412. .get_eeprom = asix_get_eeprom,
  413. .get_settings = asix_get_settings,
  414. .set_settings = asix_set_settings,
  415. };
  416. static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
  417. {
  418. struct usbnet *dev = netdev_priv(net);
  419. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  420. }
  421. static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
  422. {
  423. int ret = 0;
  424. void *buf;
  425. int i;
  426. unsigned long gpio_bits = dev->driver_info->data;
  427. usbnet_get_endpoints(dev,intf);
  428. buf = kmalloc(ETH_ALEN, GFP_KERNEL);
  429. if(!buf) {
  430. ret = -ENOMEM;
  431. goto out1;
  432. }
  433. /* Toggle the GPIOs in a manufacturer/model specific way */
  434. for (i = 2; i >= 0; i--) {
  435. if ((ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
  436. (gpio_bits >> (i * 8)) & 0xff, 0, 0,
  437. buf)) < 0)
  438. goto out2;
  439. msleep(5);
  440. }
  441. if ((ret = asix_write_rx_ctl(dev,0x80)) < 0)
  442. goto out2;
  443. /* Get the MAC address */
  444. memset(buf, 0, ETH_ALEN);
  445. if ((ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
  446. 0, 0, 6, buf)) < 0) {
  447. dbg("read AX_CMD_READ_NODE_ID failed: %d", ret);
  448. goto out2;
  449. }
  450. memcpy(dev->net->dev_addr, buf, ETH_ALEN);
  451. /* Initialize MII structure */
  452. dev->mii.dev = dev->net;
  453. dev->mii.mdio_read = asix_mdio_read;
  454. dev->mii.mdio_write = asix_mdio_write;
  455. dev->mii.phy_id_mask = 0x3f;
  456. dev->mii.reg_num_mask = 0x1f;
  457. dev->mii.phy_id = asix_get_phyid(dev);
  458. dev->net->do_ioctl = asix_ioctl;
  459. dev->net->set_multicast_list = asix_set_multicast;
  460. dev->net->ethtool_ops = &ax88172_ethtool_ops;
  461. asix_mdio_write_le(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  462. asix_mdio_write_le(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  463. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  464. mii_nway_restart(&dev->mii);
  465. return 0;
  466. out2:
  467. kfree(buf);
  468. out1:
  469. return ret;
  470. }
  471. static struct ethtool_ops ax88772_ethtool_ops = {
  472. .get_drvinfo = asix_get_drvinfo,
  473. .get_link = ethtool_op_get_link,
  474. .get_msglevel = usbnet_get_msglevel,
  475. .set_msglevel = usbnet_set_msglevel,
  476. .get_wol = asix_get_wol,
  477. .set_wol = asix_set_wol,
  478. .get_eeprom_len = asix_get_eeprom_len,
  479. .get_eeprom = asix_get_eeprom,
  480. .get_settings = asix_get_settings,
  481. .set_settings = asix_set_settings,
  482. };
  483. static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
  484. {
  485. int ret;
  486. void *buf;
  487. usbnet_get_endpoints(dev,intf);
  488. buf = kmalloc(6, GFP_KERNEL);
  489. if(!buf) {
  490. dbg ("Cannot allocate memory for buffer");
  491. ret = -ENOMEM;
  492. goto out1;
  493. }
  494. if ((ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
  495. 0x00B0, 0, 0, buf)) < 0)
  496. goto out2;
  497. msleep(5);
  498. if ((ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT,
  499. 0x0001, 0, 0, buf)) < 0) {
  500. dbg("Select PHY #1 failed: %d", ret);
  501. goto out2;
  502. }
  503. if ((ret = asix_sw_reset(dev, AX_SWRESET_IPPD)) < 0)
  504. goto out2;
  505. msleep(150);
  506. if ((ret = asix_sw_reset(dev, AX_SWRESET_CLEAR)) < 0)
  507. goto out2;
  508. msleep(150);
  509. if ((ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL)) < 0)
  510. goto out2;
  511. msleep(150);
  512. if ((ret = asix_write_rx_ctl(dev, 0x00)) < 0)
  513. goto out2;
  514. /* Get the MAC address */
  515. memset(buf, 0, ETH_ALEN);
  516. if ((ret = asix_read_cmd(dev, AX88772_CMD_READ_NODE_ID,
  517. 0, 0, ETH_ALEN, buf)) < 0) {
  518. dbg("Failed to read MAC address: %d", ret);
  519. goto out2;
  520. }
  521. memcpy(dev->net->dev_addr, buf, ETH_ALEN);
  522. if ((ret = asix_set_sw_mii(dev)) < 0)
  523. goto out2;
  524. if (((ret = asix_read_cmd(dev, AX_CMD_READ_MII_REG,
  525. 0x0010, 2, 2, buf)) < 0)
  526. || (*((u16 *)buf) != 0x003b)) {
  527. dbg("Read PHY register 2 must be 0x3b00: %d", ret);
  528. goto out2;
  529. }
  530. /* Initialize MII structure */
  531. dev->mii.dev = dev->net;
  532. dev->mii.mdio_read = asix_mdio_read;
  533. dev->mii.mdio_write = asix_mdio_write;
  534. dev->mii.phy_id_mask = 0xff;
  535. dev->mii.reg_num_mask = 0xff;
  536. dev->net->do_ioctl = asix_ioctl;
  537. dev->mii.phy_id = asix_get_phyid(dev);
  538. if ((ret = asix_sw_reset(dev, AX_SWRESET_PRL)) < 0)
  539. goto out2;
  540. msleep(150);
  541. if ((ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL)) < 0)
  542. goto out2;
  543. msleep(150);
  544. dev->net->set_multicast_list = asix_set_multicast;
  545. dev->net->ethtool_ops = &ax88772_ethtool_ops;
  546. asix_mdio_write_le(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  547. asix_mdio_write_le(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  548. ADVERTISE_ALL | ADVERTISE_CSMA);
  549. mii_nway_restart(&dev->mii);
  550. if ((ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE,
  551. AX88772_MEDIUM_DEFAULT, 0, 0, buf)) < 0) {
  552. dbg("Write medium mode register: %d", ret);
  553. goto out2;
  554. }
  555. if ((ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
  556. AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
  557. AX88772_IPG2_DEFAULT, 0, buf)) < 0) {
  558. dbg("Write IPG,IPG1,IPG2 failed: %d", ret);
  559. goto out2;
  560. }
  561. if ((ret = asix_set_hw_mii(dev)) < 0)
  562. goto out2;
  563. /* Set RX_CTL to default values with 2k buffer, and enable cactus */
  564. if ((ret = asix_write_rx_ctl(dev, 0x0088)) < 0)
  565. goto out2;
  566. kfree(buf);
  567. /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
  568. if (dev->driver_info->flags & FLAG_FRAMING_AX) {
  569. /* hard_mtu is still the default - the device does not support
  570. jumbo eth frames */
  571. dev->rx_urb_size = 2048;
  572. }
  573. return 0;
  574. out2:
  575. kfree(buf);
  576. out1:
  577. return ret;
  578. }
  579. static int ax88772_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  580. {
  581. u8 *head;
  582. u32 header;
  583. char *packet;
  584. struct sk_buff *ax_skb;
  585. u16 size;
  586. head = (u8 *) skb->data;
  587. memcpy(&header, head, sizeof(header));
  588. le32_to_cpus(&header);
  589. packet = head + sizeof(header);
  590. skb_pull(skb, 4);
  591. while (skb->len > 0) {
  592. if ((short)(header & 0x0000ffff) !=
  593. ~((short)((header & 0xffff0000) >> 16))) {
  594. devdbg(dev,"header length data is error");
  595. }
  596. /* get the packet length */
  597. size = (u16) (header & 0x0000ffff);
  598. if ((skb->len) - ((size + 1) & 0xfffe) == 0)
  599. return 2;
  600. if (size > ETH_FRAME_LEN) {
  601. devdbg(dev,"invalid rx length %d", size);
  602. return 0;
  603. }
  604. ax_skb = skb_clone(skb, GFP_ATOMIC);
  605. if (ax_skb) {
  606. ax_skb->len = size;
  607. ax_skb->data = packet;
  608. ax_skb->tail = packet + size;
  609. usbnet_skb_return(dev, ax_skb);
  610. } else {
  611. return 0;
  612. }
  613. skb_pull(skb, (size + 1) & 0xfffe);
  614. if (skb->len == 0)
  615. break;
  616. head = (u8 *) skb->data;
  617. memcpy(&header, head, sizeof(header));
  618. le32_to_cpus(&header);
  619. packet = head + sizeof(header);
  620. skb_pull(skb, 4);
  621. }
  622. if (skb->len < 0) {
  623. devdbg(dev,"invalid rx length %d", skb->len);
  624. return 0;
  625. }
  626. return 1;
  627. }
  628. static struct sk_buff *ax88772_tx_fixup(struct usbnet *dev, struct sk_buff *skb,
  629. gfp_t flags)
  630. {
  631. int padlen;
  632. int headroom = skb_headroom(skb);
  633. int tailroom = skb_tailroom(skb);
  634. u32 packet_len;
  635. u32 padbytes = 0xffff0000;
  636. padlen = ((skb->len + 4) % 512) ? 0 : 4;
  637. if ((!skb_cloned(skb))
  638. && ((headroom + tailroom) >= (4 + padlen))) {
  639. if ((headroom < 4) || (tailroom < padlen)) {
  640. skb->data = memmove(skb->head + 4, skb->data, skb->len);
  641. skb->tail = skb->data + skb->len;
  642. }
  643. } else {
  644. struct sk_buff *skb2;
  645. skb2 = skb_copy_expand(skb, 4, padlen, flags);
  646. dev_kfree_skb_any(skb);
  647. skb = skb2;
  648. if (!skb)
  649. return NULL;
  650. }
  651. skb_push(skb, 4);
  652. packet_len = (((skb->len - 4) ^ 0x0000ffff) << 16) + (skb->len - 4);
  653. memcpy(skb->data, &packet_len, sizeof(packet_len));
  654. if ((skb->len % 512) == 0) {
  655. memcpy( skb->tail, &padbytes, sizeof(padbytes));
  656. skb_put(skb, sizeof(padbytes));
  657. }
  658. return skb;
  659. }
  660. static int ax88772_link_reset(struct usbnet *dev)
  661. {
  662. u16 lpa;
  663. u16 adv;
  664. u16 res;
  665. u16 mode;
  666. mode = AX88772_MEDIUM_DEFAULT;
  667. lpa = asix_mdio_read_le(dev->net, dev->mii.phy_id, MII_LPA);
  668. adv = asix_mdio_read_le(dev->net, dev->mii.phy_id, MII_ADVERTISE);
  669. res = mii_nway_result(lpa|adv);
  670. if ((res & LPA_DUPLEX) == 0)
  671. mode &= ~AX88772_MEDIUM_FULL_DUPLEX;
  672. if ((res & LPA_100) == 0)
  673. mode &= ~AX88772_MEDIUM_100MB;
  674. asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode, 0, 0, NULL);
  675. return 0;
  676. }
  677. static const struct driver_info ax8817x_info = {
  678. .description = "ASIX AX8817x USB 2.0 Ethernet",
  679. .bind = ax88172_bind,
  680. .status = asix_status,
  681. .link_reset = ax88172_link_reset,
  682. .reset = ax88172_link_reset,
  683. .flags = FLAG_ETHER,
  684. .data = 0x00130103,
  685. };
  686. static const struct driver_info dlink_dub_e100_info = {
  687. .description = "DLink DUB-E100 USB Ethernet",
  688. .bind = ax88172_bind,
  689. .status = asix_status,
  690. .link_reset = ax88172_link_reset,
  691. .reset = ax88172_link_reset,
  692. .flags = FLAG_ETHER,
  693. .data = 0x009f9d9f,
  694. };
  695. static const struct driver_info netgear_fa120_info = {
  696. .description = "Netgear FA-120 USB Ethernet",
  697. .bind = ax88172_bind,
  698. .status = asix_status,
  699. .link_reset = ax88172_link_reset,
  700. .reset = ax88172_link_reset,
  701. .flags = FLAG_ETHER,
  702. .data = 0x00130103,
  703. };
  704. static const struct driver_info hawking_uf200_info = {
  705. .description = "Hawking UF200 USB Ethernet",
  706. .bind = ax88172_bind,
  707. .status = asix_status,
  708. .link_reset = ax88172_link_reset,
  709. .reset = ax88172_link_reset,
  710. .flags = FLAG_ETHER,
  711. .data = 0x001f1d1f,
  712. };
  713. static const struct driver_info ax88772_info = {
  714. .description = "ASIX AX88772 USB 2.0 Ethernet",
  715. .bind = ax88772_bind,
  716. .status = asix_status,
  717. .link_reset = ax88772_link_reset,
  718. .reset = ax88772_link_reset,
  719. .flags = FLAG_ETHER | FLAG_FRAMING_AX,
  720. .rx_fixup = ax88772_rx_fixup,
  721. .tx_fixup = ax88772_tx_fixup,
  722. };
  723. static const struct usb_device_id products [] = {
  724. {
  725. // Linksys USB200M
  726. USB_DEVICE (0x077b, 0x2226),
  727. .driver_info = (unsigned long) &ax8817x_info,
  728. }, {
  729. // Netgear FA120
  730. USB_DEVICE (0x0846, 0x1040),
  731. .driver_info = (unsigned long) &netgear_fa120_info,
  732. }, {
  733. // DLink DUB-E100
  734. USB_DEVICE (0x2001, 0x1a00),
  735. .driver_info = (unsigned long) &dlink_dub_e100_info,
  736. }, {
  737. // Intellinet, ST Lab USB Ethernet
  738. USB_DEVICE (0x0b95, 0x1720),
  739. .driver_info = (unsigned long) &ax8817x_info,
  740. }, {
  741. // Hawking UF200, TrendNet TU2-ET100
  742. USB_DEVICE (0x07b8, 0x420a),
  743. .driver_info = (unsigned long) &hawking_uf200_info,
  744. }, {
  745. // Billionton Systems, USB2AR
  746. USB_DEVICE (0x08dd, 0x90ff),
  747. .driver_info = (unsigned long) &ax8817x_info,
  748. }, {
  749. // ATEN UC210T
  750. USB_DEVICE (0x0557, 0x2009),
  751. .driver_info = (unsigned long) &ax8817x_info,
  752. }, {
  753. // Buffalo LUA-U2-KTX
  754. USB_DEVICE (0x0411, 0x003d),
  755. .driver_info = (unsigned long) &ax8817x_info,
  756. }, {
  757. // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
  758. USB_DEVICE (0x6189, 0x182d),
  759. .driver_info = (unsigned long) &ax8817x_info,
  760. }, {
  761. // corega FEther USB2-TX
  762. USB_DEVICE (0x07aa, 0x0017),
  763. .driver_info = (unsigned long) &ax8817x_info,
  764. }, {
  765. // Surecom EP-1427X-2
  766. USB_DEVICE (0x1189, 0x0893),
  767. .driver_info = (unsigned long) &ax8817x_info,
  768. }, {
  769. // goodway corp usb gwusb2e
  770. USB_DEVICE (0x1631, 0x6200),
  771. .driver_info = (unsigned long) &ax8817x_info,
  772. }, {
  773. // ASIX AX88772 10/100
  774. USB_DEVICE (0x0b95, 0x7720),
  775. .driver_info = (unsigned long) &ax88772_info,
  776. }, {
  777. // ASIX AX88178 10/100/1000
  778. USB_DEVICE (0x0b95, 0x1780),
  779. .driver_info = (unsigned long) &ax88772_info,
  780. }, {
  781. // Linksys USB200M Rev 2
  782. USB_DEVICE (0x13b1, 0x0018),
  783. .driver_info = (unsigned long) &ax88772_info,
  784. }, {
  785. // 0Q0 cable ethernet
  786. USB_DEVICE (0x1557, 0x7720),
  787. .driver_info = (unsigned long) &ax88772_info,
  788. },
  789. { }, // END
  790. };
  791. MODULE_DEVICE_TABLE(usb, products);
  792. static struct usb_driver asix_driver = {
  793. .name = "asix",
  794. .id_table = products,
  795. .probe = usbnet_probe,
  796. .suspend = usbnet_suspend,
  797. .resume = usbnet_resume,
  798. .disconnect = usbnet_disconnect,
  799. };
  800. static int __init asix_init(void)
  801. {
  802. return usb_register(&asix_driver);
  803. }
  804. module_init(asix_init);
  805. static void __exit asix_exit(void)
  806. {
  807. usb_deregister(&asix_driver);
  808. }
  809. module_exit(asix_exit);
  810. MODULE_AUTHOR("David Hollis");
  811. MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
  812. MODULE_LICENSE("GPL");