ohci-hcd.c 26 KB

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  1. /*
  2. * OHCI HCD (Host Controller Driver) for USB.
  3. *
  4. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  5. * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
  6. *
  7. * [ Initialisation is based on Linus' ]
  8. * [ uhci code and gregs ohci fragments ]
  9. * [ (C) Copyright 1999 Linus Torvalds ]
  10. * [ (C) Copyright 1999 Gregory P. Smith]
  11. *
  12. *
  13. * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
  14. * interfaces (though some non-x86 Intel chips use it). It supports
  15. * smarter hardware than UHCI. A download link for the spec available
  16. * through the http://www.usb.org website.
  17. *
  18. * History:
  19. *
  20. * 2004/03/24 LH7A404 support (Durgesh Pattamatta & Marc Singer)
  21. * 2004/02/04 use generic dma_* functions instead of pci_* (dsaxena@plexity.net)
  22. * 2003/02/24 show registers in sysfs (Kevin Brosius)
  23. *
  24. * 2002/09/03 get rid of ed hashtables, rework periodic scheduling and
  25. * bandwidth accounting; if debugging, show schedules in driverfs
  26. * 2002/07/19 fixes to management of ED and schedule state.
  27. * 2002/06/09 SA-1111 support (Christopher Hoover)
  28. * 2002/06/01 remember frame when HC won't see EDs any more; use that info
  29. * to fix urb unlink races caused by interrupt latency assumptions;
  30. * minor ED field and function naming updates
  31. * 2002/01/18 package as a patch for 2.5.3; this should match the
  32. * 2.4.17 kernel modulo some bugs being fixed.
  33. *
  34. * 2001/10/18 merge pmac cleanup (Benjamin Herrenschmidt) and bugfixes
  35. * from post-2.4.5 patches.
  36. * 2001/09/20 URB_ZERO_PACKET support; hcca_dma portability, OPTi warning
  37. * 2001/09/07 match PCI PM changes, errnos from Linus' tree
  38. * 2001/05/05 fork 2.4.5 version into "hcd" framework, cleanup, simplify;
  39. * pbook pci quirks gone (please fix pbook pci sw!) (db)
  40. *
  41. * 2001/04/08 Identify version on module load (gb)
  42. * 2001/03/24 td/ed hashing to remove bus_to_virt (Steve Longerbeam);
  43. pci_map_single (db)
  44. * 2001/03/21 td and dev/ed allocation uses new pci_pool API (db)
  45. * 2001/03/07 hcca allocation uses pci_alloc_consistent (Steve Longerbeam)
  46. *
  47. * 2000/09/26 fixed races in removing the private portion of the urb
  48. * 2000/09/07 disable bulk and control lists when unlinking the last
  49. * endpoint descriptor in order to avoid unrecoverable errors on
  50. * the Lucent chips. (rwc@sgi)
  51. * 2000/08/29 use bandwidth claiming hooks (thanks Randy!), fix some
  52. * urb unlink probs, indentation fixes
  53. * 2000/08/11 various oops fixes mostly affecting iso and cleanup from
  54. * device unplugs.
  55. * 2000/06/28 use PCI hotplug framework, for better power management
  56. * and for Cardbus support (David Brownell)
  57. * 2000/earlier: fixes for NEC/Lucent chips; suspend/resume handling
  58. * when the controller loses power; handle UE; cleanup; ...
  59. *
  60. * v5.2 1999/12/07 URB 3rd preview,
  61. * v5.1 1999/11/30 URB 2nd preview, cpia, (usb-scsi)
  62. * v5.0 1999/11/22 URB Technical preview, Paul Mackerras powerbook susp/resume
  63. * i386: HUB, Keyboard, Mouse, Printer
  64. *
  65. * v4.3 1999/10/27 multiple HCs, bulk_request
  66. * v4.2 1999/09/05 ISO API alpha, new dev alloc, neg Error-codes
  67. * v4.1 1999/08/27 Randy Dunlap's - ISO API first impl.
  68. * v4.0 1999/08/18
  69. * v3.0 1999/06/25
  70. * v2.1 1999/05/09 code clean up
  71. * v2.0 1999/05/04
  72. * v1.0 1999/04/27 initial release
  73. *
  74. * This file is licenced under the GPL.
  75. */
  76. #include <linux/module.h>
  77. #include <linux/moduleparam.h>
  78. #include <linux/pci.h>
  79. #include <linux/kernel.h>
  80. #include <linux/delay.h>
  81. #include <linux/ioport.h>
  82. #include <linux/sched.h>
  83. #include <linux/slab.h>
  84. #include <linux/smp_lock.h>
  85. #include <linux/errno.h>
  86. #include <linux/init.h>
  87. #include <linux/timer.h>
  88. #include <linux/list.h>
  89. #include <linux/usb.h>
  90. #include <linux/usb_otg.h>
  91. #include <linux/dma-mapping.h>
  92. #include <linux/dmapool.h>
  93. #include <linux/reboot.h>
  94. #include <asm/io.h>
  95. #include <asm/irq.h>
  96. #include <asm/system.h>
  97. #include <asm/unaligned.h>
  98. #include <asm/byteorder.h>
  99. #include "../core/hcd.h"
  100. #define DRIVER_VERSION "2005 April 22"
  101. #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
  102. #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
  103. /*-------------------------------------------------------------------------*/
  104. #undef OHCI_VERBOSE_DEBUG /* not always helpful */
  105. /* For initializing controller (mask in an HCFS mode too) */
  106. #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
  107. #define OHCI_INTR_INIT \
  108. (OHCI_INTR_MIE | OHCI_INTR_UE | OHCI_INTR_RD | OHCI_INTR_WDH)
  109. #ifdef __hppa__
  110. /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
  111. #define IR_DISABLE
  112. #endif
  113. #ifdef CONFIG_ARCH_OMAP
  114. /* OMAP doesn't support IR (no SMM; not needed) */
  115. #define IR_DISABLE
  116. #endif
  117. /*-------------------------------------------------------------------------*/
  118. static const char hcd_name [] = "ohci_hcd";
  119. #include "ohci.h"
  120. static void ohci_dump (struct ohci_hcd *ohci, int verbose);
  121. static int ohci_init (struct ohci_hcd *ohci);
  122. static void ohci_stop (struct usb_hcd *hcd);
  123. static int ohci_reboot (struct notifier_block *, unsigned long , void *);
  124. #include "ohci-hub.c"
  125. #include "ohci-dbg.c"
  126. #include "ohci-mem.c"
  127. #include "ohci-q.c"
  128. /*
  129. * On architectures with edge-triggered interrupts we must never return
  130. * IRQ_NONE.
  131. */
  132. #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
  133. #define IRQ_NOTMINE IRQ_HANDLED
  134. #else
  135. #define IRQ_NOTMINE IRQ_NONE
  136. #endif
  137. /* Some boards misreport power switching/overcurrent */
  138. static int distrust_firmware = 1;
  139. module_param (distrust_firmware, bool, 0);
  140. MODULE_PARM_DESC (distrust_firmware,
  141. "true to distrust firmware power/overcurrent setup");
  142. /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
  143. static int no_handshake = 0;
  144. module_param (no_handshake, bool, 0);
  145. MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
  146. /*-------------------------------------------------------------------------*/
  147. /*
  148. * queue up an urb for anything except the root hub
  149. */
  150. static int ohci_urb_enqueue (
  151. struct usb_hcd *hcd,
  152. struct usb_host_endpoint *ep,
  153. struct urb *urb,
  154. gfp_t mem_flags
  155. ) {
  156. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  157. struct ed *ed;
  158. urb_priv_t *urb_priv;
  159. unsigned int pipe = urb->pipe;
  160. int i, size = 0;
  161. unsigned long flags;
  162. int retval = 0;
  163. #ifdef OHCI_VERBOSE_DEBUG
  164. urb_print (urb, "SUB", usb_pipein (pipe));
  165. #endif
  166. /* every endpoint has a ed, locate and maybe (re)initialize it */
  167. if (! (ed = ed_get (ohci, ep, urb->dev, pipe, urb->interval)))
  168. return -ENOMEM;
  169. /* for the private part of the URB we need the number of TDs (size) */
  170. switch (ed->type) {
  171. case PIPE_CONTROL:
  172. /* td_submit_urb() doesn't yet handle these */
  173. if (urb->transfer_buffer_length > 4096)
  174. return -EMSGSIZE;
  175. /* 1 TD for setup, 1 for ACK, plus ... */
  176. size = 2;
  177. /* FALLTHROUGH */
  178. // case PIPE_INTERRUPT:
  179. // case PIPE_BULK:
  180. default:
  181. /* one TD for every 4096 Bytes (can be upto 8K) */
  182. size += urb->transfer_buffer_length / 4096;
  183. /* ... and for any remaining bytes ... */
  184. if ((urb->transfer_buffer_length % 4096) != 0)
  185. size++;
  186. /* ... and maybe a zero length packet to wrap it up */
  187. if (size == 0)
  188. size++;
  189. else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
  190. && (urb->transfer_buffer_length
  191. % usb_maxpacket (urb->dev, pipe,
  192. usb_pipeout (pipe))) == 0)
  193. size++;
  194. break;
  195. case PIPE_ISOCHRONOUS: /* number of packets from URB */
  196. size = urb->number_of_packets;
  197. break;
  198. }
  199. /* allocate the private part of the URB */
  200. urb_priv = kmalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
  201. mem_flags);
  202. if (!urb_priv)
  203. return -ENOMEM;
  204. memset (urb_priv, 0, sizeof (urb_priv_t) + size * sizeof (struct td *));
  205. INIT_LIST_HEAD (&urb_priv->pending);
  206. urb_priv->length = size;
  207. urb_priv->ed = ed;
  208. /* allocate the TDs (deferring hash chain updates) */
  209. for (i = 0; i < size; i++) {
  210. urb_priv->td [i] = td_alloc (ohci, mem_flags);
  211. if (!urb_priv->td [i]) {
  212. urb_priv->length = i;
  213. urb_free_priv (ohci, urb_priv);
  214. return -ENOMEM;
  215. }
  216. }
  217. spin_lock_irqsave (&ohci->lock, flags);
  218. /* don't submit to a dead HC */
  219. if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
  220. retval = -ENODEV;
  221. goto fail;
  222. }
  223. if (!HC_IS_RUNNING(hcd->state)) {
  224. retval = -ENODEV;
  225. goto fail;
  226. }
  227. /* in case of unlink-during-submit */
  228. spin_lock (&urb->lock);
  229. if (urb->status != -EINPROGRESS) {
  230. spin_unlock (&urb->lock);
  231. urb->hcpriv = urb_priv;
  232. finish_urb (ohci, urb, NULL);
  233. retval = 0;
  234. goto fail;
  235. }
  236. /* schedule the ed if needed */
  237. if (ed->state == ED_IDLE) {
  238. retval = ed_schedule (ohci, ed);
  239. if (retval < 0)
  240. goto fail0;
  241. if (ed->type == PIPE_ISOCHRONOUS) {
  242. u16 frame = ohci_frame_no(ohci);
  243. /* delay a few frames before the first TD */
  244. frame += max_t (u16, 8, ed->interval);
  245. frame &= ~(ed->interval - 1);
  246. frame |= ed->branch;
  247. urb->start_frame = frame;
  248. /* yes, only URB_ISO_ASAP is supported, and
  249. * urb->start_frame is never used as input.
  250. */
  251. }
  252. } else if (ed->type == PIPE_ISOCHRONOUS)
  253. urb->start_frame = ed->last_iso + ed->interval;
  254. /* fill the TDs and link them to the ed; and
  255. * enable that part of the schedule, if needed
  256. * and update count of queued periodic urbs
  257. */
  258. urb->hcpriv = urb_priv;
  259. td_submit_urb (ohci, urb);
  260. fail0:
  261. spin_unlock (&urb->lock);
  262. fail:
  263. if (retval)
  264. urb_free_priv (ohci, urb_priv);
  265. spin_unlock_irqrestore (&ohci->lock, flags);
  266. return retval;
  267. }
  268. /*
  269. * decouple the URB from the HC queues (TDs, urb_priv); it's
  270. * already marked using urb->status. reporting is always done
  271. * asynchronously, and we might be dealing with an urb that's
  272. * partially transferred, or an ED with other urbs being unlinked.
  273. */
  274. static int ohci_urb_dequeue (struct usb_hcd *hcd, struct urb *urb)
  275. {
  276. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  277. unsigned long flags;
  278. #ifdef OHCI_VERBOSE_DEBUG
  279. urb_print (urb, "UNLINK", 1);
  280. #endif
  281. spin_lock_irqsave (&ohci->lock, flags);
  282. if (HC_IS_RUNNING(hcd->state)) {
  283. urb_priv_t *urb_priv;
  284. /* Unless an IRQ completed the unlink while it was being
  285. * handed to us, flag it for unlink and giveback, and force
  286. * some upcoming INTR_SF to call finish_unlinks()
  287. */
  288. urb_priv = urb->hcpriv;
  289. if (urb_priv) {
  290. if (urb_priv->ed->state == ED_OPER)
  291. start_ed_unlink (ohci, urb_priv->ed);
  292. }
  293. } else {
  294. /*
  295. * with HC dead, we won't respect hc queue pointers
  296. * any more ... just clean up every urb's memory.
  297. */
  298. if (urb->hcpriv)
  299. finish_urb (ohci, urb, NULL);
  300. }
  301. spin_unlock_irqrestore (&ohci->lock, flags);
  302. return 0;
  303. }
  304. /*-------------------------------------------------------------------------*/
  305. /* frees config/altsetting state for endpoints,
  306. * including ED memory, dummy TD, and bulk/intr data toggle
  307. */
  308. static void
  309. ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
  310. {
  311. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  312. unsigned long flags;
  313. struct ed *ed = ep->hcpriv;
  314. unsigned limit = 1000;
  315. /* ASSERT: any requests/urbs are being unlinked */
  316. /* ASSERT: nobody can be submitting urbs for this any more */
  317. if (!ed)
  318. return;
  319. rescan:
  320. spin_lock_irqsave (&ohci->lock, flags);
  321. if (!HC_IS_RUNNING (hcd->state)) {
  322. sanitize:
  323. ed->state = ED_IDLE;
  324. finish_unlinks (ohci, 0, NULL);
  325. }
  326. switch (ed->state) {
  327. case ED_UNLINK: /* wait for hw to finish? */
  328. /* major IRQ delivery trouble loses INTR_SF too... */
  329. if (limit-- == 0) {
  330. ohci_warn (ohci, "IRQ INTR_SF lossage\n");
  331. goto sanitize;
  332. }
  333. spin_unlock_irqrestore (&ohci->lock, flags);
  334. schedule_timeout_uninterruptible(1);
  335. goto rescan;
  336. case ED_IDLE: /* fully unlinked */
  337. if (list_empty (&ed->td_list)) {
  338. td_free (ohci, ed->dummy);
  339. ed_free (ohci, ed);
  340. break;
  341. }
  342. /* else FALL THROUGH */
  343. default:
  344. /* caller was supposed to have unlinked any requests;
  345. * that's not our job. can't recover; must leak ed.
  346. */
  347. ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
  348. ed, ep->desc.bEndpointAddress, ed->state,
  349. list_empty (&ed->td_list) ? "" : " (has tds)");
  350. td_free (ohci, ed->dummy);
  351. break;
  352. }
  353. ep->hcpriv = NULL;
  354. spin_unlock_irqrestore (&ohci->lock, flags);
  355. return;
  356. }
  357. static int ohci_get_frame (struct usb_hcd *hcd)
  358. {
  359. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  360. return ohci_frame_no(ohci);
  361. }
  362. static void ohci_usb_reset (struct ohci_hcd *ohci)
  363. {
  364. ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
  365. ohci->hc_control &= OHCI_CTRL_RWC;
  366. ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  367. }
  368. /* reboot notifier forcibly disables IRQs and DMA, helping kexec and
  369. * other cases where the next software may expect clean state from the
  370. * "firmware". this is bus-neutral, unlike shutdown() methods.
  371. */
  372. static int
  373. ohci_reboot (struct notifier_block *block, unsigned long code, void *null)
  374. {
  375. struct ohci_hcd *ohci;
  376. ohci = container_of (block, struct ohci_hcd, reboot_notifier);
  377. ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
  378. ohci_usb_reset (ohci);
  379. /* flush the writes */
  380. (void) ohci_readl (ohci, &ohci->regs->control);
  381. return 0;
  382. }
  383. /*-------------------------------------------------------------------------*
  384. * HC functions
  385. *-------------------------------------------------------------------------*/
  386. /* init memory, and kick BIOS/SMM off */
  387. static int ohci_init (struct ohci_hcd *ohci)
  388. {
  389. int ret;
  390. struct usb_hcd *hcd = ohci_to_hcd(ohci);
  391. disable (ohci);
  392. ohci->regs = hcd->regs;
  393. ohci->next_statechange = jiffies;
  394. /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
  395. * was never needed for most non-PCI systems ... remove the code?
  396. */
  397. #ifndef IR_DISABLE
  398. /* SMM owns the HC? not for long! */
  399. if (!no_handshake && ohci_readl (ohci,
  400. &ohci->regs->control) & OHCI_CTRL_IR) {
  401. u32 temp;
  402. ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
  403. /* this timeout is arbitrary. we make it long, so systems
  404. * depending on usb keyboards may be usable even if the
  405. * BIOS/SMM code seems pretty broken.
  406. */
  407. temp = 500; /* arbitrary: five seconds */
  408. ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
  409. ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
  410. while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
  411. msleep (10);
  412. if (--temp == 0) {
  413. ohci_err (ohci, "USB HC takeover failed!"
  414. " (BIOS/SMM bug)\n");
  415. return -EBUSY;
  416. }
  417. }
  418. ohci_usb_reset (ohci);
  419. }
  420. #endif
  421. /* Disable HC interrupts */
  422. ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
  423. /* flush the writes, and save key bits like RWC */
  424. if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
  425. ohci->hc_control |= OHCI_CTRL_RWC;
  426. /* Read the number of ports unless overridden */
  427. if (ohci->num_ports == 0)
  428. ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
  429. if (ohci->hcca)
  430. return 0;
  431. ohci->hcca = dma_alloc_coherent (hcd->self.controller,
  432. sizeof *ohci->hcca, &ohci->hcca_dma, 0);
  433. if (!ohci->hcca)
  434. return -ENOMEM;
  435. if ((ret = ohci_mem_init (ohci)) < 0)
  436. ohci_stop (hcd);
  437. else {
  438. register_reboot_notifier (&ohci->reboot_notifier);
  439. create_debug_files (ohci);
  440. }
  441. return ret;
  442. }
  443. /*-------------------------------------------------------------------------*/
  444. /* Start an OHCI controller, set the BUS operational
  445. * resets USB and controller
  446. * enable interrupts
  447. */
  448. static int ohci_run (struct ohci_hcd *ohci)
  449. {
  450. u32 mask, temp;
  451. int first = ohci->fminterval == 0;
  452. struct usb_hcd *hcd = ohci_to_hcd(ohci);
  453. disable (ohci);
  454. /* boot firmware should have set this up (5.1.1.3.1) */
  455. if (first) {
  456. temp = ohci_readl (ohci, &ohci->regs->fminterval);
  457. ohci->fminterval = temp & 0x3fff;
  458. if (ohci->fminterval != FI)
  459. ohci_dbg (ohci, "fminterval delta %d\n",
  460. ohci->fminterval - FI);
  461. ohci->fminterval |= FSMP (ohci->fminterval) << 16;
  462. /* also: power/overcurrent flags in roothub.a */
  463. }
  464. /* Reset USB nearly "by the book". RemoteWakeupConnected was
  465. * saved if boot firmware (BIOS/SMM/...) told us it's connected,
  466. * or if bus glue did the same (e.g. for PCI add-in cards with
  467. * PCI PM support).
  468. */
  469. ohci_dbg (ohci, "resetting from state '%s', control = 0x%x\n",
  470. hcfs2string (ohci->hc_control & OHCI_CTRL_HCFS),
  471. ohci_readl (ohci, &ohci->regs->control));
  472. if ((ohci->hc_control & OHCI_CTRL_RWC) != 0
  473. && !device_may_wakeup(hcd->self.controller))
  474. device_init_wakeup(hcd->self.controller, 1);
  475. switch (ohci->hc_control & OHCI_CTRL_HCFS) {
  476. case OHCI_USB_OPER:
  477. temp = 0;
  478. break;
  479. case OHCI_USB_SUSPEND:
  480. case OHCI_USB_RESUME:
  481. ohci->hc_control &= OHCI_CTRL_RWC;
  482. ohci->hc_control |= OHCI_USB_RESUME;
  483. temp = 10 /* msec wait */;
  484. break;
  485. // case OHCI_USB_RESET:
  486. default:
  487. ohci->hc_control &= OHCI_CTRL_RWC;
  488. ohci->hc_control |= OHCI_USB_RESET;
  489. temp = 50 /* msec wait */;
  490. break;
  491. }
  492. ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  493. // flush the writes
  494. (void) ohci_readl (ohci, &ohci->regs->control);
  495. msleep(temp);
  496. temp = roothub_a (ohci);
  497. if (!(temp & RH_A_NPS)) {
  498. /* power down each port */
  499. for (temp = 0; temp < ohci->num_ports; temp++)
  500. ohci_writel (ohci, RH_PS_LSDA,
  501. &ohci->regs->roothub.portstatus [temp]);
  502. }
  503. // flush those writes
  504. (void) ohci_readl (ohci, &ohci->regs->control);
  505. memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
  506. /* 2msec timelimit here means no irqs/preempt */
  507. spin_lock_irq (&ohci->lock);
  508. retry:
  509. /* HC Reset requires max 10 us delay */
  510. ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
  511. temp = 30; /* ... allow extra time */
  512. while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
  513. if (--temp == 0) {
  514. spin_unlock_irq (&ohci->lock);
  515. ohci_err (ohci, "USB HC reset timed out!\n");
  516. return -1;
  517. }
  518. udelay (1);
  519. }
  520. /* now we're in the SUSPEND state ... must go OPERATIONAL
  521. * within 2msec else HC enters RESUME
  522. *
  523. * ... but some hardware won't init fmInterval "by the book"
  524. * (SiS, OPTi ...), so reset again instead. SiS doesn't need
  525. * this if we write fmInterval after we're OPERATIONAL.
  526. * Unclear about ALi, ServerWorks, and others ... this could
  527. * easily be a longstanding bug in chip init on Linux.
  528. */
  529. if (ohci->flags & OHCI_QUIRK_INITRESET) {
  530. ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  531. // flush those writes
  532. (void) ohci_readl (ohci, &ohci->regs->control);
  533. }
  534. /* Tell the controller where the control and bulk lists are
  535. * The lists are empty now. */
  536. ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
  537. ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
  538. /* a reset clears this */
  539. ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
  540. periodic_reinit (ohci);
  541. /* some OHCI implementations are finicky about how they init.
  542. * bogus values here mean not even enumeration could work.
  543. */
  544. if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
  545. || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
  546. if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
  547. ohci->flags |= OHCI_QUIRK_INITRESET;
  548. ohci_dbg (ohci, "enabling initreset quirk\n");
  549. goto retry;
  550. }
  551. spin_unlock_irq (&ohci->lock);
  552. ohci_err (ohci, "init err (%08x %04x)\n",
  553. ohci_readl (ohci, &ohci->regs->fminterval),
  554. ohci_readl (ohci, &ohci->regs->periodicstart));
  555. return -EOVERFLOW;
  556. }
  557. /* start controller operations */
  558. ohci->hc_control &= OHCI_CTRL_RWC;
  559. ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
  560. ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  561. hcd->state = HC_STATE_RUNNING;
  562. /* wake on ConnectStatusChange, matching external hubs */
  563. ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
  564. /* Choose the interrupts we care about now, others later on demand */
  565. mask = OHCI_INTR_INIT;
  566. ohci_writel (ohci, mask, &ohci->regs->intrstatus);
  567. ohci_writel (ohci, mask, &ohci->regs->intrenable);
  568. /* handle root hub init quirks ... */
  569. temp = roothub_a (ohci);
  570. temp &= ~(RH_A_PSM | RH_A_OCPM);
  571. if (ohci->flags & OHCI_QUIRK_SUPERIO) {
  572. /* NSC 87560 and maybe others */
  573. temp |= RH_A_NOCP;
  574. temp &= ~(RH_A_POTPGT | RH_A_NPS);
  575. ohci_writel (ohci, temp, &ohci->regs->roothub.a);
  576. } else if ((ohci->flags & OHCI_QUIRK_AMD756) || distrust_firmware) {
  577. /* hub power always on; required for AMD-756 and some
  578. * Mac platforms. ganged overcurrent reporting, if any.
  579. */
  580. temp |= RH_A_NPS;
  581. ohci_writel (ohci, temp, &ohci->regs->roothub.a);
  582. }
  583. ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
  584. ohci_writel (ohci, (temp & RH_A_NPS) ? 0 : RH_B_PPCM,
  585. &ohci->regs->roothub.b);
  586. // flush those writes
  587. (void) ohci_readl (ohci, &ohci->regs->control);
  588. spin_unlock_irq (&ohci->lock);
  589. // POTPGT delay is bits 24-31, in 2 ms units.
  590. mdelay ((temp >> 23) & 0x1fe);
  591. hcd->state = HC_STATE_RUNNING;
  592. ohci_dump (ohci, 1);
  593. return 0;
  594. }
  595. /*-------------------------------------------------------------------------*/
  596. /* an interrupt happens */
  597. static irqreturn_t ohci_irq (struct usb_hcd *hcd, struct pt_regs *ptregs)
  598. {
  599. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  600. struct ohci_regs __iomem *regs = ohci->regs;
  601. int ints;
  602. /* we can eliminate a (slow) ohci_readl()
  603. if _only_ WDH caused this irq */
  604. if ((ohci->hcca->done_head != 0)
  605. && ! (hc32_to_cpup (ohci, &ohci->hcca->done_head)
  606. & 0x01)) {
  607. ints = OHCI_INTR_WDH;
  608. /* cardbus/... hardware gone before remove() */
  609. } else if ((ints = ohci_readl (ohci, &regs->intrstatus)) == ~(u32)0) {
  610. disable (ohci);
  611. ohci_dbg (ohci, "device removed!\n");
  612. return IRQ_HANDLED;
  613. /* interrupt for some other device? */
  614. } else if ((ints &= ohci_readl (ohci, &regs->intrenable)) == 0) {
  615. return IRQ_NOTMINE;
  616. }
  617. if (ints & OHCI_INTR_UE) {
  618. disable (ohci);
  619. ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
  620. // e.g. due to PCI Master/Target Abort
  621. ohci_dump (ohci, 1);
  622. ohci_usb_reset (ohci);
  623. }
  624. if (ints & OHCI_INTR_RD) {
  625. ohci_vdbg (ohci, "resume detect\n");
  626. ohci_writel (ohci, OHCI_INTR_RD, &regs->intrstatus);
  627. if (hcd->state != HC_STATE_QUIESCING)
  628. usb_hcd_resume_root_hub(hcd);
  629. }
  630. if (ints & OHCI_INTR_WDH) {
  631. if (HC_IS_RUNNING(hcd->state))
  632. ohci_writel (ohci, OHCI_INTR_WDH, &regs->intrdisable);
  633. spin_lock (&ohci->lock);
  634. dl_done_list (ohci, ptregs);
  635. spin_unlock (&ohci->lock);
  636. if (HC_IS_RUNNING(hcd->state))
  637. ohci_writel (ohci, OHCI_INTR_WDH, &regs->intrenable);
  638. }
  639. /* could track INTR_SO to reduce available PCI/... bandwidth */
  640. /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
  641. * when there's still unlinking to be done (next frame).
  642. */
  643. spin_lock (&ohci->lock);
  644. if (ohci->ed_rm_list)
  645. finish_unlinks (ohci, ohci_frame_no(ohci), ptregs);
  646. if ((ints & OHCI_INTR_SF) != 0 && !ohci->ed_rm_list
  647. && HC_IS_RUNNING(hcd->state))
  648. ohci_writel (ohci, OHCI_INTR_SF, &regs->intrdisable);
  649. spin_unlock (&ohci->lock);
  650. if (HC_IS_RUNNING(hcd->state)) {
  651. ohci_writel (ohci, ints, &regs->intrstatus);
  652. ohci_writel (ohci, OHCI_INTR_MIE, &regs->intrenable);
  653. // flush those writes
  654. (void) ohci_readl (ohci, &ohci->regs->control);
  655. }
  656. return IRQ_HANDLED;
  657. }
  658. /*-------------------------------------------------------------------------*/
  659. static void ohci_stop (struct usb_hcd *hcd)
  660. {
  661. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  662. ohci_dbg (ohci, "stop %s controller (state 0x%02x)\n",
  663. hcfs2string (ohci->hc_control & OHCI_CTRL_HCFS),
  664. hcd->state);
  665. ohci_dump (ohci, 1);
  666. flush_scheduled_work();
  667. ohci_usb_reset (ohci);
  668. ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
  669. remove_debug_files (ohci);
  670. unregister_reboot_notifier (&ohci->reboot_notifier);
  671. ohci_mem_cleanup (ohci);
  672. if (ohci->hcca) {
  673. dma_free_coherent (hcd->self.controller,
  674. sizeof *ohci->hcca,
  675. ohci->hcca, ohci->hcca_dma);
  676. ohci->hcca = NULL;
  677. ohci->hcca_dma = 0;
  678. }
  679. }
  680. /*-------------------------------------------------------------------------*/
  681. /* must not be called from interrupt context */
  682. #ifdef CONFIG_PM
  683. static int ohci_restart (struct ohci_hcd *ohci)
  684. {
  685. int temp;
  686. int i;
  687. struct urb_priv *priv;
  688. /* mark any devices gone, so they do nothing till khubd disconnects.
  689. * recycle any "live" eds/tds (and urbs) right away.
  690. * later, khubd disconnect processing will recycle the other state,
  691. * (either as disconnect/reconnect, or maybe someday as a reset).
  692. */
  693. spin_lock_irq(&ohci->lock);
  694. disable (ohci);
  695. usb_root_hub_lost_power(ohci_to_hcd(ohci)->self.root_hub);
  696. if (!list_empty (&ohci->pending))
  697. ohci_dbg(ohci, "abort schedule...\n");
  698. list_for_each_entry (priv, &ohci->pending, pending) {
  699. struct urb *urb = priv->td[0]->urb;
  700. struct ed *ed = priv->ed;
  701. switch (ed->state) {
  702. case ED_OPER:
  703. ed->state = ED_UNLINK;
  704. ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
  705. ed_deschedule (ohci, ed);
  706. ed->ed_next = ohci->ed_rm_list;
  707. ed->ed_prev = NULL;
  708. ohci->ed_rm_list = ed;
  709. /* FALLTHROUGH */
  710. case ED_UNLINK:
  711. break;
  712. default:
  713. ohci_dbg(ohci, "bogus ed %p state %d\n",
  714. ed, ed->state);
  715. }
  716. spin_lock (&urb->lock);
  717. urb->status = -ESHUTDOWN;
  718. spin_unlock (&urb->lock);
  719. }
  720. finish_unlinks (ohci, 0, NULL);
  721. spin_unlock_irq(&ohci->lock);
  722. /* paranoia, in case that didn't work: */
  723. /* empty the interrupt branches */
  724. for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
  725. for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
  726. /* no EDs to remove */
  727. ohci->ed_rm_list = NULL;
  728. /* empty control and bulk lists */
  729. ohci->ed_controltail = NULL;
  730. ohci->ed_bulktail = NULL;
  731. if ((temp = ohci_run (ohci)) < 0) {
  732. ohci_err (ohci, "can't restart, %d\n", temp);
  733. return temp;
  734. } else {
  735. /* here we "know" root ports should always stay powered,
  736. * and that if we try to turn them back on the root hub
  737. * will respond to CSC processing.
  738. */
  739. i = ohci->num_ports;
  740. while (i--)
  741. ohci_writel (ohci, RH_PS_PSS,
  742. &ohci->regs->roothub.portstatus [i]);
  743. ohci_dbg (ohci, "restart complete\n");
  744. }
  745. return 0;
  746. }
  747. #endif
  748. /*-------------------------------------------------------------------------*/
  749. #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
  750. MODULE_AUTHOR (DRIVER_AUTHOR);
  751. MODULE_DESCRIPTION (DRIVER_INFO);
  752. MODULE_LICENSE ("GPL");
  753. #ifdef CONFIG_PCI
  754. #include "ohci-pci.c"
  755. #endif
  756. #ifdef CONFIG_SA1111
  757. #include "ohci-sa1111.c"
  758. #endif
  759. #ifdef CONFIG_ARCH_S3C2410
  760. #include "ohci-s3c2410.c"
  761. #endif
  762. #ifdef CONFIG_ARCH_OMAP
  763. #include "ohci-omap.c"
  764. #endif
  765. #ifdef CONFIG_ARCH_LH7A404
  766. #include "ohci-lh7a404.c"
  767. #endif
  768. #ifdef CONFIG_PXA27x
  769. #include "ohci-pxa27x.c"
  770. #endif
  771. #ifdef CONFIG_ARCH_EP93XX
  772. #include "ohci-ep93xx.c"
  773. #endif
  774. #ifdef CONFIG_SOC_AU1X00
  775. #include "ohci-au1xxx.c"
  776. #endif
  777. #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC
  778. #include "ohci-ppc-soc.c"
  779. #endif
  780. #if defined(CONFIG_ARCH_AT91RM9200) || defined(CONFIG_ARCH_AT91SAM9261)
  781. #include "ohci-at91.c"
  782. #endif
  783. #if !(defined(CONFIG_PCI) \
  784. || defined(CONFIG_SA1111) \
  785. || defined(CONFIG_ARCH_S3C2410) \
  786. || defined(CONFIG_ARCH_OMAP) \
  787. || defined (CONFIG_ARCH_LH7A404) \
  788. || defined (CONFIG_PXA27x) \
  789. || defined (CONFIG_ARCH_EP93XX) \
  790. || defined (CONFIG_SOC_AU1X00) \
  791. || defined (CONFIG_USB_OHCI_HCD_PPC_SOC) \
  792. || defined (CONFIG_ARCH_AT91RM9200) \
  793. || defined (CONFIG_ARCH_AT91SAM9261) \
  794. )
  795. #error "missing bus glue for ohci-hcd"
  796. #endif