nmi.c 20 KB

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  1. /*
  2. * linux/arch/x86_64/nmi.c
  3. *
  4. * NMI watchdog support on APIC systems
  5. *
  6. * Started by Ingo Molnar <mingo@redhat.com>
  7. *
  8. * Fixes:
  9. * Mikael Pettersson : AMD K7 support for local APIC NMI watchdog.
  10. * Mikael Pettersson : Power Management for local APIC NMI watchdog.
  11. * Pavel Machek and
  12. * Mikael Pettersson : PM converted to driver model. Disable/enable API.
  13. */
  14. #include <linux/mm.h>
  15. #include <linux/delay.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/module.h>
  18. #include <linux/sysdev.h>
  19. #include <linux/nmi.h>
  20. #include <linux/sysctl.h>
  21. #include <linux/kprobes.h>
  22. #include <asm/smp.h>
  23. #include <asm/nmi.h>
  24. #include <asm/proto.h>
  25. #include <asm/kdebug.h>
  26. #include <asm/mce.h>
  27. /* perfctr_nmi_owner tracks the ownership of the perfctr registers:
  28. * evtsel_nmi_owner tracks the ownership of the event selection
  29. * - different performance counters/ event selection may be reserved for
  30. * different subsystems this reservation system just tries to coordinate
  31. * things a little
  32. */
  33. static DEFINE_PER_CPU(unsigned, perfctr_nmi_owner);
  34. static DEFINE_PER_CPU(unsigned, evntsel_nmi_owner[2]);
  35. /* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
  36. * offset from MSR_P4_BSU_ESCR0. It will be the max for all platforms (for now)
  37. */
  38. #define NMI_MAX_COUNTER_BITS 66
  39. /*
  40. * lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
  41. * - it may be reserved by some other driver, or not
  42. * - when not reserved by some other driver, it may be used for
  43. * the NMI watchdog, or not
  44. *
  45. * This is maintained separately from nmi_active because the NMI
  46. * watchdog may also be driven from the I/O APIC timer.
  47. */
  48. static DEFINE_SPINLOCK(lapic_nmi_owner_lock);
  49. static unsigned int lapic_nmi_owner;
  50. #define LAPIC_NMI_WATCHDOG (1<<0)
  51. #define LAPIC_NMI_RESERVED (1<<1)
  52. /* nmi_active:
  53. * >0: the lapic NMI watchdog is active, but can be disabled
  54. * <0: the lapic NMI watchdog has not been set up, and cannot
  55. * be enabled
  56. * 0: the lapic NMI watchdog is disabled, but can be enabled
  57. */
  58. atomic_t nmi_active = ATOMIC_INIT(0); /* oprofile uses this */
  59. int panic_on_timeout;
  60. unsigned int nmi_watchdog = NMI_DEFAULT;
  61. static unsigned int nmi_hz = HZ;
  62. struct nmi_watchdog_ctlblk {
  63. int enabled;
  64. u64 check_bit;
  65. unsigned int cccr_msr;
  66. unsigned int perfctr_msr; /* the MSR to reset in NMI handler */
  67. unsigned int evntsel_msr; /* the MSR to select the events to handle */
  68. };
  69. static DEFINE_PER_CPU(struct nmi_watchdog_ctlblk, nmi_watchdog_ctlblk);
  70. /* local prototypes */
  71. static void stop_apic_nmi_watchdog(void *unused);
  72. static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu);
  73. /* converts an msr to an appropriate reservation bit */
  74. static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
  75. {
  76. /* returns the bit offset of the performance counter register */
  77. switch (boot_cpu_data.x86_vendor) {
  78. case X86_VENDOR_AMD:
  79. return (msr - MSR_K7_PERFCTR0);
  80. case X86_VENDOR_INTEL:
  81. return (msr - MSR_P4_BPU_PERFCTR0);
  82. }
  83. return 0;
  84. }
  85. /* converts an msr to an appropriate reservation bit */
  86. static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
  87. {
  88. /* returns the bit offset of the event selection register */
  89. switch (boot_cpu_data.x86_vendor) {
  90. case X86_VENDOR_AMD:
  91. return (msr - MSR_K7_EVNTSEL0);
  92. case X86_VENDOR_INTEL:
  93. return (msr - MSR_P4_BSU_ESCR0);
  94. }
  95. return 0;
  96. }
  97. /* checks for a bit availability (hack for oprofile) */
  98. int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
  99. {
  100. BUG_ON(counter > NMI_MAX_COUNTER_BITS);
  101. return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
  102. }
  103. /* checks the an msr for availability */
  104. int avail_to_resrv_perfctr_nmi(unsigned int msr)
  105. {
  106. unsigned int counter;
  107. counter = nmi_perfctr_msr_to_bit(msr);
  108. BUG_ON(counter > NMI_MAX_COUNTER_BITS);
  109. return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
  110. }
  111. int reserve_perfctr_nmi(unsigned int msr)
  112. {
  113. unsigned int counter;
  114. counter = nmi_perfctr_msr_to_bit(msr);
  115. BUG_ON(counter > NMI_MAX_COUNTER_BITS);
  116. if (!test_and_set_bit(counter, &__get_cpu_var(perfctr_nmi_owner)))
  117. return 1;
  118. return 0;
  119. }
  120. void release_perfctr_nmi(unsigned int msr)
  121. {
  122. unsigned int counter;
  123. counter = nmi_perfctr_msr_to_bit(msr);
  124. BUG_ON(counter > NMI_MAX_COUNTER_BITS);
  125. clear_bit(counter, &__get_cpu_var(perfctr_nmi_owner));
  126. }
  127. int reserve_evntsel_nmi(unsigned int msr)
  128. {
  129. unsigned int counter;
  130. counter = nmi_evntsel_msr_to_bit(msr);
  131. BUG_ON(counter > NMI_MAX_COUNTER_BITS);
  132. if (!test_and_set_bit(counter, &__get_cpu_var(evntsel_nmi_owner)))
  133. return 1;
  134. return 0;
  135. }
  136. void release_evntsel_nmi(unsigned int msr)
  137. {
  138. unsigned int counter;
  139. counter = nmi_evntsel_msr_to_bit(msr);
  140. BUG_ON(counter > NMI_MAX_COUNTER_BITS);
  141. clear_bit(counter, &__get_cpu_var(evntsel_nmi_owner));
  142. }
  143. static __cpuinit inline int nmi_known_cpu(void)
  144. {
  145. switch (boot_cpu_data.x86_vendor) {
  146. case X86_VENDOR_AMD:
  147. return boot_cpu_data.x86 == 15;
  148. case X86_VENDOR_INTEL:
  149. return boot_cpu_data.x86 == 15;
  150. }
  151. return 0;
  152. }
  153. /* Run after command line and cpu_init init, but before all other checks */
  154. void __cpuinit nmi_watchdog_default(void)
  155. {
  156. if (nmi_watchdog != NMI_DEFAULT)
  157. return;
  158. if (nmi_known_cpu())
  159. nmi_watchdog = NMI_LOCAL_APIC;
  160. else
  161. nmi_watchdog = NMI_IO_APIC;
  162. }
  163. #ifdef CONFIG_SMP
  164. /* The performance counters used by NMI_LOCAL_APIC don't trigger when
  165. * the CPU is idle. To make sure the NMI watchdog really ticks on all
  166. * CPUs during the test make them busy.
  167. */
  168. static __init void nmi_cpu_busy(void *data)
  169. {
  170. volatile int *endflag = data;
  171. local_irq_enable_in_hardirq();
  172. /* Intentionally don't use cpu_relax here. This is
  173. to make sure that the performance counter really ticks,
  174. even if there is a simulator or similar that catches the
  175. pause instruction. On a real HT machine this is fine because
  176. all other CPUs are busy with "useless" delay loops and don't
  177. care if they get somewhat less cycles. */
  178. while (*endflag == 0)
  179. barrier();
  180. }
  181. #endif
  182. int __init check_nmi_watchdog (void)
  183. {
  184. volatile int endflag = 0;
  185. int *counts;
  186. int cpu;
  187. if ((nmi_watchdog == NMI_NONE) || (nmi_watchdog == NMI_DEFAULT))
  188. return 0;
  189. if (!atomic_read(&nmi_active))
  190. return 0;
  191. counts = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
  192. if (!counts)
  193. return -1;
  194. printk(KERN_INFO "testing NMI watchdog ... ");
  195. #ifdef CONFIG_SMP
  196. if (nmi_watchdog == NMI_LOCAL_APIC)
  197. smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
  198. #endif
  199. for (cpu = 0; cpu < NR_CPUS; cpu++)
  200. counts[cpu] = cpu_pda(cpu)->__nmi_count;
  201. local_irq_enable();
  202. mdelay((10*1000)/nmi_hz); // wait 10 ticks
  203. for_each_online_cpu(cpu) {
  204. if (!per_cpu(nmi_watchdog_ctlblk, cpu).enabled)
  205. continue;
  206. if (cpu_pda(cpu)->__nmi_count - counts[cpu] <= 5) {
  207. printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
  208. cpu,
  209. counts[cpu],
  210. cpu_pda(cpu)->__nmi_count);
  211. per_cpu(nmi_watchdog_ctlblk, cpu).enabled = 0;
  212. atomic_dec(&nmi_active);
  213. }
  214. }
  215. if (!atomic_read(&nmi_active)) {
  216. kfree(counts);
  217. atomic_set(&nmi_active, -1);
  218. return -1;
  219. }
  220. endflag = 1;
  221. printk("OK.\n");
  222. /* now that we know it works we can reduce NMI frequency to
  223. something more reasonable; makes a difference in some configs */
  224. if (nmi_watchdog == NMI_LOCAL_APIC)
  225. nmi_hz = 1;
  226. kfree(counts);
  227. return 0;
  228. }
  229. int __init setup_nmi_watchdog(char *str)
  230. {
  231. int nmi;
  232. if (!strncmp(str,"panic",5)) {
  233. panic_on_timeout = 1;
  234. str = strchr(str, ',');
  235. if (!str)
  236. return 1;
  237. ++str;
  238. }
  239. get_option(&str, &nmi);
  240. if ((nmi >= NMI_INVALID) || (nmi < NMI_NONE))
  241. return 0;
  242. if ((nmi == NMI_LOCAL_APIC) && (nmi_known_cpu() == 0))
  243. return 0; /* no lapic support */
  244. nmi_watchdog = nmi;
  245. return 1;
  246. }
  247. __setup("nmi_watchdog=", setup_nmi_watchdog);
  248. static void disable_lapic_nmi_watchdog(void)
  249. {
  250. BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
  251. if (atomic_read(&nmi_active) <= 0)
  252. return;
  253. on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
  254. BUG_ON(atomic_read(&nmi_active) != 0);
  255. }
  256. static void enable_lapic_nmi_watchdog(void)
  257. {
  258. BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
  259. /* are we already enabled */
  260. if (atomic_read(&nmi_active) != 0)
  261. return;
  262. /* are we lapic aware */
  263. if (nmi_known_cpu() <= 0)
  264. return;
  265. on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
  266. touch_nmi_watchdog();
  267. }
  268. int reserve_lapic_nmi(void)
  269. {
  270. unsigned int old_owner;
  271. spin_lock(&lapic_nmi_owner_lock);
  272. old_owner = lapic_nmi_owner;
  273. lapic_nmi_owner |= LAPIC_NMI_RESERVED;
  274. spin_unlock(&lapic_nmi_owner_lock);
  275. if (old_owner & LAPIC_NMI_RESERVED)
  276. return -EBUSY;
  277. if (old_owner & LAPIC_NMI_WATCHDOG)
  278. disable_lapic_nmi_watchdog();
  279. return 0;
  280. }
  281. void release_lapic_nmi(void)
  282. {
  283. unsigned int new_owner;
  284. spin_lock(&lapic_nmi_owner_lock);
  285. new_owner = lapic_nmi_owner & ~LAPIC_NMI_RESERVED;
  286. lapic_nmi_owner = new_owner;
  287. spin_unlock(&lapic_nmi_owner_lock);
  288. if (new_owner & LAPIC_NMI_WATCHDOG)
  289. enable_lapic_nmi_watchdog();
  290. }
  291. void disable_timer_nmi_watchdog(void)
  292. {
  293. BUG_ON(nmi_watchdog != NMI_IO_APIC);
  294. if (atomic_read(&nmi_active) <= 0)
  295. return;
  296. disable_irq(0);
  297. on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
  298. BUG_ON(atomic_read(&nmi_active) != 0);
  299. }
  300. void enable_timer_nmi_watchdog(void)
  301. {
  302. BUG_ON(nmi_watchdog != NMI_IO_APIC);
  303. if (atomic_read(&nmi_active) == 0) {
  304. touch_nmi_watchdog();
  305. on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
  306. enable_irq(0);
  307. }
  308. }
  309. #ifdef CONFIG_PM
  310. static int nmi_pm_active; /* nmi_active before suspend */
  311. static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
  312. {
  313. nmi_pm_active = atomic_read(&nmi_active);
  314. disable_lapic_nmi_watchdog();
  315. return 0;
  316. }
  317. static int lapic_nmi_resume(struct sys_device *dev)
  318. {
  319. if (nmi_pm_active > 0)
  320. enable_lapic_nmi_watchdog();
  321. return 0;
  322. }
  323. static struct sysdev_class nmi_sysclass = {
  324. set_kset_name("lapic_nmi"),
  325. .resume = lapic_nmi_resume,
  326. .suspend = lapic_nmi_suspend,
  327. };
  328. static struct sys_device device_lapic_nmi = {
  329. .id = 0,
  330. .cls = &nmi_sysclass,
  331. };
  332. static int __init init_lapic_nmi_sysfs(void)
  333. {
  334. int error;
  335. /* should really be a BUG_ON but b/c this is an
  336. * init call, it just doesn't work. -dcz
  337. */
  338. if (nmi_watchdog != NMI_LOCAL_APIC)
  339. return 0;
  340. if ( atomic_read(&nmi_active) < 0 )
  341. return 0;
  342. error = sysdev_class_register(&nmi_sysclass);
  343. if (!error)
  344. error = sysdev_register(&device_lapic_nmi);
  345. return error;
  346. }
  347. /* must come after the local APIC's device_initcall() */
  348. late_initcall(init_lapic_nmi_sysfs);
  349. #endif /* CONFIG_PM */
  350. /*
  351. * Activate the NMI watchdog via the local APIC.
  352. * Original code written by Keith Owens.
  353. */
  354. /* Note that these events don't tick when the CPU idles. This means
  355. the frequency varies with CPU load. */
  356. #define K7_EVNTSEL_ENABLE (1 << 22)
  357. #define K7_EVNTSEL_INT (1 << 20)
  358. #define K7_EVNTSEL_OS (1 << 17)
  359. #define K7_EVNTSEL_USR (1 << 16)
  360. #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76
  361. #define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
  362. static int setup_k7_watchdog(void)
  363. {
  364. unsigned int perfctr_msr, evntsel_msr;
  365. unsigned int evntsel;
  366. struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
  367. perfctr_msr = MSR_K7_PERFCTR0;
  368. evntsel_msr = MSR_K7_EVNTSEL0;
  369. if (!reserve_perfctr_nmi(perfctr_msr))
  370. goto fail;
  371. if (!reserve_evntsel_nmi(evntsel_msr))
  372. goto fail1;
  373. /* Simulator may not support it */
  374. if (checking_wrmsrl(evntsel_msr, 0UL))
  375. goto fail2;
  376. wrmsrl(perfctr_msr, 0UL);
  377. evntsel = K7_EVNTSEL_INT
  378. | K7_EVNTSEL_OS
  379. | K7_EVNTSEL_USR
  380. | K7_NMI_EVENT;
  381. /* setup the timer */
  382. wrmsr(evntsel_msr, evntsel, 0);
  383. wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
  384. apic_write(APIC_LVTPC, APIC_DM_NMI);
  385. evntsel |= K7_EVNTSEL_ENABLE;
  386. wrmsr(evntsel_msr, evntsel, 0);
  387. wd->perfctr_msr = perfctr_msr;
  388. wd->evntsel_msr = evntsel_msr;
  389. wd->cccr_msr = 0; //unused
  390. wd->check_bit = 1ULL<<63;
  391. return 1;
  392. fail2:
  393. release_evntsel_nmi(evntsel_msr);
  394. fail1:
  395. release_perfctr_nmi(perfctr_msr);
  396. fail:
  397. return 0;
  398. }
  399. static void stop_k7_watchdog(void)
  400. {
  401. struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
  402. wrmsr(wd->evntsel_msr, 0, 0);
  403. release_evntsel_nmi(wd->evntsel_msr);
  404. release_perfctr_nmi(wd->perfctr_msr);
  405. }
  406. /* Note that these events don't tick when the CPU idles. This means
  407. the frequency varies with CPU load. */
  408. #define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
  409. #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
  410. #define P4_ESCR_OS (1<<3)
  411. #define P4_ESCR_USR (1<<2)
  412. #define P4_CCCR_OVF_PMI0 (1<<26)
  413. #define P4_CCCR_OVF_PMI1 (1<<27)
  414. #define P4_CCCR_THRESHOLD(N) ((N)<<20)
  415. #define P4_CCCR_COMPLEMENT (1<<19)
  416. #define P4_CCCR_COMPARE (1<<18)
  417. #define P4_CCCR_REQUIRED (3<<16)
  418. #define P4_CCCR_ESCR_SELECT(N) ((N)<<13)
  419. #define P4_CCCR_ENABLE (1<<12)
  420. #define P4_CCCR_OVF (1<<31)
  421. /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
  422. CRU_ESCR0 (with any non-null event selector) through a complemented
  423. max threshold. [IA32-Vol3, Section 14.9.9] */
  424. static int setup_p4_watchdog(void)
  425. {
  426. unsigned int perfctr_msr, evntsel_msr, cccr_msr;
  427. unsigned int evntsel, cccr_val;
  428. unsigned int misc_enable, dummy;
  429. unsigned int ht_num;
  430. struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
  431. rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy);
  432. if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
  433. return 0;
  434. #ifdef CONFIG_SMP
  435. /* detect which hyperthread we are on */
  436. if (smp_num_siblings == 2) {
  437. unsigned int ebx, apicid;
  438. ebx = cpuid_ebx(1);
  439. apicid = (ebx >> 24) & 0xff;
  440. ht_num = apicid & 1;
  441. } else
  442. #endif
  443. ht_num = 0;
  444. /* performance counters are shared resources
  445. * assign each hyperthread its own set
  446. * (re-use the ESCR0 register, seems safe
  447. * and keeps the cccr_val the same)
  448. */
  449. if (!ht_num) {
  450. /* logical cpu 0 */
  451. perfctr_msr = MSR_P4_IQ_PERFCTR0;
  452. evntsel_msr = MSR_P4_CRU_ESCR0;
  453. cccr_msr = MSR_P4_IQ_CCCR0;
  454. cccr_val = P4_CCCR_OVF_PMI0 | P4_CCCR_ESCR_SELECT(4);
  455. } else {
  456. /* logical cpu 1 */
  457. perfctr_msr = MSR_P4_IQ_PERFCTR1;
  458. evntsel_msr = MSR_P4_CRU_ESCR0;
  459. cccr_msr = MSR_P4_IQ_CCCR1;
  460. cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4);
  461. }
  462. if (!reserve_perfctr_nmi(perfctr_msr))
  463. goto fail;
  464. if (!reserve_evntsel_nmi(evntsel_msr))
  465. goto fail1;
  466. evntsel = P4_ESCR_EVENT_SELECT(0x3F)
  467. | P4_ESCR_OS
  468. | P4_ESCR_USR;
  469. cccr_val |= P4_CCCR_THRESHOLD(15)
  470. | P4_CCCR_COMPLEMENT
  471. | P4_CCCR_COMPARE
  472. | P4_CCCR_REQUIRED;
  473. wrmsr(evntsel_msr, evntsel, 0);
  474. wrmsr(cccr_msr, cccr_val, 0);
  475. wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
  476. apic_write(APIC_LVTPC, APIC_DM_NMI);
  477. cccr_val |= P4_CCCR_ENABLE;
  478. wrmsr(cccr_msr, cccr_val, 0);
  479. wd->perfctr_msr = perfctr_msr;
  480. wd->evntsel_msr = evntsel_msr;
  481. wd->cccr_msr = cccr_msr;
  482. wd->check_bit = 1ULL<<39;
  483. return 1;
  484. fail1:
  485. release_perfctr_nmi(perfctr_msr);
  486. fail:
  487. return 0;
  488. }
  489. static void stop_p4_watchdog(void)
  490. {
  491. struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
  492. wrmsr(wd->cccr_msr, 0, 0);
  493. wrmsr(wd->evntsel_msr, 0, 0);
  494. release_evntsel_nmi(wd->evntsel_msr);
  495. release_perfctr_nmi(wd->perfctr_msr);
  496. }
  497. void setup_apic_nmi_watchdog(void *unused)
  498. {
  499. /* only support LOCAL and IO APICs for now */
  500. if ((nmi_watchdog != NMI_LOCAL_APIC) &&
  501. (nmi_watchdog != NMI_IO_APIC))
  502. return;
  503. if (nmi_watchdog == NMI_LOCAL_APIC) {
  504. switch (boot_cpu_data.x86_vendor) {
  505. case X86_VENDOR_AMD:
  506. if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
  507. return;
  508. if (!setup_k7_watchdog())
  509. return;
  510. break;
  511. case X86_VENDOR_INTEL:
  512. if (!setup_p4_watchdog())
  513. return;
  514. break;
  515. default:
  516. return;
  517. }
  518. }
  519. __get_cpu_var(nmi_watchdog_ctlblk.enabled) = 1;
  520. atomic_inc(&nmi_active);
  521. }
  522. static void stop_apic_nmi_watchdog(void *unused)
  523. {
  524. /* only support LOCAL and IO APICs for now */
  525. if ((nmi_watchdog != NMI_LOCAL_APIC) &&
  526. (nmi_watchdog != NMI_IO_APIC))
  527. return;
  528. if (nmi_watchdog == NMI_LOCAL_APIC) {
  529. switch (boot_cpu_data.x86_vendor) {
  530. case X86_VENDOR_AMD:
  531. if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
  532. return;
  533. stop_k7_watchdog();
  534. break;
  535. case X86_VENDOR_INTEL:
  536. stop_p4_watchdog();
  537. break;
  538. default:
  539. return;
  540. }
  541. }
  542. __get_cpu_var(nmi_watchdog_ctlblk.enabled) = 0;
  543. atomic_dec(&nmi_active);
  544. }
  545. /*
  546. * the best way to detect whether a CPU has a 'hard lockup' problem
  547. * is to check it's local APIC timer IRQ counts. If they are not
  548. * changing then that CPU has some problem.
  549. *
  550. * as these watchdog NMI IRQs are generated on every CPU, we only
  551. * have to check the current processor.
  552. */
  553. static DEFINE_PER_CPU(unsigned, last_irq_sum);
  554. static DEFINE_PER_CPU(local_t, alert_counter);
  555. static DEFINE_PER_CPU(int, nmi_touch);
  556. void touch_nmi_watchdog (void)
  557. {
  558. if (nmi_watchdog > 0) {
  559. unsigned cpu;
  560. /*
  561. * Tell other CPUs to reset their alert counters. We cannot
  562. * do it ourselves because the alert count increase is not
  563. * atomic.
  564. */
  565. for_each_present_cpu (cpu)
  566. per_cpu(nmi_touch, cpu) = 1;
  567. }
  568. touch_softlockup_watchdog();
  569. }
  570. void __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
  571. {
  572. int sum;
  573. int touched = 0;
  574. struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
  575. u64 dummy;
  576. /* check for other users first */
  577. if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
  578. == NOTIFY_STOP) {
  579. touched = 1;
  580. }
  581. sum = read_pda(apic_timer_irqs);
  582. if (__get_cpu_var(nmi_touch)) {
  583. __get_cpu_var(nmi_touch) = 0;
  584. touched = 1;
  585. }
  586. #ifdef CONFIG_X86_MCE
  587. /* Could check oops_in_progress here too, but it's safer
  588. not too */
  589. if (atomic_read(&mce_entry) > 0)
  590. touched = 1;
  591. #endif
  592. /* if the apic timer isn't firing, this cpu isn't doing much */
  593. if (!touched && __get_cpu_var(last_irq_sum) == sum) {
  594. /*
  595. * Ayiee, looks like this CPU is stuck ...
  596. * wait a few IRQs (5 seconds) before doing the oops ...
  597. */
  598. local_inc(&__get_cpu_var(alert_counter));
  599. if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz)
  600. die_nmi("NMI Watchdog detected LOCKUP on CPU %d\n", regs);
  601. } else {
  602. __get_cpu_var(last_irq_sum) = sum;
  603. local_set(&__get_cpu_var(alert_counter), 0);
  604. }
  605. /* see if the nmi watchdog went off */
  606. if (wd->enabled) {
  607. if (nmi_watchdog == NMI_LOCAL_APIC) {
  608. rdmsrl(wd->perfctr_msr, dummy);
  609. if (dummy & wd->check_bit){
  610. /* this wasn't a watchdog timer interrupt */
  611. goto done;
  612. }
  613. /* only Intel uses the cccr msr */
  614. if (wd->cccr_msr != 0) {
  615. /*
  616. * P4 quirks:
  617. * - An overflown perfctr will assert its interrupt
  618. * until the OVF flag in its CCCR is cleared.
  619. * - LVTPC is masked on interrupt and must be
  620. * unmasked by the LVTPC handler.
  621. */
  622. rdmsrl(wd->cccr_msr, dummy);
  623. dummy &= ~P4_CCCR_OVF;
  624. wrmsrl(wd->cccr_msr, dummy);
  625. apic_write(APIC_LVTPC, APIC_DM_NMI);
  626. }
  627. /* start the cycle over again */
  628. wrmsrl(wd->perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
  629. }
  630. }
  631. done:
  632. return;
  633. }
  634. static __kprobes int dummy_nmi_callback(struct pt_regs * regs, int cpu)
  635. {
  636. return 0;
  637. }
  638. static nmi_callback_t nmi_callback = dummy_nmi_callback;
  639. asmlinkage __kprobes void do_nmi(struct pt_regs * regs, long error_code)
  640. {
  641. int cpu = safe_smp_processor_id();
  642. nmi_enter();
  643. add_pda(__nmi_count,1);
  644. if (!rcu_dereference(nmi_callback)(regs, cpu))
  645. default_do_nmi(regs);
  646. nmi_exit();
  647. }
  648. void set_nmi_callback(nmi_callback_t callback)
  649. {
  650. vmalloc_sync_all();
  651. rcu_assign_pointer(nmi_callback, callback);
  652. }
  653. EXPORT_SYMBOL_GPL(set_nmi_callback);
  654. void unset_nmi_callback(void)
  655. {
  656. nmi_callback = dummy_nmi_callback;
  657. }
  658. EXPORT_SYMBOL_GPL(unset_nmi_callback);
  659. #ifdef CONFIG_SYSCTL
  660. static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
  661. {
  662. unsigned char reason = get_nmi_reason();
  663. char buf[64];
  664. if (!(reason & 0xc0)) {
  665. sprintf(buf, "NMI received for unknown reason %02x\n", reason);
  666. die_nmi(buf,regs);
  667. }
  668. return 0;
  669. }
  670. /*
  671. * proc handler for /proc/sys/kernel/unknown_nmi_panic
  672. */
  673. int proc_unknown_nmi_panic(struct ctl_table *table, int write, struct file *file,
  674. void __user *buffer, size_t *length, loff_t *ppos)
  675. {
  676. int old_state;
  677. old_state = unknown_nmi_panic;
  678. proc_dointvec(table, write, file, buffer, length, ppos);
  679. if (!!old_state == !!unknown_nmi_panic)
  680. return 0;
  681. if (unknown_nmi_panic) {
  682. if (reserve_lapic_nmi() < 0) {
  683. unknown_nmi_panic = 0;
  684. return -EBUSY;
  685. } else {
  686. set_nmi_callback(unknown_nmi_panic_callback);
  687. }
  688. } else {
  689. release_lapic_nmi();
  690. unset_nmi_callback();
  691. }
  692. return 0;
  693. }
  694. #endif
  695. EXPORT_SYMBOL(nmi_active);
  696. EXPORT_SYMBOL(nmi_watchdog);
  697. EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi);
  698. EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
  699. EXPORT_SYMBOL(reserve_perfctr_nmi);
  700. EXPORT_SYMBOL(release_perfctr_nmi);
  701. EXPORT_SYMBOL(reserve_evntsel_nmi);
  702. EXPORT_SYMBOL(release_evntsel_nmi);
  703. EXPORT_SYMBOL(reserve_lapic_nmi);
  704. EXPORT_SYMBOL(release_lapic_nmi);
  705. EXPORT_SYMBOL(disable_timer_nmi_watchdog);
  706. EXPORT_SYMBOL(enable_timer_nmi_watchdog);
  707. EXPORT_SYMBOL(touch_nmi_watchdog);