dma-sh.c 6.7 KB

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  1. /*
  2. * arch/sh/drivers/dma/dma-sh.c
  3. *
  4. * SuperH On-chip DMAC Support
  5. *
  6. * Copyright (C) 2000 Takashi YOSHII
  7. * Copyright (C) 2003, 2004 Paul Mundt
  8. * Copyright (C) 2005 Andriy Skulysh
  9. *
  10. * This file is subject to the terms and conditions of the GNU General Public
  11. * License. See the file "COPYING" in the main directory of this archive
  12. * for more details.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/irq.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/module.h>
  18. #include <asm/dreamcast/dma.h>
  19. #include <asm/signal.h>
  20. #include <asm/irq.h>
  21. #include <asm/dma.h>
  22. #include <asm/io.h>
  23. #include "dma-sh.h"
  24. static inline unsigned int get_dmte_irq(unsigned int chan)
  25. {
  26. unsigned int irq = 0;
  27. /*
  28. * Normally we could just do DMTE0_IRQ + chan outright, though in the
  29. * case of the 7751R, the DMTE IRQs for channels > 4 start right above
  30. * the SCIF
  31. */
  32. if (chan < 4) {
  33. irq = DMTE0_IRQ + chan;
  34. } else {
  35. #ifdef DMTE4_IRQ
  36. irq = DMTE4_IRQ + chan - 4;
  37. #endif
  38. }
  39. return irq;
  40. }
  41. /*
  42. * We determine the correct shift size based off of the CHCR transmit size
  43. * for the given channel. Since we know that it will take:
  44. *
  45. * info->count >> ts_shift[transmit_size]
  46. *
  47. * iterations to complete the transfer.
  48. */
  49. static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
  50. {
  51. u32 chcr = ctrl_inl(CHCR[chan->chan]);
  52. return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT];
  53. }
  54. /*
  55. * The transfer end interrupt must read the chcr register to end the
  56. * hardware interrupt active condition.
  57. * Besides that it needs to waken any waiting process, which should handle
  58. * setting up the next transfer.
  59. */
  60. static irqreturn_t dma_tei(int irq, void *dev_id, struct pt_regs *regs)
  61. {
  62. struct dma_channel *chan = (struct dma_channel *)dev_id;
  63. u32 chcr;
  64. chcr = ctrl_inl(CHCR[chan->chan]);
  65. if (!(chcr & CHCR_TE))
  66. return IRQ_NONE;
  67. chcr &= ~(CHCR_IE | CHCR_DE);
  68. ctrl_outl(chcr, CHCR[chan->chan]);
  69. wake_up(&chan->wait_queue);
  70. return IRQ_HANDLED;
  71. }
  72. static int sh_dmac_request_dma(struct dma_channel *chan)
  73. {
  74. char name[32];
  75. snprintf(name, sizeof(name), "DMAC Transfer End (Channel %d)",
  76. chan->chan);
  77. return request_irq(get_dmte_irq(chan->chan), dma_tei,
  78. IRQF_DISABLED, name, chan);
  79. }
  80. static void sh_dmac_free_dma(struct dma_channel *chan)
  81. {
  82. free_irq(get_dmte_irq(chan->chan), chan);
  83. }
  84. static void
  85. sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
  86. {
  87. if (!chcr)
  88. chcr = RS_DUAL | CHCR_IE;
  89. if (chcr & CHCR_IE) {
  90. chcr &= ~CHCR_IE;
  91. chan->flags |= DMA_TEI_CAPABLE;
  92. } else {
  93. chan->flags &= ~DMA_TEI_CAPABLE;
  94. }
  95. ctrl_outl(chcr, CHCR[chan->chan]);
  96. chan->flags |= DMA_CONFIGURED;
  97. }
  98. static void sh_dmac_enable_dma(struct dma_channel *chan)
  99. {
  100. int irq;
  101. u32 chcr;
  102. chcr = ctrl_inl(CHCR[chan->chan]);
  103. chcr |= CHCR_DE;
  104. if (chan->flags & DMA_TEI_CAPABLE)
  105. chcr |= CHCR_IE;
  106. ctrl_outl(chcr, CHCR[chan->chan]);
  107. if (chan->flags & DMA_TEI_CAPABLE) {
  108. irq = get_dmte_irq(chan->chan);
  109. enable_irq(irq);
  110. }
  111. }
  112. static void sh_dmac_disable_dma(struct dma_channel *chan)
  113. {
  114. int irq;
  115. u32 chcr;
  116. if (chan->flags & DMA_TEI_CAPABLE) {
  117. irq = get_dmte_irq(chan->chan);
  118. disable_irq(irq);
  119. }
  120. chcr = ctrl_inl(CHCR[chan->chan]);
  121. chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
  122. ctrl_outl(chcr, CHCR[chan->chan]);
  123. }
  124. static int sh_dmac_xfer_dma(struct dma_channel *chan)
  125. {
  126. /*
  127. * If we haven't pre-configured the channel with special flags, use
  128. * the defaults.
  129. */
  130. if (unlikely(!(chan->flags & DMA_CONFIGURED)))
  131. sh_dmac_configure_channel(chan, 0);
  132. sh_dmac_disable_dma(chan);
  133. /*
  134. * Single-address mode usage note!
  135. *
  136. * It's important that we don't accidentally write any value to SAR/DAR
  137. * (this includes 0) that hasn't been directly specified by the user if
  138. * we're in single-address mode.
  139. *
  140. * In this case, only one address can be defined, anything else will
  141. * result in a DMA address error interrupt (at least on the SH-4),
  142. * which will subsequently halt the transfer.
  143. *
  144. * Channel 2 on the Dreamcast is a special case, as this is used for
  145. * cascading to the PVR2 DMAC. In this case, we still need to write
  146. * SAR and DAR, regardless of value, in order for cascading to work.
  147. */
  148. if (chan->sar || (mach_is_dreamcast() &&
  149. chan->chan == PVR2_CASCADE_CHAN))
  150. ctrl_outl(chan->sar, SAR[chan->chan]);
  151. if (chan->dar || (mach_is_dreamcast() &&
  152. chan->chan == PVR2_CASCADE_CHAN))
  153. ctrl_outl(chan->dar, DAR[chan->chan]);
  154. ctrl_outl(chan->count >> calc_xmit_shift(chan), DMATCR[chan->chan]);
  155. sh_dmac_enable_dma(chan);
  156. return 0;
  157. }
  158. static int sh_dmac_get_dma_residue(struct dma_channel *chan)
  159. {
  160. if (!(ctrl_inl(CHCR[chan->chan]) & CHCR_DE))
  161. return 0;
  162. return ctrl_inl(DMATCR[chan->chan]) << calc_xmit_shift(chan);
  163. }
  164. #ifdef CONFIG_CPU_SUBTYPE_SH7780
  165. #define dmaor_read_reg() ctrl_inw(DMAOR)
  166. #define dmaor_write_reg(data) ctrl_outw(data, DMAOR)
  167. #else
  168. #define dmaor_read_reg() ctrl_inl(DMAOR)
  169. #define dmaor_write_reg(data) ctrl_outl(data, DMAOR)
  170. #endif
  171. static inline int dmaor_reset(void)
  172. {
  173. unsigned long dmaor = dmaor_read_reg();
  174. /* Try to clear the error flags first, incase they are set */
  175. dmaor &= ~(DMAOR_NMIF | DMAOR_AE);
  176. dmaor_write_reg(dmaor);
  177. dmaor |= DMAOR_INIT;
  178. dmaor_write_reg(dmaor);
  179. /* See if we got an error again */
  180. if ((dmaor_read_reg() & (DMAOR_AE | DMAOR_NMIF))) {
  181. printk(KERN_ERR "dma-sh: Can't initialize DMAOR.\n");
  182. return -EINVAL;
  183. }
  184. return 0;
  185. }
  186. #if defined(CONFIG_CPU_SH4)
  187. static irqreturn_t dma_err(int irq, void *dev_id, struct pt_regs *regs)
  188. {
  189. dmaor_reset();
  190. disable_irq(irq);
  191. return IRQ_HANDLED;
  192. }
  193. #endif
  194. static struct dma_ops sh_dmac_ops = {
  195. .request = sh_dmac_request_dma,
  196. .free = sh_dmac_free_dma,
  197. .get_residue = sh_dmac_get_dma_residue,
  198. .xfer = sh_dmac_xfer_dma,
  199. .configure = sh_dmac_configure_channel,
  200. };
  201. static struct dma_info sh_dmac_info = {
  202. .name = "sh_dmac",
  203. .nr_channels = CONFIG_NR_ONCHIP_DMA_CHANNELS,
  204. .ops = &sh_dmac_ops,
  205. .flags = DMAC_CHANNELS_TEI_CAPABLE,
  206. };
  207. static int __init sh_dmac_init(void)
  208. {
  209. struct dma_info *info = &sh_dmac_info;
  210. int i;
  211. #ifdef CONFIG_CPU_SH4
  212. make_ipr_irq(DMAE_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
  213. i = request_irq(DMAE_IRQ, dma_err, IRQF_DISABLED, "DMAC Address Error", 0);
  214. if (i < 0)
  215. return i;
  216. #endif
  217. for (i = 0; i < info->nr_channels; i++) {
  218. int irq = get_dmte_irq(i);
  219. make_ipr_irq(irq, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
  220. }
  221. /*
  222. * Initialize DMAOR, and clean up any error flags that may have
  223. * been set.
  224. */
  225. i = dmaor_reset();
  226. if (i < 0)
  227. return i;
  228. return register_dmac(info);
  229. }
  230. static void __exit sh_dmac_exit(void)
  231. {
  232. #ifdef CONFIG_CPU_SH4
  233. free_irq(DMAE_IRQ, 0);
  234. #endif
  235. unregister_dmac(&sh_dmac_info);
  236. }
  237. subsys_initcall(sh_dmac_init);
  238. module_exit(sh_dmac_exit);
  239. MODULE_AUTHOR("Takashi YOSHII, Paul Mundt, Andriy Skulysh");
  240. MODULE_DESCRIPTION("SuperH On-Chip DMAC Support");
  241. MODULE_LICENSE("GPL");