spu_priv1_mmio.c 4.2 KB

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  1. /*
  2. * spu hypervisor abstraction for direct hardware access.
  3. *
  4. * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
  5. * Copyright 2006 Sony Corp.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; version 2 of the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. */
  20. #include <linux/module.h>
  21. #include <asm/io.h>
  22. #include <asm/spu.h>
  23. #include <asm/spu_priv1.h>
  24. #include "interrupt.h"
  25. static void int_mask_and(struct spu *spu, int class, u64 mask)
  26. {
  27. u64 old_mask;
  28. old_mask = in_be64(&spu->priv1->int_mask_RW[class]);
  29. out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask);
  30. }
  31. static void int_mask_or(struct spu *spu, int class, u64 mask)
  32. {
  33. u64 old_mask;
  34. old_mask = in_be64(&spu->priv1->int_mask_RW[class]);
  35. out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask);
  36. }
  37. static void int_mask_set(struct spu *spu, int class, u64 mask)
  38. {
  39. out_be64(&spu->priv1->int_mask_RW[class], mask);
  40. }
  41. static u64 int_mask_get(struct spu *spu, int class)
  42. {
  43. return in_be64(&spu->priv1->int_mask_RW[class]);
  44. }
  45. static void int_stat_clear(struct spu *spu, int class, u64 stat)
  46. {
  47. out_be64(&spu->priv1->int_stat_RW[class], stat);
  48. }
  49. static u64 int_stat_get(struct spu *spu, int class)
  50. {
  51. return in_be64(&spu->priv1->int_stat_RW[class]);
  52. }
  53. static void cpu_affinity_set(struct spu *spu, int cpu)
  54. {
  55. u64 target = iic_get_target_id(cpu);
  56. u64 route = target << 48 | target << 32 | target << 16;
  57. out_be64(&spu->priv1->int_route_RW, route);
  58. }
  59. static u64 mfc_dar_get(struct spu *spu)
  60. {
  61. return in_be64(&spu->priv1->mfc_dar_RW);
  62. }
  63. static u64 mfc_dsisr_get(struct spu *spu)
  64. {
  65. return in_be64(&spu->priv1->mfc_dsisr_RW);
  66. }
  67. static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
  68. {
  69. out_be64(&spu->priv1->mfc_dsisr_RW, dsisr);
  70. }
  71. static void mfc_sdr_set(struct spu *spu, u64 sdr)
  72. {
  73. out_be64(&spu->priv1->mfc_sdr_RW, sdr);
  74. }
  75. static void mfc_sr1_set(struct spu *spu, u64 sr1)
  76. {
  77. out_be64(&spu->priv1->mfc_sr1_RW, sr1);
  78. }
  79. static u64 mfc_sr1_get(struct spu *spu)
  80. {
  81. return in_be64(&spu->priv1->mfc_sr1_RW);
  82. }
  83. static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
  84. {
  85. out_be64(&spu->priv1->mfc_tclass_id_RW, tclass_id);
  86. }
  87. static u64 mfc_tclass_id_get(struct spu *spu)
  88. {
  89. return in_be64(&spu->priv1->mfc_tclass_id_RW);
  90. }
  91. static void tlb_invalidate(struct spu *spu)
  92. {
  93. out_be64(&spu->priv1->tlb_invalidate_entry_W, 0ul);
  94. }
  95. static void resource_allocation_groupID_set(struct spu *spu, u64 id)
  96. {
  97. out_be64(&spu->priv1->resource_allocation_groupID_RW, id);
  98. }
  99. static u64 resource_allocation_groupID_get(struct spu *spu)
  100. {
  101. return in_be64(&spu->priv1->resource_allocation_groupID_RW);
  102. }
  103. static void resource_allocation_enable_set(struct spu *spu, u64 enable)
  104. {
  105. out_be64(&spu->priv1->resource_allocation_enable_RW, enable);
  106. }
  107. static u64 resource_allocation_enable_get(struct spu *spu)
  108. {
  109. return in_be64(&spu->priv1->resource_allocation_enable_RW);
  110. }
  111. const struct spu_priv1_ops spu_priv1_mmio_ops =
  112. {
  113. .int_mask_and = int_mask_and,
  114. .int_mask_or = int_mask_or,
  115. .int_mask_set = int_mask_set,
  116. .int_mask_get = int_mask_get,
  117. .int_stat_clear = int_stat_clear,
  118. .int_stat_get = int_stat_get,
  119. .cpu_affinity_set = cpu_affinity_set,
  120. .mfc_dar_get = mfc_dar_get,
  121. .mfc_dsisr_get = mfc_dsisr_get,
  122. .mfc_dsisr_set = mfc_dsisr_set,
  123. .mfc_sdr_set = mfc_sdr_set,
  124. .mfc_sr1_set = mfc_sr1_set,
  125. .mfc_sr1_get = mfc_sr1_get,
  126. .mfc_tclass_id_set = mfc_tclass_id_set,
  127. .mfc_tclass_id_get = mfc_tclass_id_get,
  128. .tlb_invalidate = tlb_invalidate,
  129. .resource_allocation_groupID_set = resource_allocation_groupID_set,
  130. .resource_allocation_groupID_get = resource_allocation_groupID_get,
  131. .resource_allocation_enable_set = resource_allocation_enable_set,
  132. .resource_allocation_enable_get = resource_allocation_enable_get,
  133. };