irq.c 11 KB

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  1. /*
  2. * Platform dependent support for SGI SN
  3. *
  4. * This file is subject to the terms and conditions of the GNU General Public
  5. * License. See the file "COPYING" in the main directory of this archive
  6. * for more details.
  7. *
  8. * Copyright (c) 2000-2006 Silicon Graphics, Inc. All Rights Reserved.
  9. */
  10. #include <linux/irq.h>
  11. #include <linux/spinlock.h>
  12. #include <linux/init.h>
  13. #include <asm/sn/addrs.h>
  14. #include <asm/sn/arch.h>
  15. #include <asm/sn/intr.h>
  16. #include <asm/sn/pcibr_provider.h>
  17. #include <asm/sn/pcibus_provider_defs.h>
  18. #include <asm/sn/pcidev.h>
  19. #include <asm/sn/shub_mmr.h>
  20. #include <asm/sn/sn_sal.h>
  21. static void force_interrupt(int irq);
  22. static void register_intr_pda(struct sn_irq_info *sn_irq_info);
  23. static void unregister_intr_pda(struct sn_irq_info *sn_irq_info);
  24. int sn_force_interrupt_flag = 1;
  25. extern int sn_ioif_inited;
  26. struct list_head **sn_irq_lh;
  27. static DEFINE_SPINLOCK(sn_irq_info_lock); /* non-IRQ lock */
  28. u64 sn_intr_alloc(nasid_t local_nasid, int local_widget,
  29. struct sn_irq_info *sn_irq_info,
  30. int req_irq, nasid_t req_nasid,
  31. int req_slice)
  32. {
  33. struct ia64_sal_retval ret_stuff;
  34. ret_stuff.status = 0;
  35. ret_stuff.v0 = 0;
  36. SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
  37. (u64) SAL_INTR_ALLOC, (u64) local_nasid,
  38. (u64) local_widget, __pa(sn_irq_info), (u64) req_irq,
  39. (u64) req_nasid, (u64) req_slice);
  40. return ret_stuff.status;
  41. }
  42. void sn_intr_free(nasid_t local_nasid, int local_widget,
  43. struct sn_irq_info *sn_irq_info)
  44. {
  45. struct ia64_sal_retval ret_stuff;
  46. ret_stuff.status = 0;
  47. ret_stuff.v0 = 0;
  48. SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
  49. (u64) SAL_INTR_FREE, (u64) local_nasid,
  50. (u64) local_widget, (u64) sn_irq_info->irq_irq,
  51. (u64) sn_irq_info->irq_cookie, 0, 0);
  52. }
  53. static unsigned int sn_startup_irq(unsigned int irq)
  54. {
  55. return 0;
  56. }
  57. static void sn_shutdown_irq(unsigned int irq)
  58. {
  59. }
  60. static void sn_disable_irq(unsigned int irq)
  61. {
  62. }
  63. static void sn_enable_irq(unsigned int irq)
  64. {
  65. }
  66. static void sn_ack_irq(unsigned int irq)
  67. {
  68. u64 event_occurred, mask;
  69. irq = irq & 0xff;
  70. event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED));
  71. mask = event_occurred & SH_ALL_INT_MASK;
  72. HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), mask);
  73. __set_bit(irq, (volatile void *)pda->sn_in_service_ivecs);
  74. move_native_irq(irq);
  75. }
  76. static void sn_end_irq(unsigned int irq)
  77. {
  78. int ivec;
  79. u64 event_occurred;
  80. ivec = irq & 0xff;
  81. if (ivec == SGI_UART_VECTOR) {
  82. event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR (SH_EVENT_OCCURRED));
  83. /* If the UART bit is set here, we may have received an
  84. * interrupt from the UART that the driver missed. To
  85. * make sure, we IPI ourselves to force us to look again.
  86. */
  87. if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) {
  88. platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR,
  89. IA64_IPI_DM_INT, 0);
  90. }
  91. }
  92. __clear_bit(ivec, (volatile void *)pda->sn_in_service_ivecs);
  93. if (sn_force_interrupt_flag)
  94. force_interrupt(irq);
  95. }
  96. static void sn_irq_info_free(struct rcu_head *head);
  97. struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *sn_irq_info,
  98. nasid_t nasid, int slice)
  99. {
  100. int vector;
  101. int cpuphys;
  102. int64_t bridge;
  103. int local_widget, status;
  104. nasid_t local_nasid;
  105. struct sn_irq_info *new_irq_info;
  106. struct sn_pcibus_provider *pci_provider;
  107. new_irq_info = kmalloc(sizeof(struct sn_irq_info), GFP_ATOMIC);
  108. if (new_irq_info == NULL)
  109. return NULL;
  110. memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info));
  111. bridge = (u64) new_irq_info->irq_bridge;
  112. if (!bridge) {
  113. kfree(new_irq_info);
  114. return NULL; /* irq is not a device interrupt */
  115. }
  116. local_nasid = NASID_GET(bridge);
  117. if (local_nasid & 1)
  118. local_widget = TIO_SWIN_WIDGETNUM(bridge);
  119. else
  120. local_widget = SWIN_WIDGETNUM(bridge);
  121. vector = sn_irq_info->irq_irq;
  122. /* Free the old PROM new_irq_info structure */
  123. sn_intr_free(local_nasid, local_widget, new_irq_info);
  124. /* Update kernels new_irq_info with new target info */
  125. unregister_intr_pda(new_irq_info);
  126. /* allocate a new PROM new_irq_info struct */
  127. status = sn_intr_alloc(local_nasid, local_widget,
  128. new_irq_info, vector,
  129. nasid, slice);
  130. /* SAL call failed */
  131. if (status) {
  132. kfree(new_irq_info);
  133. return NULL;
  134. }
  135. cpuphys = nasid_slice_to_cpuid(nasid, slice);
  136. new_irq_info->irq_cpuid = cpuphys;
  137. register_intr_pda(new_irq_info);
  138. pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type];
  139. /*
  140. * If this represents a line interrupt, target it. If it's
  141. * an msi (irq_int_bit < 0), it's already targeted.
  142. */
  143. if (new_irq_info->irq_int_bit >= 0 &&
  144. pci_provider && pci_provider->target_interrupt)
  145. (pci_provider->target_interrupt)(new_irq_info);
  146. spin_lock(&sn_irq_info_lock);
  147. list_replace_rcu(&sn_irq_info->list, &new_irq_info->list);
  148. spin_unlock(&sn_irq_info_lock);
  149. call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
  150. #ifdef CONFIG_SMP
  151. set_irq_affinity_info((vector & 0xff), cpuphys, 0);
  152. #endif
  153. return new_irq_info;
  154. }
  155. static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask)
  156. {
  157. struct sn_irq_info *sn_irq_info, *sn_irq_info_safe;
  158. nasid_t nasid;
  159. int slice;
  160. nasid = cpuid_to_nasid(first_cpu(mask));
  161. slice = cpuid_to_slice(first_cpu(mask));
  162. list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe,
  163. sn_irq_lh[irq], list)
  164. (void)sn_retarget_vector(sn_irq_info, nasid, slice);
  165. }
  166. struct hw_interrupt_type irq_type_sn = {
  167. .typename = "SN hub",
  168. .startup = sn_startup_irq,
  169. .shutdown = sn_shutdown_irq,
  170. .enable = sn_enable_irq,
  171. .disable = sn_disable_irq,
  172. .ack = sn_ack_irq,
  173. .end = sn_end_irq,
  174. .set_affinity = sn_set_affinity_irq
  175. };
  176. unsigned int sn_local_vector_to_irq(u8 vector)
  177. {
  178. return (CPU_VECTOR_TO_IRQ(smp_processor_id(), vector));
  179. }
  180. void sn_irq_init(void)
  181. {
  182. int i;
  183. irq_desc_t *base_desc = irq_desc;
  184. ia64_first_device_vector = IA64_SN2_FIRST_DEVICE_VECTOR;
  185. ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR;
  186. for (i = 0; i < NR_IRQS; i++) {
  187. if (base_desc[i].chip == &no_irq_type) {
  188. base_desc[i].chip = &irq_type_sn;
  189. }
  190. }
  191. }
  192. static void register_intr_pda(struct sn_irq_info *sn_irq_info)
  193. {
  194. int irq = sn_irq_info->irq_irq;
  195. int cpu = sn_irq_info->irq_cpuid;
  196. if (pdacpu(cpu)->sn_last_irq < irq) {
  197. pdacpu(cpu)->sn_last_irq = irq;
  198. }
  199. if (pdacpu(cpu)->sn_first_irq == 0 || pdacpu(cpu)->sn_first_irq > irq)
  200. pdacpu(cpu)->sn_first_irq = irq;
  201. }
  202. static void unregister_intr_pda(struct sn_irq_info *sn_irq_info)
  203. {
  204. int irq = sn_irq_info->irq_irq;
  205. int cpu = sn_irq_info->irq_cpuid;
  206. struct sn_irq_info *tmp_irq_info;
  207. int i, foundmatch;
  208. rcu_read_lock();
  209. if (pdacpu(cpu)->sn_last_irq == irq) {
  210. foundmatch = 0;
  211. for (i = pdacpu(cpu)->sn_last_irq - 1;
  212. i && !foundmatch; i--) {
  213. list_for_each_entry_rcu(tmp_irq_info,
  214. sn_irq_lh[i],
  215. list) {
  216. if (tmp_irq_info->irq_cpuid == cpu) {
  217. foundmatch = 1;
  218. break;
  219. }
  220. }
  221. }
  222. pdacpu(cpu)->sn_last_irq = i;
  223. }
  224. if (pdacpu(cpu)->sn_first_irq == irq) {
  225. foundmatch = 0;
  226. for (i = pdacpu(cpu)->sn_first_irq + 1;
  227. i < NR_IRQS && !foundmatch; i++) {
  228. list_for_each_entry_rcu(tmp_irq_info,
  229. sn_irq_lh[i],
  230. list) {
  231. if (tmp_irq_info->irq_cpuid == cpu) {
  232. foundmatch = 1;
  233. break;
  234. }
  235. }
  236. }
  237. pdacpu(cpu)->sn_first_irq = ((i == NR_IRQS) ? 0 : i);
  238. }
  239. rcu_read_unlock();
  240. }
  241. static void sn_irq_info_free(struct rcu_head *head)
  242. {
  243. struct sn_irq_info *sn_irq_info;
  244. sn_irq_info = container_of(head, struct sn_irq_info, rcu);
  245. kfree(sn_irq_info);
  246. }
  247. void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info)
  248. {
  249. nasid_t nasid = sn_irq_info->irq_nasid;
  250. int slice = sn_irq_info->irq_slice;
  251. int cpu = nasid_slice_to_cpuid(nasid, slice);
  252. pci_dev_get(pci_dev);
  253. sn_irq_info->irq_cpuid = cpu;
  254. sn_irq_info->irq_pciioinfo = SN_PCIDEV_INFO(pci_dev);
  255. /* link it into the sn_irq[irq] list */
  256. spin_lock(&sn_irq_info_lock);
  257. list_add_rcu(&sn_irq_info->list, sn_irq_lh[sn_irq_info->irq_irq]);
  258. reserve_irq_vector(sn_irq_info->irq_irq);
  259. spin_unlock(&sn_irq_info_lock);
  260. register_intr_pda(sn_irq_info);
  261. }
  262. void sn_irq_unfixup(struct pci_dev *pci_dev)
  263. {
  264. struct sn_irq_info *sn_irq_info;
  265. /* Only cleanup IRQ stuff if this device has a host bus context */
  266. if (!SN_PCIDEV_BUSSOFT(pci_dev))
  267. return;
  268. sn_irq_info = SN_PCIDEV_INFO(pci_dev)->pdi_sn_irq_info;
  269. if (!sn_irq_info)
  270. return;
  271. if (!sn_irq_info->irq_irq) {
  272. kfree(sn_irq_info);
  273. return;
  274. }
  275. unregister_intr_pda(sn_irq_info);
  276. spin_lock(&sn_irq_info_lock);
  277. list_del_rcu(&sn_irq_info->list);
  278. spin_unlock(&sn_irq_info_lock);
  279. if (list_empty(sn_irq_lh[sn_irq_info->irq_irq]))
  280. free_irq_vector(sn_irq_info->irq_irq);
  281. call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
  282. pci_dev_put(pci_dev);
  283. }
  284. static inline void
  285. sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info)
  286. {
  287. struct sn_pcibus_provider *pci_provider;
  288. pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type];
  289. if (pci_provider && pci_provider->force_interrupt)
  290. (*pci_provider->force_interrupt)(sn_irq_info);
  291. }
  292. static void force_interrupt(int irq)
  293. {
  294. struct sn_irq_info *sn_irq_info;
  295. if (!sn_ioif_inited)
  296. return;
  297. rcu_read_lock();
  298. list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[irq], list)
  299. sn_call_force_intr_provider(sn_irq_info);
  300. rcu_read_unlock();
  301. }
  302. /*
  303. * Check for lost interrupts. If the PIC int_status reg. says that
  304. * an interrupt has been sent, but not handled, and the interrupt
  305. * is not pending in either the cpu irr regs or in the soft irr regs,
  306. * and the interrupt is not in service, then the interrupt may have
  307. * been lost. Force an interrupt on that pin. It is possible that
  308. * the interrupt is in flight, so we may generate a spurious interrupt,
  309. * but we should never miss a real lost interrupt.
  310. */
  311. static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info)
  312. {
  313. u64 regval;
  314. struct pcidev_info *pcidev_info;
  315. struct pcibus_info *pcibus_info;
  316. /*
  317. * Bridge types attached to TIO (anything but PIC) do not need this WAR
  318. * since they do not target Shub II interrupt registers. If that
  319. * ever changes, this check needs to accomodate.
  320. */
  321. if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_PIC)
  322. return;
  323. pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
  324. if (!pcidev_info)
  325. return;
  326. pcibus_info =
  327. (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
  328. pdi_pcibus_info;
  329. regval = pcireg_intr_status_get(pcibus_info);
  330. if (!ia64_get_irr(irq_to_vector(irq))) {
  331. if (!test_bit(irq, pda->sn_in_service_ivecs)) {
  332. regval &= 0xff;
  333. if (sn_irq_info->irq_int_bit & regval &
  334. sn_irq_info->irq_last_intr) {
  335. regval &= ~(sn_irq_info->irq_int_bit & regval);
  336. sn_call_force_intr_provider(sn_irq_info);
  337. }
  338. }
  339. }
  340. sn_irq_info->irq_last_intr = regval;
  341. }
  342. void sn_lb_int_war_check(void)
  343. {
  344. struct sn_irq_info *sn_irq_info;
  345. int i;
  346. if (!sn_ioif_inited || pda->sn_first_irq == 0)
  347. return;
  348. rcu_read_lock();
  349. for (i = pda->sn_first_irq; i <= pda->sn_last_irq; i++) {
  350. list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[i], list) {
  351. sn_check_intr(i, sn_irq_info);
  352. }
  353. }
  354. rcu_read_unlock();
  355. }
  356. void __init sn_irq_lh_init(void)
  357. {
  358. int i;
  359. sn_irq_lh = kmalloc(sizeof(struct list_head *) * NR_IRQS, GFP_KERNEL);
  360. if (!sn_irq_lh)
  361. panic("SN PCI INIT: Failed to allocate memory for PCI init\n");
  362. for (i = 0; i < NR_IRQS; i++) {
  363. sn_irq_lh[i] = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  364. if (!sn_irq_lh[i])
  365. panic("SN PCI INIT: Failed IRQ memory allocation\n");
  366. INIT_LIST_HEAD(sn_irq_lh[i]);
  367. }
  368. }