sm501fb.c 42 KB

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  1. /* linux/drivers/video/sm501fb.c
  2. *
  3. * Copyright (c) 2006 Simtec Electronics
  4. * Vincent Sanders <vince@simtec.co.uk>
  5. * Ben Dooks <ben@simtec.co.uk>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * Framebuffer driver for the Silicon Motion SM501
  12. */
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/string.h>
  17. #include <linux/mm.h>
  18. #include <linux/tty.h>
  19. #include <linux/slab.h>
  20. #include <linux/delay.h>
  21. #include <linux/fb.h>
  22. #include <linux/init.h>
  23. #include <linux/vmalloc.h>
  24. #include <linux/dma-mapping.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/workqueue.h>
  27. #include <linux/wait.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/clk.h>
  30. #include <linux/console.h>
  31. #include <asm/io.h>
  32. #include <asm/uaccess.h>
  33. #include <asm/div64.h>
  34. #ifdef CONFIG_PM
  35. #include <linux/pm.h>
  36. #endif
  37. #include <linux/sm501.h>
  38. #include <linux/sm501-regs.h>
  39. #define NR_PALETTE 256
  40. enum sm501_controller {
  41. HEAD_CRT = 0,
  42. HEAD_PANEL = 1,
  43. };
  44. /* SM501 memory adress */
  45. struct sm501_mem {
  46. unsigned long size;
  47. unsigned long sm_addr;
  48. void __iomem *k_addr;
  49. };
  50. /* private data that is shared between all frambuffers* */
  51. struct sm501fb_info {
  52. struct device *dev;
  53. struct fb_info *fb[2]; /* fb info for both heads */
  54. struct resource *fbmem_res; /* framebuffer resource */
  55. struct resource *regs_res; /* registers resource */
  56. struct sm501_platdata_fb *pdata; /* our platform data */
  57. unsigned long pm_crt_ctrl; /* pm: crt ctrl save */
  58. int irq;
  59. int swap_endian; /* set to swap rgb=>bgr */
  60. void __iomem *regs; /* remapped registers */
  61. void __iomem *fbmem; /* remapped framebuffer */
  62. size_t fbmem_len; /* length of remapped region */
  63. };
  64. /* per-framebuffer private data */
  65. struct sm501fb_par {
  66. u32 pseudo_palette[16];
  67. enum sm501_controller head;
  68. struct sm501_mem cursor;
  69. struct sm501_mem screen;
  70. struct fb_ops ops;
  71. void *store_fb;
  72. void *store_cursor;
  73. void __iomem *cursor_regs;
  74. struct sm501fb_info *info;
  75. };
  76. /* Helper functions */
  77. static inline int h_total(struct fb_var_screeninfo *var)
  78. {
  79. return var->xres + var->left_margin +
  80. var->right_margin + var->hsync_len;
  81. }
  82. static inline int v_total(struct fb_var_screeninfo *var)
  83. {
  84. return var->yres + var->upper_margin +
  85. var->lower_margin + var->vsync_len;
  86. }
  87. /* sm501fb_sync_regs()
  88. *
  89. * This call is mainly for PCI bus systems where we need to
  90. * ensure that any writes to the bus are completed before the
  91. * next phase, or after completing a function.
  92. */
  93. static inline void sm501fb_sync_regs(struct sm501fb_info *info)
  94. {
  95. readl(info->regs);
  96. }
  97. /* sm501_alloc_mem
  98. *
  99. * This is an attempt to lay out memory for the two framebuffers and
  100. * everything else
  101. *
  102. * |fbmem_res->start fbmem_res->end|
  103. * | |
  104. * |fb[0].fix.smem_start | |fb[1].fix.smem_start | 2K |
  105. * |-> fb[0].fix.smem_len <-| spare |-> fb[1].fix.smem_len <-|-> cursors <-|
  106. *
  107. * The "spare" space is for the 2d engine data
  108. * the fixed is space for the cursors (2x1Kbyte)
  109. *
  110. * we need to allocate memory for the 2D acceleration engine
  111. * command list and the data for the engine to deal with.
  112. *
  113. * - all allocations must be 128bit aligned
  114. * - cursors are 64x64x2 bits (1Kbyte)
  115. *
  116. */
  117. #define SM501_MEMF_CURSOR (1)
  118. #define SM501_MEMF_PANEL (2)
  119. #define SM501_MEMF_CRT (4)
  120. #define SM501_MEMF_ACCEL (8)
  121. static int sm501_alloc_mem(struct sm501fb_info *inf, struct sm501_mem *mem,
  122. unsigned int why, size_t size)
  123. {
  124. unsigned int ptr = 0;
  125. switch (why) {
  126. case SM501_MEMF_CURSOR:
  127. ptr = inf->fbmem_len - size;
  128. inf->fbmem_len = ptr;
  129. break;
  130. case SM501_MEMF_PANEL:
  131. ptr = inf->fbmem_len - size;
  132. if (ptr < inf->fb[0]->fix.smem_len)
  133. return -ENOMEM;
  134. break;
  135. case SM501_MEMF_CRT:
  136. ptr = 0;
  137. break;
  138. case SM501_MEMF_ACCEL:
  139. ptr = inf->fb[0]->fix.smem_len;
  140. if ((ptr + size) >
  141. (inf->fb[1]->fix.smem_start - inf->fbmem_res->start))
  142. return -ENOMEM;
  143. break;
  144. default:
  145. return -EINVAL;
  146. }
  147. mem->size = size;
  148. mem->sm_addr = ptr;
  149. mem->k_addr = inf->fbmem + ptr;
  150. dev_dbg(inf->dev, "%s: result %08lx, %p - %u, %zd\n",
  151. __func__, mem->sm_addr, mem->k_addr, why, size);
  152. return 0;
  153. }
  154. /* sm501fb_ps_to_hz
  155. *
  156. * Converts a period in picoseconds to Hz.
  157. *
  158. * Note, we try to keep this in Hz to minimise rounding with
  159. * the limited PLL settings on the SM501.
  160. */
  161. static unsigned long sm501fb_ps_to_hz(unsigned long psvalue)
  162. {
  163. unsigned long long numerator=1000000000000ULL;
  164. /* 10^12 / picosecond period gives frequency in Hz */
  165. do_div(numerator, psvalue);
  166. return (unsigned long)numerator;
  167. }
  168. /* sm501fb_hz_to_ps is identical to the oposite transform */
  169. #define sm501fb_hz_to_ps(x) sm501fb_ps_to_hz(x)
  170. /* sm501fb_setup_gamma
  171. *
  172. * Programs a linear 1.0 gamma ramp in case the gamma
  173. * correction is enabled without programming anything else.
  174. */
  175. static void sm501fb_setup_gamma(struct sm501fb_info *fbi,
  176. unsigned long palette)
  177. {
  178. unsigned long value = 0;
  179. int offset;
  180. /* set gamma values */
  181. for (offset = 0; offset < 256 * 4; offset += 4) {
  182. writel(value, fbi->regs + palette + offset);
  183. value += 0x010101; /* Advance RGB by 1,1,1.*/
  184. }
  185. }
  186. /* sm501fb_check_var
  187. *
  188. * check common variables for both panel and crt
  189. */
  190. static int sm501fb_check_var(struct fb_var_screeninfo *var,
  191. struct fb_info *info)
  192. {
  193. struct sm501fb_par *par = info->par;
  194. struct sm501fb_info *sm = par->info;
  195. unsigned long tmp;
  196. /* check we can fit these values into the registers */
  197. if (var->hsync_len > 255 || var->vsync_len > 255)
  198. return -EINVAL;
  199. if ((var->xres + var->right_margin) >= 4096)
  200. return -EINVAL;
  201. if ((var->yres + var->lower_margin) > 2048)
  202. return -EINVAL;
  203. /* hard limits of device */
  204. if (h_total(var) > 4096 || v_total(var) > 2048)
  205. return -EINVAL;
  206. /* check our line length is going to be 128 bit aligned */
  207. tmp = (var->xres * var->bits_per_pixel) / 8;
  208. if ((tmp & 15) != 0)
  209. return -EINVAL;
  210. /* check the virtual size */
  211. if (var->xres_virtual > 4096 || var->yres_virtual > 2048)
  212. return -EINVAL;
  213. /* can cope with 8,16 or 32bpp */
  214. if (var->bits_per_pixel <= 8)
  215. var->bits_per_pixel = 8;
  216. else if (var->bits_per_pixel <= 16)
  217. var->bits_per_pixel = 16;
  218. else if (var->bits_per_pixel == 24)
  219. var->bits_per_pixel = 32;
  220. /* set r/g/b positions and validate bpp */
  221. switch(var->bits_per_pixel) {
  222. case 8:
  223. var->red.length = var->bits_per_pixel;
  224. var->red.offset = 0;
  225. var->green.length = var->bits_per_pixel;
  226. var->green.offset = 0;
  227. var->blue.length = var->bits_per_pixel;
  228. var->blue.offset = 0;
  229. var->transp.length = 0;
  230. break;
  231. case 16:
  232. if (sm->pdata->flags & SM501_FBPD_SWAP_FB_ENDIAN) {
  233. var->red.offset = 11;
  234. var->green.offset = 5;
  235. var->blue.offset = 0;
  236. } else {
  237. var->blue.offset = 11;
  238. var->green.offset = 5;
  239. var->red.offset = 0;
  240. }
  241. var->red.length = 5;
  242. var->green.length = 6;
  243. var->blue.length = 5;
  244. var->transp.length = 0;
  245. break;
  246. case 32:
  247. if (sm->pdata->flags & SM501_FBPD_SWAP_FB_ENDIAN) {
  248. var->transp.offset = 0;
  249. var->red.offset = 8;
  250. var->green.offset = 16;
  251. var->blue.offset = 24;
  252. } else {
  253. var->transp.offset = 24;
  254. var->red.offset = 16;
  255. var->green.offset = 8;
  256. var->blue.offset = 0;
  257. }
  258. var->red.length = 8;
  259. var->green.length = 8;
  260. var->blue.length = 8;
  261. var->transp.length = 0;
  262. break;
  263. default:
  264. return -EINVAL;
  265. }
  266. return 0;
  267. }
  268. /*
  269. * sm501fb_check_var_crt():
  270. *
  271. * check the parameters for the CRT head, and either bring them
  272. * back into range, or return -EINVAL.
  273. */
  274. static int sm501fb_check_var_crt(struct fb_var_screeninfo *var,
  275. struct fb_info *info)
  276. {
  277. return sm501fb_check_var(var, info);
  278. }
  279. /* sm501fb_check_var_pnl():
  280. *
  281. * check the parameters for the CRT head, and either bring them
  282. * back into range, or return -EINVAL.
  283. */
  284. static int sm501fb_check_var_pnl(struct fb_var_screeninfo *var,
  285. struct fb_info *info)
  286. {
  287. return sm501fb_check_var(var, info);
  288. }
  289. /* sm501fb_set_par_common
  290. *
  291. * set common registers for framebuffers
  292. */
  293. static int sm501fb_set_par_common(struct fb_info *info,
  294. struct fb_var_screeninfo *var)
  295. {
  296. struct sm501fb_par *par = info->par;
  297. struct sm501fb_info *fbi = par->info;
  298. unsigned long pixclock; /* pixelclock in Hz */
  299. unsigned long sm501pixclock; /* pixelclock the 501 can achive in Hz */
  300. unsigned int mem_type;
  301. unsigned int clock_type;
  302. unsigned int head_addr;
  303. dev_dbg(fbi->dev, "%s: %dx%d, bpp = %d, virtual %dx%d\n",
  304. __func__, var->xres, var->yres, var->bits_per_pixel,
  305. var->xres_virtual, var->yres_virtual);
  306. switch (par->head) {
  307. case HEAD_CRT:
  308. mem_type = SM501_MEMF_CRT;
  309. clock_type = SM501_CLOCK_V2XCLK;
  310. head_addr = SM501_DC_CRT_FB_ADDR;
  311. break;
  312. case HEAD_PANEL:
  313. mem_type = SM501_MEMF_PANEL;
  314. clock_type = SM501_CLOCK_P2XCLK;
  315. head_addr = SM501_DC_PANEL_FB_ADDR;
  316. break;
  317. default:
  318. mem_type = 0; /* stop compiler warnings */
  319. head_addr = 0;
  320. clock_type = 0;
  321. }
  322. switch (var->bits_per_pixel) {
  323. case 8:
  324. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  325. break;
  326. case 16:
  327. info->fix.visual = FB_VISUAL_DIRECTCOLOR;
  328. break;
  329. case 32:
  330. info->fix.visual = FB_VISUAL_TRUECOLOR;
  331. break;
  332. }
  333. /* allocate fb memory within 501 */
  334. info->fix.line_length = (var->xres_virtual * var->bits_per_pixel)/8;
  335. info->fix.smem_len = info->fix.line_length * var->yres_virtual;
  336. dev_dbg(fbi->dev, "%s: line length = %u\n", __func__,
  337. info->fix.line_length);
  338. if (sm501_alloc_mem(fbi, &par->screen, mem_type,
  339. info->fix.smem_len)) {
  340. dev_err(fbi->dev, "no memory available\n");
  341. return -ENOMEM;
  342. }
  343. info->fix.smem_start = fbi->fbmem_res->start + par->screen.sm_addr;
  344. info->screen_base = fbi->fbmem + par->screen.sm_addr;
  345. info->screen_size = info->fix.smem_len;
  346. /* set start of framebuffer to the screen */
  347. writel(par->screen.sm_addr | SM501_ADDR_FLIP, fbi->regs + head_addr);
  348. /* program CRT clock */
  349. pixclock = sm501fb_ps_to_hz(var->pixclock);
  350. sm501pixclock = sm501_set_clock(fbi->dev->parent, clock_type,
  351. pixclock);
  352. /* update fb layer with actual clock used */
  353. var->pixclock = sm501fb_hz_to_ps(sm501pixclock);
  354. dev_dbg(fbi->dev, "%s: pixclock(ps) = %u, pixclock(Hz) = %lu, "
  355. "sm501pixclock = %lu, error = %ld%%\n",
  356. __func__, var->pixclock, pixclock, sm501pixclock,
  357. ((pixclock - sm501pixclock)*100)/pixclock);
  358. return 0;
  359. }
  360. /* sm501fb_set_par_geometry
  361. *
  362. * set the geometry registers for specified framebuffer.
  363. */
  364. static void sm501fb_set_par_geometry(struct fb_info *info,
  365. struct fb_var_screeninfo *var)
  366. {
  367. struct sm501fb_par *par = info->par;
  368. struct sm501fb_info *fbi = par->info;
  369. void __iomem *base = fbi->regs;
  370. unsigned long reg;
  371. if (par->head == HEAD_CRT)
  372. base += SM501_DC_CRT_H_TOT;
  373. else
  374. base += SM501_DC_PANEL_H_TOT;
  375. /* set framebuffer width and display width */
  376. reg = info->fix.line_length;
  377. reg |= ((var->xres * var->bits_per_pixel)/8) << 16;
  378. writel(reg, fbi->regs + (par->head == HEAD_CRT ?
  379. SM501_DC_CRT_FB_OFFSET : SM501_DC_PANEL_FB_OFFSET));
  380. /* program horizontal total */
  381. reg = (h_total(var) - 1) << 16;
  382. reg |= (var->xres - 1);
  383. writel(reg, base + SM501_OFF_DC_H_TOT);
  384. /* program horizontal sync */
  385. reg = var->hsync_len << 16;
  386. reg |= var->xres + var->right_margin - 1;
  387. writel(reg, base + SM501_OFF_DC_H_SYNC);
  388. /* program vertical total */
  389. reg = (v_total(var) - 1) << 16;
  390. reg |= (var->yres - 1);
  391. writel(reg, base + SM501_OFF_DC_V_TOT);
  392. /* program vertical sync */
  393. reg = var->vsync_len << 16;
  394. reg |= var->yres + var->lower_margin - 1;
  395. writel(reg, base + SM501_OFF_DC_V_SYNC);
  396. }
  397. /* sm501fb_pan_crt
  398. *
  399. * pan the CRT display output within an virtual framebuffer
  400. */
  401. static int sm501fb_pan_crt(struct fb_var_screeninfo *var,
  402. struct fb_info *info)
  403. {
  404. struct sm501fb_par *par = info->par;
  405. struct sm501fb_info *fbi = par->info;
  406. unsigned int bytes_pixel = var->bits_per_pixel / 8;
  407. unsigned long reg;
  408. unsigned long xoffs;
  409. xoffs = var->xoffset * bytes_pixel;
  410. reg = readl(fbi->regs + SM501_DC_CRT_CONTROL);
  411. reg &= ~SM501_DC_CRT_CONTROL_PIXEL_MASK;
  412. reg |= ((xoffs & 15) / bytes_pixel) << 4;
  413. writel(reg, fbi->regs + SM501_DC_CRT_CONTROL);
  414. reg = (par->screen.sm_addr + xoffs +
  415. var->yoffset * info->fix.line_length);
  416. writel(reg | SM501_ADDR_FLIP, fbi->regs + SM501_DC_CRT_FB_ADDR);
  417. sm501fb_sync_regs(fbi);
  418. return 0;
  419. }
  420. /* sm501fb_pan_pnl
  421. *
  422. * pan the panel display output within an virtual framebuffer
  423. */
  424. static int sm501fb_pan_pnl(struct fb_var_screeninfo *var,
  425. struct fb_info *info)
  426. {
  427. struct sm501fb_par *par = info->par;
  428. struct sm501fb_info *fbi = par->info;
  429. unsigned long reg;
  430. reg = var->xoffset | (var->xres_virtual << 16);
  431. writel(reg, fbi->regs + SM501_DC_PANEL_FB_WIDTH);
  432. reg = var->yoffset | (var->yres_virtual << 16);
  433. writel(reg, fbi->regs + SM501_DC_PANEL_FB_HEIGHT);
  434. sm501fb_sync_regs(fbi);
  435. return 0;
  436. }
  437. /* sm501fb_set_par_crt
  438. *
  439. * Set the CRT video mode from the fb_info structure
  440. */
  441. static int sm501fb_set_par_crt(struct fb_info *info)
  442. {
  443. struct sm501fb_par *par = info->par;
  444. struct sm501fb_info *fbi = par->info;
  445. struct fb_var_screeninfo *var = &info->var;
  446. unsigned long control; /* control register */
  447. int ret;
  448. /* activate new configuration */
  449. dev_dbg(fbi->dev, "%s(%p)\n", __func__, info);
  450. /* enable CRT DAC - note 0 is on!*/
  451. sm501_misc_control(fbi->dev->parent, 0, SM501_MISC_DAC_POWER);
  452. control = readl(fbi->regs + SM501_DC_CRT_CONTROL);
  453. control &= (SM501_DC_CRT_CONTROL_PIXEL_MASK |
  454. SM501_DC_CRT_CONTROL_GAMMA |
  455. SM501_DC_CRT_CONTROL_BLANK |
  456. SM501_DC_CRT_CONTROL_SEL |
  457. SM501_DC_CRT_CONTROL_CP |
  458. SM501_DC_CRT_CONTROL_TVP);
  459. /* set the sync polarities before we check data source */
  460. if ((var->sync & FB_SYNC_HOR_HIGH_ACT) == 0)
  461. control |= SM501_DC_CRT_CONTROL_HSP;
  462. if ((var->sync & FB_SYNC_VERT_HIGH_ACT) == 0)
  463. control |= SM501_DC_CRT_CONTROL_VSP;
  464. if ((control & SM501_DC_CRT_CONTROL_SEL) == 0) {
  465. /* the head is displaying panel data... */
  466. sm501_alloc_mem(fbi, &par->screen, SM501_MEMF_CRT, 0);
  467. goto out_update;
  468. }
  469. ret = sm501fb_set_par_common(info, var);
  470. if (ret) {
  471. dev_err(fbi->dev, "failed to set common parameters\n");
  472. return ret;
  473. }
  474. sm501fb_pan_crt(var, info);
  475. sm501fb_set_par_geometry(info, var);
  476. control |= SM501_FIFO_3; /* fill if >3 free slots */
  477. switch(var->bits_per_pixel) {
  478. case 8:
  479. control |= SM501_DC_CRT_CONTROL_8BPP;
  480. break;
  481. case 16:
  482. control |= SM501_DC_CRT_CONTROL_16BPP;
  483. break;
  484. case 32:
  485. control |= SM501_DC_CRT_CONTROL_32BPP;
  486. sm501fb_setup_gamma(fbi, SM501_DC_CRT_PALETTE);
  487. break;
  488. default:
  489. BUG();
  490. }
  491. control |= SM501_DC_CRT_CONTROL_SEL; /* CRT displays CRT data */
  492. control |= SM501_DC_CRT_CONTROL_TE; /* enable CRT timing */
  493. control |= SM501_DC_CRT_CONTROL_ENABLE; /* enable CRT plane */
  494. out_update:
  495. dev_dbg(fbi->dev, "new control is %08lx\n", control);
  496. writel(control, fbi->regs + SM501_DC_CRT_CONTROL);
  497. sm501fb_sync_regs(fbi);
  498. return 0;
  499. }
  500. static void sm501fb_panel_power(struct sm501fb_info *fbi, int to)
  501. {
  502. unsigned long control;
  503. void __iomem *ctrl_reg = fbi->regs + SM501_DC_PANEL_CONTROL;
  504. control = readl(ctrl_reg);
  505. if (to && (control & SM501_DC_PANEL_CONTROL_VDD) == 0) {
  506. /* enable panel power */
  507. control |= SM501_DC_PANEL_CONTROL_VDD; /* FPVDDEN */
  508. writel(control, ctrl_reg);
  509. sm501fb_sync_regs(fbi);
  510. mdelay(10);
  511. control |= SM501_DC_PANEL_CONTROL_DATA; /* DATA */
  512. writel(control, ctrl_reg);
  513. sm501fb_sync_regs(fbi);
  514. mdelay(10);
  515. control |= SM501_DC_PANEL_CONTROL_BIAS; /* VBIASEN */
  516. writel(control, ctrl_reg);
  517. sm501fb_sync_regs(fbi);
  518. mdelay(10);
  519. control |= SM501_DC_PANEL_CONTROL_FPEN;
  520. writel(control, ctrl_reg);
  521. } else if (!to && (control & SM501_DC_PANEL_CONTROL_VDD) != 0) {
  522. /* disable panel power */
  523. control &= ~SM501_DC_PANEL_CONTROL_FPEN;
  524. writel(control, ctrl_reg);
  525. sm501fb_sync_regs(fbi);
  526. mdelay(10);
  527. control &= ~SM501_DC_PANEL_CONTROL_BIAS;
  528. writel(control, ctrl_reg);
  529. sm501fb_sync_regs(fbi);
  530. mdelay(10);
  531. control &= ~SM501_DC_PANEL_CONTROL_DATA;
  532. writel(control, ctrl_reg);
  533. sm501fb_sync_regs(fbi);
  534. mdelay(10);
  535. control &= ~SM501_DC_PANEL_CONTROL_VDD;
  536. writel(control, ctrl_reg);
  537. sm501fb_sync_regs(fbi);
  538. mdelay(10);
  539. }
  540. sm501fb_sync_regs(fbi);
  541. }
  542. /* sm501fb_set_par_pnl
  543. *
  544. * Set the panel video mode from the fb_info structure
  545. */
  546. static int sm501fb_set_par_pnl(struct fb_info *info)
  547. {
  548. struct sm501fb_par *par = info->par;
  549. struct sm501fb_info *fbi = par->info;
  550. struct fb_var_screeninfo *var = &info->var;
  551. unsigned long control;
  552. unsigned long reg;
  553. int ret;
  554. dev_dbg(fbi->dev, "%s(%p)\n", __func__, info);
  555. /* activate this new configuration */
  556. ret = sm501fb_set_par_common(info, var);
  557. if (ret)
  558. return ret;
  559. sm501fb_pan_pnl(var, info);
  560. sm501fb_set_par_geometry(info, var);
  561. /* update control register */
  562. control = readl(fbi->regs + SM501_DC_PANEL_CONTROL);
  563. control &= (SM501_DC_PANEL_CONTROL_GAMMA |
  564. SM501_DC_PANEL_CONTROL_VDD |
  565. SM501_DC_PANEL_CONTROL_DATA |
  566. SM501_DC_PANEL_CONTROL_BIAS |
  567. SM501_DC_PANEL_CONTROL_FPEN |
  568. SM501_DC_PANEL_CONTROL_CP |
  569. SM501_DC_PANEL_CONTROL_CK |
  570. SM501_DC_PANEL_CONTROL_HP |
  571. SM501_DC_PANEL_CONTROL_VP |
  572. SM501_DC_PANEL_CONTROL_HPD |
  573. SM501_DC_PANEL_CONTROL_VPD);
  574. control |= SM501_FIFO_3; /* fill if >3 free slots */
  575. switch(var->bits_per_pixel) {
  576. case 8:
  577. control |= SM501_DC_PANEL_CONTROL_8BPP;
  578. break;
  579. case 16:
  580. control |= SM501_DC_PANEL_CONTROL_16BPP;
  581. break;
  582. case 32:
  583. control |= SM501_DC_PANEL_CONTROL_32BPP;
  584. sm501fb_setup_gamma(fbi, SM501_DC_PANEL_PALETTE);
  585. break;
  586. default:
  587. BUG();
  588. }
  589. writel(0x0, fbi->regs + SM501_DC_PANEL_PANNING_CONTROL);
  590. /* panel plane top left and bottom right location */
  591. writel(0x00, fbi->regs + SM501_DC_PANEL_TL_LOC);
  592. reg = var->xres - 1;
  593. reg |= (var->yres - 1) << 16;
  594. writel(reg, fbi->regs + SM501_DC_PANEL_BR_LOC);
  595. /* program panel control register */
  596. control |= SM501_DC_PANEL_CONTROL_TE; /* enable PANEL timing */
  597. control |= SM501_DC_PANEL_CONTROL_EN; /* enable PANEL gfx plane */
  598. if ((var->sync & FB_SYNC_HOR_HIGH_ACT) == 0)
  599. control |= SM501_DC_PANEL_CONTROL_HSP;
  600. if ((var->sync & FB_SYNC_VERT_HIGH_ACT) == 0)
  601. control |= SM501_DC_PANEL_CONTROL_VSP;
  602. writel(control, fbi->regs + SM501_DC_PANEL_CONTROL);
  603. sm501fb_sync_regs(fbi);
  604. /* power the panel up */
  605. sm501fb_panel_power(fbi, 1);
  606. return 0;
  607. }
  608. /* chan_to_field
  609. *
  610. * convert a colour value into a field position
  611. *
  612. * from pxafb.c
  613. */
  614. static inline unsigned int chan_to_field(unsigned int chan,
  615. struct fb_bitfield *bf)
  616. {
  617. chan &= 0xffff;
  618. chan >>= 16 - bf->length;
  619. return chan << bf->offset;
  620. }
  621. /* sm501fb_setcolreg
  622. *
  623. * set the colour mapping for modes that support palettised data
  624. */
  625. static int sm501fb_setcolreg(unsigned regno,
  626. unsigned red, unsigned green, unsigned blue,
  627. unsigned transp, struct fb_info *info)
  628. {
  629. struct sm501fb_par *par = info->par;
  630. struct sm501fb_info *fbi = par->info;
  631. void __iomem *base = fbi->regs;
  632. unsigned int val;
  633. if (par->head == HEAD_CRT)
  634. base += SM501_DC_CRT_PALETTE;
  635. else
  636. base += SM501_DC_PANEL_PALETTE;
  637. switch (info->fix.visual) {
  638. case FB_VISUAL_TRUECOLOR:
  639. /* true-colour, use pseuo-palette */
  640. if (regno < 16) {
  641. u32 *pal = par->pseudo_palette;
  642. val = chan_to_field(red, &info->var.red);
  643. val |= chan_to_field(green, &info->var.green);
  644. val |= chan_to_field(blue, &info->var.blue);
  645. pal[regno] = val;
  646. }
  647. break;
  648. case FB_VISUAL_PSEUDOCOLOR:
  649. if (regno < 256) {
  650. val = (red >> 8) << 16;
  651. val |= (green >> 8) << 8;
  652. val |= blue >> 8;
  653. writel(val, base + (regno * 4));
  654. }
  655. break;
  656. default:
  657. return 1; /* unknown type */
  658. }
  659. return 0;
  660. }
  661. /* sm501fb_blank_pnl
  662. *
  663. * Blank or un-blank the panel interface
  664. */
  665. static int sm501fb_blank_pnl(int blank_mode, struct fb_info *info)
  666. {
  667. struct sm501fb_par *par = info->par;
  668. struct sm501fb_info *fbi = par->info;
  669. dev_dbg(fbi->dev, "%s(mode=%d, %p)\n", __func__, blank_mode, info);
  670. switch (blank_mode) {
  671. case FB_BLANK_POWERDOWN:
  672. sm501fb_panel_power(fbi, 0);
  673. break;
  674. case FB_BLANK_UNBLANK:
  675. sm501fb_panel_power(fbi, 1);
  676. break;
  677. case FB_BLANK_NORMAL:
  678. case FB_BLANK_VSYNC_SUSPEND:
  679. case FB_BLANK_HSYNC_SUSPEND:
  680. default:
  681. return 1;
  682. }
  683. return 0;
  684. }
  685. /* sm501fb_blank_crt
  686. *
  687. * Blank or un-blank the crt interface
  688. */
  689. static int sm501fb_blank_crt(int blank_mode, struct fb_info *info)
  690. {
  691. struct sm501fb_par *par = info->par;
  692. struct sm501fb_info *fbi = par->info;
  693. unsigned long ctrl;
  694. dev_dbg(fbi->dev, "%s(mode=%d, %p)\n", __func__, blank_mode, info);
  695. ctrl = readl(fbi->regs + SM501_DC_CRT_CONTROL);
  696. switch (blank_mode) {
  697. case FB_BLANK_POWERDOWN:
  698. ctrl &= ~SM501_DC_CRT_CONTROL_ENABLE;
  699. sm501_misc_control(fbi->dev->parent, SM501_MISC_DAC_POWER, 0);
  700. case FB_BLANK_NORMAL:
  701. ctrl |= SM501_DC_CRT_CONTROL_BLANK;
  702. break;
  703. case FB_BLANK_UNBLANK:
  704. ctrl &= ~SM501_DC_CRT_CONTROL_BLANK;
  705. ctrl |= SM501_DC_CRT_CONTROL_ENABLE;
  706. sm501_misc_control(fbi->dev->parent, 0, SM501_MISC_DAC_POWER);
  707. break;
  708. case FB_BLANK_VSYNC_SUSPEND:
  709. case FB_BLANK_HSYNC_SUSPEND:
  710. default:
  711. return 1;
  712. }
  713. writel(ctrl, fbi->regs + SM501_DC_CRT_CONTROL);
  714. sm501fb_sync_regs(fbi);
  715. return 0;
  716. }
  717. /* sm501fb_cursor
  718. *
  719. * set or change the hardware cursor parameters
  720. */
  721. static int sm501fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
  722. {
  723. struct sm501fb_par *par = info->par;
  724. struct sm501fb_info *fbi = par->info;
  725. void __iomem *base = fbi->regs;
  726. unsigned long hwc_addr;
  727. unsigned long fg, bg;
  728. dev_dbg(fbi->dev, "%s(%p,%p)\n", __func__, info, cursor);
  729. if (par->head == HEAD_CRT)
  730. base += SM501_DC_CRT_HWC_BASE;
  731. else
  732. base += SM501_DC_PANEL_HWC_BASE;
  733. /* check not being asked to exceed capabilities */
  734. if (cursor->image.width > 64)
  735. return -EINVAL;
  736. if (cursor->image.height > 64)
  737. return -EINVAL;
  738. if (cursor->image.depth > 1)
  739. return -EINVAL;
  740. hwc_addr = readl(base + SM501_OFF_HWC_ADDR);
  741. if (cursor->enable)
  742. writel(hwc_addr | SM501_HWC_EN, base + SM501_OFF_HWC_ADDR);
  743. else
  744. writel(hwc_addr & ~SM501_HWC_EN, base + SM501_OFF_HWC_ADDR);
  745. /* set data */
  746. if (cursor->set & FB_CUR_SETPOS) {
  747. unsigned int x = cursor->image.dx;
  748. unsigned int y = cursor->image.dy;
  749. if (x >= 2048 || y >= 2048 )
  750. return -EINVAL;
  751. dev_dbg(fbi->dev, "set position %d,%d\n", x, y);
  752. //y += cursor->image.height;
  753. writel(x | (y << 16), base + SM501_OFF_HWC_LOC);
  754. }
  755. if (cursor->set & FB_CUR_SETCMAP) {
  756. unsigned int bg_col = cursor->image.bg_color;
  757. unsigned int fg_col = cursor->image.fg_color;
  758. dev_dbg(fbi->dev, "%s: update cmap (%08x,%08x)\n",
  759. __func__, bg_col, fg_col);
  760. bg = ((info->cmap.red[bg_col] & 0xF8) << 8) |
  761. ((info->cmap.green[bg_col] & 0xFC) << 3) |
  762. ((info->cmap.blue[bg_col] & 0xF8) >> 3);
  763. fg = ((info->cmap.red[fg_col] & 0xF8) << 8) |
  764. ((info->cmap.green[fg_col] & 0xFC) << 3) |
  765. ((info->cmap.blue[fg_col] & 0xF8) >> 3);
  766. dev_dbg(fbi->dev, "fgcol %08lx, bgcol %08lx\n", fg, bg);
  767. writel(bg, base + SM501_OFF_HWC_COLOR_1_2);
  768. writel(fg, base + SM501_OFF_HWC_COLOR_3);
  769. }
  770. if (cursor->set & FB_CUR_SETSIZE ||
  771. cursor->set & (FB_CUR_SETIMAGE | FB_CUR_SETSHAPE)) {
  772. /* SM501 cursor is a two bpp 64x64 bitmap this routine
  773. * clears it to transparent then combines the cursor
  774. * shape plane with the colour plane to set the
  775. * cursor */
  776. int x, y;
  777. const unsigned char *pcol = cursor->image.data;
  778. const unsigned char *pmsk = cursor->mask;
  779. void __iomem *dst = par->cursor.k_addr;
  780. unsigned char dcol = 0;
  781. unsigned char dmsk = 0;
  782. unsigned int op;
  783. dev_dbg(fbi->dev, "%s: setting shape (%d,%d)\n",
  784. __func__, cursor->image.width, cursor->image.height);
  785. for (op = 0; op < (64*64*2)/8; op+=4)
  786. writel(0x0, dst + op);
  787. for (y = 0; y < cursor->image.height; y++) {
  788. for (x = 0; x < cursor->image.width; x++) {
  789. if ((x % 8) == 0) {
  790. dcol = *pcol++;
  791. dmsk = *pmsk++;
  792. } else {
  793. dcol >>= 1;
  794. dmsk >>= 1;
  795. }
  796. if (dmsk & 1) {
  797. op = (dcol & 1) ? 1 : 3;
  798. op <<= ((x % 4) * 2);
  799. op |= readb(dst + (x / 4));
  800. writeb(op, dst + (x / 4));
  801. }
  802. }
  803. dst += (64*2)/8;
  804. }
  805. }
  806. sm501fb_sync_regs(fbi); /* ensure cursor data flushed */
  807. return 0;
  808. }
  809. /* sm501fb_crtsrc_show
  810. *
  811. * device attribute code to show where the crt output is sourced from
  812. */
  813. static ssize_t sm501fb_crtsrc_show(struct device *dev,
  814. struct device_attribute *attr, char *buf)
  815. {
  816. struct sm501fb_info *info = dev_get_drvdata(dev);
  817. unsigned long ctrl;
  818. ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
  819. ctrl &= SM501_DC_CRT_CONTROL_SEL;
  820. return snprintf(buf, PAGE_SIZE, "%s\n", ctrl ? "crt" : "panel");
  821. }
  822. /* sm501fb_crtsrc_show
  823. *
  824. * device attribute code to set where the crt output is sourced from
  825. */
  826. static ssize_t sm501fb_crtsrc_store(struct device *dev,
  827. struct device_attribute *attr,
  828. const char *buf, size_t len)
  829. {
  830. struct sm501fb_info *info = dev_get_drvdata(dev);
  831. enum sm501_controller head;
  832. unsigned long ctrl;
  833. if (len < 1)
  834. return -EINVAL;
  835. if (strnicmp(buf, "crt", 3) == 0)
  836. head = HEAD_CRT;
  837. else if (strnicmp(buf, "panel", 5) == 0)
  838. head = HEAD_PANEL;
  839. else
  840. return -EINVAL;
  841. dev_info(dev, "setting crt source to head %d\n", head);
  842. ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
  843. if (head == HEAD_CRT) {
  844. ctrl |= SM501_DC_CRT_CONTROL_SEL;
  845. ctrl |= SM501_DC_CRT_CONTROL_ENABLE;
  846. ctrl |= SM501_DC_CRT_CONTROL_TE;
  847. } else {
  848. ctrl &= ~SM501_DC_CRT_CONTROL_SEL;
  849. ctrl &= ~SM501_DC_CRT_CONTROL_ENABLE;
  850. ctrl &= ~SM501_DC_CRT_CONTROL_TE;
  851. }
  852. writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
  853. sm501fb_sync_regs(info);
  854. return len;
  855. }
  856. /* Prepare the device_attr for registration with sysfs later */
  857. static DEVICE_ATTR(crt_src, 0666, sm501fb_crtsrc_show, sm501fb_crtsrc_store);
  858. /* sm501fb_show_regs
  859. *
  860. * show the primary sm501 registers
  861. */
  862. static int sm501fb_show_regs(struct sm501fb_info *info, char *ptr,
  863. unsigned int start, unsigned int len)
  864. {
  865. void __iomem *mem = info->regs;
  866. char *buf = ptr;
  867. unsigned int reg;
  868. for (reg = start; reg < (len + start); reg += 4)
  869. ptr += sprintf(ptr, "%08x = %08x\n", reg, readl(mem + reg));
  870. return ptr - buf;
  871. }
  872. /* sm501fb_debug_show_crt
  873. *
  874. * show the crt control and cursor registers
  875. */
  876. static ssize_t sm501fb_debug_show_crt(struct device *dev,
  877. struct device_attribute *attr, char *buf)
  878. {
  879. struct sm501fb_info *info = dev_get_drvdata(dev);
  880. char *ptr = buf;
  881. ptr += sm501fb_show_regs(info, ptr, SM501_DC_CRT_CONTROL, 0x40);
  882. ptr += sm501fb_show_regs(info, ptr, SM501_DC_CRT_HWC_BASE, 0x10);
  883. return ptr - buf;
  884. }
  885. static DEVICE_ATTR(fbregs_crt, 0444, sm501fb_debug_show_crt, NULL);
  886. /* sm501fb_debug_show_pnl
  887. *
  888. * show the panel control and cursor registers
  889. */
  890. static ssize_t sm501fb_debug_show_pnl(struct device *dev,
  891. struct device_attribute *attr, char *buf)
  892. {
  893. struct sm501fb_info *info = dev_get_drvdata(dev);
  894. char *ptr = buf;
  895. ptr += sm501fb_show_regs(info, ptr, 0x0, 0x40);
  896. ptr += sm501fb_show_regs(info, ptr, SM501_DC_PANEL_HWC_BASE, 0x10);
  897. return ptr - buf;
  898. }
  899. static DEVICE_ATTR(fbregs_pnl, 0444, sm501fb_debug_show_pnl, NULL);
  900. /* framebuffer ops */
  901. static struct fb_ops sm501fb_ops_crt = {
  902. .owner = THIS_MODULE,
  903. .fb_check_var = sm501fb_check_var_crt,
  904. .fb_set_par = sm501fb_set_par_crt,
  905. .fb_blank = sm501fb_blank_crt,
  906. .fb_setcolreg = sm501fb_setcolreg,
  907. .fb_pan_display = sm501fb_pan_crt,
  908. .fb_cursor = sm501fb_cursor,
  909. .fb_fillrect = cfb_fillrect,
  910. .fb_copyarea = cfb_copyarea,
  911. .fb_imageblit = cfb_imageblit,
  912. };
  913. static struct fb_ops sm501fb_ops_pnl = {
  914. .owner = THIS_MODULE,
  915. .fb_check_var = sm501fb_check_var_pnl,
  916. .fb_set_par = sm501fb_set_par_pnl,
  917. .fb_pan_display = sm501fb_pan_pnl,
  918. .fb_blank = sm501fb_blank_pnl,
  919. .fb_setcolreg = sm501fb_setcolreg,
  920. .fb_cursor = sm501fb_cursor,
  921. .fb_fillrect = cfb_fillrect,
  922. .fb_copyarea = cfb_copyarea,
  923. .fb_imageblit = cfb_imageblit,
  924. };
  925. /* sm501fb_info_alloc
  926. *
  927. * creates and initialises an sm501fb_info structure
  928. */
  929. static struct sm501fb_info *sm501fb_info_alloc(struct fb_info *fbinfo_crt,
  930. struct fb_info *fbinfo_pnl)
  931. {
  932. struct sm501fb_info *info;
  933. struct sm501fb_par *par;
  934. info = kzalloc(sizeof(struct sm501fb_info), GFP_KERNEL);
  935. if (info) {
  936. /* set the references back */
  937. par = fbinfo_crt->par;
  938. par->info = info;
  939. par->head = HEAD_CRT;
  940. fbinfo_crt->pseudo_palette = &par->pseudo_palette;
  941. par = fbinfo_pnl->par;
  942. par->info = info;
  943. par->head = HEAD_PANEL;
  944. fbinfo_pnl->pseudo_palette = &par->pseudo_palette;
  945. /* store the two fbs into our info */
  946. info->fb[HEAD_CRT] = fbinfo_crt;
  947. info->fb[HEAD_PANEL] = fbinfo_pnl;
  948. }
  949. return info;
  950. }
  951. /* sm501_init_cursor
  952. *
  953. * initialise hw cursor parameters
  954. */
  955. static int sm501_init_cursor(struct fb_info *fbi, unsigned int reg_base)
  956. {
  957. struct sm501fb_par *par = fbi->par;
  958. struct sm501fb_info *info = par->info;
  959. int ret;
  960. par->cursor_regs = info->regs + reg_base;
  961. ret = sm501_alloc_mem(info, &par->cursor, SM501_MEMF_CURSOR, 1024);
  962. if (ret < 0)
  963. return ret;
  964. /* initialise the colour registers */
  965. writel(par->cursor.sm_addr, par->cursor_regs + SM501_OFF_HWC_ADDR);
  966. writel(0x00, par->cursor_regs + SM501_OFF_HWC_LOC);
  967. writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_1_2);
  968. writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_3);
  969. sm501fb_sync_regs(info);
  970. return 0;
  971. }
  972. /* sm501fb_info_start
  973. *
  974. * fills the par structure claiming resources and remapping etc.
  975. */
  976. static int sm501fb_start(struct sm501fb_info *info,
  977. struct platform_device *pdev)
  978. {
  979. struct resource *res;
  980. struct device *dev;
  981. int ret;
  982. info->dev = dev = &pdev->dev;
  983. platform_set_drvdata(pdev, info);
  984. info->irq = ret = platform_get_irq(pdev, 0);
  985. if (ret < 0) {
  986. /* we currently do not use the IRQ */
  987. dev_warn(dev, "no irq for device\n");
  988. }
  989. /* allocate, reserve and remap resources for registers */
  990. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  991. if (res == NULL) {
  992. dev_err(dev, "no resource definition for registers\n");
  993. ret = -ENOENT;
  994. goto err_release;
  995. }
  996. info->regs_res = request_mem_region(res->start,
  997. res->end - res->start,
  998. pdev->name);
  999. if (info->regs_res == NULL) {
  1000. dev_err(dev, "cannot claim registers\n");
  1001. ret = -ENXIO;
  1002. goto err_release;
  1003. }
  1004. info->regs = ioremap(res->start, (res->end - res->start)+1);
  1005. if (info->regs == NULL) {
  1006. dev_err(dev, "cannot remap registers\n");
  1007. ret = -ENXIO;
  1008. goto err_regs_res;
  1009. }
  1010. /* allocate, reserve resources for framebuffer */
  1011. res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
  1012. if (res == NULL) {
  1013. dev_err(dev, "no memory resource defined\n");
  1014. ret = -ENXIO;
  1015. goto err_regs_map;
  1016. }
  1017. info->fbmem_res = request_mem_region(res->start,
  1018. (res->end - res->start)+1,
  1019. pdev->name);
  1020. if (info->fbmem_res == NULL) {
  1021. dev_err(dev, "cannot claim framebuffer\n");
  1022. ret = -ENXIO;
  1023. goto err_regs_map;
  1024. }
  1025. info->fbmem = ioremap(res->start, (res->end - res->start)+1);
  1026. if (info->fbmem == NULL) {
  1027. dev_err(dev, "cannot remap framebuffer\n");
  1028. goto err_mem_res;
  1029. }
  1030. info->fbmem_len = (res->end - res->start)+1;
  1031. /* enable display controller */
  1032. sm501_unit_power(dev->parent, SM501_GATE_DISPLAY, 1);
  1033. /* setup cursors */
  1034. sm501_init_cursor(info->fb[HEAD_CRT], SM501_DC_CRT_HWC_ADDR);
  1035. sm501_init_cursor(info->fb[HEAD_PANEL], SM501_DC_PANEL_HWC_ADDR);
  1036. return 0; /* everything is setup */
  1037. err_mem_res:
  1038. release_resource(info->fbmem_res);
  1039. kfree(info->fbmem_res);
  1040. err_regs_map:
  1041. iounmap(info->regs);
  1042. err_regs_res:
  1043. release_resource(info->regs_res);
  1044. kfree(info->regs_res);
  1045. err_release:
  1046. return ret;
  1047. }
  1048. static void sm501fb_stop(struct sm501fb_info *info)
  1049. {
  1050. /* disable display controller */
  1051. sm501_unit_power(info->dev->parent, SM501_GATE_DISPLAY, 0);
  1052. iounmap(info->fbmem);
  1053. release_resource(info->fbmem_res);
  1054. kfree(info->fbmem_res);
  1055. iounmap(info->regs);
  1056. release_resource(info->regs_res);
  1057. kfree(info->regs_res);
  1058. }
  1059. static void sm501fb_info_release(struct sm501fb_info *info)
  1060. {
  1061. kfree(info);
  1062. }
  1063. static int sm501fb_init_fb(struct fb_info *fb,
  1064. enum sm501_controller head,
  1065. const char *fbname)
  1066. {
  1067. struct sm501_platdata_fbsub *pd;
  1068. struct sm501fb_par *par = fb->par;
  1069. struct sm501fb_info *info = par->info;
  1070. unsigned long ctrl;
  1071. unsigned int enable;
  1072. int ret;
  1073. switch (head) {
  1074. case HEAD_CRT:
  1075. pd = info->pdata->fb_crt;
  1076. ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
  1077. enable = (ctrl & SM501_DC_CRT_CONTROL_ENABLE) ? 1 : 0;
  1078. /* ensure we set the correct source register */
  1079. if (info->pdata->fb_route != SM501_FB_CRT_PANEL) {
  1080. ctrl |= SM501_DC_CRT_CONTROL_SEL;
  1081. writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
  1082. }
  1083. break;
  1084. case HEAD_PANEL:
  1085. pd = info->pdata->fb_pnl;
  1086. ctrl = readl(info->regs + SM501_DC_PANEL_CONTROL);
  1087. enable = (ctrl & SM501_DC_PANEL_CONTROL_EN) ? 1 : 0;
  1088. break;
  1089. default:
  1090. pd = NULL; /* stop compiler warnings */
  1091. ctrl = 0;
  1092. enable = 0;
  1093. BUG();
  1094. }
  1095. dev_info(info->dev, "fb %s %sabled at start\n",
  1096. fbname, enable ? "en" : "dis");
  1097. /* check to see if our routing allows this */
  1098. if (head == HEAD_CRT && info->pdata->fb_route == SM501_FB_CRT_PANEL) {
  1099. ctrl &= ~SM501_DC_CRT_CONTROL_SEL;
  1100. writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
  1101. enable = 0;
  1102. }
  1103. strlcpy(fb->fix.id, fbname, sizeof(fb->fix.id));
  1104. memcpy(&par->ops,
  1105. (head == HEAD_CRT) ? &sm501fb_ops_crt : &sm501fb_ops_pnl,
  1106. sizeof(struct fb_ops));
  1107. /* update ops dependant on what we've been passed */
  1108. if ((pd->flags & SM501FB_FLAG_USE_HWCURSOR) == 0)
  1109. par->ops.fb_cursor = NULL;
  1110. fb->fbops = &par->ops;
  1111. fb->flags = FBINFO_FLAG_DEFAULT |
  1112. FBINFO_HWACCEL_XPAN | FBINFO_HWACCEL_YPAN;
  1113. /* fixed data */
  1114. fb->fix.type = FB_TYPE_PACKED_PIXELS;
  1115. fb->fix.type_aux = 0;
  1116. fb->fix.xpanstep = 1;
  1117. fb->fix.ypanstep = 1;
  1118. fb->fix.ywrapstep = 0;
  1119. fb->fix.accel = FB_ACCEL_NONE;
  1120. /* screenmode */
  1121. fb->var.nonstd = 0;
  1122. fb->var.activate = FB_ACTIVATE_NOW;
  1123. fb->var.accel_flags = 0;
  1124. fb->var.vmode = FB_VMODE_NONINTERLACED;
  1125. fb->var.bits_per_pixel = 16;
  1126. if (enable && (pd->flags & SM501FB_FLAG_USE_INIT_MODE) && 0) {
  1127. /* TODO read the mode from the current display */
  1128. } else {
  1129. if (pd->def_mode) {
  1130. dev_info(info->dev, "using supplied mode\n");
  1131. fb_videomode_to_var(&fb->var, pd->def_mode);
  1132. fb->var.bits_per_pixel = pd->def_bpp ? pd->def_bpp : 8;
  1133. fb->var.xres_virtual = fb->var.xres;
  1134. fb->var.yres_virtual = fb->var.yres;
  1135. } else {
  1136. ret = fb_find_mode(&fb->var, fb,
  1137. NULL, NULL, 0, NULL, 8);
  1138. if (ret == 0 || ret == 4) {
  1139. dev_err(info->dev,
  1140. "failed to get initial mode\n");
  1141. return -EINVAL;
  1142. }
  1143. }
  1144. }
  1145. /* initialise and set the palette */
  1146. fb_alloc_cmap(&fb->cmap, NR_PALETTE, 0);
  1147. fb_set_cmap(&fb->cmap, fb);
  1148. ret = (fb->fbops->fb_check_var)(&fb->var, fb);
  1149. if (ret)
  1150. dev_err(info->dev, "check_var() failed on initial setup?\n");
  1151. /* ensure we've activated our new configuration */
  1152. (fb->fbops->fb_set_par)(fb);
  1153. return 0;
  1154. }
  1155. /* default platform data if none is supplied (ie, PCI device) */
  1156. static struct sm501_platdata_fbsub sm501fb_pdata_crt = {
  1157. .flags = (SM501FB_FLAG_USE_INIT_MODE |
  1158. SM501FB_FLAG_USE_HWCURSOR |
  1159. SM501FB_FLAG_USE_HWACCEL |
  1160. SM501FB_FLAG_DISABLE_AT_EXIT),
  1161. };
  1162. static struct sm501_platdata_fbsub sm501fb_pdata_pnl = {
  1163. .flags = (SM501FB_FLAG_USE_INIT_MODE |
  1164. SM501FB_FLAG_USE_HWCURSOR |
  1165. SM501FB_FLAG_USE_HWACCEL |
  1166. SM501FB_FLAG_DISABLE_AT_EXIT),
  1167. };
  1168. static struct sm501_platdata_fb sm501fb_def_pdata = {
  1169. .fb_route = SM501_FB_OWN,
  1170. .fb_crt = &sm501fb_pdata_crt,
  1171. .fb_pnl = &sm501fb_pdata_pnl,
  1172. };
  1173. static char driver_name_crt[] = "sm501fb-crt";
  1174. static char driver_name_pnl[] = "sm501fb-panel";
  1175. static int __init sm501fb_probe(struct platform_device *pdev)
  1176. {
  1177. struct sm501fb_info *info;
  1178. struct device *dev = &pdev->dev;
  1179. struct fb_info *fbinfo_crt;
  1180. struct fb_info *fbinfo_pnl;
  1181. int ret;
  1182. /* allocate our framebuffers */
  1183. fbinfo_crt = framebuffer_alloc(sizeof(struct sm501fb_par), dev);
  1184. if (fbinfo_crt == NULL) {
  1185. dev_err(dev, "cannot allocate crt framebuffer\n");
  1186. return -ENOMEM;
  1187. }
  1188. fbinfo_pnl = framebuffer_alloc(sizeof(struct sm501fb_par), dev);
  1189. if (fbinfo_pnl == NULL) {
  1190. dev_err(dev, "cannot allocate panel framebuffer\n");
  1191. ret = -ENOMEM;
  1192. goto fbinfo_crt_alloc_fail;
  1193. }
  1194. info = sm501fb_info_alloc(fbinfo_crt, fbinfo_pnl);
  1195. if (info == NULL) {
  1196. dev_err(dev, "cannot allocate par\n");
  1197. ret = -ENOMEM;
  1198. goto sm501fb_alloc_fail;
  1199. }
  1200. if (dev->parent->platform_data) {
  1201. struct sm501_platdata *pd = dev->parent->platform_data;
  1202. info->pdata = pd->fb;
  1203. }
  1204. if (info->pdata == NULL) {
  1205. dev_info(dev, "using default configuration data\n");
  1206. info->pdata = &sm501fb_def_pdata;
  1207. }
  1208. /* start the framebuffers */
  1209. ret = sm501fb_start(info, pdev);
  1210. if (ret) {
  1211. dev_err(dev, "cannot initialise SM501\n");
  1212. goto sm501fb_start_fail;
  1213. }
  1214. /* CRT framebuffer setup */
  1215. ret = sm501fb_init_fb(fbinfo_crt, HEAD_CRT, driver_name_crt);
  1216. if (ret) {
  1217. dev_err(dev, "cannot initialise CRT fb\n");
  1218. goto sm501fb_start_fail;
  1219. }
  1220. /* Panel framebuffer setup */
  1221. ret = sm501fb_init_fb(fbinfo_pnl, HEAD_PANEL, driver_name_pnl);
  1222. if (ret) {
  1223. dev_err(dev, "cannot initialise Panel fb\n");
  1224. goto sm501fb_start_fail;
  1225. }
  1226. /* register framebuffers */
  1227. ret = register_framebuffer(fbinfo_crt);
  1228. if (ret < 0) {
  1229. dev_err(dev, "failed to register CRT fb (%d)\n", ret);
  1230. goto register_crt_fail;
  1231. }
  1232. ret = register_framebuffer(fbinfo_pnl);
  1233. if (ret < 0) {
  1234. dev_err(dev, "failed to register panel fb (%d)\n", ret);
  1235. goto register_pnl_fail;
  1236. }
  1237. dev_info(dev, "fb%d: %s frame buffer device\n",
  1238. fbinfo_crt->node, fbinfo_crt->fix.id);
  1239. dev_info(dev, "fb%d: %s frame buffer device\n",
  1240. fbinfo_pnl->node, fbinfo_pnl->fix.id);
  1241. /* create device files */
  1242. ret = device_create_file(dev, &dev_attr_crt_src);
  1243. if (ret)
  1244. goto crtsrc_fail;
  1245. ret = device_create_file(dev, &dev_attr_fbregs_pnl);
  1246. if (ret)
  1247. goto fbregs_pnl_fail;
  1248. ret = device_create_file(dev, &dev_attr_fbregs_crt);
  1249. if (ret)
  1250. goto fbregs_crt_fail;
  1251. /* we registered, return ok */
  1252. return 0;
  1253. fbregs_crt_fail:
  1254. device_remove_file(dev, &dev_attr_fbregs_pnl);
  1255. fbregs_pnl_fail:
  1256. device_remove_file(dev, &dev_attr_crt_src);
  1257. crtsrc_fail:
  1258. unregister_framebuffer(fbinfo_pnl);
  1259. register_pnl_fail:
  1260. unregister_framebuffer(fbinfo_crt);
  1261. register_crt_fail:
  1262. sm501fb_stop(info);
  1263. sm501fb_start_fail:
  1264. sm501fb_info_release(info);
  1265. sm501fb_alloc_fail:
  1266. framebuffer_release(fbinfo_pnl);
  1267. fbinfo_crt_alloc_fail:
  1268. framebuffer_release(fbinfo_crt);
  1269. return ret;
  1270. }
  1271. /*
  1272. * Cleanup
  1273. */
  1274. static int sm501fb_remove(struct platform_device *pdev)
  1275. {
  1276. struct sm501fb_info *info = platform_get_drvdata(pdev);
  1277. struct fb_info *fbinfo_crt = info->fb[0];
  1278. struct fb_info *fbinfo_pnl = info->fb[1];
  1279. device_remove_file(&pdev->dev, &dev_attr_fbregs_crt);
  1280. device_remove_file(&pdev->dev, &dev_attr_fbregs_pnl);
  1281. device_remove_file(&pdev->dev, &dev_attr_crt_src);
  1282. unregister_framebuffer(fbinfo_crt);
  1283. unregister_framebuffer(fbinfo_pnl);
  1284. sm501fb_stop(info);
  1285. sm501fb_info_release(info);
  1286. framebuffer_release(fbinfo_pnl);
  1287. framebuffer_release(fbinfo_crt);
  1288. return 0;
  1289. }
  1290. #ifdef CONFIG_PM
  1291. static int sm501fb_suspend_fb(struct sm501fb_info *info,
  1292. enum sm501_controller head)
  1293. {
  1294. struct fb_info *fbi = info->fb[head];
  1295. struct sm501fb_par *par = fbi->par;
  1296. if (par->screen.size == 0)
  1297. return 0;
  1298. /* backup copies in case chip is powered down over suspend */
  1299. par->store_fb = vmalloc(par->screen.size);
  1300. if (par->store_fb == NULL) {
  1301. dev_err(info->dev, "no memory to store screen\n");
  1302. return -ENOMEM;
  1303. }
  1304. par->store_cursor = vmalloc(par->cursor.size);
  1305. if (par->store_cursor == NULL) {
  1306. dev_err(info->dev, "no memory to store cursor\n");
  1307. goto err_nocursor;
  1308. }
  1309. dev_dbg(info->dev, "suspending screen to %p\n", par->store_fb);
  1310. dev_dbg(info->dev, "suspending cursor to %p\n", par->store_cursor);
  1311. memcpy_fromio(par->store_fb, par->screen.k_addr, par->screen.size);
  1312. memcpy_fromio(par->store_cursor, par->cursor.k_addr, par->cursor.size);
  1313. /* blank the relevant interface to ensure unit power minimised */
  1314. (par->ops.fb_blank)(FB_BLANK_POWERDOWN, fbi);
  1315. acquire_console_sem();
  1316. fb_set_suspend(fbi, 1);
  1317. release_console_sem();
  1318. return 0;
  1319. err_nocursor:
  1320. vfree(par->store_fb);
  1321. par->store_fb = NULL;
  1322. return -ENOMEM;
  1323. }
  1324. static void sm501fb_resume_fb(struct sm501fb_info *info,
  1325. enum sm501_controller head)
  1326. {
  1327. struct fb_info *fbi = info->fb[head];
  1328. struct sm501fb_par *par = fbi->par;
  1329. if (par->screen.size == 0)
  1330. return;
  1331. /* re-activate the configuration */
  1332. (par->ops.fb_set_par)(fbi);
  1333. /* restore the data */
  1334. dev_dbg(info->dev, "restoring screen from %p\n", par->store_fb);
  1335. dev_dbg(info->dev, "restoring cursor from %p\n", par->store_cursor);
  1336. if (par->store_fb)
  1337. memcpy_toio(par->screen.k_addr, par->store_fb,
  1338. par->screen.size);
  1339. if (par->store_cursor)
  1340. memcpy_toio(par->cursor.k_addr, par->store_cursor,
  1341. par->cursor.size);
  1342. acquire_console_sem();
  1343. fb_set_suspend(fbi, 0);
  1344. release_console_sem();
  1345. vfree(par->store_fb);
  1346. vfree(par->store_cursor);
  1347. }
  1348. /* suspend and resume support */
  1349. static int sm501fb_suspend(struct platform_device *pdev, pm_message_t state)
  1350. {
  1351. struct sm501fb_info *info = platform_get_drvdata(pdev);
  1352. /* store crt control to resume with */
  1353. info->pm_crt_ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
  1354. sm501fb_suspend_fb(info, HEAD_CRT);
  1355. sm501fb_suspend_fb(info, HEAD_PANEL);
  1356. /* turn off the clocks, in case the device is not powered down */
  1357. sm501_unit_power(info->dev->parent, SM501_GATE_DISPLAY, 0);
  1358. return 0;
  1359. }
  1360. #define SM501_CRT_CTRL_SAVE (SM501_DC_CRT_CONTROL_TVP | \
  1361. SM501_DC_CRT_CONTROL_SEL)
  1362. static int sm501fb_resume(struct platform_device *pdev)
  1363. {
  1364. struct sm501fb_info *info = platform_get_drvdata(pdev);
  1365. unsigned long crt_ctrl;
  1366. sm501_unit_power(info->dev->parent, SM501_GATE_DISPLAY, 1);
  1367. /* restore the items we want to be saved for crt control */
  1368. crt_ctrl = readl(info->regs + SM501_DC_CRT_CONTROL);
  1369. crt_ctrl &= ~SM501_CRT_CTRL_SAVE;
  1370. crt_ctrl |= info->pm_crt_ctrl & SM501_CRT_CTRL_SAVE;
  1371. writel(crt_ctrl, info->regs + SM501_DC_CRT_CONTROL);
  1372. sm501fb_resume_fb(info, HEAD_CRT);
  1373. sm501fb_resume_fb(info, HEAD_PANEL);
  1374. return 0;
  1375. }
  1376. #else
  1377. #define sm501fb_suspend NULL
  1378. #define sm501fb_resume NULL
  1379. #endif
  1380. static struct platform_driver sm501fb_driver = {
  1381. .probe = sm501fb_probe,
  1382. .remove = sm501fb_remove,
  1383. .suspend = sm501fb_suspend,
  1384. .resume = sm501fb_resume,
  1385. .driver = {
  1386. .name = "sm501-fb",
  1387. .owner = THIS_MODULE,
  1388. },
  1389. };
  1390. static int __devinit sm501fb_init(void)
  1391. {
  1392. return platform_driver_register(&sm501fb_driver);
  1393. }
  1394. static void __exit sm501fb_cleanup(void)
  1395. {
  1396. platform_driver_unregister(&sm501fb_driver);
  1397. }
  1398. module_init(sm501fb_init);
  1399. module_exit(sm501fb_cleanup);
  1400. MODULE_AUTHOR("Ben Dooks, Vincent Sanders");
  1401. MODULE_DESCRIPTION("SM501 Framebuffer driver");
  1402. MODULE_LICENSE("GPL v2");