mce_amd.c 17 KB

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  1. /*
  2. * (c) 2005, 2006 Advanced Micro Devices, Inc.
  3. * Your use of this code is subject to the terms and conditions of the
  4. * GNU general public license version 2. See "COPYING" or
  5. * http://www.gnu.org/licenses/gpl.html
  6. *
  7. * Written by Jacob Shin - AMD, Inc.
  8. *
  9. * Support : jacob.shin@amd.com
  10. *
  11. * April 2006
  12. * - added support for AMD Family 0x10 processors
  13. *
  14. * All MC4_MISCi registers are shared between multi-cores
  15. */
  16. #include <linux/interrupt.h>
  17. #include <linux/notifier.h>
  18. #include <linux/kobject.h>
  19. #include <linux/percpu.h>
  20. #include <linux/errno.h>
  21. #include <linux/sched.h>
  22. #include <linux/sysfs.h>
  23. #include <linux/slab.h>
  24. #include <linux/init.h>
  25. #include <linux/cpu.h>
  26. #include <linux/smp.h>
  27. #include <asm/apic.h>
  28. #include <asm/idle.h>
  29. #include <asm/mce.h>
  30. #include <asm/msr.h>
  31. #define NR_BANKS 6
  32. #define NR_BLOCKS 9
  33. #define THRESHOLD_MAX 0xFFF
  34. #define INT_TYPE_APIC 0x00020000
  35. #define MASK_VALID_HI 0x80000000
  36. #define MASK_CNTP_HI 0x40000000
  37. #define MASK_LOCKED_HI 0x20000000
  38. #define MASK_LVTOFF_HI 0x00F00000
  39. #define MASK_COUNT_EN_HI 0x00080000
  40. #define MASK_INT_TYPE_HI 0x00060000
  41. #define MASK_OVERFLOW_HI 0x00010000
  42. #define MASK_ERR_COUNT_HI 0x00000FFF
  43. #define MASK_BLKPTR_LO 0xFF000000
  44. #define MCG_XBLK_ADDR 0xC0000400
  45. struct threshold_block {
  46. unsigned int block;
  47. unsigned int bank;
  48. unsigned int cpu;
  49. u32 address;
  50. u16 interrupt_enable;
  51. bool interrupt_capable;
  52. u16 threshold_limit;
  53. struct kobject kobj;
  54. struct list_head miscj;
  55. };
  56. struct threshold_bank {
  57. struct kobject *kobj;
  58. struct threshold_block *blocks;
  59. cpumask_var_t cpus;
  60. };
  61. static DEFINE_PER_CPU(struct threshold_bank * [NR_BANKS], threshold_banks);
  62. static unsigned char shared_bank[NR_BANKS] = {
  63. 0, 0, 0, 0, 1
  64. };
  65. static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
  66. static void amd_threshold_interrupt(void);
  67. /*
  68. * CPU Initialization
  69. */
  70. struct thresh_restart {
  71. struct threshold_block *b;
  72. int reset;
  73. int set_lvt_off;
  74. int lvt_off;
  75. u16 old_limit;
  76. };
  77. static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
  78. {
  79. /*
  80. * bank 4 supports APIC LVT interrupts implicitly since forever.
  81. */
  82. if (bank == 4)
  83. return true;
  84. /*
  85. * IntP: interrupt present; if this bit is set, the thresholding
  86. * bank can generate APIC LVT interrupts
  87. */
  88. return msr_high_bits & BIT(28);
  89. }
  90. static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
  91. {
  92. int msr = (hi & MASK_LVTOFF_HI) >> 20;
  93. if (apic < 0) {
  94. pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
  95. "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
  96. b->bank, b->block, b->address, hi, lo);
  97. return 0;
  98. }
  99. if (apic != msr) {
  100. pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
  101. "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
  102. b->cpu, apic, b->bank, b->block, b->address, hi, lo);
  103. return 0;
  104. }
  105. return 1;
  106. };
  107. /*
  108. * Called via smp_call_function_single(), must be called with correct
  109. * cpu affinity.
  110. */
  111. static void threshold_restart_bank(void *_tr)
  112. {
  113. struct thresh_restart *tr = _tr;
  114. u32 hi, lo;
  115. rdmsr(tr->b->address, lo, hi);
  116. if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
  117. tr->reset = 1; /* limit cannot be lower than err count */
  118. if (tr->reset) { /* reset err count and overflow bit */
  119. hi =
  120. (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
  121. (THRESHOLD_MAX - tr->b->threshold_limit);
  122. } else if (tr->old_limit) { /* change limit w/o reset */
  123. int new_count = (hi & THRESHOLD_MAX) +
  124. (tr->old_limit - tr->b->threshold_limit);
  125. hi = (hi & ~MASK_ERR_COUNT_HI) |
  126. (new_count & THRESHOLD_MAX);
  127. }
  128. /* clear IntType */
  129. hi &= ~MASK_INT_TYPE_HI;
  130. if (!tr->b->interrupt_capable)
  131. goto done;
  132. if (tr->set_lvt_off) {
  133. if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
  134. /* set new lvt offset */
  135. hi &= ~MASK_LVTOFF_HI;
  136. hi |= tr->lvt_off << 20;
  137. }
  138. }
  139. if (tr->b->interrupt_enable)
  140. hi |= INT_TYPE_APIC;
  141. done:
  142. hi |= MASK_COUNT_EN_HI;
  143. wrmsr(tr->b->address, lo, hi);
  144. }
  145. static void mce_threshold_block_init(struct threshold_block *b, int offset)
  146. {
  147. struct thresh_restart tr = {
  148. .b = b,
  149. .set_lvt_off = 1,
  150. .lvt_off = offset,
  151. };
  152. b->threshold_limit = THRESHOLD_MAX;
  153. threshold_restart_bank(&tr);
  154. };
  155. static int setup_APIC_mce(int reserved, int new)
  156. {
  157. if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
  158. APIC_EILVT_MSG_FIX, 0))
  159. return new;
  160. return reserved;
  161. }
  162. /* cpu init entry point, called from mce.c with preempt off */
  163. void mce_amd_feature_init(struct cpuinfo_x86 *c)
  164. {
  165. struct threshold_block b;
  166. unsigned int cpu = smp_processor_id();
  167. u32 low = 0, high = 0, address = 0;
  168. unsigned int bank, block;
  169. int offset = -1;
  170. for (bank = 0; bank < NR_BANKS; ++bank) {
  171. for (block = 0; block < NR_BLOCKS; ++block) {
  172. if (block == 0)
  173. address = MSR_IA32_MC0_MISC + bank * 4;
  174. else if (block == 1) {
  175. address = (low & MASK_BLKPTR_LO) >> 21;
  176. if (!address)
  177. break;
  178. address += MCG_XBLK_ADDR;
  179. } else
  180. ++address;
  181. if (rdmsr_safe(address, &low, &high))
  182. break;
  183. if (!(high & MASK_VALID_HI))
  184. continue;
  185. if (!(high & MASK_CNTP_HI) ||
  186. (high & MASK_LOCKED_HI))
  187. continue;
  188. if (!block)
  189. per_cpu(bank_map, cpu) |= (1 << bank);
  190. if (shared_bank[bank] && c->cpu_core_id)
  191. break;
  192. memset(&b, 0, sizeof(b));
  193. b.cpu = cpu;
  194. b.bank = bank;
  195. b.block = block;
  196. b.address = address;
  197. b.interrupt_capable = lvt_interrupt_supported(bank, high);
  198. if (b.interrupt_capable) {
  199. int new = (high & MASK_LVTOFF_HI) >> 20;
  200. offset = setup_APIC_mce(offset, new);
  201. }
  202. mce_threshold_block_init(&b, offset);
  203. mce_threshold_vector = amd_threshold_interrupt;
  204. }
  205. }
  206. }
  207. /*
  208. * APIC Interrupt Handler
  209. */
  210. /*
  211. * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
  212. * the interrupt goes off when error_count reaches threshold_limit.
  213. * the handler will simply log mcelog w/ software defined bank number.
  214. */
  215. static void amd_threshold_interrupt(void)
  216. {
  217. u32 low = 0, high = 0, address = 0;
  218. unsigned int bank, block;
  219. struct mce m;
  220. mce_setup(&m);
  221. /* assume first bank caused it */
  222. for (bank = 0; bank < NR_BANKS; ++bank) {
  223. if (!(per_cpu(bank_map, m.cpu) & (1 << bank)))
  224. continue;
  225. for (block = 0; block < NR_BLOCKS; ++block) {
  226. if (block == 0) {
  227. address = MSR_IA32_MC0_MISC + bank * 4;
  228. } else if (block == 1) {
  229. address = (low & MASK_BLKPTR_LO) >> 21;
  230. if (!address)
  231. break;
  232. address += MCG_XBLK_ADDR;
  233. } else {
  234. ++address;
  235. }
  236. if (rdmsr_safe(address, &low, &high))
  237. break;
  238. if (!(high & MASK_VALID_HI)) {
  239. if (block)
  240. continue;
  241. else
  242. break;
  243. }
  244. if (!(high & MASK_CNTP_HI) ||
  245. (high & MASK_LOCKED_HI))
  246. continue;
  247. /*
  248. * Log the machine check that caused the threshold
  249. * event.
  250. */
  251. machine_check_poll(MCP_TIMESTAMP,
  252. &__get_cpu_var(mce_poll_banks));
  253. if (high & MASK_OVERFLOW_HI) {
  254. rdmsrl(address, m.misc);
  255. rdmsrl(MSR_IA32_MC0_STATUS + bank * 4,
  256. m.status);
  257. m.bank = K8_MCE_THRESHOLD_BASE
  258. + bank * NR_BLOCKS
  259. + block;
  260. mce_log(&m);
  261. return;
  262. }
  263. }
  264. }
  265. }
  266. /*
  267. * Sysfs Interface
  268. */
  269. struct threshold_attr {
  270. struct attribute attr;
  271. ssize_t (*show) (struct threshold_block *, char *);
  272. ssize_t (*store) (struct threshold_block *, const char *, size_t count);
  273. };
  274. #define SHOW_FIELDS(name) \
  275. static ssize_t show_ ## name(struct threshold_block *b, char *buf) \
  276. { \
  277. return sprintf(buf, "%lx\n", (unsigned long) b->name); \
  278. }
  279. SHOW_FIELDS(interrupt_enable)
  280. SHOW_FIELDS(threshold_limit)
  281. static ssize_t
  282. store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
  283. {
  284. struct thresh_restart tr;
  285. unsigned long new;
  286. if (!b->interrupt_capable)
  287. return -EINVAL;
  288. if (strict_strtoul(buf, 0, &new) < 0)
  289. return -EINVAL;
  290. b->interrupt_enable = !!new;
  291. memset(&tr, 0, sizeof(tr));
  292. tr.b = b;
  293. smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
  294. return size;
  295. }
  296. static ssize_t
  297. store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
  298. {
  299. struct thresh_restart tr;
  300. unsigned long new;
  301. if (strict_strtoul(buf, 0, &new) < 0)
  302. return -EINVAL;
  303. if (new > THRESHOLD_MAX)
  304. new = THRESHOLD_MAX;
  305. if (new < 1)
  306. new = 1;
  307. memset(&tr, 0, sizeof(tr));
  308. tr.old_limit = b->threshold_limit;
  309. b->threshold_limit = new;
  310. tr.b = b;
  311. smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
  312. return size;
  313. }
  314. struct threshold_block_cross_cpu {
  315. struct threshold_block *tb;
  316. long retval;
  317. };
  318. static void local_error_count_handler(void *_tbcc)
  319. {
  320. struct threshold_block_cross_cpu *tbcc = _tbcc;
  321. struct threshold_block *b = tbcc->tb;
  322. u32 low, high;
  323. rdmsr(b->address, low, high);
  324. tbcc->retval = (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit);
  325. }
  326. static ssize_t show_error_count(struct threshold_block *b, char *buf)
  327. {
  328. struct threshold_block_cross_cpu tbcc = { .tb = b, };
  329. smp_call_function_single(b->cpu, local_error_count_handler, &tbcc, 1);
  330. return sprintf(buf, "%lx\n", tbcc.retval);
  331. }
  332. static ssize_t store_error_count(struct threshold_block *b,
  333. const char *buf, size_t count)
  334. {
  335. struct thresh_restart tr = { .b = b, .reset = 1, .old_limit = 0 };
  336. smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
  337. return 1;
  338. }
  339. #define RW_ATTR(val) \
  340. static struct threshold_attr val = { \
  341. .attr = {.name = __stringify(val), .mode = 0644 }, \
  342. .show = show_## val, \
  343. .store = store_## val, \
  344. };
  345. RW_ATTR(interrupt_enable);
  346. RW_ATTR(threshold_limit);
  347. RW_ATTR(error_count);
  348. static struct attribute *default_attrs[] = {
  349. &interrupt_enable.attr,
  350. &threshold_limit.attr,
  351. &error_count.attr,
  352. NULL
  353. };
  354. #define to_block(k) container_of(k, struct threshold_block, kobj)
  355. #define to_attr(a) container_of(a, struct threshold_attr, attr)
  356. static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
  357. {
  358. struct threshold_block *b = to_block(kobj);
  359. struct threshold_attr *a = to_attr(attr);
  360. ssize_t ret;
  361. ret = a->show ? a->show(b, buf) : -EIO;
  362. return ret;
  363. }
  364. static ssize_t store(struct kobject *kobj, struct attribute *attr,
  365. const char *buf, size_t count)
  366. {
  367. struct threshold_block *b = to_block(kobj);
  368. struct threshold_attr *a = to_attr(attr);
  369. ssize_t ret;
  370. ret = a->store ? a->store(b, buf, count) : -EIO;
  371. return ret;
  372. }
  373. static const struct sysfs_ops threshold_ops = {
  374. .show = show,
  375. .store = store,
  376. };
  377. static struct kobj_type threshold_ktype = {
  378. .sysfs_ops = &threshold_ops,
  379. .default_attrs = default_attrs,
  380. };
  381. static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
  382. unsigned int bank,
  383. unsigned int block,
  384. u32 address)
  385. {
  386. struct threshold_block *b = NULL;
  387. u32 low, high;
  388. int err;
  389. if ((bank >= NR_BANKS) || (block >= NR_BLOCKS))
  390. return 0;
  391. if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
  392. return 0;
  393. if (!(high & MASK_VALID_HI)) {
  394. if (block)
  395. goto recurse;
  396. else
  397. return 0;
  398. }
  399. if (!(high & MASK_CNTP_HI) ||
  400. (high & MASK_LOCKED_HI))
  401. goto recurse;
  402. b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
  403. if (!b)
  404. return -ENOMEM;
  405. b->block = block;
  406. b->bank = bank;
  407. b->cpu = cpu;
  408. b->address = address;
  409. b->interrupt_enable = 0;
  410. b->interrupt_capable = lvt_interrupt_supported(bank, high);
  411. b->threshold_limit = THRESHOLD_MAX;
  412. INIT_LIST_HEAD(&b->miscj);
  413. if (per_cpu(threshold_banks, cpu)[bank]->blocks) {
  414. list_add(&b->miscj,
  415. &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
  416. } else {
  417. per_cpu(threshold_banks, cpu)[bank]->blocks = b;
  418. }
  419. err = kobject_init_and_add(&b->kobj, &threshold_ktype,
  420. per_cpu(threshold_banks, cpu)[bank]->kobj,
  421. "misc%i", block);
  422. if (err)
  423. goto out_free;
  424. recurse:
  425. if (!block) {
  426. address = (low & MASK_BLKPTR_LO) >> 21;
  427. if (!address)
  428. return 0;
  429. address += MCG_XBLK_ADDR;
  430. } else {
  431. ++address;
  432. }
  433. err = allocate_threshold_blocks(cpu, bank, ++block, address);
  434. if (err)
  435. goto out_free;
  436. if (b)
  437. kobject_uevent(&b->kobj, KOBJ_ADD);
  438. return err;
  439. out_free:
  440. if (b) {
  441. kobject_put(&b->kobj);
  442. list_del(&b->miscj);
  443. kfree(b);
  444. }
  445. return err;
  446. }
  447. static __cpuinit long
  448. local_allocate_threshold_blocks(int cpu, unsigned int bank)
  449. {
  450. return allocate_threshold_blocks(cpu, bank, 0,
  451. MSR_IA32_MC0_MISC + bank * 4);
  452. }
  453. /* symlinks sibling shared banks to first core. first core owns dir/files. */
  454. static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
  455. {
  456. int i, err = 0;
  457. struct threshold_bank *b = NULL;
  458. struct device *dev = per_cpu(mce_device, cpu);
  459. char name[32];
  460. sprintf(name, "threshold_bank%i", bank);
  461. #ifdef CONFIG_SMP
  462. if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) { /* symlink */
  463. i = cpumask_first(cpu_llc_shared_mask(cpu));
  464. /* first core not up yet */
  465. if (cpu_data(i).cpu_core_id)
  466. goto out;
  467. /* already linked */
  468. if (per_cpu(threshold_banks, cpu)[bank])
  469. goto out;
  470. b = per_cpu(threshold_banks, i)[bank];
  471. if (!b)
  472. goto out;
  473. err = sysfs_create_link(&dev->kobj, b->kobj, name);
  474. if (err)
  475. goto out;
  476. cpumask_copy(b->cpus, cpu_llc_shared_mask(cpu));
  477. per_cpu(threshold_banks, cpu)[bank] = b;
  478. goto out;
  479. }
  480. #endif
  481. b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
  482. if (!b) {
  483. err = -ENOMEM;
  484. goto out;
  485. }
  486. if (!zalloc_cpumask_var(&b->cpus, GFP_KERNEL)) {
  487. kfree(b);
  488. err = -ENOMEM;
  489. goto out;
  490. }
  491. b->kobj = kobject_create_and_add(name, &dev->kobj);
  492. if (!b->kobj)
  493. goto out_free;
  494. #ifndef CONFIG_SMP
  495. cpumask_setall(b->cpus);
  496. #else
  497. cpumask_set_cpu(cpu, b->cpus);
  498. #endif
  499. per_cpu(threshold_banks, cpu)[bank] = b;
  500. err = local_allocate_threshold_blocks(cpu, bank);
  501. if (err)
  502. goto out_free;
  503. for_each_cpu(i, b->cpus) {
  504. if (i == cpu)
  505. continue;
  506. dev = per_cpu(mce_device, i);
  507. if (dev)
  508. err = sysfs_create_link(&dev->kobj,b->kobj, name);
  509. if (err)
  510. goto out;
  511. per_cpu(threshold_banks, i)[bank] = b;
  512. }
  513. goto out;
  514. out_free:
  515. per_cpu(threshold_banks, cpu)[bank] = NULL;
  516. free_cpumask_var(b->cpus);
  517. kfree(b);
  518. out:
  519. return err;
  520. }
  521. /* create dir/files for all valid threshold banks */
  522. static __cpuinit int threshold_create_device(unsigned int cpu)
  523. {
  524. unsigned int bank;
  525. int err = 0;
  526. for (bank = 0; bank < NR_BANKS; ++bank) {
  527. if (!(per_cpu(bank_map, cpu) & (1 << bank)))
  528. continue;
  529. err = threshold_create_bank(cpu, bank);
  530. if (err)
  531. return err;
  532. }
  533. return err;
  534. }
  535. /*
  536. * let's be hotplug friendly.
  537. * in case of multiple core processors, the first core always takes ownership
  538. * of shared sysfs dir/files, and rest of the cores will be symlinked to it.
  539. */
  540. static void deallocate_threshold_block(unsigned int cpu,
  541. unsigned int bank)
  542. {
  543. struct threshold_block *pos = NULL;
  544. struct threshold_block *tmp = NULL;
  545. struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
  546. if (!head)
  547. return;
  548. list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
  549. kobject_put(&pos->kobj);
  550. list_del(&pos->miscj);
  551. kfree(pos);
  552. }
  553. kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
  554. per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
  555. }
  556. static void threshold_remove_bank(unsigned int cpu, int bank)
  557. {
  558. struct threshold_bank *b;
  559. struct device *dev;
  560. char name[32];
  561. int i = 0;
  562. b = per_cpu(threshold_banks, cpu)[bank];
  563. if (!b)
  564. return;
  565. if (!b->blocks)
  566. goto free_out;
  567. sprintf(name, "threshold_bank%i", bank);
  568. #ifdef CONFIG_SMP
  569. /* sibling symlink */
  570. if (shared_bank[bank] && b->blocks->cpu != cpu) {
  571. dev = per_cpu(mce_device, cpu);
  572. sysfs_remove_link(&dev->kobj, name);
  573. per_cpu(threshold_banks, cpu)[bank] = NULL;
  574. return;
  575. }
  576. #endif
  577. /* remove all sibling symlinks before unregistering */
  578. for_each_cpu(i, b->cpus) {
  579. if (i == cpu)
  580. continue;
  581. dev = per_cpu(mce_device, i);
  582. if (dev)
  583. sysfs_remove_link(&dev->kobj, name);
  584. per_cpu(threshold_banks, i)[bank] = NULL;
  585. }
  586. deallocate_threshold_block(cpu, bank);
  587. free_out:
  588. kobject_del(b->kobj);
  589. kobject_put(b->kobj);
  590. free_cpumask_var(b->cpus);
  591. kfree(b);
  592. per_cpu(threshold_banks, cpu)[bank] = NULL;
  593. }
  594. static void threshold_remove_device(unsigned int cpu)
  595. {
  596. unsigned int bank;
  597. for (bank = 0; bank < NR_BANKS; ++bank) {
  598. if (!(per_cpu(bank_map, cpu) & (1 << bank)))
  599. continue;
  600. threshold_remove_bank(cpu, bank);
  601. }
  602. }
  603. /* get notified when a cpu comes on/off */
  604. static void __cpuinit
  605. amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu)
  606. {
  607. switch (action) {
  608. case CPU_ONLINE:
  609. case CPU_ONLINE_FROZEN:
  610. threshold_create_device(cpu);
  611. break;
  612. case CPU_DEAD:
  613. case CPU_DEAD_FROZEN:
  614. threshold_remove_device(cpu);
  615. break;
  616. default:
  617. break;
  618. }
  619. }
  620. static __init int threshold_init_device(void)
  621. {
  622. unsigned lcpu = 0;
  623. /* to hit CPUs online before the notifier is up */
  624. for_each_online_cpu(lcpu) {
  625. int err = threshold_create_device(lcpu);
  626. if (err)
  627. return err;
  628. }
  629. threshold_cpu_callback = amd_64_threshold_cpu_callback;
  630. return 0;
  631. }
  632. device_initcall(threshold_init_device);