wm8958-dsp2.c 12 KB

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  1. /*
  2. * wm8958-dsp2.c -- WM8958 DSP2 support
  3. *
  4. * Copyright 2011 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/init.h>
  15. #include <linux/delay.h>
  16. #include <linux/pm.h>
  17. #include <linux/i2c.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/slab.h>
  20. #include <sound/soc.h>
  21. #include <sound/initval.h>
  22. #include <sound/tlv.h>
  23. #include <trace/events/asoc.h>
  24. #include <linux/mfd/wm8994/core.h>
  25. #include <linux/mfd/wm8994/registers.h>
  26. #include <linux/mfd/wm8994/pdata.h>
  27. #include <linux/mfd/wm8994/gpio.h>
  28. #include "wm8994.h"
  29. #define WM_FW_BLOCK_INFO 0xff
  30. #define WM_FW_BLOCK_PM 0x00
  31. #define WM_FW_BLOCK_X 0x01
  32. #define WM_FW_BLOCK_Y 0x02
  33. #define WM_FW_BLOCK_Z 0x03
  34. #define WM_FW_BLOCK_I 0x06
  35. #define WM_FW_BLOCK_A 0x08
  36. #define WM_FW_BLOCK_C 0x0c
  37. static int wm8958_dsp2_fw(struct snd_soc_codec *codec, const char *name,
  38. const struct firmware *fw, bool check)
  39. {
  40. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  41. u64 data64;
  42. u32 data32;
  43. const u8 *data;
  44. char *str;
  45. size_t block_len, len;
  46. int ret = 0;
  47. /* Suppress unneeded downloads */
  48. if (wm8994->cur_fw == fw)
  49. return 0;
  50. if (fw->size < 32) {
  51. dev_err(codec->dev, "%s: firmware too short\n", name);
  52. goto err;
  53. }
  54. if (memcmp(fw->data, "WMFW", 4) != 0) {
  55. dev_err(codec->dev, "%s: firmware has bad file magic %08x\n",
  56. name, data32);
  57. goto err;
  58. }
  59. memcpy(&data32, fw->data + 4, sizeof(data32));
  60. len = be32_to_cpu(data32);
  61. memcpy(&data32, fw->data + 8, sizeof(data32));
  62. data32 = be32_to_cpu(data32);
  63. if ((data32 >> 24) & 0xff) {
  64. dev_err(codec->dev, "%s: unsupported firmware version %d\n",
  65. name, (data32 >> 24) & 0xff);
  66. goto err;
  67. }
  68. if ((data32 & 0xffff) != 8958) {
  69. dev_err(codec->dev, "%s: unsupported target device %d\n",
  70. name, data32 & 0xffff);
  71. goto err;
  72. }
  73. if (((data32 >> 16) & 0xff) != 0xc) {
  74. dev_err(codec->dev, "%s: unsupported target core %d\n",
  75. name, (data32 >> 16) & 0xff);
  76. goto err;
  77. }
  78. if (check) {
  79. memcpy(&data64, fw->data + 24, sizeof(u64));
  80. dev_info(codec->dev, "%s timestamp %llx\n",
  81. name, be64_to_cpu(data64));
  82. } else {
  83. snd_soc_write(codec, 0x102, 0x2);
  84. snd_soc_write(codec, 0x900, 0x2);
  85. }
  86. data = fw->data + len;
  87. len = fw->size - len;
  88. while (len) {
  89. if (len < 12) {
  90. dev_err(codec->dev, "%s short data block of %d\n",
  91. name, len);
  92. goto err;
  93. }
  94. memcpy(&data32, data + 4, sizeof(data32));
  95. block_len = be32_to_cpu(data32);
  96. if (block_len + 8 > len) {
  97. dev_err(codec->dev, "%d byte block longer than file\n",
  98. block_len);
  99. goto err;
  100. }
  101. if (block_len == 0) {
  102. dev_err(codec->dev, "Zero length block\n");
  103. goto err;
  104. }
  105. memcpy(&data32, data, sizeof(data32));
  106. data32 = be32_to_cpu(data32);
  107. switch ((data32 >> 24) & 0xff) {
  108. case WM_FW_BLOCK_INFO:
  109. /* Informational text */
  110. if (!check)
  111. break;
  112. str = kzalloc(block_len + 1, GFP_KERNEL);
  113. if (str) {
  114. memcpy(str, data + 8, block_len);
  115. dev_info(codec->dev, "%s: %s\n", name, str);
  116. kfree(str);
  117. } else {
  118. dev_err(codec->dev, "Out of memory\n");
  119. }
  120. break;
  121. case WM_FW_BLOCK_PM:
  122. case WM_FW_BLOCK_X:
  123. case WM_FW_BLOCK_Y:
  124. case WM_FW_BLOCK_Z:
  125. case WM_FW_BLOCK_I:
  126. case WM_FW_BLOCK_A:
  127. case WM_FW_BLOCK_C:
  128. dev_dbg(codec->dev, "%s: %d bytes of %x@%x\n", name,
  129. block_len, (data32 >> 24) & 0xff,
  130. data32 & 0xffffff);
  131. if (check)
  132. break;
  133. data32 &= 0xffffff;
  134. wm8994_bulk_write(codec->control_data,
  135. data32 & 0xffffff,
  136. block_len / 2,
  137. (void *)(data + 8));
  138. break;
  139. default:
  140. dev_warn(codec->dev, "%s: unknown block type %d\n",
  141. name, (data32 >> 24) & 0xff);
  142. break;
  143. }
  144. /* Round up to the next 32 bit word */
  145. block_len += block_len % 4;
  146. data += block_len + 8;
  147. len -= block_len + 8;
  148. }
  149. if (!check) {
  150. dev_dbg(codec->dev, "%s: download done\n", name);
  151. wm8994->cur_fw = fw;
  152. } else {
  153. dev_info(codec->dev, "%s: got firmware\n", name);
  154. }
  155. goto ok;
  156. err:
  157. ret = -EINVAL;
  158. ok:
  159. if (!check) {
  160. snd_soc_write(codec, 0x900, 0x0);
  161. snd_soc_write(codec, 0x102, 0x0);
  162. }
  163. return ret;
  164. }
  165. static void wm8958_dsp_start_mbc(struct snd_soc_codec *codec, int path)
  166. {
  167. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  168. struct wm8994_pdata *pdata = wm8994->pdata;
  169. int i;
  170. /* If the DSP is already running then noop */
  171. if (snd_soc_read(codec, WM8958_DSP2_PROGRAM) & WM8958_DSP2_ENA)
  172. return;
  173. /* If we have MBC firmware download it */
  174. if (wm8994->mbc)
  175. wm8958_dsp2_fw(codec, "MBC", wm8994->mbc, false);
  176. snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
  177. WM8958_DSP2_ENA, WM8958_DSP2_ENA);
  178. /* If we've got user supplied MBC settings use them */
  179. if (pdata && pdata->num_mbc_cfgs) {
  180. struct wm8958_mbc_cfg *cfg
  181. = &pdata->mbc_cfgs[wm8994->mbc_cfg];
  182. for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
  183. snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1,
  184. cfg->coeff_regs[i]);
  185. for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
  186. snd_soc_write(codec,
  187. i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
  188. cfg->cutoff_regs[i]);
  189. }
  190. /* Run the DSP */
  191. snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
  192. WM8958_DSP2_RUNR);
  193. /* And we're off! */
  194. snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
  195. WM8958_MBC_ENA |
  196. WM8958_MBC_SEL_MASK,
  197. path << WM8958_MBC_SEL_SHIFT |
  198. WM8958_MBC_ENA);
  199. }
  200. static void wm8958_dsp_apply(struct snd_soc_codec *codec, int path, int start)
  201. {
  202. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  203. int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
  204. int ena, reg, aif;
  205. switch (path) {
  206. case 0:
  207. pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
  208. aif = 0;
  209. break;
  210. case 1:
  211. pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
  212. aif = 0;
  213. break;
  214. case 2:
  215. pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
  216. aif = 1;
  217. break;
  218. default:
  219. BUG();
  220. return;
  221. }
  222. /* Do we have both an active AIF and an active algorithm? */
  223. ena = wm8994->mbc_ena[path];
  224. if (!pwr_reg)
  225. ena = 0;
  226. reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
  227. dev_dbg(codec->dev, "DSP path %d %d startup: %d, power: %x, DSP: %x\n",
  228. path, wm8994->dsp_active, start, pwr_reg, reg);
  229. if (start && ena) {
  230. /* If either AIFnCLK is not yet enabled postpone */
  231. if (!(snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
  232. & WM8994_AIF1CLK_ENA_MASK) &&
  233. !(snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
  234. & WM8994_AIF2CLK_ENA_MASK))
  235. return;
  236. /* Switch the clock over to the appropriate AIF */
  237. snd_soc_update_bits(codec, WM8994_CLOCKING_1,
  238. WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
  239. aif << WM8958_DSP2CLK_SRC_SHIFT |
  240. WM8958_DSP2CLK_ENA);
  241. if (wm8994->mbc_ena[path])
  242. wm8958_dsp_start_mbc(codec, path);
  243. dev_dbg(codec->dev, "DSP running\n");
  244. } else {
  245. /* If the DSP is already stopped then noop */
  246. if (!(reg & WM8958_DSP2_ENA))
  247. return;
  248. snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
  249. WM8958_MBC_ENA, 0);
  250. snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
  251. WM8958_DSP2_STOP);
  252. snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
  253. WM8958_DSP2_ENA, 0);
  254. snd_soc_update_bits(codec, WM8994_CLOCKING_1,
  255. WM8958_DSP2CLK_ENA, 0);
  256. wm8994->dsp_active = -1;
  257. dev_dbg(codec->dev, "DSP stopped\n");
  258. }
  259. }
  260. int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
  261. struct snd_kcontrol *kcontrol, int event)
  262. {
  263. struct snd_soc_codec *codec = w->codec;
  264. int i;
  265. switch (event) {
  266. case SND_SOC_DAPM_POST_PMU:
  267. case SND_SOC_DAPM_PRE_PMU:
  268. for (i = 0; i < 3; i++)
  269. wm8958_dsp_apply(codec, i, 1);
  270. break;
  271. case SND_SOC_DAPM_POST_PMD:
  272. case SND_SOC_DAPM_PRE_PMD:
  273. for (i = 0; i < 3; i++)
  274. wm8958_dsp_apply(codec, i, 0);
  275. break;
  276. }
  277. return 0;
  278. }
  279. /* Check if DSP2 is in use on another AIF */
  280. static int wm8958_dsp2_busy(struct wm8994_priv *wm8994, int aif)
  281. {
  282. int i;
  283. for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
  284. if (i == aif)
  285. continue;
  286. if (wm8994->mbc_ena[i])
  287. return 1;
  288. }
  289. return 0;
  290. }
  291. static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
  292. struct snd_ctl_elem_value *ucontrol)
  293. {
  294. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  295. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  296. struct wm8994_pdata *pdata = wm8994->pdata;
  297. int value = ucontrol->value.integer.value[0];
  298. int reg;
  299. /* Don't allow on the fly reconfiguration */
  300. reg = snd_soc_read(codec, WM8994_CLOCKING_1);
  301. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  302. return -EBUSY;
  303. if (value >= pdata->num_mbc_cfgs)
  304. return -EINVAL;
  305. wm8994->mbc_cfg = value;
  306. return 0;
  307. }
  308. static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
  309. struct snd_ctl_elem_value *ucontrol)
  310. {
  311. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  312. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  313. ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
  314. return 0;
  315. }
  316. static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
  317. struct snd_ctl_elem_info *uinfo)
  318. {
  319. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  320. uinfo->count = 1;
  321. uinfo->value.integer.min = 0;
  322. uinfo->value.integer.max = 1;
  323. return 0;
  324. }
  325. static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
  326. struct snd_ctl_elem_value *ucontrol)
  327. {
  328. int mbc = kcontrol->private_value;
  329. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  330. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  331. ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
  332. return 0;
  333. }
  334. static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
  335. struct snd_ctl_elem_value *ucontrol)
  336. {
  337. int mbc = kcontrol->private_value;
  338. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  339. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  340. if (ucontrol->value.integer.value[0] > 1)
  341. return -EINVAL;
  342. if (wm8958_dsp2_busy(wm8994, mbc)) {
  343. dev_dbg(codec->dev, "DSP2 active on %d already\n", mbc);
  344. return -EBUSY;
  345. }
  346. wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
  347. wm8958_dsp_apply(codec, mbc, wm8994->mbc_ena[mbc]);
  348. return 0;
  349. }
  350. #define WM8958_MBC_SWITCH(xname, xval) {\
  351. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  352. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  353. .info = wm8958_mbc_info, \
  354. .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
  355. .private_value = xval }
  356. static const struct snd_kcontrol_new wm8958_mbc_snd_controls[] = {
  357. WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
  358. WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
  359. WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
  360. };
  361. static void wm8958_mbc_loaded(const struct firmware *fw, void *context)
  362. {
  363. struct snd_soc_codec *codec = context;
  364. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  365. if (fw && wm8958_dsp2_fw(codec, "MBC", fw, true) != 0) {
  366. mutex_lock(&codec->mutex);
  367. wm8994->mbc = fw;
  368. mutex_unlock(&codec->mutex);
  369. }
  370. }
  371. void wm8958_dsp2_init(struct snd_soc_codec *codec)
  372. {
  373. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  374. struct wm8994_pdata *pdata = wm8994->pdata;
  375. int ret, i;
  376. wm8994->dsp_active = -1;
  377. snd_soc_add_controls(codec, wm8958_mbc_snd_controls,
  378. ARRAY_SIZE(wm8958_mbc_snd_controls));
  379. /* We don't *require* firmware and don't want to delay boot */
  380. request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
  381. "wm8958_mbc.wfw", codec->dev, GFP_KERNEL,
  382. codec, wm8958_mbc_loaded);
  383. if (!pdata)
  384. return;
  385. if (pdata->num_mbc_cfgs) {
  386. struct snd_kcontrol_new control[] = {
  387. SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
  388. wm8958_get_mbc_enum, wm8958_put_mbc_enum),
  389. };
  390. /* We need an array of texts for the enum API */
  391. wm8994->mbc_texts = kmalloc(sizeof(char *)
  392. * pdata->num_mbc_cfgs, GFP_KERNEL);
  393. if (!wm8994->mbc_texts) {
  394. dev_err(wm8994->codec->dev,
  395. "Failed to allocate %d MBC config texts\n",
  396. pdata->num_mbc_cfgs);
  397. return;
  398. }
  399. for (i = 0; i < pdata->num_mbc_cfgs; i++)
  400. wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
  401. wm8994->mbc_enum.max = pdata->num_mbc_cfgs;
  402. wm8994->mbc_enum.texts = wm8994->mbc_texts;
  403. ret = snd_soc_add_controls(wm8994->codec, control, 1);
  404. if (ret != 0)
  405. dev_err(wm8994->codec->dev,
  406. "Failed to add MBC mode controls: %d\n", ret);
  407. }
  408. }