mach-imx6q.c 6.4 KB

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  1. /*
  2. * Copyright 2011-2013 Freescale Semiconductor, Inc.
  3. * Copyright 2011 Linaro Ltd.
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/clkdev.h>
  14. #include <linux/cpu.h>
  15. #include <linux/delay.h>
  16. #include <linux/export.h>
  17. #include <linux/init.h>
  18. #include <linux/io.h>
  19. #include <linux/irq.h>
  20. #include <linux/irqchip.h>
  21. #include <linux/of.h>
  22. #include <linux/of_address.h>
  23. #include <linux/of_irq.h>
  24. #include <linux/of_platform.h>
  25. #include <linux/opp.h>
  26. #include <linux/phy.h>
  27. #include <linux/reboot.h>
  28. #include <linux/regmap.h>
  29. #include <linux/micrel_phy.h>
  30. #include <linux/mfd/syscon.h>
  31. #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  32. #include <asm/mach/arch.h>
  33. #include <asm/mach/map.h>
  34. #include <asm/system_misc.h>
  35. #include "common.h"
  36. #include "cpuidle.h"
  37. #include "hardware.h"
  38. static void imx6q_restart(enum reboot_mode mode, const char *cmd)
  39. {
  40. struct device_node *np;
  41. void __iomem *wdog_base;
  42. np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
  43. wdog_base = of_iomap(np, 0);
  44. if (!wdog_base)
  45. goto soft;
  46. imx_src_prepare_restart();
  47. /* enable wdog */
  48. writew_relaxed(1 << 2, wdog_base);
  49. /* write twice to ensure the request will not get ignored */
  50. writew_relaxed(1 << 2, wdog_base);
  51. /* wait for reset to assert ... */
  52. mdelay(500);
  53. pr_err("Watchdog reset failed to assert reset\n");
  54. /* delay to allow the serial port to show the message */
  55. mdelay(50);
  56. soft:
  57. /* we'll take a jump through zero as a poor second */
  58. soft_restart(0);
  59. }
  60. /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
  61. static int ksz9021rn_phy_fixup(struct phy_device *phydev)
  62. {
  63. if (IS_BUILTIN(CONFIG_PHYLIB)) {
  64. /* min rx data delay */
  65. phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
  66. 0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW);
  67. phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
  68. /* max rx/tx clock delay, min rx/tx control delay */
  69. phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
  70. 0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
  71. phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0);
  72. phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
  73. MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
  74. }
  75. return 0;
  76. }
  77. static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
  78. {
  79. phy_write(dev, 0x0d, device);
  80. phy_write(dev, 0x0e, reg);
  81. phy_write(dev, 0x0d, (1 << 14) | device);
  82. phy_write(dev, 0x0e, val);
  83. }
  84. static int ksz9031rn_phy_fixup(struct phy_device *dev)
  85. {
  86. /*
  87. * min rx data delay, max rx/tx clock delay,
  88. * min rx/tx control delay
  89. */
  90. mmd_write_reg(dev, 2, 4, 0);
  91. mmd_write_reg(dev, 2, 5, 0);
  92. mmd_write_reg(dev, 2, 8, 0x003ff);
  93. return 0;
  94. }
  95. static int ar8031_phy_fixup(struct phy_device *dev)
  96. {
  97. u16 val;
  98. /* To enable AR8031 output a 125MHz clk from CLK_25M */
  99. phy_write(dev, 0xd, 0x7);
  100. phy_write(dev, 0xe, 0x8016);
  101. phy_write(dev, 0xd, 0x4007);
  102. val = phy_read(dev, 0xe);
  103. val &= 0xffe3;
  104. val |= 0x18;
  105. phy_write(dev, 0xe, val);
  106. /* introduce tx clock delay */
  107. phy_write(dev, 0x1d, 0x5);
  108. val = phy_read(dev, 0x1e);
  109. val |= 0x0100;
  110. phy_write(dev, 0x1e, val);
  111. return 0;
  112. }
  113. #define PHY_ID_AR8031 0x004dd074
  114. static void __init imx6q_enet_phy_init(void)
  115. {
  116. if (IS_BUILTIN(CONFIG_PHYLIB)) {
  117. phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
  118. ksz9021rn_phy_fixup);
  119. phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
  120. ksz9031rn_phy_fixup);
  121. phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
  122. ar8031_phy_fixup);
  123. }
  124. }
  125. static void __init imx6q_1588_init(void)
  126. {
  127. struct regmap *gpr;
  128. gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
  129. if (!IS_ERR(gpr))
  130. regmap_update_bits(gpr, IOMUXC_GPR1,
  131. IMX6Q_GPR1_ENET_CLK_SEL_MASK,
  132. IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
  133. else
  134. pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
  135. }
  136. static void __init imx6q_init_machine(void)
  137. {
  138. imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
  139. imx_get_soc_revision());
  140. imx6q_enet_phy_init();
  141. of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
  142. imx_anatop_init();
  143. imx6q_pm_init();
  144. imx6q_1588_init();
  145. }
  146. #define OCOTP_CFG3 0x440
  147. #define OCOTP_CFG3_SPEED_SHIFT 16
  148. #define OCOTP_CFG3_SPEED_1P2GHZ 0x3
  149. static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
  150. {
  151. struct device_node *np;
  152. void __iomem *base;
  153. u32 val;
  154. np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
  155. if (!np) {
  156. pr_warn("failed to find ocotp node\n");
  157. return;
  158. }
  159. base = of_iomap(np, 0);
  160. if (!base) {
  161. pr_warn("failed to map ocotp\n");
  162. goto put_node;
  163. }
  164. val = readl_relaxed(base + OCOTP_CFG3);
  165. val >>= OCOTP_CFG3_SPEED_SHIFT;
  166. if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
  167. if (opp_disable(cpu_dev, 1200000000))
  168. pr_warn("failed to disable 1.2 GHz OPP\n");
  169. put_node:
  170. of_node_put(np);
  171. }
  172. static void __init imx6q_opp_init(void)
  173. {
  174. struct device_node *np;
  175. struct device *cpu_dev = get_cpu_device(0);
  176. if (!cpu_dev) {
  177. pr_warn("failed to get cpu0 device\n");
  178. return;
  179. }
  180. np = of_node_get(cpu_dev->of_node);
  181. if (!np) {
  182. pr_warn("failed to find cpu0 node\n");
  183. return;
  184. }
  185. if (of_init_opp_table(cpu_dev)) {
  186. pr_warn("failed to init OPP table\n");
  187. goto put_node;
  188. }
  189. imx6q_opp_check_1p2ghz(cpu_dev);
  190. put_node:
  191. of_node_put(np);
  192. }
  193. static struct platform_device imx6q_cpufreq_pdev = {
  194. .name = "imx6q-cpufreq",
  195. };
  196. static void __init imx6q_init_late(void)
  197. {
  198. /*
  199. * WAIT mode is broken on TO 1.0 and 1.1, so there is no point
  200. * to run cpuidle on them.
  201. */
  202. if (imx_get_soc_revision() > IMX_CHIP_REVISION_1_1)
  203. imx6q_cpuidle_init();
  204. if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
  205. imx6q_opp_init();
  206. platform_device_register(&imx6q_cpufreq_pdev);
  207. }
  208. }
  209. static void __init imx6q_map_io(void)
  210. {
  211. debug_ll_io_init();
  212. imx_scu_map_io();
  213. }
  214. static void __init imx6q_init_irq(void)
  215. {
  216. imx_init_revision_from_anatop();
  217. imx_init_l2cache();
  218. imx_src_init();
  219. imx_gpc_init();
  220. irqchip_init();
  221. }
  222. static const char *imx6q_dt_compat[] __initdata = {
  223. "fsl,imx6dl",
  224. "fsl,imx6q",
  225. NULL,
  226. };
  227. DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
  228. .smp = smp_ops(imx_smp_ops),
  229. .map_io = imx6q_map_io,
  230. .init_irq = imx6q_init_irq,
  231. .init_machine = imx6q_init_machine,
  232. .init_late = imx6q_init_late,
  233. .dt_compat = imx6q_dt_compat,
  234. .restart = imx6q_restart,
  235. MACHINE_END