lcd.c 36 KB

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  1. /*
  2. * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
  3. * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public
  6. * License as published by the Free Software Foundation;
  7. * either version 2, or (at your option) any later version.
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  10. * the implied warranty of MERCHANTABILITY or FITNESS FOR
  11. * A PARTICULAR PURPOSE.See the GNU General Public License
  12. * for more details.
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc.,
  16. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. */
  18. #include <linux/via-core.h>
  19. #include <linux/via_i2c.h>
  20. #include "global.h"
  21. #include "lcdtbl.h"
  22. #define viafb_compact_res(x, y) (((x)<<16)|(y))
  23. static struct _lcd_scaling_factor lcd_scaling_factor = {
  24. /* LCD Horizontal Scaling Factor Register */
  25. {LCD_HOR_SCALING_FACTOR_REG_NUM,
  26. {{CR9F, 0, 1}, {CR77, 0, 7}, {CR79, 4, 5} } },
  27. /* LCD Vertical Scaling Factor Register */
  28. {LCD_VER_SCALING_FACTOR_REG_NUM,
  29. {{CR79, 3, 3}, {CR78, 0, 7}, {CR79, 6, 7} } }
  30. };
  31. static struct _lcd_scaling_factor lcd_scaling_factor_CLE = {
  32. /* LCD Horizontal Scaling Factor Register */
  33. {LCD_HOR_SCALING_FACTOR_REG_NUM_CLE, {{CR77, 0, 7}, {CR79, 4, 5} } },
  34. /* LCD Vertical Scaling Factor Register */
  35. {LCD_VER_SCALING_FACTOR_REG_NUM_CLE, {{CR78, 0, 7}, {CR79, 6, 7} } }
  36. };
  37. static int check_lvds_chip(int device_id_subaddr, int device_id);
  38. static bool lvds_identify_integratedlvds(void);
  39. static void fp_id_to_vindex(int panel_id);
  40. static int lvds_register_read(int index);
  41. static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
  42. int panel_vres);
  43. static void via_pitch_alignment_patch_lcd(
  44. struct lvds_setting_information *plvds_setting_info,
  45. struct lvds_chip_information
  46. *plvds_chip_info);
  47. static void lcd_patch_skew_dvp0(struct lvds_setting_information
  48. *plvds_setting_info,
  49. struct lvds_chip_information *plvds_chip_info);
  50. static void lcd_patch_skew_dvp1(struct lvds_setting_information
  51. *plvds_setting_info,
  52. struct lvds_chip_information *plvds_chip_info);
  53. static void lcd_patch_skew(struct lvds_setting_information
  54. *plvds_setting_info, struct lvds_chip_information *plvds_chip_info);
  55. static void integrated_lvds_disable(struct lvds_setting_information
  56. *plvds_setting_info,
  57. struct lvds_chip_information *plvds_chip_info);
  58. static void integrated_lvds_enable(struct lvds_setting_information
  59. *plvds_setting_info,
  60. struct lvds_chip_information *plvds_chip_info);
  61. static void lcd_powersequence_off(void);
  62. static void lcd_powersequence_on(void);
  63. static void fill_lcd_format(void);
  64. static void check_diport_of_integrated_lvds(
  65. struct lvds_chip_information *plvds_chip_info,
  66. struct lvds_setting_information
  67. *plvds_setting_info);
  68. static struct display_timing lcd_centering_timging(struct display_timing
  69. mode_crt_reg,
  70. struct display_timing panel_crt_reg);
  71. static int check_lvds_chip(int device_id_subaddr, int device_id)
  72. {
  73. if (lvds_register_read(device_id_subaddr) == device_id)
  74. return OK;
  75. else
  76. return FAIL;
  77. }
  78. void viafb_init_lcd_size(void)
  79. {
  80. DEBUG_MSG(KERN_INFO "viafb_init_lcd_size()\n");
  81. DEBUG_MSG(KERN_INFO
  82. "viaparinfo->lvds_setting_info->get_lcd_size_method %d\n",
  83. viaparinfo->lvds_setting_info->get_lcd_size_method);
  84. switch (viaparinfo->lvds_setting_info->get_lcd_size_method) {
  85. case GET_LCD_SIZE_BY_SYSTEM_BIOS:
  86. break;
  87. case GET_LCD_SZIE_BY_HW_STRAPPING:
  88. break;
  89. case GET_LCD_SIZE_BY_VGA_BIOS:
  90. DEBUG_MSG(KERN_INFO "Get LCD Size method by VGA BIOS !!\n");
  91. fp_id_to_vindex(viafb_lcd_panel_id);
  92. DEBUG_MSG(KERN_INFO "LCD Panel_ID = %d\n",
  93. viaparinfo->lvds_setting_info->lcd_panel_id);
  94. break;
  95. case GET_LCD_SIZE_BY_USER_SETTING:
  96. DEBUG_MSG(KERN_INFO "Get LCD Size method by user setting !!\n");
  97. fp_id_to_vindex(viafb_lcd_panel_id);
  98. DEBUG_MSG(KERN_INFO "LCD Panel_ID = %d\n",
  99. viaparinfo->lvds_setting_info->lcd_panel_id);
  100. break;
  101. default:
  102. DEBUG_MSG(KERN_INFO "viafb_init_lcd_size fail\n");
  103. viaparinfo->lvds_setting_info->lcd_panel_id =
  104. LCD_PANEL_ID1_800X600;
  105. fp_id_to_vindex(LCD_PANEL_ID1_800X600);
  106. }
  107. viaparinfo->lvds_setting_info2->lcd_panel_id =
  108. viaparinfo->lvds_setting_info->lcd_panel_id;
  109. viaparinfo->lvds_setting_info2->lcd_panel_hres =
  110. viaparinfo->lvds_setting_info->lcd_panel_hres;
  111. viaparinfo->lvds_setting_info2->lcd_panel_vres =
  112. viaparinfo->lvds_setting_info->lcd_panel_vres;
  113. viaparinfo->lvds_setting_info2->device_lcd_dualedge =
  114. viaparinfo->lvds_setting_info->device_lcd_dualedge;
  115. viaparinfo->lvds_setting_info2->LCDDithering =
  116. viaparinfo->lvds_setting_info->LCDDithering;
  117. }
  118. static bool lvds_identify_integratedlvds(void)
  119. {
  120. if (viafb_display_hardware_layout == HW_LAYOUT_LCD_EXTERNAL_LCD2) {
  121. /* Two dual channel LCD (Internal LVDS + External LVDS): */
  122. /* If we have an external LVDS, such as VT1636, we should
  123. have its chip ID already. */
  124. if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
  125. viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
  126. INTEGRATED_LVDS;
  127. DEBUG_MSG(KERN_INFO "Support two dual channel LVDS! "
  128. "(Internal LVDS + External LVDS)\n");
  129. } else {
  130. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
  131. INTEGRATED_LVDS;
  132. DEBUG_MSG(KERN_INFO "Not found external LVDS, "
  133. "so can't support two dual channel LVDS!\n");
  134. }
  135. } else if (viafb_display_hardware_layout == HW_LAYOUT_LCD1_LCD2) {
  136. /* Two single channel LCD (Internal LVDS + Internal LVDS): */
  137. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
  138. INTEGRATED_LVDS;
  139. viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
  140. INTEGRATED_LVDS;
  141. DEBUG_MSG(KERN_INFO "Support two single channel LVDS! "
  142. "(Internal LVDS + Internal LVDS)\n");
  143. } else if (viafb_display_hardware_layout != HW_LAYOUT_DVI_ONLY) {
  144. /* If we have found external LVDS, just use it,
  145. otherwise, we will use internal LVDS as default. */
  146. if (!viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
  147. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
  148. INTEGRATED_LVDS;
  149. DEBUG_MSG(KERN_INFO "Found Integrated LVDS!\n");
  150. }
  151. } else {
  152. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
  153. NON_LVDS_TRANSMITTER;
  154. DEBUG_MSG(KERN_INFO "Do not support LVDS!\n");
  155. return false;
  156. }
  157. return true;
  158. }
  159. int viafb_lvds_trasmitter_identify(void)
  160. {
  161. if (viafb_lvds_identify_vt1636(VIA_PORT_31)) {
  162. viaparinfo->chip_info->lvds_chip_info.i2c_port = VIA_PORT_31;
  163. DEBUG_MSG(KERN_INFO
  164. "Found VIA VT1636 LVDS on port i2c 0x31\n");
  165. } else {
  166. if (viafb_lvds_identify_vt1636(VIA_PORT_2C)) {
  167. viaparinfo->chip_info->lvds_chip_info.i2c_port =
  168. VIA_PORT_2C;
  169. DEBUG_MSG(KERN_INFO
  170. "Found VIA VT1636 LVDS on port gpio 0x2c\n");
  171. }
  172. }
  173. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
  174. lvds_identify_integratedlvds();
  175. if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
  176. return true;
  177. /* Check for VT1631: */
  178. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name = VT1631_LVDS;
  179. viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
  180. VT1631_LVDS_I2C_ADDR;
  181. if (check_lvds_chip(VT1631_DEVICE_ID_REG, VT1631_DEVICE_ID) != FAIL) {
  182. DEBUG_MSG(KERN_INFO "\n VT1631 LVDS ! \n");
  183. DEBUG_MSG(KERN_INFO "\n %2d",
  184. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
  185. DEBUG_MSG(KERN_INFO "\n %2d",
  186. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
  187. return OK;
  188. }
  189. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
  190. NON_LVDS_TRANSMITTER;
  191. viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
  192. VT1631_LVDS_I2C_ADDR;
  193. return FAIL;
  194. }
  195. static void fp_id_to_vindex(int panel_id)
  196. {
  197. DEBUG_MSG(KERN_INFO "fp_get_panel_id()\n");
  198. if (panel_id > LCD_PANEL_ID_MAXIMUM)
  199. viafb_lcd_panel_id = panel_id =
  200. viafb_read_reg(VIACR, CR3F) & 0x0F;
  201. switch (panel_id) {
  202. case 0x0:
  203. viaparinfo->lvds_setting_info->lcd_panel_hres = 640;
  204. viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
  205. viaparinfo->lvds_setting_info->lcd_panel_id =
  206. LCD_PANEL_ID0_640X480;
  207. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  208. viaparinfo->lvds_setting_info->LCDDithering = 1;
  209. break;
  210. case 0x1:
  211. viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
  212. viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
  213. viaparinfo->lvds_setting_info->lcd_panel_id =
  214. LCD_PANEL_ID1_800X600;
  215. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  216. viaparinfo->lvds_setting_info->LCDDithering = 1;
  217. break;
  218. case 0x2:
  219. viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
  220. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  221. viaparinfo->lvds_setting_info->lcd_panel_id =
  222. LCD_PANEL_ID2_1024X768;
  223. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  224. viaparinfo->lvds_setting_info->LCDDithering = 1;
  225. break;
  226. case 0x3:
  227. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  228. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  229. viaparinfo->lvds_setting_info->lcd_panel_id =
  230. LCD_PANEL_ID3_1280X768;
  231. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  232. viaparinfo->lvds_setting_info->LCDDithering = 1;
  233. break;
  234. case 0x4:
  235. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  236. viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
  237. viaparinfo->lvds_setting_info->lcd_panel_id =
  238. LCD_PANEL_ID4_1280X1024;
  239. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  240. viaparinfo->lvds_setting_info->LCDDithering = 1;
  241. break;
  242. case 0x5:
  243. viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
  244. viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
  245. viaparinfo->lvds_setting_info->lcd_panel_id =
  246. LCD_PANEL_ID5_1400X1050;
  247. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  248. viaparinfo->lvds_setting_info->LCDDithering = 1;
  249. break;
  250. case 0x6:
  251. viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
  252. viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
  253. viaparinfo->lvds_setting_info->lcd_panel_id =
  254. LCD_PANEL_ID6_1600X1200;
  255. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  256. viaparinfo->lvds_setting_info->LCDDithering = 1;
  257. break;
  258. case 0x8:
  259. viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
  260. viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
  261. viaparinfo->lvds_setting_info->lcd_panel_id =
  262. LCD_PANEL_IDA_800X480;
  263. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  264. viaparinfo->lvds_setting_info->LCDDithering = 1;
  265. break;
  266. case 0x9:
  267. viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
  268. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  269. viaparinfo->lvds_setting_info->lcd_panel_id =
  270. LCD_PANEL_ID2_1024X768;
  271. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  272. viaparinfo->lvds_setting_info->LCDDithering = 1;
  273. break;
  274. case 0xA:
  275. viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
  276. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  277. viaparinfo->lvds_setting_info->lcd_panel_id =
  278. LCD_PANEL_ID2_1024X768;
  279. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  280. viaparinfo->lvds_setting_info->LCDDithering = 0;
  281. break;
  282. case 0xB:
  283. viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
  284. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  285. viaparinfo->lvds_setting_info->lcd_panel_id =
  286. LCD_PANEL_ID2_1024X768;
  287. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  288. viaparinfo->lvds_setting_info->LCDDithering = 0;
  289. break;
  290. case 0xC:
  291. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  292. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  293. viaparinfo->lvds_setting_info->lcd_panel_id =
  294. LCD_PANEL_ID3_1280X768;
  295. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  296. viaparinfo->lvds_setting_info->LCDDithering = 0;
  297. break;
  298. case 0xD:
  299. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  300. viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
  301. viaparinfo->lvds_setting_info->lcd_panel_id =
  302. LCD_PANEL_ID4_1280X1024;
  303. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  304. viaparinfo->lvds_setting_info->LCDDithering = 0;
  305. break;
  306. case 0xE:
  307. viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
  308. viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
  309. viaparinfo->lvds_setting_info->lcd_panel_id =
  310. LCD_PANEL_ID5_1400X1050;
  311. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  312. viaparinfo->lvds_setting_info->LCDDithering = 0;
  313. break;
  314. case 0xF:
  315. viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
  316. viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
  317. viaparinfo->lvds_setting_info->lcd_panel_id =
  318. LCD_PANEL_ID6_1600X1200;
  319. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  320. viaparinfo->lvds_setting_info->LCDDithering = 0;
  321. break;
  322. case 0x10:
  323. viaparinfo->lvds_setting_info->lcd_panel_hres = 1366;
  324. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  325. viaparinfo->lvds_setting_info->lcd_panel_id =
  326. LCD_PANEL_ID7_1366X768;
  327. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  328. viaparinfo->lvds_setting_info->LCDDithering = 0;
  329. break;
  330. case 0x11:
  331. viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
  332. viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
  333. viaparinfo->lvds_setting_info->lcd_panel_id =
  334. LCD_PANEL_ID8_1024X600;
  335. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  336. viaparinfo->lvds_setting_info->LCDDithering = 1;
  337. break;
  338. case 0x12:
  339. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  340. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  341. viaparinfo->lvds_setting_info->lcd_panel_id =
  342. LCD_PANEL_ID3_1280X768;
  343. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  344. viaparinfo->lvds_setting_info->LCDDithering = 1;
  345. break;
  346. case 0x13:
  347. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  348. viaparinfo->lvds_setting_info->lcd_panel_vres = 800;
  349. viaparinfo->lvds_setting_info->lcd_panel_id =
  350. LCD_PANEL_ID9_1280X800;
  351. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  352. viaparinfo->lvds_setting_info->LCDDithering = 1;
  353. break;
  354. case 0x14:
  355. viaparinfo->lvds_setting_info->lcd_panel_hres = 1360;
  356. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  357. viaparinfo->lvds_setting_info->lcd_panel_id =
  358. LCD_PANEL_IDB_1360X768;
  359. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  360. viaparinfo->lvds_setting_info->LCDDithering = 0;
  361. break;
  362. case 0x15:
  363. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  364. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  365. viaparinfo->lvds_setting_info->lcd_panel_id =
  366. LCD_PANEL_ID3_1280X768;
  367. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  368. viaparinfo->lvds_setting_info->LCDDithering = 0;
  369. break;
  370. case 0x16:
  371. viaparinfo->lvds_setting_info->lcd_panel_hres = 480;
  372. viaparinfo->lvds_setting_info->lcd_panel_vres = 640;
  373. viaparinfo->lvds_setting_info->lcd_panel_id =
  374. LCD_PANEL_IDC_480X640;
  375. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  376. viaparinfo->lvds_setting_info->LCDDithering = 1;
  377. break;
  378. case 0x17:
  379. /* OLPC XO-1.5 panel */
  380. viaparinfo->lvds_setting_info->lcd_panel_hres = 1200;
  381. viaparinfo->lvds_setting_info->lcd_panel_vres = 900;
  382. viaparinfo->lvds_setting_info->lcd_panel_id =
  383. LCD_PANEL_IDD_1200X900;
  384. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  385. viaparinfo->lvds_setting_info->LCDDithering = 0;
  386. break;
  387. default:
  388. viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
  389. viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
  390. viaparinfo->lvds_setting_info->lcd_panel_id =
  391. LCD_PANEL_ID1_800X600;
  392. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  393. viaparinfo->lvds_setting_info->LCDDithering = 1;
  394. }
  395. }
  396. static int lvds_register_read(int index)
  397. {
  398. u8 data;
  399. viafb_i2c_readbyte(VIA_PORT_2C,
  400. (u8) viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr,
  401. (u8) index, &data);
  402. return data;
  403. }
  404. static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
  405. int panel_vres)
  406. {
  407. int reg_value = 0;
  408. int viafb_load_reg_num;
  409. struct io_register *reg = NULL;
  410. DEBUG_MSG(KERN_INFO "load_lcd_scaling()!!\n");
  411. /* LCD Scaling Enable */
  412. viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
  413. /* Check if expansion for horizontal */
  414. if (set_hres < panel_hres) {
  415. /* Load Horizontal Scaling Factor */
  416. switch (viaparinfo->chip_info->gfx_chip_name) {
  417. case UNICHROME_CLE266:
  418. case UNICHROME_K400:
  419. reg_value =
  420. CLE266_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
  421. viafb_load_reg_num =
  422. lcd_scaling_factor_CLE.lcd_hor_scaling_factor.
  423. reg_num;
  424. reg = lcd_scaling_factor_CLE.lcd_hor_scaling_factor.reg;
  425. viafb_load_reg(reg_value,
  426. viafb_load_reg_num, reg, VIACR);
  427. break;
  428. case UNICHROME_K800:
  429. case UNICHROME_PM800:
  430. case UNICHROME_CN700:
  431. case UNICHROME_CX700:
  432. case UNICHROME_K8M890:
  433. case UNICHROME_P4M890:
  434. case UNICHROME_P4M900:
  435. case UNICHROME_CN750:
  436. case UNICHROME_VX800:
  437. case UNICHROME_VX855:
  438. reg_value =
  439. K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
  440. /* Horizontal scaling enabled */
  441. viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);
  442. viafb_load_reg_num =
  443. lcd_scaling_factor.lcd_hor_scaling_factor.reg_num;
  444. reg = lcd_scaling_factor.lcd_hor_scaling_factor.reg;
  445. viafb_load_reg(reg_value,
  446. viafb_load_reg_num, reg, VIACR);
  447. break;
  448. }
  449. DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d", reg_value);
  450. } else {
  451. /* Horizontal scaling disabled */
  452. viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7);
  453. }
  454. /* Check if expansion for vertical */
  455. if (set_vres < panel_vres) {
  456. /* Load Vertical Scaling Factor */
  457. switch (viaparinfo->chip_info->gfx_chip_name) {
  458. case UNICHROME_CLE266:
  459. case UNICHROME_K400:
  460. reg_value =
  461. CLE266_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
  462. viafb_load_reg_num =
  463. lcd_scaling_factor_CLE.lcd_ver_scaling_factor.
  464. reg_num;
  465. reg = lcd_scaling_factor_CLE.lcd_ver_scaling_factor.reg;
  466. viafb_load_reg(reg_value,
  467. viafb_load_reg_num, reg, VIACR);
  468. break;
  469. case UNICHROME_K800:
  470. case UNICHROME_PM800:
  471. case UNICHROME_CN700:
  472. case UNICHROME_CX700:
  473. case UNICHROME_K8M890:
  474. case UNICHROME_P4M890:
  475. case UNICHROME_P4M900:
  476. case UNICHROME_CN750:
  477. case UNICHROME_VX800:
  478. case UNICHROME_VX855:
  479. reg_value =
  480. K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
  481. /* Vertical scaling enabled */
  482. viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3);
  483. viafb_load_reg_num =
  484. lcd_scaling_factor.lcd_ver_scaling_factor.reg_num;
  485. reg = lcd_scaling_factor.lcd_ver_scaling_factor.reg;
  486. viafb_load_reg(reg_value,
  487. viafb_load_reg_num, reg, VIACR);
  488. break;
  489. }
  490. DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d", reg_value);
  491. } else {
  492. /* Vertical scaling disabled */
  493. viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3);
  494. }
  495. }
  496. static void via_pitch_alignment_patch_lcd(
  497. struct lvds_setting_information *plvds_setting_info,
  498. struct lvds_chip_information
  499. *plvds_chip_info)
  500. {
  501. unsigned char cr13, cr35, cr65, cr66, cr67;
  502. unsigned long dwScreenPitch = 0;
  503. unsigned long dwPitch;
  504. dwPitch = plvds_setting_info->h_active * (plvds_setting_info->bpp >> 3);
  505. if (dwPitch & 0x1F) {
  506. dwScreenPitch = ((dwPitch + 31) & ~31) >> 3;
  507. if (plvds_setting_info->iga_path == IGA2) {
  508. if (plvds_setting_info->bpp > 8) {
  509. cr66 = (unsigned char)(dwScreenPitch & 0xFF);
  510. viafb_write_reg(CR66, VIACR, cr66);
  511. cr67 = viafb_read_reg(VIACR, CR67) & 0xFC;
  512. cr67 |=
  513. (unsigned
  514. char)((dwScreenPitch & 0x300) >> 8);
  515. viafb_write_reg(CR67, VIACR, cr67);
  516. }
  517. /* Fetch Count */
  518. cr67 = viafb_read_reg(VIACR, CR67) & 0xF3;
  519. cr67 |= (unsigned char)((dwScreenPitch & 0x600) >> 7);
  520. viafb_write_reg(CR67, VIACR, cr67);
  521. cr65 = (unsigned char)((dwScreenPitch >> 1) & 0xFF);
  522. cr65 += 2;
  523. viafb_write_reg(CR65, VIACR, cr65);
  524. } else {
  525. if (plvds_setting_info->bpp > 8) {
  526. cr13 = (unsigned char)(dwScreenPitch & 0xFF);
  527. viafb_write_reg(CR13, VIACR, cr13);
  528. cr35 = viafb_read_reg(VIACR, CR35) & 0x1F;
  529. cr35 |=
  530. (unsigned
  531. char)((dwScreenPitch & 0x700) >> 3);
  532. viafb_write_reg(CR35, VIACR, cr35);
  533. }
  534. }
  535. }
  536. }
  537. static void lcd_patch_skew_dvp0(struct lvds_setting_information
  538. *plvds_setting_info,
  539. struct lvds_chip_information *plvds_chip_info)
  540. {
  541. if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
  542. switch (viaparinfo->chip_info->gfx_chip_name) {
  543. case UNICHROME_P4M900:
  544. viafb_vt1636_patch_skew_on_vt3364(plvds_setting_info,
  545. plvds_chip_info);
  546. break;
  547. case UNICHROME_P4M890:
  548. viafb_vt1636_patch_skew_on_vt3327(plvds_setting_info,
  549. plvds_chip_info);
  550. break;
  551. }
  552. }
  553. }
  554. static void lcd_patch_skew_dvp1(struct lvds_setting_information
  555. *plvds_setting_info,
  556. struct lvds_chip_information *plvds_chip_info)
  557. {
  558. if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
  559. switch (viaparinfo->chip_info->gfx_chip_name) {
  560. case UNICHROME_CX700:
  561. viafb_vt1636_patch_skew_on_vt3324(plvds_setting_info,
  562. plvds_chip_info);
  563. break;
  564. }
  565. }
  566. }
  567. static void lcd_patch_skew(struct lvds_setting_information
  568. *plvds_setting_info, struct lvds_chip_information *plvds_chip_info)
  569. {
  570. DEBUG_MSG(KERN_INFO "lcd_patch_skew\n");
  571. switch (plvds_chip_info->output_interface) {
  572. case INTERFACE_DVP0:
  573. lcd_patch_skew_dvp0(plvds_setting_info, plvds_chip_info);
  574. break;
  575. case INTERFACE_DVP1:
  576. lcd_patch_skew_dvp1(plvds_setting_info, plvds_chip_info);
  577. break;
  578. case INTERFACE_DFP_LOW:
  579. if (UNICHROME_P4M900 == viaparinfo->chip_info->gfx_chip_name) {
  580. viafb_write_reg_mask(CR99, VIACR, 0x08,
  581. BIT0 + BIT1 + BIT2 + BIT3);
  582. }
  583. break;
  584. }
  585. }
  586. /* LCD Set Mode */
  587. void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
  588. struct lvds_setting_information *plvds_setting_info,
  589. struct lvds_chip_information *plvds_chip_info)
  590. {
  591. int set_iga = plvds_setting_info->iga_path;
  592. int mode_bpp = plvds_setting_info->bpp;
  593. int set_hres = plvds_setting_info->h_active;
  594. int set_vres = plvds_setting_info->v_active;
  595. int panel_hres = plvds_setting_info->lcd_panel_hres;
  596. int panel_vres = plvds_setting_info->lcd_panel_vres;
  597. u32 pll_D_N;
  598. struct display_timing mode_crt_reg, panel_crt_reg;
  599. struct crt_mode_table *panel_crt_table = NULL;
  600. struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres,
  601. panel_vres);
  602. DEBUG_MSG(KERN_INFO "viafb_lcd_set_mode!!\n");
  603. /* Get mode table */
  604. mode_crt_reg = mode_crt_table->crtc;
  605. /* Get panel table Pointer */
  606. panel_crt_table = vmode_tbl->crtc;
  607. panel_crt_reg = panel_crt_table->crtc;
  608. DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
  609. if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
  610. viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
  611. plvds_setting_info->vclk = panel_crt_table->clk;
  612. if (set_iga == IGA1) {
  613. /* IGA1 doesn't have LCD scaling, so set it as centering. */
  614. viafb_load_crtc_timing(lcd_centering_timging
  615. (mode_crt_reg, panel_crt_reg), IGA1);
  616. } else {
  617. /* Expansion */
  618. if (plvds_setting_info->display_method == LCD_EXPANDSION
  619. && (set_hres < panel_hres || set_vres < panel_vres)) {
  620. /* expansion timing IGA2 loaded panel set timing*/
  621. viafb_load_crtc_timing(panel_crt_reg, IGA2);
  622. DEBUG_MSG(KERN_INFO "viafb_load_crtc_timing!!\n");
  623. load_lcd_scaling(set_hres, set_vres, panel_hres,
  624. panel_vres);
  625. DEBUG_MSG(KERN_INFO "load_lcd_scaling!!\n");
  626. } else { /* Centering */
  627. /* centering timing IGA2 always loaded panel
  628. and mode releative timing */
  629. viafb_load_crtc_timing(lcd_centering_timging
  630. (mode_crt_reg, panel_crt_reg), IGA2);
  631. viafb_write_reg_mask(CR79, VIACR, 0x00,
  632. BIT0 + BIT1 + BIT2);
  633. /* LCD scaling disabled */
  634. }
  635. }
  636. /* Fetch count for IGA2 only */
  637. viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga);
  638. if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
  639. && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
  640. viafb_load_FIFO_reg(set_iga, set_hres, set_vres);
  641. fill_lcd_format();
  642. pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk);
  643. DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);
  644. viafb_set_vclock(pll_D_N, set_iga);
  645. viafb_set_output_path(DEVICE_LCD, set_iga,
  646. plvds_chip_info->output_interface);
  647. lcd_patch_skew(plvds_setting_info, plvds_chip_info);
  648. /* If K8M800, enable LCD Prefetch Mode. */
  649. if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
  650. || (UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name))
  651. viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);
  652. /* Patch for non 32bit alignment mode */
  653. via_pitch_alignment_patch_lcd(plvds_setting_info, plvds_chip_info);
  654. }
  655. static void integrated_lvds_disable(struct lvds_setting_information
  656. *plvds_setting_info,
  657. struct lvds_chip_information *plvds_chip_info)
  658. {
  659. bool turn_off_first_powersequence = false;
  660. bool turn_off_second_powersequence = false;
  661. if (INTERFACE_LVDS0LVDS1 == plvds_chip_info->output_interface)
  662. turn_off_first_powersequence = true;
  663. if (INTERFACE_LVDS0 == plvds_chip_info->output_interface)
  664. turn_off_first_powersequence = true;
  665. if (INTERFACE_LVDS1 == plvds_chip_info->output_interface)
  666. turn_off_second_powersequence = true;
  667. if (turn_off_second_powersequence) {
  668. /* Use second power sequence control: */
  669. /* Turn off power sequence. */
  670. viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);
  671. /* Turn off back light. */
  672. viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);
  673. }
  674. if (turn_off_first_powersequence) {
  675. /* Use first power sequence control: */
  676. /* Turn off power sequence. */
  677. viafb_write_reg_mask(CR6A, VIACR, 0, BIT3);
  678. /* Turn off back light. */
  679. viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
  680. }
  681. /* Turn DFP High/Low Pad off. */
  682. viafb_write_reg_mask(SR2A, VIASR, 0, BIT0 + BIT1 + BIT2 + BIT3);
  683. /* Power off LVDS channel. */
  684. switch (plvds_chip_info->output_interface) {
  685. case INTERFACE_LVDS0:
  686. {
  687. viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7);
  688. break;
  689. }
  690. case INTERFACE_LVDS1:
  691. {
  692. viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6);
  693. break;
  694. }
  695. case INTERFACE_LVDS0LVDS1:
  696. {
  697. viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);
  698. break;
  699. }
  700. }
  701. }
  702. static void integrated_lvds_enable(struct lvds_setting_information
  703. *plvds_setting_info,
  704. struct lvds_chip_information *plvds_chip_info)
  705. {
  706. DEBUG_MSG(KERN_INFO "integrated_lvds_enable, out_interface:%d\n",
  707. plvds_chip_info->output_interface);
  708. if (plvds_setting_info->lcd_mode == LCD_SPWG)
  709. viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
  710. else
  711. viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
  712. switch (plvds_chip_info->output_interface) {
  713. case INTERFACE_LVDS0LVDS1:
  714. case INTERFACE_LVDS0:
  715. /* Use first power sequence control: */
  716. /* Use hardware control power sequence. */
  717. viafb_write_reg_mask(CR91, VIACR, 0, BIT0);
  718. /* Turn on back light. */
  719. viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);
  720. /* Turn on hardware power sequence. */
  721. viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
  722. break;
  723. case INTERFACE_LVDS1:
  724. /* Use second power sequence control: */
  725. /* Use hardware control power sequence. */
  726. viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);
  727. /* Turn on back light. */
  728. viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);
  729. /* Turn on hardware power sequence. */
  730. viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1);
  731. break;
  732. }
  733. /* Turn DFP High/Low pad on. */
  734. viafb_write_reg_mask(SR2A, VIASR, 0x0F, BIT0 + BIT1 + BIT2 + BIT3);
  735. /* Power on LVDS channel. */
  736. switch (plvds_chip_info->output_interface) {
  737. case INTERFACE_LVDS0:
  738. {
  739. viafb_write_reg_mask(CRD2, VIACR, 0, BIT7);
  740. break;
  741. }
  742. case INTERFACE_LVDS1:
  743. {
  744. viafb_write_reg_mask(CRD2, VIACR, 0, BIT6);
  745. break;
  746. }
  747. case INTERFACE_LVDS0LVDS1:
  748. {
  749. viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);
  750. break;
  751. }
  752. }
  753. }
  754. void viafb_lcd_disable(void)
  755. {
  756. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
  757. lcd_powersequence_off();
  758. /* DI1 pad off */
  759. viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30);
  760. } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
  761. if (viafb_LCD2_ON
  762. && (INTEGRATED_LVDS ==
  763. viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
  764. integrated_lvds_disable(viaparinfo->lvds_setting_info,
  765. &viaparinfo->chip_info->lvds_chip_info2);
  766. if (INTEGRATED_LVDS ==
  767. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
  768. integrated_lvds_disable(viaparinfo->lvds_setting_info,
  769. &viaparinfo->chip_info->lvds_chip_info);
  770. if (VT1636_LVDS == viaparinfo->chip_info->
  771. lvds_chip_info.lvds_chip_name)
  772. viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
  773. &viaparinfo->chip_info->lvds_chip_info);
  774. } else if (VT1636_LVDS ==
  775. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
  776. viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
  777. &viaparinfo->chip_info->lvds_chip_info);
  778. } else {
  779. /* DFP-HL pad off */
  780. viafb_write_reg_mask(SR2A, VIASR, 0x00, 0x0F);
  781. /* Backlight off */
  782. viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20);
  783. /* 24 bit DI data paht off */
  784. viafb_write_reg_mask(CR91, VIACR, 0x80, 0x80);
  785. /* Simultaneout disabled */
  786. viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
  787. }
  788. /* Disable expansion bit */
  789. viafb_write_reg_mask(CR79, VIACR, 0x00, 0x01);
  790. /* CRT path set to IGA1 */
  791. viafb_write_reg_mask(SR16, VIASR, 0x00, 0x40);
  792. /* Simultaneout disabled */
  793. viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
  794. /* IGA2 path disabled */
  795. viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
  796. }
  797. void viafb_lcd_enable(void)
  798. {
  799. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
  800. /* DI1 pad on */
  801. viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);
  802. lcd_powersequence_on();
  803. } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
  804. if (viafb_LCD2_ON && (INTEGRATED_LVDS ==
  805. viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
  806. integrated_lvds_enable(viaparinfo->lvds_setting_info2, \
  807. &viaparinfo->chip_info->lvds_chip_info2);
  808. if (INTEGRATED_LVDS ==
  809. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
  810. integrated_lvds_enable(viaparinfo->lvds_setting_info,
  811. &viaparinfo->chip_info->lvds_chip_info);
  812. if (VT1636_LVDS == viaparinfo->chip_info->
  813. lvds_chip_info.lvds_chip_name)
  814. viafb_enable_lvds_vt1636(viaparinfo->
  815. lvds_setting_info, &viaparinfo->chip_info->
  816. lvds_chip_info);
  817. } else if (VT1636_LVDS ==
  818. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
  819. viafb_enable_lvds_vt1636(viaparinfo->lvds_setting_info,
  820. &viaparinfo->chip_info->lvds_chip_info);
  821. } else {
  822. /* DFP-HL pad on */
  823. viafb_write_reg_mask(SR2A, VIASR, 0x0F, 0x0F);
  824. /* Backlight on */
  825. viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20);
  826. /* 24 bit DI data paht on */
  827. viafb_write_reg_mask(CR91, VIACR, 0x00, 0x80);
  828. /* Set data source selection bit by iga path */
  829. if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
  830. /* DFP-H set to IGA1 */
  831. viafb_write_reg_mask(CR97, VIACR, 0x00, 0x10);
  832. /* DFP-L set to IGA1 */
  833. viafb_write_reg_mask(CR99, VIACR, 0x00, 0x10);
  834. } else {
  835. /* DFP-H set to IGA2 */
  836. viafb_write_reg_mask(CR97, VIACR, 0x10, 0x10);
  837. /* DFP-L set to IGA2 */
  838. viafb_write_reg_mask(CR99, VIACR, 0x10, 0x10);
  839. }
  840. /* LCD enabled */
  841. viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48);
  842. }
  843. if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
  844. /* CRT path set to IGA2 */
  845. viafb_write_reg_mask(SR16, VIASR, 0x40, 0x40);
  846. /* IGA2 path disabled */
  847. viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
  848. /* IGA2 path enabled */
  849. } else { /* IGA2 */
  850. viafb_write_reg_mask(CR6A, VIACR, 0x80, 0x80);
  851. }
  852. }
  853. static void lcd_powersequence_off(void)
  854. {
  855. int i, mask, data;
  856. /* Software control power sequence */
  857. viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
  858. for (i = 0; i < 3; i++) {
  859. mask = PowerSequenceOff[0][i];
  860. data = PowerSequenceOff[1][i] & mask;
  861. viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
  862. udelay(PowerSequenceOff[2][i]);
  863. }
  864. /* Disable LCD */
  865. viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x08);
  866. }
  867. static void lcd_powersequence_on(void)
  868. {
  869. int i, mask, data;
  870. /* Software control power sequence */
  871. viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
  872. /* Enable LCD */
  873. viafb_write_reg_mask(CR6A, VIACR, 0x08, 0x08);
  874. for (i = 0; i < 3; i++) {
  875. mask = PowerSequenceOn[0][i];
  876. data = PowerSequenceOn[1][i] & mask;
  877. viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
  878. udelay(PowerSequenceOn[2][i]);
  879. }
  880. udelay(1);
  881. }
  882. static void fill_lcd_format(void)
  883. {
  884. u8 bdithering = 0, bdual = 0;
  885. if (viaparinfo->lvds_setting_info->device_lcd_dualedge)
  886. bdual = BIT4;
  887. if (viaparinfo->lvds_setting_info->LCDDithering)
  888. bdithering = BIT0;
  889. /* Dual & Dithering */
  890. viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0);
  891. }
  892. static void check_diport_of_integrated_lvds(
  893. struct lvds_chip_information *plvds_chip_info,
  894. struct lvds_setting_information
  895. *plvds_setting_info)
  896. {
  897. /* Determine LCD DI Port by hardware layout. */
  898. switch (viafb_display_hardware_layout) {
  899. case HW_LAYOUT_LCD_ONLY:
  900. {
  901. if (plvds_setting_info->device_lcd_dualedge) {
  902. plvds_chip_info->output_interface =
  903. INTERFACE_LVDS0LVDS1;
  904. } else {
  905. plvds_chip_info->output_interface =
  906. INTERFACE_LVDS0;
  907. }
  908. break;
  909. }
  910. case HW_LAYOUT_DVI_ONLY:
  911. {
  912. plvds_chip_info->output_interface = INTERFACE_NONE;
  913. break;
  914. }
  915. case HW_LAYOUT_LCD1_LCD2:
  916. case HW_LAYOUT_LCD_EXTERNAL_LCD2:
  917. {
  918. plvds_chip_info->output_interface =
  919. INTERFACE_LVDS0LVDS1;
  920. break;
  921. }
  922. case HW_LAYOUT_LCD_DVI:
  923. {
  924. plvds_chip_info->output_interface = INTERFACE_LVDS1;
  925. break;
  926. }
  927. default:
  928. {
  929. plvds_chip_info->output_interface = INTERFACE_LVDS1;
  930. break;
  931. }
  932. }
  933. DEBUG_MSG(KERN_INFO
  934. "Display Hardware Layout: 0x%x, LCD DI Port: 0x%x\n",
  935. viafb_display_hardware_layout,
  936. plvds_chip_info->output_interface);
  937. }
  938. void viafb_init_lvds_output_interface(struct lvds_chip_information
  939. *plvds_chip_info,
  940. struct lvds_setting_information
  941. *plvds_setting_info)
  942. {
  943. if (INTERFACE_NONE != plvds_chip_info->output_interface) {
  944. /*Do nothing, lcd port is specified by module parameter */
  945. return;
  946. }
  947. switch (plvds_chip_info->lvds_chip_name) {
  948. case VT1636_LVDS:
  949. switch (viaparinfo->chip_info->gfx_chip_name) {
  950. case UNICHROME_CX700:
  951. plvds_chip_info->output_interface = INTERFACE_DVP1;
  952. break;
  953. case UNICHROME_CN700:
  954. plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
  955. break;
  956. default:
  957. plvds_chip_info->output_interface = INTERFACE_DVP0;
  958. break;
  959. }
  960. break;
  961. case INTEGRATED_LVDS:
  962. check_diport_of_integrated_lvds(plvds_chip_info,
  963. plvds_setting_info);
  964. break;
  965. default:
  966. switch (viaparinfo->chip_info->gfx_chip_name) {
  967. case UNICHROME_K8M890:
  968. case UNICHROME_P4M900:
  969. case UNICHROME_P4M890:
  970. plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
  971. break;
  972. default:
  973. plvds_chip_info->output_interface = INTERFACE_DFP;
  974. break;
  975. }
  976. break;
  977. }
  978. }
  979. static struct display_timing lcd_centering_timging(struct display_timing
  980. mode_crt_reg,
  981. struct display_timing panel_crt_reg)
  982. {
  983. struct display_timing crt_reg;
  984. crt_reg.hor_total = panel_crt_reg.hor_total;
  985. crt_reg.hor_addr = mode_crt_reg.hor_addr;
  986. crt_reg.hor_blank_start =
  987. (panel_crt_reg.hor_addr - mode_crt_reg.hor_addr) / 2 +
  988. crt_reg.hor_addr;
  989. crt_reg.hor_blank_end = panel_crt_reg.hor_blank_end;
  990. crt_reg.hor_sync_start =
  991. (panel_crt_reg.hor_sync_start -
  992. panel_crt_reg.hor_blank_start) + crt_reg.hor_blank_start;
  993. crt_reg.hor_sync_end = panel_crt_reg.hor_sync_end;
  994. crt_reg.ver_total = panel_crt_reg.ver_total;
  995. crt_reg.ver_addr = mode_crt_reg.ver_addr;
  996. crt_reg.ver_blank_start =
  997. (panel_crt_reg.ver_addr - mode_crt_reg.ver_addr) / 2 +
  998. crt_reg.ver_addr;
  999. crt_reg.ver_blank_end = panel_crt_reg.ver_blank_end;
  1000. crt_reg.ver_sync_start =
  1001. (panel_crt_reg.ver_sync_start -
  1002. panel_crt_reg.ver_blank_start) + crt_reg.ver_blank_start;
  1003. crt_reg.ver_sync_end = panel_crt_reg.ver_sync_end;
  1004. return crt_reg;
  1005. }
  1006. bool viafb_lcd_get_mobile_state(bool *mobile)
  1007. {
  1008. unsigned char *romptr, *tableptr;
  1009. u8 core_base;
  1010. unsigned char *biosptr;
  1011. /* Rom address */
  1012. u32 romaddr = 0x000C0000;
  1013. u16 start_pattern = 0;
  1014. biosptr = ioremap(romaddr, 0x10000);
  1015. memcpy(&start_pattern, biosptr, 2);
  1016. /* Compare pattern */
  1017. if (start_pattern == 0xAA55) {
  1018. /* Get the start of Table */
  1019. /* 0x1B means BIOS offset position */
  1020. romptr = biosptr + 0x1B;
  1021. tableptr = biosptr + *((u16 *) romptr);
  1022. /* Get the start of biosver structure */
  1023. /* 18 means BIOS version position. */
  1024. romptr = tableptr + 18;
  1025. romptr = biosptr + *((u16 *) romptr);
  1026. /* The offset should be 44, but the
  1027. actual image is less three char. */
  1028. /* pRom += 44; */
  1029. romptr += 41;
  1030. core_base = *romptr++;
  1031. if (core_base & 0x8)
  1032. *mobile = false;
  1033. else
  1034. *mobile = true;
  1035. /* release memory */
  1036. iounmap(biosptr);
  1037. return true;
  1038. } else {
  1039. iounmap(biosptr);
  1040. return false;
  1041. }
  1042. }