bcm43xx_main.c 108 KB

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  1. /*
  2. Broadcom BCM43xx wireless driver
  3. Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
  4. Stefano Brivio <st3@riseup.net>
  5. Michael Buesch <mbuesch@freenet.de>
  6. Danny van Dyk <kugelfang@gentoo.org>
  7. Andreas Jaggi <andreas.jaggi@waterwave.ch>
  8. Some parts of the code in this file are derived from the ipw2200
  9. driver Copyright(c) 2003 - 2004 Intel Corporation.
  10. This program is free software; you can redistribute it and/or modify
  11. it under the terms of the GNU General Public License as published by
  12. the Free Software Foundation; either version 2 of the License, or
  13. (at your option) any later version.
  14. This program is distributed in the hope that it will be useful,
  15. but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. GNU General Public License for more details.
  18. You should have received a copy of the GNU General Public License
  19. along with this program; see the file COPYING. If not, write to
  20. the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21. Boston, MA 02110-1301, USA.
  22. */
  23. #include <linux/delay.h>
  24. #include <linux/init.h>
  25. #include <linux/moduleparam.h>
  26. #include <linux/if_arp.h>
  27. #include <linux/etherdevice.h>
  28. #include <linux/version.h>
  29. #include <linux/firmware.h>
  30. #include <linux/wireless.h>
  31. #include <linux/workqueue.h>
  32. #include <linux/skbuff.h>
  33. #include <linux/dma-mapping.h>
  34. #include <net/iw_handler.h>
  35. #include "bcm43xx.h"
  36. #include "bcm43xx_main.h"
  37. #include "bcm43xx_debugfs.h"
  38. #include "bcm43xx_radio.h"
  39. #include "bcm43xx_phy.h"
  40. #include "bcm43xx_dma.h"
  41. #include "bcm43xx_pio.h"
  42. #include "bcm43xx_power.h"
  43. #include "bcm43xx_wx.h"
  44. #include "bcm43xx_ethtool.h"
  45. #include "bcm43xx_xmit.h"
  46. #include "bcm43xx_sysfs.h"
  47. MODULE_DESCRIPTION("Broadcom BCM43xx wireless driver");
  48. MODULE_AUTHOR("Martin Langer");
  49. MODULE_AUTHOR("Stefano Brivio");
  50. MODULE_AUTHOR("Michael Buesch");
  51. MODULE_LICENSE("GPL");
  52. #ifdef CONFIG_BCM947XX
  53. extern char *nvram_get(char *name);
  54. #endif
  55. #if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO)
  56. static int modparam_pio;
  57. module_param_named(pio, modparam_pio, int, 0444);
  58. MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
  59. #elif defined(CONFIG_BCM43XX_DMA)
  60. # define modparam_pio 0
  61. #elif defined(CONFIG_BCM43XX_PIO)
  62. # define modparam_pio 1
  63. #endif
  64. static int modparam_bad_frames_preempt;
  65. module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  66. MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames Preemption");
  67. static int modparam_short_retry = BCM43xx_DEFAULT_SHORT_RETRY_LIMIT;
  68. module_param_named(short_retry, modparam_short_retry, int, 0444);
  69. MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
  70. static int modparam_long_retry = BCM43xx_DEFAULT_LONG_RETRY_LIMIT;
  71. module_param_named(long_retry, modparam_long_retry, int, 0444);
  72. MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
  73. static int modparam_locale = -1;
  74. module_param_named(locale, modparam_locale, int, 0444);
  75. MODULE_PARM_DESC(country, "Select LocaleCode 0-11 (For travelers)");
  76. static int modparam_noleds;
  77. module_param_named(noleds, modparam_noleds, int, 0444);
  78. MODULE_PARM_DESC(noleds, "Turn off all LED activity");
  79. #ifdef CONFIG_BCM43XX_DEBUG
  80. static char modparam_fwpostfix[64];
  81. module_param_string(fwpostfix, modparam_fwpostfix, 64, 0444);
  82. MODULE_PARM_DESC(fwpostfix, "Postfix for .fw files. Useful for debugging.");
  83. #else
  84. # define modparam_fwpostfix ""
  85. #endif /* CONFIG_BCM43XX_DEBUG*/
  86. /* If you want to debug with just a single device, enable this,
  87. * where the string is the pci device ID (as given by the kernel's
  88. * pci_name function) of the device to be used.
  89. */
  90. //#define DEBUG_SINGLE_DEVICE_ONLY "0001:11:00.0"
  91. /* If you want to enable printing of each MMIO access, enable this. */
  92. //#define DEBUG_ENABLE_MMIO_PRINT
  93. /* If you want to enable printing of MMIO access within
  94. * ucode/pcm upload, initvals write, enable this.
  95. */
  96. //#define DEBUG_ENABLE_UCODE_MMIO_PRINT
  97. /* If you want to enable printing of PCI Config Space access, enable this */
  98. //#define DEBUG_ENABLE_PCILOG
  99. /* Detailed list maintained at:
  100. * http://openfacts.berlios.de/index-en.phtml?title=Bcm43xxDevices
  101. */
  102. static struct pci_device_id bcm43xx_pci_tbl[] = {
  103. /* Broadcom 4303 802.11b */
  104. { PCI_VENDOR_ID_BROADCOM, 0x4301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  105. /* Broadcom 4307 802.11b */
  106. { PCI_VENDOR_ID_BROADCOM, 0x4307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  107. /* Broadcom 4318 802.11b/g */
  108. { PCI_VENDOR_ID_BROADCOM, 0x4318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  109. /* Broadcom 4306 802.11b/g */
  110. { PCI_VENDOR_ID_BROADCOM, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  111. /* Broadcom 4306 802.11a */
  112. // { PCI_VENDOR_ID_BROADCOM, 0x4321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  113. /* Broadcom 4309 802.11a/b/g */
  114. { PCI_VENDOR_ID_BROADCOM, 0x4324, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  115. /* Broadcom 43XG 802.11b/g */
  116. { PCI_VENDOR_ID_BROADCOM, 0x4325, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  117. #ifdef CONFIG_BCM947XX
  118. /* SB bus on BCM947xx */
  119. { PCI_VENDOR_ID_BROADCOM, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  120. #endif
  121. { 0 },
  122. };
  123. MODULE_DEVICE_TABLE(pci, bcm43xx_pci_tbl);
  124. static void bcm43xx_ram_write(struct bcm43xx_private *bcm, u16 offset, u32 val)
  125. {
  126. u32 status;
  127. status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
  128. if (!(status & BCM43xx_SBF_XFER_REG_BYTESWAP))
  129. val = swab32(val);
  130. bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_CONTROL, offset);
  131. mmiowb();
  132. bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_DATA, val);
  133. }
  134. static inline
  135. void bcm43xx_shm_control_word(struct bcm43xx_private *bcm,
  136. u16 routing, u16 offset)
  137. {
  138. u32 control;
  139. /* "offset" is the WORD offset. */
  140. control = routing;
  141. control <<= 16;
  142. control |= offset;
  143. bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_CONTROL, control);
  144. }
  145. u32 bcm43xx_shm_read32(struct bcm43xx_private *bcm,
  146. u16 routing, u16 offset)
  147. {
  148. u32 ret;
  149. if (routing == BCM43xx_SHM_SHARED) {
  150. if (offset & 0x0003) {
  151. /* Unaligned access */
  152. bcm43xx_shm_control_word(bcm, routing, offset >> 2);
  153. ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
  154. ret <<= 16;
  155. bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
  156. ret |= bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
  157. return ret;
  158. }
  159. offset >>= 2;
  160. }
  161. bcm43xx_shm_control_word(bcm, routing, offset);
  162. ret = bcm43xx_read32(bcm, BCM43xx_MMIO_SHM_DATA);
  163. return ret;
  164. }
  165. u16 bcm43xx_shm_read16(struct bcm43xx_private *bcm,
  166. u16 routing, u16 offset)
  167. {
  168. u16 ret;
  169. if (routing == BCM43xx_SHM_SHARED) {
  170. if (offset & 0x0003) {
  171. /* Unaligned access */
  172. bcm43xx_shm_control_word(bcm, routing, offset >> 2);
  173. ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
  174. return ret;
  175. }
  176. offset >>= 2;
  177. }
  178. bcm43xx_shm_control_word(bcm, routing, offset);
  179. ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
  180. return ret;
  181. }
  182. void bcm43xx_shm_write32(struct bcm43xx_private *bcm,
  183. u16 routing, u16 offset,
  184. u32 value)
  185. {
  186. if (routing == BCM43xx_SHM_SHARED) {
  187. if (offset & 0x0003) {
  188. /* Unaligned access */
  189. bcm43xx_shm_control_word(bcm, routing, offset >> 2);
  190. mmiowb();
  191. bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
  192. (value >> 16) & 0xffff);
  193. mmiowb();
  194. bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
  195. mmiowb();
  196. bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA,
  197. value & 0xffff);
  198. return;
  199. }
  200. offset >>= 2;
  201. }
  202. bcm43xx_shm_control_word(bcm, routing, offset);
  203. mmiowb();
  204. bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, value);
  205. }
  206. void bcm43xx_shm_write16(struct bcm43xx_private *bcm,
  207. u16 routing, u16 offset,
  208. u16 value)
  209. {
  210. if (routing == BCM43xx_SHM_SHARED) {
  211. if (offset & 0x0003) {
  212. /* Unaligned access */
  213. bcm43xx_shm_control_word(bcm, routing, offset >> 2);
  214. mmiowb();
  215. bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
  216. value);
  217. return;
  218. }
  219. offset >>= 2;
  220. }
  221. bcm43xx_shm_control_word(bcm, routing, offset);
  222. mmiowb();
  223. bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA, value);
  224. }
  225. void bcm43xx_tsf_read(struct bcm43xx_private *bcm, u64 *tsf)
  226. {
  227. /* We need to be careful. As we read the TSF from multiple
  228. * registers, we should take care of register overflows.
  229. * In theory, the whole tsf read process should be atomic.
  230. * We try to be atomic here, by restaring the read process,
  231. * if any of the high registers changed (overflew).
  232. */
  233. if (bcm->current_core->rev >= 3) {
  234. u32 low, high, high2;
  235. do {
  236. high = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
  237. low = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW);
  238. high2 = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
  239. } while (unlikely(high != high2));
  240. *tsf = high;
  241. *tsf <<= 32;
  242. *tsf |= low;
  243. } else {
  244. u64 tmp;
  245. u16 v0, v1, v2, v3;
  246. u16 test1, test2, test3;
  247. do {
  248. v3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
  249. v2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
  250. v1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
  251. v0 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_0);
  252. test3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
  253. test2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
  254. test1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
  255. } while (v3 != test3 || v2 != test2 || v1 != test1);
  256. *tsf = v3;
  257. *tsf <<= 48;
  258. tmp = v2;
  259. tmp <<= 32;
  260. *tsf |= tmp;
  261. tmp = v1;
  262. tmp <<= 16;
  263. *tsf |= tmp;
  264. *tsf |= v0;
  265. }
  266. }
  267. void bcm43xx_tsf_write(struct bcm43xx_private *bcm, u64 tsf)
  268. {
  269. u32 status;
  270. status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
  271. status |= BCM43xx_SBF_TIME_UPDATE;
  272. bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
  273. mmiowb();
  274. /* Be careful with the in-progress timer.
  275. * First zero out the low register, so we have a full
  276. * register-overflow duration to complete the operation.
  277. */
  278. if (bcm->current_core->rev >= 3) {
  279. u32 lo = (tsf & 0x00000000FFFFFFFFULL);
  280. u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
  281. bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, 0);
  282. mmiowb();
  283. bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH, hi);
  284. mmiowb();
  285. bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, lo);
  286. } else {
  287. u16 v0 = (tsf & 0x000000000000FFFFULL);
  288. u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
  289. u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
  290. u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
  291. bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, 0);
  292. mmiowb();
  293. bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_3, v3);
  294. mmiowb();
  295. bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_2, v2);
  296. mmiowb();
  297. bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_1, v1);
  298. mmiowb();
  299. bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, v0);
  300. }
  301. status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
  302. status &= ~BCM43xx_SBF_TIME_UPDATE;
  303. bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
  304. }
  305. static
  306. void bcm43xx_macfilter_set(struct bcm43xx_private *bcm,
  307. u16 offset,
  308. const u8 *mac)
  309. {
  310. u16 data;
  311. offset |= 0x0020;
  312. bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_CONTROL, offset);
  313. data = mac[0];
  314. data |= mac[1] << 8;
  315. bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
  316. data = mac[2];
  317. data |= mac[3] << 8;
  318. bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
  319. data = mac[4];
  320. data |= mac[5] << 8;
  321. bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
  322. }
  323. static void bcm43xx_macfilter_clear(struct bcm43xx_private *bcm,
  324. u16 offset)
  325. {
  326. const u8 zero_addr[ETH_ALEN] = { 0 };
  327. bcm43xx_macfilter_set(bcm, offset, zero_addr);
  328. }
  329. static void bcm43xx_write_mac_bssid_templates(struct bcm43xx_private *bcm)
  330. {
  331. const u8 *mac = (const u8 *)(bcm->net_dev->dev_addr);
  332. const u8 *bssid = (const u8 *)(bcm->ieee->bssid);
  333. u8 mac_bssid[ETH_ALEN * 2];
  334. int i;
  335. memcpy(mac_bssid, mac, ETH_ALEN);
  336. memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
  337. /* Write our MAC address and BSSID to template ram */
  338. for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
  339. bcm43xx_ram_write(bcm, 0x20 + i, *((u32 *)(mac_bssid + i)));
  340. for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
  341. bcm43xx_ram_write(bcm, 0x78 + i, *((u32 *)(mac_bssid + i)));
  342. for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
  343. bcm43xx_ram_write(bcm, 0x478 + i, *((u32 *)(mac_bssid + i)));
  344. }
  345. //FIXME: Well, we should probably call them from somewhere.
  346. #if 0
  347. static void bcm43xx_set_slot_time(struct bcm43xx_private *bcm, u16 slot_time)
  348. {
  349. /* slot_time is in usec. */
  350. if (bcm43xx_current_phy(bcm)->type != BCM43xx_PHYTYPE_G)
  351. return;
  352. bcm43xx_write16(bcm, 0x684, 510 + slot_time);
  353. bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0010, slot_time);
  354. }
  355. static void bcm43xx_short_slot_timing_enable(struct bcm43xx_private *bcm)
  356. {
  357. bcm43xx_set_slot_time(bcm, 9);
  358. }
  359. static void bcm43xx_short_slot_timing_disable(struct bcm43xx_private *bcm)
  360. {
  361. bcm43xx_set_slot_time(bcm, 20);
  362. }
  363. #endif
  364. /* FIXME: To get the MAC-filter working, we need to implement the
  365. * following functions (and rename them :)
  366. */
  367. #if 0
  368. static void bcm43xx_disassociate(struct bcm43xx_private *bcm)
  369. {
  370. bcm43xx_mac_suspend(bcm);
  371. bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
  372. bcm43xx_ram_write(bcm, 0x0026, 0x0000);
  373. bcm43xx_ram_write(bcm, 0x0028, 0x0000);
  374. bcm43xx_ram_write(bcm, 0x007E, 0x0000);
  375. bcm43xx_ram_write(bcm, 0x0080, 0x0000);
  376. bcm43xx_ram_write(bcm, 0x047E, 0x0000);
  377. bcm43xx_ram_write(bcm, 0x0480, 0x0000);
  378. if (bcm->current_core->rev < 3) {
  379. bcm43xx_write16(bcm, 0x0610, 0x8000);
  380. bcm43xx_write16(bcm, 0x060E, 0x0000);
  381. } else
  382. bcm43xx_write32(bcm, 0x0188, 0x80000000);
  383. bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
  384. if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G &&
  385. ieee80211_is_ofdm_rate(bcm->softmac->txrates.default_rate))
  386. bcm43xx_short_slot_timing_enable(bcm);
  387. bcm43xx_mac_enable(bcm);
  388. }
  389. static void bcm43xx_associate(struct bcm43xx_private *bcm,
  390. const u8 *mac)
  391. {
  392. memcpy(bcm->ieee->bssid, mac, ETH_ALEN);
  393. bcm43xx_mac_suspend(bcm);
  394. bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_ASSOC, mac);
  395. bcm43xx_write_mac_bssid_templates(bcm);
  396. bcm43xx_mac_enable(bcm);
  397. }
  398. #endif
  399. /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
  400. * Returns the _previously_ enabled IRQ mask.
  401. */
  402. static inline u32 bcm43xx_interrupt_enable(struct bcm43xx_private *bcm, u32 mask)
  403. {
  404. u32 old_mask;
  405. old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
  406. bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask | mask);
  407. return old_mask;
  408. }
  409. /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
  410. * Returns the _previously_ enabled IRQ mask.
  411. */
  412. static inline u32 bcm43xx_interrupt_disable(struct bcm43xx_private *bcm, u32 mask)
  413. {
  414. u32 old_mask;
  415. old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
  416. bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
  417. return old_mask;
  418. }
  419. /* Make sure we don't receive more data from the device. */
  420. static int bcm43xx_disable_interrupts_sync(struct bcm43xx_private *bcm, u32 *oldstate)
  421. {
  422. u32 old;
  423. unsigned long flags;
  424. bcm43xx_lock_mmio(bcm, flags);
  425. if (bcm43xx_is_initializing(bcm) || bcm->shutting_down) {
  426. bcm43xx_unlock_mmio(bcm, flags);
  427. return -EBUSY;
  428. }
  429. old = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
  430. tasklet_disable(&bcm->isr_tasklet);
  431. bcm43xx_unlock_mmio(bcm, flags);
  432. if (oldstate)
  433. *oldstate = old;
  434. return 0;
  435. }
  436. static int bcm43xx_read_radioinfo(struct bcm43xx_private *bcm)
  437. {
  438. struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
  439. struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
  440. u32 radio_id;
  441. u16 manufact;
  442. u16 version;
  443. u8 revision;
  444. s8 i;
  445. if (bcm->chip_id == 0x4317) {
  446. if (bcm->chip_rev == 0x00)
  447. radio_id = 0x3205017F;
  448. else if (bcm->chip_rev == 0x01)
  449. radio_id = 0x4205017F;
  450. else
  451. radio_id = 0x5205017F;
  452. } else {
  453. bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
  454. radio_id = bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_HIGH);
  455. radio_id <<= 16;
  456. bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
  457. radio_id |= bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_LOW);
  458. }
  459. manufact = (radio_id & 0x00000FFF);
  460. version = (radio_id & 0x0FFFF000) >> 12;
  461. revision = (radio_id & 0xF0000000) >> 28;
  462. dprintk(KERN_INFO PFX "Detected Radio: ID: %x (Manuf: %x Ver: %x Rev: %x)\n",
  463. radio_id, manufact, version, revision);
  464. switch (phy->type) {
  465. case BCM43xx_PHYTYPE_A:
  466. if ((version != 0x2060) || (revision != 1) || (manufact != 0x17f))
  467. goto err_unsupported_radio;
  468. break;
  469. case BCM43xx_PHYTYPE_B:
  470. if ((version & 0xFFF0) != 0x2050)
  471. goto err_unsupported_radio;
  472. break;
  473. case BCM43xx_PHYTYPE_G:
  474. if (version != 0x2050)
  475. goto err_unsupported_radio;
  476. break;
  477. }
  478. radio->manufact = manufact;
  479. radio->version = version;
  480. radio->revision = revision;
  481. /* Set default attenuation values. */
  482. radio->baseband_atten = bcm43xx_default_baseband_attenuation(bcm);
  483. radio->radio_atten = bcm43xx_default_radio_attenuation(bcm);
  484. radio->txctl1 = bcm43xx_default_txctl1(bcm);
  485. radio->txctl2 = 0xFFFF;
  486. if (phy->type == BCM43xx_PHYTYPE_A)
  487. radio->txpower_desired = bcm->sprom.maxpower_aphy;
  488. else
  489. radio->txpower_desired = bcm->sprom.maxpower_bgphy;
  490. /* Initialize the in-memory nrssi Lookup Table. */
  491. for (i = 0; i < 64; i++)
  492. radio->nrssi_lt[i] = i;
  493. return 0;
  494. err_unsupported_radio:
  495. printk(KERN_ERR PFX "Unsupported Radio connected to the PHY!\n");
  496. return -ENODEV;
  497. }
  498. static const char * bcm43xx_locale_iso(u8 locale)
  499. {
  500. /* ISO 3166-1 country codes.
  501. * Note that there aren't ISO 3166-1 codes for
  502. * all or locales. (Not all locales are countries)
  503. */
  504. switch (locale) {
  505. case BCM43xx_LOCALE_WORLD:
  506. case BCM43xx_LOCALE_ALL:
  507. return "XX";
  508. case BCM43xx_LOCALE_THAILAND:
  509. return "TH";
  510. case BCM43xx_LOCALE_ISRAEL:
  511. return "IL";
  512. case BCM43xx_LOCALE_JORDAN:
  513. return "JO";
  514. case BCM43xx_LOCALE_CHINA:
  515. return "CN";
  516. case BCM43xx_LOCALE_JAPAN:
  517. case BCM43xx_LOCALE_JAPAN_HIGH:
  518. return "JP";
  519. case BCM43xx_LOCALE_USA_CANADA_ANZ:
  520. case BCM43xx_LOCALE_USA_LOW:
  521. return "US";
  522. case BCM43xx_LOCALE_EUROPE:
  523. return "EU";
  524. case BCM43xx_LOCALE_NONE:
  525. return " ";
  526. }
  527. assert(0);
  528. return " ";
  529. }
  530. static const char * bcm43xx_locale_string(u8 locale)
  531. {
  532. switch (locale) {
  533. case BCM43xx_LOCALE_WORLD:
  534. return "World";
  535. case BCM43xx_LOCALE_THAILAND:
  536. return "Thailand";
  537. case BCM43xx_LOCALE_ISRAEL:
  538. return "Israel";
  539. case BCM43xx_LOCALE_JORDAN:
  540. return "Jordan";
  541. case BCM43xx_LOCALE_CHINA:
  542. return "China";
  543. case BCM43xx_LOCALE_JAPAN:
  544. return "Japan";
  545. case BCM43xx_LOCALE_USA_CANADA_ANZ:
  546. return "USA/Canada/ANZ";
  547. case BCM43xx_LOCALE_EUROPE:
  548. return "Europe";
  549. case BCM43xx_LOCALE_USA_LOW:
  550. return "USAlow";
  551. case BCM43xx_LOCALE_JAPAN_HIGH:
  552. return "JapanHigh";
  553. case BCM43xx_LOCALE_ALL:
  554. return "All";
  555. case BCM43xx_LOCALE_NONE:
  556. return "None";
  557. }
  558. assert(0);
  559. return "";
  560. }
  561. static inline u8 bcm43xx_crc8(u8 crc, u8 data)
  562. {
  563. static const u8 t[] = {
  564. 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
  565. 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
  566. 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
  567. 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
  568. 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
  569. 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
  570. 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
  571. 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
  572. 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
  573. 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
  574. 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
  575. 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
  576. 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
  577. 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
  578. 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
  579. 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
  580. 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
  581. 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
  582. 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
  583. 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
  584. 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
  585. 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
  586. 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
  587. 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
  588. 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
  589. 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
  590. 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
  591. 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
  592. 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
  593. 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
  594. 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
  595. 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
  596. };
  597. return t[crc ^ data];
  598. }
  599. static u8 bcm43xx_sprom_crc(const u16 *sprom)
  600. {
  601. int word;
  602. u8 crc = 0xFF;
  603. for (word = 0; word < BCM43xx_SPROM_SIZE - 1; word++) {
  604. crc = bcm43xx_crc8(crc, sprom[word] & 0x00FF);
  605. crc = bcm43xx_crc8(crc, (sprom[word] & 0xFF00) >> 8);
  606. }
  607. crc = bcm43xx_crc8(crc, sprom[BCM43xx_SPROM_VERSION] & 0x00FF);
  608. crc ^= 0xFF;
  609. return crc;
  610. }
  611. int bcm43xx_sprom_read(struct bcm43xx_private *bcm, u16 *sprom)
  612. {
  613. int i;
  614. u8 crc, expected_crc;
  615. for (i = 0; i < BCM43xx_SPROM_SIZE; i++)
  616. sprom[i] = bcm43xx_read16(bcm, BCM43xx_SPROM_BASE + (i * 2));
  617. /* CRC-8 check. */
  618. crc = bcm43xx_sprom_crc(sprom);
  619. expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
  620. if (crc != expected_crc) {
  621. printk(KERN_WARNING PFX "WARNING: Invalid SPROM checksum "
  622. "(0x%02X, expected: 0x%02X)\n",
  623. crc, expected_crc);
  624. return -EINVAL;
  625. }
  626. return 0;
  627. }
  628. int bcm43xx_sprom_write(struct bcm43xx_private *bcm, const u16 *sprom)
  629. {
  630. int i, err;
  631. u8 crc, expected_crc;
  632. u32 spromctl;
  633. /* CRC-8 validation of the input data. */
  634. crc = bcm43xx_sprom_crc(sprom);
  635. expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
  636. if (crc != expected_crc) {
  637. printk(KERN_ERR PFX "SPROM input data: Invalid CRC\n");
  638. return -EINVAL;
  639. }
  640. printk(KERN_INFO PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
  641. err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_SPROMCTL, &spromctl);
  642. if (err)
  643. goto err_ctlreg;
  644. spromctl |= 0x10; /* SPROM WRITE enable. */
  645. bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
  646. if (err)
  647. goto err_ctlreg;
  648. /* We must burn lots of CPU cycles here, but that does not
  649. * really matter as one does not write the SPROM every other minute...
  650. */
  651. printk(KERN_INFO PFX "[ 0%%");
  652. mdelay(500);
  653. for (i = 0; i < BCM43xx_SPROM_SIZE; i++) {
  654. if (i == 16)
  655. printk("25%%");
  656. else if (i == 32)
  657. printk("50%%");
  658. else if (i == 48)
  659. printk("75%%");
  660. else if (i % 2)
  661. printk(".");
  662. bcm43xx_write16(bcm, BCM43xx_SPROM_BASE + (i * 2), sprom[i]);
  663. mmiowb();
  664. mdelay(20);
  665. }
  666. spromctl &= ~0x10; /* SPROM WRITE enable. */
  667. bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
  668. if (err)
  669. goto err_ctlreg;
  670. mdelay(500);
  671. printk("100%% ]\n");
  672. printk(KERN_INFO PFX "SPROM written.\n");
  673. bcm43xx_controller_restart(bcm, "SPROM update");
  674. return 0;
  675. err_ctlreg:
  676. printk(KERN_ERR PFX "Could not access SPROM control register.\n");
  677. return -ENODEV;
  678. }
  679. static int bcm43xx_sprom_extract(struct bcm43xx_private *bcm)
  680. {
  681. u16 value;
  682. u16 *sprom;
  683. #ifdef CONFIG_BCM947XX
  684. char *c;
  685. #endif
  686. sprom = kzalloc(BCM43xx_SPROM_SIZE * sizeof(u16),
  687. GFP_KERNEL);
  688. if (!sprom) {
  689. printk(KERN_ERR PFX "sprom_extract OOM\n");
  690. return -ENOMEM;
  691. }
  692. #ifdef CONFIG_BCM947XX
  693. sprom[BCM43xx_SPROM_BOARDFLAGS2] = atoi(nvram_get("boardflags2"));
  694. sprom[BCM43xx_SPROM_BOARDFLAGS] = atoi(nvram_get("boardflags"));
  695. if ((c = nvram_get("il0macaddr")) != NULL)
  696. e_aton(c, (char *) &(sprom[BCM43xx_SPROM_IL0MACADDR]));
  697. if ((c = nvram_get("et1macaddr")) != NULL)
  698. e_aton(c, (char *) &(sprom[BCM43xx_SPROM_ET1MACADDR]));
  699. sprom[BCM43xx_SPROM_PA0B0] = atoi(nvram_get("pa0b0"));
  700. sprom[BCM43xx_SPROM_PA0B1] = atoi(nvram_get("pa0b1"));
  701. sprom[BCM43xx_SPROM_PA0B2] = atoi(nvram_get("pa0b2"));
  702. sprom[BCM43xx_SPROM_PA1B0] = atoi(nvram_get("pa1b0"));
  703. sprom[BCM43xx_SPROM_PA1B1] = atoi(nvram_get("pa1b1"));
  704. sprom[BCM43xx_SPROM_PA1B2] = atoi(nvram_get("pa1b2"));
  705. sprom[BCM43xx_SPROM_BOARDREV] = atoi(nvram_get("boardrev"));
  706. #else
  707. bcm43xx_sprom_read(bcm, sprom);
  708. #endif
  709. /* boardflags2 */
  710. value = sprom[BCM43xx_SPROM_BOARDFLAGS2];
  711. bcm->sprom.boardflags2 = value;
  712. /* il0macaddr */
  713. value = sprom[BCM43xx_SPROM_IL0MACADDR + 0];
  714. *(((u16 *)bcm->sprom.il0macaddr) + 0) = cpu_to_be16(value);
  715. value = sprom[BCM43xx_SPROM_IL0MACADDR + 1];
  716. *(((u16 *)bcm->sprom.il0macaddr) + 1) = cpu_to_be16(value);
  717. value = sprom[BCM43xx_SPROM_IL0MACADDR + 2];
  718. *(((u16 *)bcm->sprom.il0macaddr) + 2) = cpu_to_be16(value);
  719. /* et0macaddr */
  720. value = sprom[BCM43xx_SPROM_ET0MACADDR + 0];
  721. *(((u16 *)bcm->sprom.et0macaddr) + 0) = cpu_to_be16(value);
  722. value = sprom[BCM43xx_SPROM_ET0MACADDR + 1];
  723. *(((u16 *)bcm->sprom.et0macaddr) + 1) = cpu_to_be16(value);
  724. value = sprom[BCM43xx_SPROM_ET0MACADDR + 2];
  725. *(((u16 *)bcm->sprom.et0macaddr) + 2) = cpu_to_be16(value);
  726. /* et1macaddr */
  727. value = sprom[BCM43xx_SPROM_ET1MACADDR + 0];
  728. *(((u16 *)bcm->sprom.et1macaddr) + 0) = cpu_to_be16(value);
  729. value = sprom[BCM43xx_SPROM_ET1MACADDR + 1];
  730. *(((u16 *)bcm->sprom.et1macaddr) + 1) = cpu_to_be16(value);
  731. value = sprom[BCM43xx_SPROM_ET1MACADDR + 2];
  732. *(((u16 *)bcm->sprom.et1macaddr) + 2) = cpu_to_be16(value);
  733. /* ethernet phy settings */
  734. value = sprom[BCM43xx_SPROM_ETHPHY];
  735. bcm->sprom.et0phyaddr = (value & 0x001F);
  736. bcm->sprom.et1phyaddr = (value & 0x03E0) >> 5;
  737. bcm->sprom.et0mdcport = (value & (1 << 14)) >> 14;
  738. bcm->sprom.et1mdcport = (value & (1 << 15)) >> 15;
  739. /* boardrev, antennas, locale */
  740. value = sprom[BCM43xx_SPROM_BOARDREV];
  741. bcm->sprom.boardrev = (value & 0x00FF);
  742. bcm->sprom.locale = (value & 0x0F00) >> 8;
  743. bcm->sprom.antennas_aphy = (value & 0x3000) >> 12;
  744. bcm->sprom.antennas_bgphy = (value & 0xC000) >> 14;
  745. if (modparam_locale != -1) {
  746. if (modparam_locale >= 0 && modparam_locale <= 11) {
  747. bcm->sprom.locale = modparam_locale;
  748. printk(KERN_WARNING PFX "Operating with modified "
  749. "LocaleCode %u (%s)\n",
  750. bcm->sprom.locale,
  751. bcm43xx_locale_string(bcm->sprom.locale));
  752. } else {
  753. printk(KERN_WARNING PFX "Module parameter \"locale\" "
  754. "invalid value. (0 - 11)\n");
  755. }
  756. }
  757. /* pa0b* */
  758. value = sprom[BCM43xx_SPROM_PA0B0];
  759. bcm->sprom.pa0b0 = value;
  760. value = sprom[BCM43xx_SPROM_PA0B1];
  761. bcm->sprom.pa0b1 = value;
  762. value = sprom[BCM43xx_SPROM_PA0B2];
  763. bcm->sprom.pa0b2 = value;
  764. /* wl0gpio* */
  765. value = sprom[BCM43xx_SPROM_WL0GPIO0];
  766. if (value == 0x0000)
  767. value = 0xFFFF;
  768. bcm->sprom.wl0gpio0 = value & 0x00FF;
  769. bcm->sprom.wl0gpio1 = (value & 0xFF00) >> 8;
  770. value = sprom[BCM43xx_SPROM_WL0GPIO2];
  771. if (value == 0x0000)
  772. value = 0xFFFF;
  773. bcm->sprom.wl0gpio2 = value & 0x00FF;
  774. bcm->sprom.wl0gpio3 = (value & 0xFF00) >> 8;
  775. /* maxpower */
  776. value = sprom[BCM43xx_SPROM_MAXPWR];
  777. bcm->sprom.maxpower_aphy = (value & 0xFF00) >> 8;
  778. bcm->sprom.maxpower_bgphy = value & 0x00FF;
  779. /* pa1b* */
  780. value = sprom[BCM43xx_SPROM_PA1B0];
  781. bcm->sprom.pa1b0 = value;
  782. value = sprom[BCM43xx_SPROM_PA1B1];
  783. bcm->sprom.pa1b1 = value;
  784. value = sprom[BCM43xx_SPROM_PA1B2];
  785. bcm->sprom.pa1b2 = value;
  786. /* idle tssi target */
  787. value = sprom[BCM43xx_SPROM_IDL_TSSI_TGT];
  788. bcm->sprom.idle_tssi_tgt_aphy = value & 0x00FF;
  789. bcm->sprom.idle_tssi_tgt_bgphy = (value & 0xFF00) >> 8;
  790. /* boardflags */
  791. value = sprom[BCM43xx_SPROM_BOARDFLAGS];
  792. if (value == 0xFFFF)
  793. value = 0x0000;
  794. bcm->sprom.boardflags = value;
  795. /* boardflags workarounds */
  796. if (bcm->board_vendor == PCI_VENDOR_ID_DELL &&
  797. bcm->chip_id == 0x4301 &&
  798. bcm->board_revision == 0x74)
  799. bcm->sprom.boardflags |= BCM43xx_BFL_BTCOEXIST;
  800. if (bcm->board_vendor == PCI_VENDOR_ID_APPLE &&
  801. bcm->board_type == 0x4E &&
  802. bcm->board_revision > 0x40)
  803. bcm->sprom.boardflags |= BCM43xx_BFL_PACTRL;
  804. /* antenna gain */
  805. value = sprom[BCM43xx_SPROM_ANTENNA_GAIN];
  806. if (value == 0x0000 || value == 0xFFFF)
  807. value = 0x0202;
  808. /* convert values to Q5.2 */
  809. bcm->sprom.antennagain_aphy = ((value & 0xFF00) >> 8) * 4;
  810. bcm->sprom.antennagain_bgphy = (value & 0x00FF) * 4;
  811. kfree(sprom);
  812. return 0;
  813. }
  814. static void bcm43xx_geo_init(struct bcm43xx_private *bcm)
  815. {
  816. struct ieee80211_geo geo;
  817. struct ieee80211_channel *chan;
  818. int have_a = 0, have_bg = 0;
  819. int i;
  820. u8 channel;
  821. struct bcm43xx_phyinfo *phy;
  822. const char *iso_country;
  823. memset(&geo, 0, sizeof(geo));
  824. for (i = 0; i < bcm->nr_80211_available; i++) {
  825. phy = &(bcm->core_80211_ext[i].phy);
  826. switch (phy->type) {
  827. case BCM43xx_PHYTYPE_B:
  828. case BCM43xx_PHYTYPE_G:
  829. have_bg = 1;
  830. break;
  831. case BCM43xx_PHYTYPE_A:
  832. have_a = 1;
  833. break;
  834. default:
  835. assert(0);
  836. }
  837. }
  838. iso_country = bcm43xx_locale_iso(bcm->sprom.locale);
  839. if (have_a) {
  840. for (i = 0, channel = 0; channel < 201; channel++) {
  841. chan = &geo.a[i++];
  842. chan->freq = bcm43xx_channel_to_freq_a(channel);
  843. chan->channel = channel;
  844. }
  845. geo.a_channels = i;
  846. }
  847. if (have_bg) {
  848. for (i = 0, channel = 1; channel < 15; channel++) {
  849. chan = &geo.bg[i++];
  850. chan->freq = bcm43xx_channel_to_freq_bg(channel);
  851. chan->channel = channel;
  852. }
  853. geo.bg_channels = i;
  854. }
  855. memcpy(geo.name, iso_country, 2);
  856. if (0 /*TODO: Outdoor use only */)
  857. geo.name[2] = 'O';
  858. else if (0 /*TODO: Indoor use only */)
  859. geo.name[2] = 'I';
  860. else
  861. geo.name[2] = ' ';
  862. geo.name[3] = '\0';
  863. ieee80211_set_geo(bcm->ieee, &geo);
  864. }
  865. /* DummyTransmission function, as documented on
  866. * http://bcm-specs.sipsolutions.net/DummyTransmission
  867. */
  868. void bcm43xx_dummy_transmission(struct bcm43xx_private *bcm)
  869. {
  870. struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
  871. struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
  872. unsigned int i, max_loop;
  873. u16 value = 0;
  874. u32 buffer[5] = {
  875. 0x00000000,
  876. 0x0000D400,
  877. 0x00000000,
  878. 0x00000001,
  879. 0x00000000,
  880. };
  881. switch (phy->type) {
  882. case BCM43xx_PHYTYPE_A:
  883. max_loop = 0x1E;
  884. buffer[0] = 0xCC010200;
  885. break;
  886. case BCM43xx_PHYTYPE_B:
  887. case BCM43xx_PHYTYPE_G:
  888. max_loop = 0xFA;
  889. buffer[0] = 0x6E840B00;
  890. break;
  891. default:
  892. assert(0);
  893. return;
  894. }
  895. for (i = 0; i < 5; i++)
  896. bcm43xx_ram_write(bcm, i * 4, buffer[i]);
  897. bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
  898. bcm43xx_write16(bcm, 0x0568, 0x0000);
  899. bcm43xx_write16(bcm, 0x07C0, 0x0000);
  900. bcm43xx_write16(bcm, 0x050C, ((phy->type == BCM43xx_PHYTYPE_A) ? 1 : 0));
  901. bcm43xx_write16(bcm, 0x0508, 0x0000);
  902. bcm43xx_write16(bcm, 0x050A, 0x0000);
  903. bcm43xx_write16(bcm, 0x054C, 0x0000);
  904. bcm43xx_write16(bcm, 0x056A, 0x0014);
  905. bcm43xx_write16(bcm, 0x0568, 0x0826);
  906. bcm43xx_write16(bcm, 0x0500, 0x0000);
  907. bcm43xx_write16(bcm, 0x0502, 0x0030);
  908. if (radio->version == 0x2050 && radio->revision <= 0x5)
  909. bcm43xx_radio_write16(bcm, 0x0051, 0x0017);
  910. for (i = 0x00; i < max_loop; i++) {
  911. value = bcm43xx_read16(bcm, 0x050E);
  912. if (value & 0x0080)
  913. break;
  914. udelay(10);
  915. }
  916. for (i = 0x00; i < 0x0A; i++) {
  917. value = bcm43xx_read16(bcm, 0x050E);
  918. if (value & 0x0400)
  919. break;
  920. udelay(10);
  921. }
  922. for (i = 0x00; i < 0x0A; i++) {
  923. value = bcm43xx_read16(bcm, 0x0690);
  924. if (!(value & 0x0100))
  925. break;
  926. udelay(10);
  927. }
  928. if (radio->version == 0x2050 && radio->revision <= 0x5)
  929. bcm43xx_radio_write16(bcm, 0x0051, 0x0037);
  930. }
  931. static void key_write(struct bcm43xx_private *bcm,
  932. u8 index, u8 algorithm, const u16 *key)
  933. {
  934. unsigned int i, basic_wep = 0;
  935. u32 offset;
  936. u16 value;
  937. /* Write associated key information */
  938. bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x100 + (index * 2),
  939. ((index << 4) | (algorithm & 0x0F)));
  940. /* The first 4 WEP keys need extra love */
  941. if (((algorithm == BCM43xx_SEC_ALGO_WEP) ||
  942. (algorithm == BCM43xx_SEC_ALGO_WEP104)) && (index < 4))
  943. basic_wep = 1;
  944. /* Write key payload, 8 little endian words */
  945. offset = bcm->security_offset + (index * BCM43xx_SEC_KEYSIZE);
  946. for (i = 0; i < (BCM43xx_SEC_KEYSIZE / sizeof(u16)); i++) {
  947. value = cpu_to_le16(key[i]);
  948. bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
  949. offset + (i * 2), value);
  950. if (!basic_wep)
  951. continue;
  952. bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
  953. offset + (i * 2) + 4 * BCM43xx_SEC_KEYSIZE,
  954. value);
  955. }
  956. }
  957. static void keymac_write(struct bcm43xx_private *bcm,
  958. u8 index, const u32 *addr)
  959. {
  960. /* for keys 0-3 there is no associated mac address */
  961. if (index < 4)
  962. return;
  963. index -= 4;
  964. if (bcm->current_core->rev >= 5) {
  965. bcm43xx_shm_write32(bcm,
  966. BCM43xx_SHM_HWMAC,
  967. index * 2,
  968. cpu_to_be32(*addr));
  969. bcm43xx_shm_write16(bcm,
  970. BCM43xx_SHM_HWMAC,
  971. (index * 2) + 1,
  972. cpu_to_be16(*((u16 *)(addr + 1))));
  973. } else {
  974. if (index < 8) {
  975. TODO(); /* Put them in the macaddress filter */
  976. } else {
  977. TODO();
  978. /* Put them BCM43xx_SHM_SHARED, stating index 0x0120.
  979. Keep in mind to update the count of keymacs in 0x003E as well! */
  980. }
  981. }
  982. }
  983. static int bcm43xx_key_write(struct bcm43xx_private *bcm,
  984. u8 index, u8 algorithm,
  985. const u8 *_key, int key_len,
  986. const u8 *mac_addr)
  987. {
  988. u8 key[BCM43xx_SEC_KEYSIZE] = { 0 };
  989. if (index >= ARRAY_SIZE(bcm->key))
  990. return -EINVAL;
  991. if (key_len > ARRAY_SIZE(key))
  992. return -EINVAL;
  993. if (algorithm < 1 || algorithm > 5)
  994. return -EINVAL;
  995. memcpy(key, _key, key_len);
  996. key_write(bcm, index, algorithm, (const u16 *)key);
  997. keymac_write(bcm, index, (const u32 *)mac_addr);
  998. bcm->key[index].algorithm = algorithm;
  999. return 0;
  1000. }
  1001. static void bcm43xx_clear_keys(struct bcm43xx_private *bcm)
  1002. {
  1003. static const u32 zero_mac[2] = { 0 };
  1004. unsigned int i,j, nr_keys = 54;
  1005. u16 offset;
  1006. if (bcm->current_core->rev < 5)
  1007. nr_keys = 16;
  1008. assert(nr_keys <= ARRAY_SIZE(bcm->key));
  1009. for (i = 0; i < nr_keys; i++) {
  1010. bcm->key[i].enabled = 0;
  1011. /* returns for i < 4 immediately */
  1012. keymac_write(bcm, i, zero_mac);
  1013. bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
  1014. 0x100 + (i * 2), 0x0000);
  1015. for (j = 0; j < 8; j++) {
  1016. offset = bcm->security_offset + (j * 4) + (i * BCM43xx_SEC_KEYSIZE);
  1017. bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
  1018. offset, 0x0000);
  1019. }
  1020. }
  1021. dprintk(KERN_INFO PFX "Keys cleared\n");
  1022. }
  1023. /* Lowlevel core-switch function. This is only to be used in
  1024. * bcm43xx_switch_core() and bcm43xx_probe_cores()
  1025. */
  1026. static int _switch_core(struct bcm43xx_private *bcm, int core)
  1027. {
  1028. int err;
  1029. int attempts = 0;
  1030. u32 current_core;
  1031. assert(core >= 0);
  1032. while (1) {
  1033. err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
  1034. (core * 0x1000) + 0x18000000);
  1035. if (unlikely(err))
  1036. goto error;
  1037. err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
  1038. &current_core);
  1039. if (unlikely(err))
  1040. goto error;
  1041. current_core = (current_core - 0x18000000) / 0x1000;
  1042. if (current_core == core)
  1043. break;
  1044. if (unlikely(attempts++ > BCM43xx_SWITCH_CORE_MAX_RETRIES))
  1045. goto error;
  1046. udelay(10);
  1047. }
  1048. #ifdef CONFIG_BCM947XX
  1049. if (bcm->pci_dev->bus->number == 0)
  1050. bcm->current_core_offset = 0x1000 * core;
  1051. else
  1052. bcm->current_core_offset = 0;
  1053. #endif
  1054. return 0;
  1055. error:
  1056. printk(KERN_ERR PFX "Failed to switch to core %d\n", core);
  1057. return -ENODEV;
  1058. }
  1059. int bcm43xx_switch_core(struct bcm43xx_private *bcm, struct bcm43xx_coreinfo *new_core)
  1060. {
  1061. int err;
  1062. if (unlikely(!new_core))
  1063. return 0;
  1064. if (!new_core->available)
  1065. return -ENODEV;
  1066. if (bcm->current_core == new_core)
  1067. return 0;
  1068. err = _switch_core(bcm, new_core->index);
  1069. if (unlikely(err))
  1070. goto out;
  1071. bcm->current_core = new_core;
  1072. bcm->current_80211_core_idx = -1;
  1073. if (new_core->id == BCM43xx_COREID_80211)
  1074. bcm->current_80211_core_idx = (int)(new_core - &(bcm->core_80211[0]));
  1075. out:
  1076. return err;
  1077. }
  1078. static int bcm43xx_core_enabled(struct bcm43xx_private *bcm)
  1079. {
  1080. u32 value;
  1081. value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
  1082. value &= BCM43xx_SBTMSTATELOW_CLOCK | BCM43xx_SBTMSTATELOW_RESET
  1083. | BCM43xx_SBTMSTATELOW_REJECT;
  1084. return (value == BCM43xx_SBTMSTATELOW_CLOCK);
  1085. }
  1086. /* disable current core */
  1087. static int bcm43xx_core_disable(struct bcm43xx_private *bcm, u32 core_flags)
  1088. {
  1089. u32 sbtmstatelow;
  1090. u32 sbtmstatehigh;
  1091. int i;
  1092. /* fetch sbtmstatelow from core information registers */
  1093. sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
  1094. /* core is already in reset */
  1095. if (sbtmstatelow & BCM43xx_SBTMSTATELOW_RESET)
  1096. goto out;
  1097. if (sbtmstatelow & BCM43xx_SBTMSTATELOW_CLOCK) {
  1098. sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
  1099. BCM43xx_SBTMSTATELOW_REJECT;
  1100. bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
  1101. for (i = 0; i < 1000; i++) {
  1102. sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
  1103. if (sbtmstatelow & BCM43xx_SBTMSTATELOW_REJECT) {
  1104. i = -1;
  1105. break;
  1106. }
  1107. udelay(10);
  1108. }
  1109. if (i != -1) {
  1110. printk(KERN_ERR PFX "Error: core_disable() REJECT timeout!\n");
  1111. return -EBUSY;
  1112. }
  1113. for (i = 0; i < 1000; i++) {
  1114. sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
  1115. if (!(sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_BUSY)) {
  1116. i = -1;
  1117. break;
  1118. }
  1119. udelay(10);
  1120. }
  1121. if (i != -1) {
  1122. printk(KERN_ERR PFX "Error: core_disable() BUSY timeout!\n");
  1123. return -EBUSY;
  1124. }
  1125. sbtmstatelow = BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
  1126. BCM43xx_SBTMSTATELOW_REJECT |
  1127. BCM43xx_SBTMSTATELOW_RESET |
  1128. BCM43xx_SBTMSTATELOW_CLOCK |
  1129. core_flags;
  1130. bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
  1131. udelay(10);
  1132. }
  1133. sbtmstatelow = BCM43xx_SBTMSTATELOW_RESET |
  1134. BCM43xx_SBTMSTATELOW_REJECT |
  1135. core_flags;
  1136. bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
  1137. out:
  1138. bcm->current_core->enabled = 0;
  1139. return 0;
  1140. }
  1141. /* enable (reset) current core */
  1142. static int bcm43xx_core_enable(struct bcm43xx_private *bcm, u32 core_flags)
  1143. {
  1144. u32 sbtmstatelow;
  1145. u32 sbtmstatehigh;
  1146. u32 sbimstate;
  1147. int err;
  1148. err = bcm43xx_core_disable(bcm, core_flags);
  1149. if (err)
  1150. goto out;
  1151. sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
  1152. BCM43xx_SBTMSTATELOW_RESET |
  1153. BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
  1154. core_flags;
  1155. bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
  1156. udelay(1);
  1157. sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
  1158. if (sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_SERROR) {
  1159. sbtmstatehigh = 0x00000000;
  1160. bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATEHIGH, sbtmstatehigh);
  1161. }
  1162. sbimstate = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMSTATE);
  1163. if (sbimstate & (BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT)) {
  1164. sbimstate &= ~(BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT);
  1165. bcm43xx_write32(bcm, BCM43xx_CIR_SBIMSTATE, sbimstate);
  1166. }
  1167. sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
  1168. BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
  1169. core_flags;
  1170. bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
  1171. udelay(1);
  1172. sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK | core_flags;
  1173. bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
  1174. udelay(1);
  1175. bcm->current_core->enabled = 1;
  1176. assert(err == 0);
  1177. out:
  1178. return err;
  1179. }
  1180. /* http://bcm-specs.sipsolutions.net/80211CoreReset */
  1181. void bcm43xx_wireless_core_reset(struct bcm43xx_private *bcm, int connect_phy)
  1182. {
  1183. u32 flags = 0x00040000;
  1184. if ((bcm43xx_core_enabled(bcm)) &&
  1185. !bcm43xx_using_pio(bcm)) {
  1186. //FIXME: Do we _really_ want #ifndef CONFIG_BCM947XX here?
  1187. #ifndef CONFIG_BCM947XX
  1188. /* reset all used DMA controllers. */
  1189. bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
  1190. bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA2_BASE);
  1191. bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA3_BASE);
  1192. bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
  1193. bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
  1194. if (bcm->current_core->rev < 5)
  1195. bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
  1196. #endif
  1197. }
  1198. if (bcm->shutting_down) {
  1199. bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
  1200. bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
  1201. & ~(BCM43xx_SBF_MAC_ENABLED | 0x00000002));
  1202. } else {
  1203. if (connect_phy)
  1204. flags |= 0x20000000;
  1205. bcm43xx_phy_connect(bcm, connect_phy);
  1206. bcm43xx_core_enable(bcm, flags);
  1207. bcm43xx_write16(bcm, 0x03E6, 0x0000);
  1208. bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
  1209. bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
  1210. | BCM43xx_SBF_400);
  1211. }
  1212. }
  1213. static void bcm43xx_wireless_core_disable(struct bcm43xx_private *bcm)
  1214. {
  1215. bcm43xx_radio_turn_off(bcm);
  1216. bcm43xx_write16(bcm, 0x03E6, 0x00F4);
  1217. bcm43xx_core_disable(bcm, 0);
  1218. }
  1219. /* Mark the current 80211 core inactive.
  1220. * "active_80211_core" is the other 80211 core, which is used.
  1221. */
  1222. static int bcm43xx_wireless_core_mark_inactive(struct bcm43xx_private *bcm,
  1223. struct bcm43xx_coreinfo *active_80211_core)
  1224. {
  1225. u32 sbtmstatelow;
  1226. struct bcm43xx_coreinfo *old_core;
  1227. int err = 0;
  1228. bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
  1229. bcm43xx_radio_turn_off(bcm);
  1230. sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
  1231. sbtmstatelow &= ~0x200a0000;
  1232. sbtmstatelow |= 0xa0000;
  1233. bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
  1234. udelay(1);
  1235. sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
  1236. sbtmstatelow &= ~0xa0000;
  1237. sbtmstatelow |= 0x80000;
  1238. bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
  1239. udelay(1);
  1240. if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G) {
  1241. old_core = bcm->current_core;
  1242. err = bcm43xx_switch_core(bcm, active_80211_core);
  1243. if (err)
  1244. goto out;
  1245. sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
  1246. sbtmstatelow &= ~0x20000000;
  1247. sbtmstatelow |= 0x20000000;
  1248. bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
  1249. err = bcm43xx_switch_core(bcm, old_core);
  1250. }
  1251. out:
  1252. return err;
  1253. }
  1254. static void handle_irq_transmit_status(struct bcm43xx_private *bcm)
  1255. {
  1256. u32 v0, v1;
  1257. u16 tmp;
  1258. struct bcm43xx_xmitstatus stat;
  1259. while (1) {
  1260. v0 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_0);
  1261. if (!v0)
  1262. break;
  1263. v1 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_1);
  1264. stat.cookie = (v0 >> 16) & 0x0000FFFF;
  1265. tmp = (u16)((v0 & 0xFFF0) | ((v0 & 0xF) >> 1));
  1266. stat.flags = tmp & 0xFF;
  1267. stat.cnt1 = (tmp & 0x0F00) >> 8;
  1268. stat.cnt2 = (tmp & 0xF000) >> 12;
  1269. stat.seq = (u16)(v1 & 0xFFFF);
  1270. stat.unknown = (u16)((v1 >> 16) & 0xFF);
  1271. bcm43xx_debugfs_log_txstat(bcm, &stat);
  1272. if (stat.flags & BCM43xx_TXSTAT_FLAG_IGNORE)
  1273. continue;
  1274. if (!(stat.flags & BCM43xx_TXSTAT_FLAG_ACK)) {
  1275. //TODO: packet was not acked (was lost)
  1276. }
  1277. //TODO: There are more (unknown) flags to test. see bcm43xx_main.h
  1278. if (bcm43xx_using_pio(bcm))
  1279. bcm43xx_pio_handle_xmitstatus(bcm, &stat);
  1280. else
  1281. bcm43xx_dma_handle_xmitstatus(bcm, &stat);
  1282. }
  1283. }
  1284. static void bcm43xx_generate_noise_sample(struct bcm43xx_private *bcm)
  1285. {
  1286. bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x408, 0x7F7F);
  1287. bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x40A, 0x7F7F);
  1288. bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
  1289. bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD) | (1 << 4));
  1290. assert(bcm->noisecalc.core_at_start == bcm->current_core);
  1291. assert(bcm->noisecalc.channel_at_start == bcm43xx_current_radio(bcm)->channel);
  1292. }
  1293. static void bcm43xx_calculate_link_quality(struct bcm43xx_private *bcm)
  1294. {
  1295. /* Top half of Link Quality calculation. */
  1296. if (bcm->noisecalc.calculation_running)
  1297. return;
  1298. bcm->noisecalc.core_at_start = bcm->current_core;
  1299. bcm->noisecalc.channel_at_start = bcm43xx_current_radio(bcm)->channel;
  1300. bcm->noisecalc.calculation_running = 1;
  1301. bcm->noisecalc.nr_samples = 0;
  1302. bcm43xx_generate_noise_sample(bcm);
  1303. }
  1304. static void handle_irq_noise(struct bcm43xx_private *bcm)
  1305. {
  1306. struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
  1307. u16 tmp;
  1308. u8 noise[4];
  1309. u8 i, j;
  1310. s32 average;
  1311. /* Bottom half of Link Quality calculation. */
  1312. assert(bcm->noisecalc.calculation_running);
  1313. if (bcm->noisecalc.core_at_start != bcm->current_core ||
  1314. bcm->noisecalc.channel_at_start != radio->channel)
  1315. goto drop_calculation;
  1316. tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x408);
  1317. noise[0] = (tmp & 0x00FF);
  1318. noise[1] = (tmp & 0xFF00) >> 8;
  1319. tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40A);
  1320. noise[2] = (tmp & 0x00FF);
  1321. noise[3] = (tmp & 0xFF00) >> 8;
  1322. if (noise[0] == 0x7F || noise[1] == 0x7F ||
  1323. noise[2] == 0x7F || noise[3] == 0x7F)
  1324. goto generate_new;
  1325. /* Get the noise samples. */
  1326. assert(bcm->noisecalc.nr_samples <= 8);
  1327. i = bcm->noisecalc.nr_samples;
  1328. noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
  1329. noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
  1330. noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
  1331. noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
  1332. bcm->noisecalc.samples[i][0] = radio->nrssi_lt[noise[0]];
  1333. bcm->noisecalc.samples[i][1] = radio->nrssi_lt[noise[1]];
  1334. bcm->noisecalc.samples[i][2] = radio->nrssi_lt[noise[2]];
  1335. bcm->noisecalc.samples[i][3] = radio->nrssi_lt[noise[3]];
  1336. bcm->noisecalc.nr_samples++;
  1337. if (bcm->noisecalc.nr_samples == 8) {
  1338. /* Calculate the Link Quality by the noise samples. */
  1339. average = 0;
  1340. for (i = 0; i < 8; i++) {
  1341. for (j = 0; j < 4; j++)
  1342. average += bcm->noisecalc.samples[i][j];
  1343. }
  1344. average /= (8 * 4);
  1345. average *= 125;
  1346. average += 64;
  1347. average /= 128;
  1348. tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40C);
  1349. tmp = (tmp / 128) & 0x1F;
  1350. if (tmp >= 8)
  1351. average += 2;
  1352. else
  1353. average -= 25;
  1354. if (tmp == 8)
  1355. average -= 72;
  1356. else
  1357. average -= 48;
  1358. /* FIXME: This is wrong, but people want fancy stats. well... */
  1359. bcm->stats.noise = average;
  1360. if (average > -65)
  1361. bcm->stats.link_quality = 0;
  1362. else if (average > -75)
  1363. bcm->stats.link_quality = 1;
  1364. else if (average > -85)
  1365. bcm->stats.link_quality = 2;
  1366. else
  1367. bcm->stats.link_quality = 3;
  1368. // dprintk(KERN_INFO PFX "Link Quality: %u (avg was %d)\n", bcm->stats.link_quality, average);
  1369. drop_calculation:
  1370. bcm->noisecalc.calculation_running = 0;
  1371. return;
  1372. }
  1373. generate_new:
  1374. bcm43xx_generate_noise_sample(bcm);
  1375. }
  1376. static void handle_irq_ps(struct bcm43xx_private *bcm)
  1377. {
  1378. if (bcm->ieee->iw_mode == IW_MODE_MASTER) {
  1379. ///TODO: PS TBTT
  1380. } else {
  1381. if (1/*FIXME: the last PSpoll frame was sent successfully */)
  1382. bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
  1383. }
  1384. if (bcm->ieee->iw_mode == IW_MODE_ADHOC)
  1385. bcm->reg124_set_0x4 = 1;
  1386. //FIXME else set to false?
  1387. }
  1388. static void handle_irq_reg124(struct bcm43xx_private *bcm)
  1389. {
  1390. if (!bcm->reg124_set_0x4)
  1391. return;
  1392. bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
  1393. bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD)
  1394. | 0x4);
  1395. //FIXME: reset reg124_set_0x4 to false?
  1396. }
  1397. static void handle_irq_pmq(struct bcm43xx_private *bcm)
  1398. {
  1399. u32 tmp;
  1400. //TODO: AP mode.
  1401. while (1) {
  1402. tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_PS_STATUS);
  1403. if (!(tmp & 0x00000008))
  1404. break;
  1405. }
  1406. /* 16bit write is odd, but correct. */
  1407. bcm43xx_write16(bcm, BCM43xx_MMIO_PS_STATUS, 0x0002);
  1408. }
  1409. static void bcm43xx_generate_beacon_template(struct bcm43xx_private *bcm,
  1410. u16 ram_offset, u16 shm_size_offset)
  1411. {
  1412. u32 value;
  1413. u16 size = 0;
  1414. /* Timestamp. */
  1415. //FIXME: assumption: The chip sets the timestamp
  1416. value = 0;
  1417. bcm43xx_ram_write(bcm, ram_offset++, value);
  1418. bcm43xx_ram_write(bcm, ram_offset++, value);
  1419. size += 8;
  1420. /* Beacon Interval / Capability Information */
  1421. value = 0x0000;//FIXME: Which interval?
  1422. value |= (1 << 0) << 16; /* ESS */
  1423. value |= (1 << 2) << 16; /* CF Pollable */ //FIXME?
  1424. value |= (1 << 3) << 16; /* CF Poll Request */ //FIXME?
  1425. if (!bcm->ieee->open_wep)
  1426. value |= (1 << 4) << 16; /* Privacy */
  1427. bcm43xx_ram_write(bcm, ram_offset++, value);
  1428. size += 4;
  1429. /* SSID */
  1430. //TODO
  1431. /* FH Parameter Set */
  1432. //TODO
  1433. /* DS Parameter Set */
  1434. //TODO
  1435. /* CF Parameter Set */
  1436. //TODO
  1437. /* TIM */
  1438. //TODO
  1439. bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, shm_size_offset, size);
  1440. }
  1441. static void handle_irq_beacon(struct bcm43xx_private *bcm)
  1442. {
  1443. u32 status;
  1444. bcm->irq_savedstate &= ~BCM43xx_IRQ_BEACON;
  1445. status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD);
  1446. if ((status & 0x1) && (status & 0x2)) {
  1447. /* ACK beacon IRQ. */
  1448. bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON,
  1449. BCM43xx_IRQ_BEACON);
  1450. bcm->irq_savedstate |= BCM43xx_IRQ_BEACON;
  1451. return;
  1452. }
  1453. if (!(status & 0x1)) {
  1454. bcm43xx_generate_beacon_template(bcm, 0x68, 0x18);
  1455. status |= 0x1;
  1456. bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
  1457. }
  1458. if (!(status & 0x2)) {
  1459. bcm43xx_generate_beacon_template(bcm, 0x468, 0x1A);
  1460. status |= 0x2;
  1461. bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
  1462. }
  1463. }
  1464. /* Interrupt handler bottom-half */
  1465. static void bcm43xx_interrupt_tasklet(struct bcm43xx_private *bcm)
  1466. {
  1467. u32 reason;
  1468. u32 dma_reason[4];
  1469. int activity = 0;
  1470. unsigned long flags;
  1471. #ifdef CONFIG_BCM43XX_DEBUG
  1472. u32 _handled = 0x00000000;
  1473. # define bcmirq_handled(irq) do { _handled |= (irq); } while (0)
  1474. #else
  1475. # define bcmirq_handled(irq) do { /* nothing */ } while (0)
  1476. #endif /* CONFIG_BCM43XX_DEBUG*/
  1477. bcm43xx_lock_mmio(bcm, flags);
  1478. reason = bcm->irq_reason;
  1479. dma_reason[0] = bcm->dma_reason[0];
  1480. dma_reason[1] = bcm->dma_reason[1];
  1481. dma_reason[2] = bcm->dma_reason[2];
  1482. dma_reason[3] = bcm->dma_reason[3];
  1483. if (unlikely(reason & BCM43xx_IRQ_XMIT_ERROR)) {
  1484. /* TX error. We get this when Template Ram is written in wrong endianess
  1485. * in dummy_tx(). We also get this if something is wrong with the TX header
  1486. * on DMA or PIO queues.
  1487. * Maybe we get this in other error conditions, too.
  1488. */
  1489. printkl(KERN_ERR PFX "FATAL ERROR: BCM43xx_IRQ_XMIT_ERROR\n");
  1490. bcmirq_handled(BCM43xx_IRQ_XMIT_ERROR);
  1491. }
  1492. if (unlikely((dma_reason[0] & BCM43xx_DMAIRQ_FATALMASK) |
  1493. (dma_reason[1] & BCM43xx_DMAIRQ_FATALMASK) |
  1494. (dma_reason[2] & BCM43xx_DMAIRQ_FATALMASK) |
  1495. (dma_reason[3] & BCM43xx_DMAIRQ_FATALMASK))) {
  1496. printkl(KERN_ERR PFX "FATAL ERROR: Fatal DMA error: "
  1497. "0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
  1498. dma_reason[0], dma_reason[1],
  1499. dma_reason[2], dma_reason[3]);
  1500. bcm43xx_controller_restart(bcm, "DMA error");
  1501. bcm43xx_unlock_mmio(bcm, flags);
  1502. return;
  1503. }
  1504. if (unlikely((dma_reason[0] & BCM43xx_DMAIRQ_NONFATALMASK) |
  1505. (dma_reason[1] & BCM43xx_DMAIRQ_NONFATALMASK) |
  1506. (dma_reason[2] & BCM43xx_DMAIRQ_NONFATALMASK) |
  1507. (dma_reason[3] & BCM43xx_DMAIRQ_NONFATALMASK))) {
  1508. printkl(KERN_ERR PFX "DMA error: "
  1509. "0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
  1510. dma_reason[0], dma_reason[1],
  1511. dma_reason[2], dma_reason[3]);
  1512. }
  1513. if (reason & BCM43xx_IRQ_PS) {
  1514. handle_irq_ps(bcm);
  1515. bcmirq_handled(BCM43xx_IRQ_PS);
  1516. }
  1517. if (reason & BCM43xx_IRQ_REG124) {
  1518. handle_irq_reg124(bcm);
  1519. bcmirq_handled(BCM43xx_IRQ_REG124);
  1520. }
  1521. if (reason & BCM43xx_IRQ_BEACON) {
  1522. if (bcm->ieee->iw_mode == IW_MODE_MASTER)
  1523. handle_irq_beacon(bcm);
  1524. bcmirq_handled(BCM43xx_IRQ_BEACON);
  1525. }
  1526. if (reason & BCM43xx_IRQ_PMQ) {
  1527. handle_irq_pmq(bcm);
  1528. bcmirq_handled(BCM43xx_IRQ_PMQ);
  1529. }
  1530. if (reason & BCM43xx_IRQ_SCAN) {
  1531. /*TODO*/
  1532. //bcmirq_handled(BCM43xx_IRQ_SCAN);
  1533. }
  1534. if (reason & BCM43xx_IRQ_NOISE) {
  1535. handle_irq_noise(bcm);
  1536. bcmirq_handled(BCM43xx_IRQ_NOISE);
  1537. }
  1538. /* Check the DMA reason registers for received data. */
  1539. assert(!(dma_reason[1] & BCM43xx_DMAIRQ_RX_DONE));
  1540. assert(!(dma_reason[2] & BCM43xx_DMAIRQ_RX_DONE));
  1541. if (dma_reason[0] & BCM43xx_DMAIRQ_RX_DONE) {
  1542. if (bcm43xx_using_pio(bcm))
  1543. bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue0);
  1544. else
  1545. bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring0);
  1546. /* We intentionally don't set "activity" to 1, here. */
  1547. }
  1548. if (dma_reason[3] & BCM43xx_DMAIRQ_RX_DONE) {
  1549. if (bcm43xx_using_pio(bcm))
  1550. bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue3);
  1551. else
  1552. bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring1);
  1553. activity = 1;
  1554. }
  1555. bcmirq_handled(BCM43xx_IRQ_RX);
  1556. if (reason & BCM43xx_IRQ_XMIT_STATUS) {
  1557. handle_irq_transmit_status(bcm);
  1558. activity = 1;
  1559. //TODO: In AP mode, this also causes sending of powersave responses.
  1560. bcmirq_handled(BCM43xx_IRQ_XMIT_STATUS);
  1561. }
  1562. /* IRQ_PIO_WORKAROUND is handled in the top-half. */
  1563. bcmirq_handled(BCM43xx_IRQ_PIO_WORKAROUND);
  1564. #ifdef CONFIG_BCM43XX_DEBUG
  1565. if (unlikely(reason & ~_handled)) {
  1566. printkl(KERN_WARNING PFX
  1567. "Unhandled IRQ! Reason: 0x%08x, Unhandled: 0x%08x, "
  1568. "DMA: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
  1569. reason, (reason & ~_handled),
  1570. dma_reason[0], dma_reason[1],
  1571. dma_reason[2], dma_reason[3]);
  1572. }
  1573. #endif
  1574. #undef bcmirq_handled
  1575. if (!modparam_noleds)
  1576. bcm43xx_leds_update(bcm, activity);
  1577. bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
  1578. bcm43xx_unlock_mmio(bcm, flags);
  1579. }
  1580. static void pio_irq_workaround(struct bcm43xx_private *bcm,
  1581. u16 base, int queueidx)
  1582. {
  1583. u16 rxctl;
  1584. rxctl = bcm43xx_read16(bcm, base + BCM43xx_PIO_RXCTL);
  1585. if (rxctl & BCM43xx_PIO_RXCTL_DATAAVAILABLE)
  1586. bcm->dma_reason[queueidx] |= BCM43xx_DMAIRQ_RX_DONE;
  1587. else
  1588. bcm->dma_reason[queueidx] &= ~BCM43xx_DMAIRQ_RX_DONE;
  1589. }
  1590. static void bcm43xx_interrupt_ack(struct bcm43xx_private *bcm, u32 reason)
  1591. {
  1592. if (bcm43xx_using_pio(bcm) &&
  1593. (bcm->current_core->rev < 3) &&
  1594. (!(reason & BCM43xx_IRQ_PIO_WORKAROUND))) {
  1595. /* Apply a PIO specific workaround to the dma_reasons */
  1596. pio_irq_workaround(bcm, BCM43xx_MMIO_PIO1_BASE, 0);
  1597. pio_irq_workaround(bcm, BCM43xx_MMIO_PIO2_BASE, 1);
  1598. pio_irq_workaround(bcm, BCM43xx_MMIO_PIO3_BASE, 2);
  1599. pio_irq_workaround(bcm, BCM43xx_MMIO_PIO4_BASE, 3);
  1600. }
  1601. bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, reason);
  1602. bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_REASON,
  1603. bcm->dma_reason[0]);
  1604. bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_REASON,
  1605. bcm->dma_reason[1]);
  1606. bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_REASON,
  1607. bcm->dma_reason[2]);
  1608. bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_REASON,
  1609. bcm->dma_reason[3]);
  1610. }
  1611. /* Interrupt handler top-half */
  1612. static irqreturn_t bcm43xx_interrupt_handler(int irq, void *dev_id, struct pt_regs *regs)
  1613. {
  1614. irqreturn_t ret = IRQ_HANDLED;
  1615. struct bcm43xx_private *bcm = dev_id;
  1616. u32 reason;
  1617. if (!bcm)
  1618. return IRQ_NONE;
  1619. spin_lock(&bcm->_lock);
  1620. reason = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
  1621. if (reason == 0xffffffff) {
  1622. /* irq not for us (shared irq) */
  1623. ret = IRQ_NONE;
  1624. goto out;
  1625. }
  1626. reason &= bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
  1627. if (!reason)
  1628. goto out;
  1629. bcm->dma_reason[0] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA1_REASON)
  1630. & 0x0001dc00;
  1631. bcm->dma_reason[1] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA2_REASON)
  1632. & 0x0000dc00;
  1633. bcm->dma_reason[2] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA3_REASON)
  1634. & 0x0000dc00;
  1635. bcm->dma_reason[3] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA4_REASON)
  1636. & 0x0001dc00;
  1637. bcm43xx_interrupt_ack(bcm, reason);
  1638. /* Only accept IRQs, if we are initialized properly.
  1639. * This avoids an RX race while initializing.
  1640. * We should probably not enable IRQs before we are initialized
  1641. * completely, but some careful work is needed to fix this. I think it
  1642. * is best to stay with this cheap workaround for now... .
  1643. */
  1644. if (likely(bcm->initialized)) {
  1645. /* disable all IRQs. They are enabled again in the bottom half. */
  1646. bcm->irq_savedstate = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
  1647. /* save the reason code and call our bottom half. */
  1648. bcm->irq_reason = reason;
  1649. tasklet_schedule(&bcm->isr_tasklet);
  1650. }
  1651. out:
  1652. mmiowb();
  1653. spin_unlock(&bcm->_lock);
  1654. return ret;
  1655. }
  1656. static void bcm43xx_release_firmware(struct bcm43xx_private *bcm, int force)
  1657. {
  1658. if (bcm->firmware_norelease && !force)
  1659. return; /* Suspending or controller reset. */
  1660. release_firmware(bcm->ucode);
  1661. bcm->ucode = NULL;
  1662. release_firmware(bcm->pcm);
  1663. bcm->pcm = NULL;
  1664. release_firmware(bcm->initvals0);
  1665. bcm->initvals0 = NULL;
  1666. release_firmware(bcm->initvals1);
  1667. bcm->initvals1 = NULL;
  1668. }
  1669. static int bcm43xx_request_firmware(struct bcm43xx_private *bcm)
  1670. {
  1671. struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
  1672. u8 rev = bcm->current_core->rev;
  1673. int err = 0;
  1674. int nr;
  1675. char buf[22 + sizeof(modparam_fwpostfix) - 1] = { 0 };
  1676. if (!bcm->ucode) {
  1677. snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_microcode%d%s.fw",
  1678. (rev >= 5 ? 5 : rev),
  1679. modparam_fwpostfix);
  1680. err = request_firmware(&bcm->ucode, buf, &bcm->pci_dev->dev);
  1681. if (err) {
  1682. printk(KERN_ERR PFX
  1683. "Error: Microcode \"%s\" not available or load failed.\n",
  1684. buf);
  1685. goto error;
  1686. }
  1687. }
  1688. if (!bcm->pcm) {
  1689. snprintf(buf, ARRAY_SIZE(buf),
  1690. "bcm43xx_pcm%d%s.fw",
  1691. (rev < 5 ? 4 : 5),
  1692. modparam_fwpostfix);
  1693. err = request_firmware(&bcm->pcm, buf, &bcm->pci_dev->dev);
  1694. if (err) {
  1695. printk(KERN_ERR PFX
  1696. "Error: PCM \"%s\" not available or load failed.\n",
  1697. buf);
  1698. goto error;
  1699. }
  1700. }
  1701. if (!bcm->initvals0) {
  1702. if (rev == 2 || rev == 4) {
  1703. switch (phy->type) {
  1704. case BCM43xx_PHYTYPE_A:
  1705. nr = 3;
  1706. break;
  1707. case BCM43xx_PHYTYPE_B:
  1708. case BCM43xx_PHYTYPE_G:
  1709. nr = 1;
  1710. break;
  1711. default:
  1712. goto err_noinitval;
  1713. }
  1714. } else if (rev >= 5) {
  1715. switch (phy->type) {
  1716. case BCM43xx_PHYTYPE_A:
  1717. nr = 7;
  1718. break;
  1719. case BCM43xx_PHYTYPE_B:
  1720. case BCM43xx_PHYTYPE_G:
  1721. nr = 5;
  1722. break;
  1723. default:
  1724. goto err_noinitval;
  1725. }
  1726. } else
  1727. goto err_noinitval;
  1728. snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
  1729. nr, modparam_fwpostfix);
  1730. err = request_firmware(&bcm->initvals0, buf, &bcm->pci_dev->dev);
  1731. if (err) {
  1732. printk(KERN_ERR PFX
  1733. "Error: InitVals \"%s\" not available or load failed.\n",
  1734. buf);
  1735. goto error;
  1736. }
  1737. if (bcm->initvals0->size % sizeof(struct bcm43xx_initval)) {
  1738. printk(KERN_ERR PFX "InitVals fileformat error.\n");
  1739. goto error;
  1740. }
  1741. }
  1742. if (!bcm->initvals1) {
  1743. if (rev >= 5) {
  1744. u32 sbtmstatehigh;
  1745. switch (phy->type) {
  1746. case BCM43xx_PHYTYPE_A:
  1747. sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
  1748. if (sbtmstatehigh & 0x00010000)
  1749. nr = 9;
  1750. else
  1751. nr = 10;
  1752. break;
  1753. case BCM43xx_PHYTYPE_B:
  1754. case BCM43xx_PHYTYPE_G:
  1755. nr = 6;
  1756. break;
  1757. default:
  1758. goto err_noinitval;
  1759. }
  1760. snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
  1761. nr, modparam_fwpostfix);
  1762. err = request_firmware(&bcm->initvals1, buf, &bcm->pci_dev->dev);
  1763. if (err) {
  1764. printk(KERN_ERR PFX
  1765. "Error: InitVals \"%s\" not available or load failed.\n",
  1766. buf);
  1767. goto error;
  1768. }
  1769. if (bcm->initvals1->size % sizeof(struct bcm43xx_initval)) {
  1770. printk(KERN_ERR PFX "InitVals fileformat error.\n");
  1771. goto error;
  1772. }
  1773. }
  1774. }
  1775. out:
  1776. return err;
  1777. error:
  1778. bcm43xx_release_firmware(bcm, 1);
  1779. goto out;
  1780. err_noinitval:
  1781. printk(KERN_ERR PFX "Error: No InitVals available!\n");
  1782. err = -ENOENT;
  1783. goto error;
  1784. }
  1785. static void bcm43xx_upload_microcode(struct bcm43xx_private *bcm)
  1786. {
  1787. const u32 *data;
  1788. unsigned int i, len;
  1789. /* Upload Microcode. */
  1790. data = (u32 *)(bcm->ucode->data);
  1791. len = bcm->ucode->size / sizeof(u32);
  1792. bcm43xx_shm_control_word(bcm, BCM43xx_SHM_UCODE, 0x0000);
  1793. for (i = 0; i < len; i++) {
  1794. bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
  1795. be32_to_cpu(data[i]));
  1796. udelay(10);
  1797. }
  1798. /* Upload PCM data. */
  1799. data = (u32 *)(bcm->pcm->data);
  1800. len = bcm->pcm->size / sizeof(u32);
  1801. bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01ea);
  1802. bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, 0x00004000);
  1803. bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01eb);
  1804. for (i = 0; i < len; i++) {
  1805. bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
  1806. be32_to_cpu(data[i]));
  1807. udelay(10);
  1808. }
  1809. }
  1810. static int bcm43xx_write_initvals(struct bcm43xx_private *bcm,
  1811. const struct bcm43xx_initval *data,
  1812. const unsigned int len)
  1813. {
  1814. u16 offset, size;
  1815. u32 value;
  1816. unsigned int i;
  1817. for (i = 0; i < len; i++) {
  1818. offset = be16_to_cpu(data[i].offset);
  1819. size = be16_to_cpu(data[i].size);
  1820. value = be32_to_cpu(data[i].value);
  1821. if (unlikely(offset >= 0x1000))
  1822. goto err_format;
  1823. if (size == 2) {
  1824. if (unlikely(value & 0xFFFF0000))
  1825. goto err_format;
  1826. bcm43xx_write16(bcm, offset, (u16)value);
  1827. } else if (size == 4) {
  1828. bcm43xx_write32(bcm, offset, value);
  1829. } else
  1830. goto err_format;
  1831. }
  1832. return 0;
  1833. err_format:
  1834. printk(KERN_ERR PFX "InitVals (bcm43xx_initvalXX.fw) file-format error. "
  1835. "Please fix your bcm43xx firmware files.\n");
  1836. return -EPROTO;
  1837. }
  1838. static int bcm43xx_upload_initvals(struct bcm43xx_private *bcm)
  1839. {
  1840. int err;
  1841. err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)bcm->initvals0->data,
  1842. bcm->initvals0->size / sizeof(struct bcm43xx_initval));
  1843. if (err)
  1844. goto out;
  1845. if (bcm->initvals1) {
  1846. err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)bcm->initvals1->data,
  1847. bcm->initvals1->size / sizeof(struct bcm43xx_initval));
  1848. if (err)
  1849. goto out;
  1850. }
  1851. out:
  1852. return err;
  1853. }
  1854. static int bcm43xx_initialize_irq(struct bcm43xx_private *bcm)
  1855. {
  1856. int res;
  1857. unsigned int i;
  1858. u32 data;
  1859. bcm->irq = bcm->pci_dev->irq;
  1860. #ifdef CONFIG_BCM947XX
  1861. if (bcm->pci_dev->bus->number == 0) {
  1862. struct pci_dev *d = NULL;
  1863. /* FIXME: we will probably need more device IDs here... */
  1864. d = pci_find_device(PCI_VENDOR_ID_BROADCOM, 0x4324, NULL);
  1865. if (d != NULL) {
  1866. bcm->irq = d->irq;
  1867. }
  1868. }
  1869. #endif
  1870. res = request_irq(bcm->irq, bcm43xx_interrupt_handler,
  1871. SA_SHIRQ, KBUILD_MODNAME, bcm);
  1872. if (res) {
  1873. printk(KERN_ERR PFX "Cannot register IRQ%d\n", bcm->irq);
  1874. return -ENODEV;
  1875. }
  1876. bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0xffffffff);
  1877. bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, 0x00020402);
  1878. i = 0;
  1879. while (1) {
  1880. data = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
  1881. if (data == BCM43xx_IRQ_READY)
  1882. break;
  1883. i++;
  1884. if (i >= BCM43xx_IRQWAIT_MAX_RETRIES) {
  1885. printk(KERN_ERR PFX "Card IRQ register not responding. "
  1886. "Giving up.\n");
  1887. free_irq(bcm->irq, bcm);
  1888. return -ENODEV;
  1889. }
  1890. udelay(10);
  1891. }
  1892. // dummy read
  1893. bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
  1894. return 0;
  1895. }
  1896. /* Switch to the core used to write the GPIO register.
  1897. * This is either the ChipCommon, or the PCI core.
  1898. */
  1899. static int switch_to_gpio_core(struct bcm43xx_private *bcm)
  1900. {
  1901. int err;
  1902. /* Where to find the GPIO register depends on the chipset.
  1903. * If it has a ChipCommon, its register at offset 0x6c is the GPIO
  1904. * control register. Otherwise the register at offset 0x6c in the
  1905. * PCI core is the GPIO control register.
  1906. */
  1907. err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
  1908. if (err == -ENODEV) {
  1909. err = bcm43xx_switch_core(bcm, &bcm->core_pci);
  1910. if (unlikely(err == -ENODEV)) {
  1911. printk(KERN_ERR PFX "gpio error: "
  1912. "Neither ChipCommon nor PCI core available!\n");
  1913. }
  1914. }
  1915. return err;
  1916. }
  1917. /* Initialize the GPIOs
  1918. * http://bcm-specs.sipsolutions.net/GPIO
  1919. */
  1920. static int bcm43xx_gpio_init(struct bcm43xx_private *bcm)
  1921. {
  1922. struct bcm43xx_coreinfo *old_core;
  1923. int err;
  1924. u32 mask, set;
  1925. bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
  1926. bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
  1927. & 0xFFFF3FFF);
  1928. bcm43xx_leds_switch_all(bcm, 0);
  1929. bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
  1930. bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK) | 0x000F);
  1931. mask = 0x0000001F;
  1932. set = 0x0000000F;
  1933. if (bcm->chip_id == 0x4301) {
  1934. mask |= 0x0060;
  1935. set |= 0x0060;
  1936. }
  1937. if (0 /* FIXME: conditional unknown */) {
  1938. bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
  1939. bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
  1940. | 0x0100);
  1941. mask |= 0x0180;
  1942. set |= 0x0180;
  1943. }
  1944. if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL) {
  1945. bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
  1946. bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
  1947. | 0x0200);
  1948. mask |= 0x0200;
  1949. set |= 0x0200;
  1950. }
  1951. if (bcm->current_core->rev >= 2)
  1952. mask |= 0x0010; /* FIXME: This is redundant. */
  1953. old_core = bcm->current_core;
  1954. err = switch_to_gpio_core(bcm);
  1955. if (err)
  1956. goto out;
  1957. bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL,
  1958. (bcm43xx_read32(bcm, BCM43xx_GPIO_CONTROL) & mask) | set);
  1959. err = bcm43xx_switch_core(bcm, old_core);
  1960. out:
  1961. return err;
  1962. }
  1963. /* Turn off all GPIO stuff. Call this on module unload, for example. */
  1964. static int bcm43xx_gpio_cleanup(struct bcm43xx_private *bcm)
  1965. {
  1966. struct bcm43xx_coreinfo *old_core;
  1967. int err;
  1968. old_core = bcm->current_core;
  1969. err = switch_to_gpio_core(bcm);
  1970. if (err)
  1971. return err;
  1972. bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL, 0x00000000);
  1973. err = bcm43xx_switch_core(bcm, old_core);
  1974. assert(err == 0);
  1975. return 0;
  1976. }
  1977. /* http://bcm-specs.sipsolutions.net/EnableMac */
  1978. void bcm43xx_mac_enable(struct bcm43xx_private *bcm)
  1979. {
  1980. bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
  1981. bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
  1982. | BCM43xx_SBF_MAC_ENABLED);
  1983. bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, BCM43xx_IRQ_READY);
  1984. bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
  1985. bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
  1986. bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
  1987. }
  1988. /* http://bcm-specs.sipsolutions.net/SuspendMAC */
  1989. void bcm43xx_mac_suspend(struct bcm43xx_private *bcm)
  1990. {
  1991. int i;
  1992. u32 tmp;
  1993. bcm43xx_power_saving_ctl_bits(bcm, -1, 1);
  1994. bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
  1995. bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
  1996. & ~BCM43xx_SBF_MAC_ENABLED);
  1997. bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
  1998. for (i = 100000; i; i--) {
  1999. tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
  2000. if (tmp & BCM43xx_IRQ_READY)
  2001. return;
  2002. udelay(10);
  2003. }
  2004. printkl(KERN_ERR PFX "MAC suspend failed\n");
  2005. }
  2006. void bcm43xx_set_iwmode(struct bcm43xx_private *bcm,
  2007. int iw_mode)
  2008. {
  2009. unsigned long flags;
  2010. struct net_device *net_dev = bcm->net_dev;
  2011. u32 status;
  2012. u16 value;
  2013. spin_lock_irqsave(&bcm->ieee->lock, flags);
  2014. bcm->ieee->iw_mode = iw_mode;
  2015. spin_unlock_irqrestore(&bcm->ieee->lock, flags);
  2016. if (iw_mode == IW_MODE_MONITOR)
  2017. net_dev->type = ARPHRD_IEEE80211;
  2018. else
  2019. net_dev->type = ARPHRD_ETHER;
  2020. status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
  2021. /* Reset status to infrastructured mode */
  2022. status &= ~(BCM43xx_SBF_MODE_AP | BCM43xx_SBF_MODE_MONITOR);
  2023. status &= ~BCM43xx_SBF_MODE_PROMISC;
  2024. status |= BCM43xx_SBF_MODE_NOTADHOC;
  2025. /* FIXME: Always enable promisc mode, until we get the MAC filters working correctly. */
  2026. status |= BCM43xx_SBF_MODE_PROMISC;
  2027. switch (iw_mode) {
  2028. case IW_MODE_MONITOR:
  2029. status |= BCM43xx_SBF_MODE_MONITOR;
  2030. status |= BCM43xx_SBF_MODE_PROMISC;
  2031. break;
  2032. case IW_MODE_ADHOC:
  2033. status &= ~BCM43xx_SBF_MODE_NOTADHOC;
  2034. break;
  2035. case IW_MODE_MASTER:
  2036. status |= BCM43xx_SBF_MODE_AP;
  2037. break;
  2038. case IW_MODE_SECOND:
  2039. case IW_MODE_REPEAT:
  2040. TODO(); /* TODO */
  2041. break;
  2042. case IW_MODE_INFRA:
  2043. /* nothing to be done here... */
  2044. break;
  2045. default:
  2046. dprintk(KERN_ERR PFX "Unknown mode in set_iwmode: %d\n", iw_mode);
  2047. }
  2048. if (net_dev->flags & IFF_PROMISC)
  2049. status |= BCM43xx_SBF_MODE_PROMISC;
  2050. bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
  2051. value = 0x0002;
  2052. if (iw_mode != IW_MODE_ADHOC && iw_mode != IW_MODE_MASTER) {
  2053. if (bcm->chip_id == 0x4306 && bcm->chip_rev == 3)
  2054. value = 0x0064;
  2055. else
  2056. value = 0x0032;
  2057. }
  2058. bcm43xx_write16(bcm, 0x0612, value);
  2059. }
  2060. /* This is the opposite of bcm43xx_chip_init() */
  2061. static void bcm43xx_chip_cleanup(struct bcm43xx_private *bcm)
  2062. {
  2063. bcm43xx_radio_turn_off(bcm);
  2064. if (!modparam_noleds)
  2065. bcm43xx_leds_exit(bcm);
  2066. bcm43xx_gpio_cleanup(bcm);
  2067. free_irq(bcm->irq, bcm);
  2068. bcm43xx_release_firmware(bcm, 0);
  2069. }
  2070. /* Initialize the chip
  2071. * http://bcm-specs.sipsolutions.net/ChipInit
  2072. */
  2073. static int bcm43xx_chip_init(struct bcm43xx_private *bcm)
  2074. {
  2075. struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
  2076. struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
  2077. int err;
  2078. int tmp;
  2079. u32 value32;
  2080. u16 value16;
  2081. bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
  2082. BCM43xx_SBF_CORE_READY
  2083. | BCM43xx_SBF_400);
  2084. err = bcm43xx_request_firmware(bcm);
  2085. if (err)
  2086. goto out;
  2087. bcm43xx_upload_microcode(bcm);
  2088. err = bcm43xx_initialize_irq(bcm);
  2089. if (err)
  2090. goto err_release_fw;
  2091. err = bcm43xx_gpio_init(bcm);
  2092. if (err)
  2093. goto err_free_irq;
  2094. err = bcm43xx_upload_initvals(bcm);
  2095. if (err)
  2096. goto err_gpio_cleanup;
  2097. bcm43xx_radio_turn_on(bcm);
  2098. bcm43xx_write16(bcm, 0x03E6, 0x0000);
  2099. err = bcm43xx_phy_init(bcm);
  2100. if (err)
  2101. goto err_radio_off;
  2102. /* Select initial Interference Mitigation. */
  2103. tmp = radio->interfmode;
  2104. radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
  2105. bcm43xx_radio_set_interference_mitigation(bcm, tmp);
  2106. bcm43xx_phy_set_antenna_diversity(bcm);
  2107. bcm43xx_radio_set_txantenna(bcm, BCM43xx_RADIO_TXANTENNA_DEFAULT);
  2108. if (phy->type == BCM43xx_PHYTYPE_B) {
  2109. value16 = bcm43xx_read16(bcm, 0x005E);
  2110. value16 |= 0x0004;
  2111. bcm43xx_write16(bcm, 0x005E, value16);
  2112. }
  2113. bcm43xx_write32(bcm, 0x0100, 0x01000000);
  2114. if (bcm->current_core->rev < 5)
  2115. bcm43xx_write32(bcm, 0x010C, 0x01000000);
  2116. value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
  2117. value32 &= ~ BCM43xx_SBF_MODE_NOTADHOC;
  2118. bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
  2119. value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
  2120. value32 |= BCM43xx_SBF_MODE_NOTADHOC;
  2121. bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
  2122. value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
  2123. value32 |= 0x100000;
  2124. bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
  2125. if (bcm43xx_using_pio(bcm)) {
  2126. bcm43xx_write32(bcm, 0x0210, 0x00000100);
  2127. bcm43xx_write32(bcm, 0x0230, 0x00000100);
  2128. bcm43xx_write32(bcm, 0x0250, 0x00000100);
  2129. bcm43xx_write32(bcm, 0x0270, 0x00000100);
  2130. bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0034, 0x0000);
  2131. }
  2132. /* Probe Response Timeout value */
  2133. /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
  2134. bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0074, 0x0000);
  2135. /* Initially set the wireless operation mode. */
  2136. bcm43xx_set_iwmode(bcm, bcm->ieee->iw_mode);
  2137. if (bcm->current_core->rev < 3) {
  2138. bcm43xx_write16(bcm, 0x060E, 0x0000);
  2139. bcm43xx_write16(bcm, 0x0610, 0x8000);
  2140. bcm43xx_write16(bcm, 0x0604, 0x0000);
  2141. bcm43xx_write16(bcm, 0x0606, 0x0200);
  2142. } else {
  2143. bcm43xx_write32(bcm, 0x0188, 0x80000000);
  2144. bcm43xx_write32(bcm, 0x018C, 0x02000000);
  2145. }
  2146. bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0x00004000);
  2147. bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_IRQ_MASK, 0x0001DC00);
  2148. bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
  2149. bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_IRQ_MASK, 0x0000DC00);
  2150. bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_IRQ_MASK, 0x0001DC00);
  2151. value32 = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
  2152. value32 |= 0x00100000;
  2153. bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, value32);
  2154. bcm43xx_write16(bcm, BCM43xx_MMIO_POWERUP_DELAY, bcm43xx_pctl_powerup_delay(bcm));
  2155. assert(err == 0);
  2156. dprintk(KERN_INFO PFX "Chip initialized\n");
  2157. out:
  2158. return err;
  2159. err_radio_off:
  2160. bcm43xx_radio_turn_off(bcm);
  2161. err_gpio_cleanup:
  2162. bcm43xx_gpio_cleanup(bcm);
  2163. err_free_irq:
  2164. free_irq(bcm->irq, bcm);
  2165. err_release_fw:
  2166. bcm43xx_release_firmware(bcm, 1);
  2167. goto out;
  2168. }
  2169. /* Validate chip access
  2170. * http://bcm-specs.sipsolutions.net/ValidateChipAccess */
  2171. static int bcm43xx_validate_chip(struct bcm43xx_private *bcm)
  2172. {
  2173. u32 value;
  2174. u32 shm_backup;
  2175. shm_backup = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000);
  2176. bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0xAA5555AA);
  2177. if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0xAA5555AA)
  2178. goto error;
  2179. bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0x55AAAA55);
  2180. if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0x55AAAA55)
  2181. goto error;
  2182. bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, shm_backup);
  2183. value = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
  2184. if ((value | 0x80000000) != 0x80000400)
  2185. goto error;
  2186. value = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
  2187. if (value != 0x00000000)
  2188. goto error;
  2189. return 0;
  2190. error:
  2191. printk(KERN_ERR PFX "Failed to validate the chipaccess\n");
  2192. return -ENODEV;
  2193. }
  2194. static void bcm43xx_init_struct_phyinfo(struct bcm43xx_phyinfo *phy)
  2195. {
  2196. /* Initialize a "phyinfo" structure. The structure is already
  2197. * zeroed out.
  2198. */
  2199. phy->antenna_diversity = 0xFFFF;
  2200. phy->savedpctlreg = 0xFFFF;
  2201. phy->minlowsig[0] = 0xFFFF;
  2202. phy->minlowsig[1] = 0xFFFF;
  2203. spin_lock_init(&phy->lock);
  2204. }
  2205. static void bcm43xx_init_struct_radioinfo(struct bcm43xx_radioinfo *radio)
  2206. {
  2207. /* Initialize a "radioinfo" structure. The structure is already
  2208. * zeroed out.
  2209. */
  2210. radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
  2211. radio->channel = 0xFF;
  2212. radio->initial_channel = 0xFF;
  2213. radio->lofcal = 0xFFFF;
  2214. radio->initval = 0xFFFF;
  2215. radio->nrssi[0] = -1000;
  2216. radio->nrssi[1] = -1000;
  2217. }
  2218. static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
  2219. {
  2220. int err, i;
  2221. int current_core;
  2222. u32 core_vendor, core_id, core_rev;
  2223. u32 sb_id_hi, chip_id_32 = 0;
  2224. u16 pci_device, chip_id_16;
  2225. u8 core_count;
  2226. memset(&bcm->core_chipcommon, 0, sizeof(struct bcm43xx_coreinfo));
  2227. memset(&bcm->core_pci, 0, sizeof(struct bcm43xx_coreinfo));
  2228. memset(&bcm->core_80211, 0, sizeof(struct bcm43xx_coreinfo)
  2229. * BCM43xx_MAX_80211_CORES);
  2230. memset(&bcm->core_80211_ext, 0, sizeof(struct bcm43xx_coreinfo_80211)
  2231. * BCM43xx_MAX_80211_CORES);
  2232. bcm->current_80211_core_idx = -1;
  2233. bcm->nr_80211_available = 0;
  2234. bcm->current_core = NULL;
  2235. bcm->active_80211_core = NULL;
  2236. /* map core 0 */
  2237. err = _switch_core(bcm, 0);
  2238. if (err)
  2239. goto out;
  2240. /* fetch sb_id_hi from core information registers */
  2241. sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
  2242. core_id = (sb_id_hi & 0xFFF0) >> 4;
  2243. core_rev = (sb_id_hi & 0xF);
  2244. core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
  2245. /* if present, chipcommon is always core 0; read the chipid from it */
  2246. if (core_id == BCM43xx_COREID_CHIPCOMMON) {
  2247. chip_id_32 = bcm43xx_read32(bcm, 0);
  2248. chip_id_16 = chip_id_32 & 0xFFFF;
  2249. bcm->core_chipcommon.available = 1;
  2250. bcm->core_chipcommon.id = core_id;
  2251. bcm->core_chipcommon.rev = core_rev;
  2252. bcm->core_chipcommon.index = 0;
  2253. /* While we are at it, also read the capabilities. */
  2254. bcm->chipcommon_capabilities = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_CAPABILITIES);
  2255. } else {
  2256. /* without a chipCommon, use a hard coded table. */
  2257. pci_device = bcm->pci_dev->device;
  2258. if (pci_device == 0x4301)
  2259. chip_id_16 = 0x4301;
  2260. else if ((pci_device >= 0x4305) && (pci_device <= 0x4307))
  2261. chip_id_16 = 0x4307;
  2262. else if ((pci_device >= 0x4402) && (pci_device <= 0x4403))
  2263. chip_id_16 = 0x4402;
  2264. else if ((pci_device >= 0x4610) && (pci_device <= 0x4615))
  2265. chip_id_16 = 0x4610;
  2266. else if ((pci_device >= 0x4710) && (pci_device <= 0x4715))
  2267. chip_id_16 = 0x4710;
  2268. #ifdef CONFIG_BCM947XX
  2269. else if ((pci_device >= 0x4320) && (pci_device <= 0x4325))
  2270. chip_id_16 = 0x4309;
  2271. #endif
  2272. else {
  2273. printk(KERN_ERR PFX "Could not determine Chip ID\n");
  2274. return -ENODEV;
  2275. }
  2276. }
  2277. /* ChipCommon with Core Rev >=4 encodes number of cores,
  2278. * otherwise consult hardcoded table */
  2279. if ((core_id == BCM43xx_COREID_CHIPCOMMON) && (core_rev >= 4)) {
  2280. core_count = (chip_id_32 & 0x0F000000) >> 24;
  2281. } else {
  2282. switch (chip_id_16) {
  2283. case 0x4610:
  2284. case 0x4704:
  2285. case 0x4710:
  2286. core_count = 9;
  2287. break;
  2288. case 0x4310:
  2289. core_count = 8;
  2290. break;
  2291. case 0x5365:
  2292. core_count = 7;
  2293. break;
  2294. case 0x4306:
  2295. core_count = 6;
  2296. break;
  2297. case 0x4301:
  2298. case 0x4307:
  2299. core_count = 5;
  2300. break;
  2301. case 0x4402:
  2302. core_count = 3;
  2303. break;
  2304. default:
  2305. /* SOL if we get here */
  2306. assert(0);
  2307. core_count = 1;
  2308. }
  2309. }
  2310. bcm->chip_id = chip_id_16;
  2311. bcm->chip_rev = (chip_id_32 & 0x000F0000) >> 16;
  2312. bcm->chip_package = (chip_id_32 & 0x00F00000) >> 20;
  2313. dprintk(KERN_INFO PFX "Chip ID 0x%x, rev 0x%x\n",
  2314. bcm->chip_id, bcm->chip_rev);
  2315. dprintk(KERN_INFO PFX "Number of cores: %d\n", core_count);
  2316. if (bcm->core_chipcommon.available) {
  2317. dprintk(KERN_INFO PFX "Core 0: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
  2318. core_id, core_rev, core_vendor,
  2319. bcm43xx_core_enabled(bcm) ? "enabled" : "disabled");
  2320. }
  2321. if (bcm->core_chipcommon.available)
  2322. current_core = 1;
  2323. else
  2324. current_core = 0;
  2325. for ( ; current_core < core_count; current_core++) {
  2326. struct bcm43xx_coreinfo *core;
  2327. struct bcm43xx_coreinfo_80211 *ext_80211;
  2328. err = _switch_core(bcm, current_core);
  2329. if (err)
  2330. goto out;
  2331. /* Gather information */
  2332. /* fetch sb_id_hi from core information registers */
  2333. sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
  2334. /* extract core_id, core_rev, core_vendor */
  2335. core_id = (sb_id_hi & 0xFFF0) >> 4;
  2336. core_rev = (sb_id_hi & 0xF);
  2337. core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
  2338. dprintk(KERN_INFO PFX "Core %d: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
  2339. current_core, core_id, core_rev, core_vendor,
  2340. bcm43xx_core_enabled(bcm) ? "enabled" : "disabled" );
  2341. core = NULL;
  2342. switch (core_id) {
  2343. case BCM43xx_COREID_PCI:
  2344. core = &bcm->core_pci;
  2345. if (core->available) {
  2346. printk(KERN_WARNING PFX "Multiple PCI cores found.\n");
  2347. continue;
  2348. }
  2349. break;
  2350. case BCM43xx_COREID_80211:
  2351. for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
  2352. core = &(bcm->core_80211[i]);
  2353. ext_80211 = &(bcm->core_80211_ext[i]);
  2354. if (!core->available)
  2355. break;
  2356. core = NULL;
  2357. }
  2358. if (!core) {
  2359. printk(KERN_WARNING PFX "More than %d cores of type 802.11 found.\n",
  2360. BCM43xx_MAX_80211_CORES);
  2361. continue;
  2362. }
  2363. if (i != 0) {
  2364. /* More than one 80211 core is only supported
  2365. * by special chips.
  2366. * There are chips with two 80211 cores, but with
  2367. * dangling pins on the second core. Be careful
  2368. * and ignore these cores here.
  2369. */
  2370. if (bcm->pci_dev->device != 0x4324) {
  2371. dprintk(KERN_INFO PFX "Ignoring additional 802.11 core.\n");
  2372. continue;
  2373. }
  2374. }
  2375. switch (core_rev) {
  2376. case 2:
  2377. case 4:
  2378. case 5:
  2379. case 6:
  2380. case 7:
  2381. case 9:
  2382. break;
  2383. default:
  2384. printk(KERN_ERR PFX "Error: Unsupported 80211 core revision %u\n",
  2385. core_rev);
  2386. err = -ENODEV;
  2387. goto out;
  2388. }
  2389. bcm->nr_80211_available++;
  2390. bcm43xx_init_struct_phyinfo(&ext_80211->phy);
  2391. bcm43xx_init_struct_radioinfo(&ext_80211->radio);
  2392. break;
  2393. case BCM43xx_COREID_CHIPCOMMON:
  2394. printk(KERN_WARNING PFX "Multiple CHIPCOMMON cores found.\n");
  2395. break;
  2396. }
  2397. if (core) {
  2398. core->available = 1;
  2399. core->id = core_id;
  2400. core->rev = core_rev;
  2401. core->index = current_core;
  2402. }
  2403. }
  2404. if (!bcm->core_80211[0].available) {
  2405. printk(KERN_ERR PFX "Error: No 80211 core found!\n");
  2406. err = -ENODEV;
  2407. goto out;
  2408. }
  2409. err = bcm43xx_switch_core(bcm, &bcm->core_80211[0]);
  2410. assert(err == 0);
  2411. out:
  2412. return err;
  2413. }
  2414. static void bcm43xx_gen_bssid(struct bcm43xx_private *bcm)
  2415. {
  2416. const u8 *mac = (const u8*)(bcm->net_dev->dev_addr);
  2417. u8 *bssid = bcm->ieee->bssid;
  2418. switch (bcm->ieee->iw_mode) {
  2419. case IW_MODE_ADHOC:
  2420. random_ether_addr(bssid);
  2421. break;
  2422. case IW_MODE_MASTER:
  2423. case IW_MODE_INFRA:
  2424. case IW_MODE_REPEAT:
  2425. case IW_MODE_SECOND:
  2426. case IW_MODE_MONITOR:
  2427. memcpy(bssid, mac, ETH_ALEN);
  2428. break;
  2429. default:
  2430. assert(0);
  2431. }
  2432. }
  2433. static void bcm43xx_rate_memory_write(struct bcm43xx_private *bcm,
  2434. u16 rate,
  2435. int is_ofdm)
  2436. {
  2437. u16 offset;
  2438. if (is_ofdm) {
  2439. offset = 0x480;
  2440. offset += (bcm43xx_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
  2441. }
  2442. else {
  2443. offset = 0x4C0;
  2444. offset += (bcm43xx_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
  2445. }
  2446. bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, offset + 0x20,
  2447. bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, offset));
  2448. }
  2449. static void bcm43xx_rate_memory_init(struct bcm43xx_private *bcm)
  2450. {
  2451. switch (bcm43xx_current_phy(bcm)->type) {
  2452. case BCM43xx_PHYTYPE_A:
  2453. case BCM43xx_PHYTYPE_G:
  2454. bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_6MB, 1);
  2455. bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_12MB, 1);
  2456. bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_18MB, 1);
  2457. bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_24MB, 1);
  2458. bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_36MB, 1);
  2459. bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_48MB, 1);
  2460. bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_54MB, 1);
  2461. case BCM43xx_PHYTYPE_B:
  2462. bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_1MB, 0);
  2463. bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_2MB, 0);
  2464. bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_5MB, 0);
  2465. bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_11MB, 0);
  2466. break;
  2467. default:
  2468. assert(0);
  2469. }
  2470. }
  2471. static void bcm43xx_wireless_core_cleanup(struct bcm43xx_private *bcm)
  2472. {
  2473. bcm43xx_chip_cleanup(bcm);
  2474. bcm43xx_pio_free(bcm);
  2475. bcm43xx_dma_free(bcm);
  2476. bcm->current_core->initialized = 0;
  2477. }
  2478. /* http://bcm-specs.sipsolutions.net/80211Init */
  2479. static int bcm43xx_wireless_core_init(struct bcm43xx_private *bcm)
  2480. {
  2481. struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
  2482. struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
  2483. u32 ucodeflags;
  2484. int err;
  2485. u32 sbimconfiglow;
  2486. u8 limit;
  2487. if (bcm->chip_rev < 5) {
  2488. sbimconfiglow = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
  2489. sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
  2490. sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
  2491. if (bcm->bustype == BCM43xx_BUSTYPE_PCI)
  2492. sbimconfiglow |= 0x32;
  2493. else if (bcm->bustype == BCM43xx_BUSTYPE_SB)
  2494. sbimconfiglow |= 0x53;
  2495. else
  2496. assert(0);
  2497. bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, sbimconfiglow);
  2498. }
  2499. bcm43xx_phy_calibrate(bcm);
  2500. err = bcm43xx_chip_init(bcm);
  2501. if (err)
  2502. goto out;
  2503. bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0016, bcm->current_core->rev);
  2504. ucodeflags = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, BCM43xx_UCODEFLAGS_OFFSET);
  2505. if (0 /*FIXME: which condition has to be used here? */)
  2506. ucodeflags |= 0x00000010;
  2507. /* HW decryption needs to be set now */
  2508. ucodeflags |= 0x40000000;
  2509. if (phy->type == BCM43xx_PHYTYPE_G) {
  2510. ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
  2511. if (phy->rev == 1)
  2512. ucodeflags |= BCM43xx_UCODEFLAG_UNKGPHY;
  2513. if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL)
  2514. ucodeflags |= BCM43xx_UCODEFLAG_UNKPACTRL;
  2515. } else if (phy->type == BCM43xx_PHYTYPE_B) {
  2516. ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
  2517. if (phy->rev >= 2 && radio->version == 0x2050)
  2518. ucodeflags &= ~BCM43xx_UCODEFLAG_UNKGPHY;
  2519. }
  2520. if (ucodeflags != bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
  2521. BCM43xx_UCODEFLAGS_OFFSET)) {
  2522. bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
  2523. BCM43xx_UCODEFLAGS_OFFSET, ucodeflags);
  2524. }
  2525. /* Short/Long Retry Limit.
  2526. * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
  2527. * the chip-internal counter.
  2528. */
  2529. limit = limit_value(modparam_short_retry, 0, 0xF);
  2530. bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0006, limit);
  2531. limit = limit_value(modparam_long_retry, 0, 0xF);
  2532. bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0007, limit);
  2533. bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0044, 3);
  2534. bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0046, 2);
  2535. bcm43xx_rate_memory_init(bcm);
  2536. /* Minimum Contention Window */
  2537. if (phy->type == BCM43xx_PHYTYPE_B)
  2538. bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000001f);
  2539. else
  2540. bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000000f);
  2541. /* Maximum Contention Window */
  2542. bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
  2543. bcm43xx_gen_bssid(bcm);
  2544. bcm43xx_write_mac_bssid_templates(bcm);
  2545. if (bcm->current_core->rev >= 5)
  2546. bcm43xx_write16(bcm, 0x043C, 0x000C);
  2547. if (bcm43xx_using_pio(bcm))
  2548. err = bcm43xx_pio_init(bcm);
  2549. else
  2550. err = bcm43xx_dma_init(bcm);
  2551. if (err)
  2552. goto err_chip_cleanup;
  2553. bcm43xx_write16(bcm, 0x0612, 0x0050);
  2554. bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0416, 0x0050);
  2555. bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0414, 0x01F4);
  2556. bcm43xx_mac_enable(bcm);
  2557. bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
  2558. bcm->current_core->initialized = 1;
  2559. out:
  2560. return err;
  2561. err_chip_cleanup:
  2562. bcm43xx_chip_cleanup(bcm);
  2563. goto out;
  2564. }
  2565. static int bcm43xx_chipset_attach(struct bcm43xx_private *bcm)
  2566. {
  2567. int err;
  2568. u16 pci_status;
  2569. err = bcm43xx_pctl_set_crystal(bcm, 1);
  2570. if (err)
  2571. goto out;
  2572. bcm43xx_pci_read_config16(bcm, PCI_STATUS, &pci_status);
  2573. bcm43xx_pci_write_config16(bcm, PCI_STATUS, pci_status & ~PCI_STATUS_SIG_TARGET_ABORT);
  2574. out:
  2575. return err;
  2576. }
  2577. static void bcm43xx_chipset_detach(struct bcm43xx_private *bcm)
  2578. {
  2579. bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_SLOW);
  2580. bcm43xx_pctl_set_crystal(bcm, 0);
  2581. }
  2582. static void bcm43xx_pcicore_broadcast_value(struct bcm43xx_private *bcm,
  2583. u32 address,
  2584. u32 data)
  2585. {
  2586. bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_ADDR, address);
  2587. bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_DATA, data);
  2588. }
  2589. static int bcm43xx_pcicore_commit_settings(struct bcm43xx_private *bcm)
  2590. {
  2591. int err;
  2592. struct bcm43xx_coreinfo *old_core;
  2593. old_core = bcm->current_core;
  2594. err = bcm43xx_switch_core(bcm, &bcm->core_pci);
  2595. if (err)
  2596. goto out;
  2597. bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
  2598. bcm43xx_switch_core(bcm, old_core);
  2599. assert(err == 0);
  2600. out:
  2601. return err;
  2602. }
  2603. /* Make an I/O Core usable. "core_mask" is the bitmask of the cores to enable.
  2604. * To enable core 0, pass a core_mask of 1<<0
  2605. */
  2606. static int bcm43xx_setup_backplane_pci_connection(struct bcm43xx_private *bcm,
  2607. u32 core_mask)
  2608. {
  2609. u32 backplane_flag_nr;
  2610. u32 value;
  2611. struct bcm43xx_coreinfo *old_core;
  2612. int err = 0;
  2613. value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTPSFLAG);
  2614. backplane_flag_nr = value & BCM43xx_BACKPLANE_FLAG_NR_MASK;
  2615. old_core = bcm->current_core;
  2616. err = bcm43xx_switch_core(bcm, &bcm->core_pci);
  2617. if (err)
  2618. goto out;
  2619. if (bcm->core_pci.rev < 6) {
  2620. value = bcm43xx_read32(bcm, BCM43xx_CIR_SBINTVEC);
  2621. value |= (1 << backplane_flag_nr);
  2622. bcm43xx_write32(bcm, BCM43xx_CIR_SBINTVEC, value);
  2623. } else {
  2624. err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ICR, &value);
  2625. if (err) {
  2626. printk(KERN_ERR PFX "Error: ICR setup failure!\n");
  2627. goto out_switch_back;
  2628. }
  2629. value |= core_mask << 8;
  2630. err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ICR, value);
  2631. if (err) {
  2632. printk(KERN_ERR PFX "Error: ICR setup failure!\n");
  2633. goto out_switch_back;
  2634. }
  2635. }
  2636. value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
  2637. value |= BCM43xx_SBTOPCI2_PREFETCH | BCM43xx_SBTOPCI2_BURST;
  2638. bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
  2639. if (bcm->core_pci.rev < 5) {
  2640. value = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
  2641. value |= (2 << BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT)
  2642. & BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
  2643. value |= (3 << BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT)
  2644. & BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
  2645. bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, value);
  2646. err = bcm43xx_pcicore_commit_settings(bcm);
  2647. assert(err == 0);
  2648. }
  2649. out_switch_back:
  2650. err = bcm43xx_switch_core(bcm, old_core);
  2651. out:
  2652. return err;
  2653. }
  2654. static void bcm43xx_softmac_init(struct bcm43xx_private *bcm)
  2655. {
  2656. ieee80211softmac_start(bcm->net_dev);
  2657. }
  2658. static void bcm43xx_periodic_every120sec(struct bcm43xx_private *bcm)
  2659. {
  2660. struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
  2661. if (phy->type != BCM43xx_PHYTYPE_G || phy->rev < 2)
  2662. return;
  2663. bcm43xx_mac_suspend(bcm);
  2664. bcm43xx_phy_lo_g_measure(bcm);
  2665. bcm43xx_mac_enable(bcm);
  2666. }
  2667. static void bcm43xx_periodic_every60sec(struct bcm43xx_private *bcm)
  2668. {
  2669. bcm43xx_phy_lo_mark_all_unused(bcm);
  2670. if (bcm->sprom.boardflags & BCM43xx_BFL_RSSI) {
  2671. bcm43xx_mac_suspend(bcm);
  2672. bcm43xx_calc_nrssi_slope(bcm);
  2673. bcm43xx_mac_enable(bcm);
  2674. }
  2675. }
  2676. static void bcm43xx_periodic_every30sec(struct bcm43xx_private *bcm)
  2677. {
  2678. /* Update device statistics. */
  2679. bcm43xx_calculate_link_quality(bcm);
  2680. }
  2681. static void bcm43xx_periodic_every15sec(struct bcm43xx_private *bcm)
  2682. {
  2683. struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
  2684. struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
  2685. if (phy->type == BCM43xx_PHYTYPE_G) {
  2686. //TODO: update_aci_moving_average
  2687. if (radio->aci_enable && radio->aci_wlan_automatic) {
  2688. bcm43xx_mac_suspend(bcm);
  2689. if (!radio->aci_enable && 1 /*TODO: not scanning? */) {
  2690. if (0 /*TODO: bunch of conditions*/) {
  2691. bcm43xx_radio_set_interference_mitigation(bcm,
  2692. BCM43xx_RADIO_INTERFMODE_MANUALWLAN);
  2693. }
  2694. } else if (1/*TODO*/) {
  2695. /*
  2696. if ((aci_average > 1000) && !(bcm43xx_radio_aci_scan(bcm))) {
  2697. bcm43xx_radio_set_interference_mitigation(bcm,
  2698. BCM43xx_RADIO_INTERFMODE_NONE);
  2699. }
  2700. */
  2701. }
  2702. bcm43xx_mac_enable(bcm);
  2703. } else if (radio->interfmode == BCM43xx_RADIO_INTERFMODE_NONWLAN &&
  2704. phy->rev == 1) {
  2705. //TODO: implement rev1 workaround
  2706. }
  2707. }
  2708. bcm43xx_phy_xmitpower(bcm); //FIXME: unless scanning?
  2709. //TODO for APHY (temperature?)
  2710. }
  2711. static void bcm43xx_periodic_task_handler(unsigned long d)
  2712. {
  2713. struct bcm43xx_private *bcm = (struct bcm43xx_private *)d;
  2714. unsigned long flags;
  2715. unsigned int state;
  2716. bcm43xx_lock_mmio(bcm, flags);
  2717. assert(bcm->initialized);
  2718. state = bcm->periodic_state;
  2719. if (state % 8 == 0)
  2720. bcm43xx_periodic_every120sec(bcm);
  2721. if (state % 4 == 0)
  2722. bcm43xx_periodic_every60sec(bcm);
  2723. if (state % 2 == 0)
  2724. bcm43xx_periodic_every30sec(bcm);
  2725. bcm43xx_periodic_every15sec(bcm);
  2726. bcm->periodic_state = state + 1;
  2727. mod_timer(&bcm->periodic_tasks, jiffies + (HZ * 15));
  2728. bcm43xx_unlock_mmio(bcm, flags);
  2729. }
  2730. static void bcm43xx_periodic_tasks_delete(struct bcm43xx_private *bcm)
  2731. {
  2732. del_timer_sync(&bcm->periodic_tasks);
  2733. }
  2734. static void bcm43xx_periodic_tasks_setup(struct bcm43xx_private *bcm)
  2735. {
  2736. struct timer_list *timer = &(bcm->periodic_tasks);
  2737. assert(bcm->initialized);
  2738. setup_timer(timer,
  2739. bcm43xx_periodic_task_handler,
  2740. (unsigned long)bcm);
  2741. timer->expires = jiffies;
  2742. add_timer(timer);
  2743. }
  2744. static void bcm43xx_security_init(struct bcm43xx_private *bcm)
  2745. {
  2746. bcm->security_offset = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
  2747. 0x0056) * 2;
  2748. bcm43xx_clear_keys(bcm);
  2749. }
  2750. /* This is the opposite of bcm43xx_init_board() */
  2751. static void bcm43xx_free_board(struct bcm43xx_private *bcm)
  2752. {
  2753. int i, err;
  2754. unsigned long flags;
  2755. bcm43xx_sysfs_unregister(bcm);
  2756. bcm43xx_periodic_tasks_delete(bcm);
  2757. bcm43xx_lock(bcm, flags);
  2758. bcm->initialized = 0;
  2759. bcm->shutting_down = 1;
  2760. bcm43xx_unlock(bcm, flags);
  2761. for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
  2762. if (!bcm->core_80211[i].available)
  2763. continue;
  2764. if (!bcm->core_80211[i].initialized)
  2765. continue;
  2766. err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
  2767. assert(err == 0);
  2768. bcm43xx_wireless_core_cleanup(bcm);
  2769. }
  2770. bcm43xx_pctl_set_crystal(bcm, 0);
  2771. bcm43xx_lock(bcm, flags);
  2772. bcm->shutting_down = 0;
  2773. bcm43xx_unlock(bcm, flags);
  2774. }
  2775. static int bcm43xx_init_board(struct bcm43xx_private *bcm)
  2776. {
  2777. int i, err;
  2778. int connect_phy;
  2779. unsigned long flags;
  2780. might_sleep();
  2781. bcm43xx_lock(bcm, flags);
  2782. bcm->initialized = 0;
  2783. bcm->shutting_down = 0;
  2784. bcm43xx_unlock(bcm, flags);
  2785. err = bcm43xx_pctl_set_crystal(bcm, 1);
  2786. if (err)
  2787. goto out;
  2788. err = bcm43xx_pctl_init(bcm);
  2789. if (err)
  2790. goto err_crystal_off;
  2791. err = bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_FAST);
  2792. if (err)
  2793. goto err_crystal_off;
  2794. tasklet_enable(&bcm->isr_tasklet);
  2795. for (i = 0; i < bcm->nr_80211_available; i++) {
  2796. err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
  2797. assert(err != -ENODEV);
  2798. if (err)
  2799. goto err_80211_unwind;
  2800. /* Enable the selected wireless core.
  2801. * Connect PHY only on the first core.
  2802. */
  2803. if (!bcm43xx_core_enabled(bcm)) {
  2804. if (bcm->nr_80211_available == 1) {
  2805. connect_phy = bcm43xx_current_phy(bcm)->connected;
  2806. } else {
  2807. if (i == 0)
  2808. connect_phy = 1;
  2809. else
  2810. connect_phy = 0;
  2811. }
  2812. bcm43xx_wireless_core_reset(bcm, connect_phy);
  2813. }
  2814. if (i != 0)
  2815. bcm43xx_wireless_core_mark_inactive(bcm, &bcm->core_80211[0]);
  2816. err = bcm43xx_wireless_core_init(bcm);
  2817. if (err)
  2818. goto err_80211_unwind;
  2819. if (i != 0) {
  2820. bcm43xx_mac_suspend(bcm);
  2821. bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
  2822. bcm43xx_radio_turn_off(bcm);
  2823. }
  2824. }
  2825. bcm->active_80211_core = &bcm->core_80211[0];
  2826. if (bcm->nr_80211_available >= 2) {
  2827. bcm43xx_switch_core(bcm, &bcm->core_80211[0]);
  2828. bcm43xx_mac_enable(bcm);
  2829. }
  2830. bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
  2831. bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_SELF, (u8 *)(bcm->net_dev->dev_addr));
  2832. dprintk(KERN_INFO PFX "80211 cores initialized\n");
  2833. bcm43xx_security_init(bcm);
  2834. bcm43xx_softmac_init(bcm);
  2835. bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_DYNAMIC);
  2836. if (bcm43xx_current_radio(bcm)->initial_channel != 0xFF) {
  2837. bcm43xx_mac_suspend(bcm);
  2838. bcm43xx_radio_selectchannel(bcm, bcm43xx_current_radio(bcm)->initial_channel, 0);
  2839. bcm43xx_mac_enable(bcm);
  2840. }
  2841. /* Initialization of the board is done. Flag it as such. */
  2842. bcm43xx_lock(bcm, flags);
  2843. bcm->initialized = 1;
  2844. bcm43xx_unlock(bcm, flags);
  2845. bcm43xx_periodic_tasks_setup(bcm);
  2846. bcm43xx_sysfs_register(bcm);
  2847. //FIXME: check for bcm43xx_sysfs_register failure. This function is a bit messy regarding unwinding, though...
  2848. assert(err == 0);
  2849. out:
  2850. return err;
  2851. err_80211_unwind:
  2852. tasklet_disable(&bcm->isr_tasklet);
  2853. /* unwind all 80211 initialization */
  2854. for (i = 0; i < bcm->nr_80211_available; i++) {
  2855. if (!bcm->core_80211[i].initialized)
  2856. continue;
  2857. bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
  2858. bcm43xx_wireless_core_cleanup(bcm);
  2859. }
  2860. err_crystal_off:
  2861. bcm43xx_pctl_set_crystal(bcm, 0);
  2862. goto out;
  2863. }
  2864. static void bcm43xx_detach_board(struct bcm43xx_private *bcm)
  2865. {
  2866. struct pci_dev *pci_dev = bcm->pci_dev;
  2867. int i;
  2868. bcm43xx_chipset_detach(bcm);
  2869. /* Do _not_ access the chip, after it is detached. */
  2870. iounmap(bcm->mmio_addr);
  2871. pci_release_regions(pci_dev);
  2872. pci_disable_device(pci_dev);
  2873. /* Free allocated structures/fields */
  2874. for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
  2875. kfree(bcm->core_80211_ext[i].phy._lo_pairs);
  2876. if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
  2877. kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
  2878. }
  2879. }
  2880. static int bcm43xx_read_phyinfo(struct bcm43xx_private *bcm)
  2881. {
  2882. struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
  2883. u16 value;
  2884. u8 phy_version;
  2885. u8 phy_type;
  2886. u8 phy_rev;
  2887. int phy_rev_ok = 1;
  2888. void *p;
  2889. value = bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_VER);
  2890. phy_version = (value & 0xF000) >> 12;
  2891. phy_type = (value & 0x0F00) >> 8;
  2892. phy_rev = (value & 0x000F);
  2893. dprintk(KERN_INFO PFX "Detected PHY: Version: %x, Type %x, Revision %x\n",
  2894. phy_version, phy_type, phy_rev);
  2895. switch (phy_type) {
  2896. case BCM43xx_PHYTYPE_A:
  2897. if (phy_rev >= 4)
  2898. phy_rev_ok = 0;
  2899. /*FIXME: We need to switch the ieee->modulation, etc.. flags,
  2900. * if we switch 80211 cores after init is done.
  2901. * As we do not implement on the fly switching between
  2902. * wireless cores, I will leave this as a future task.
  2903. */
  2904. bcm->ieee->modulation = IEEE80211_OFDM_MODULATION;
  2905. bcm->ieee->mode = IEEE_A;
  2906. bcm->ieee->freq_band = IEEE80211_52GHZ_BAND |
  2907. IEEE80211_24GHZ_BAND;
  2908. break;
  2909. case BCM43xx_PHYTYPE_B:
  2910. if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 && phy_rev != 7)
  2911. phy_rev_ok = 0;
  2912. bcm->ieee->modulation = IEEE80211_CCK_MODULATION;
  2913. bcm->ieee->mode = IEEE_B;
  2914. bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
  2915. break;
  2916. case BCM43xx_PHYTYPE_G:
  2917. if (phy_rev > 7)
  2918. phy_rev_ok = 0;
  2919. bcm->ieee->modulation = IEEE80211_OFDM_MODULATION |
  2920. IEEE80211_CCK_MODULATION;
  2921. bcm->ieee->mode = IEEE_G;
  2922. bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
  2923. break;
  2924. default:
  2925. printk(KERN_ERR PFX "Error: Unknown PHY Type %x\n",
  2926. phy_type);
  2927. return -ENODEV;
  2928. };
  2929. if (!phy_rev_ok) {
  2930. printk(KERN_WARNING PFX "Invalid PHY Revision %x\n",
  2931. phy_rev);
  2932. }
  2933. phy->version = phy_version;
  2934. phy->type = phy_type;
  2935. phy->rev = phy_rev;
  2936. if ((phy_type == BCM43xx_PHYTYPE_B) || (phy_type == BCM43xx_PHYTYPE_G)) {
  2937. p = kzalloc(sizeof(struct bcm43xx_lopair) * BCM43xx_LO_COUNT,
  2938. GFP_KERNEL);
  2939. if (!p)
  2940. return -ENOMEM;
  2941. phy->_lo_pairs = p;
  2942. }
  2943. return 0;
  2944. }
  2945. static int bcm43xx_attach_board(struct bcm43xx_private *bcm)
  2946. {
  2947. struct pci_dev *pci_dev = bcm->pci_dev;
  2948. struct net_device *net_dev = bcm->net_dev;
  2949. int err;
  2950. int i;
  2951. unsigned long mmio_start, mmio_flags, mmio_len;
  2952. u32 coremask;
  2953. err = pci_enable_device(pci_dev);
  2954. if (err) {
  2955. printk(KERN_ERR PFX "unable to wake up pci device (%i)\n", err);
  2956. goto out;
  2957. }
  2958. mmio_start = pci_resource_start(pci_dev, 0);
  2959. mmio_flags = pci_resource_flags(pci_dev, 0);
  2960. mmio_len = pci_resource_len(pci_dev, 0);
  2961. if (!(mmio_flags & IORESOURCE_MEM)) {
  2962. printk(KERN_ERR PFX
  2963. "%s, region #0 not an MMIO resource, aborting\n",
  2964. pci_name(pci_dev));
  2965. err = -ENODEV;
  2966. goto err_pci_disable;
  2967. }
  2968. err = pci_request_regions(pci_dev, KBUILD_MODNAME);
  2969. if (err) {
  2970. printk(KERN_ERR PFX
  2971. "could not access PCI resources (%i)\n", err);
  2972. goto err_pci_disable;
  2973. }
  2974. /* enable PCI bus-mastering */
  2975. pci_set_master(pci_dev);
  2976. bcm->mmio_addr = ioremap(mmio_start, mmio_len);
  2977. if (!bcm->mmio_addr) {
  2978. printk(KERN_ERR PFX "%s: cannot remap MMIO, aborting\n",
  2979. pci_name(pci_dev));
  2980. err = -EIO;
  2981. goto err_pci_release;
  2982. }
  2983. bcm->mmio_len = mmio_len;
  2984. net_dev->base_addr = (unsigned long)bcm->mmio_addr;
  2985. bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_VENDOR_ID,
  2986. &bcm->board_vendor);
  2987. bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_ID,
  2988. &bcm->board_type);
  2989. bcm43xx_pci_read_config16(bcm, PCI_REVISION_ID,
  2990. &bcm->board_revision);
  2991. err = bcm43xx_chipset_attach(bcm);
  2992. if (err)
  2993. goto err_iounmap;
  2994. err = bcm43xx_pctl_init(bcm);
  2995. if (err)
  2996. goto err_chipset_detach;
  2997. err = bcm43xx_probe_cores(bcm);
  2998. if (err)
  2999. goto err_chipset_detach;
  3000. /* Attach all IO cores to the backplane. */
  3001. coremask = 0;
  3002. for (i = 0; i < bcm->nr_80211_available; i++)
  3003. coremask |= (1 << bcm->core_80211[i].index);
  3004. //FIXME: Also attach some non80211 cores?
  3005. err = bcm43xx_setup_backplane_pci_connection(bcm, coremask);
  3006. if (err) {
  3007. printk(KERN_ERR PFX "Backplane->PCI connection failed!\n");
  3008. goto err_chipset_detach;
  3009. }
  3010. err = bcm43xx_sprom_extract(bcm);
  3011. if (err)
  3012. goto err_chipset_detach;
  3013. err = bcm43xx_leds_init(bcm);
  3014. if (err)
  3015. goto err_chipset_detach;
  3016. for (i = 0; i < bcm->nr_80211_available; i++) {
  3017. err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
  3018. assert(err != -ENODEV);
  3019. if (err)
  3020. goto err_80211_unwind;
  3021. /* Enable the selected wireless core.
  3022. * Connect PHY only on the first core.
  3023. */
  3024. bcm43xx_wireless_core_reset(bcm, (i == 0));
  3025. err = bcm43xx_read_phyinfo(bcm);
  3026. if (err && (i == 0))
  3027. goto err_80211_unwind;
  3028. err = bcm43xx_read_radioinfo(bcm);
  3029. if (err && (i == 0))
  3030. goto err_80211_unwind;
  3031. err = bcm43xx_validate_chip(bcm);
  3032. if (err && (i == 0))
  3033. goto err_80211_unwind;
  3034. bcm43xx_radio_turn_off(bcm);
  3035. err = bcm43xx_phy_init_tssi2dbm_table(bcm);
  3036. if (err)
  3037. goto err_80211_unwind;
  3038. bcm43xx_wireless_core_disable(bcm);
  3039. }
  3040. bcm43xx_pctl_set_crystal(bcm, 0);
  3041. /* Set the MAC address in the networking subsystem */
  3042. if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_A)
  3043. memcpy(bcm->net_dev->dev_addr, bcm->sprom.et1macaddr, 6);
  3044. else
  3045. memcpy(bcm->net_dev->dev_addr, bcm->sprom.il0macaddr, 6);
  3046. bcm43xx_geo_init(bcm);
  3047. snprintf(bcm->nick, IW_ESSID_MAX_SIZE,
  3048. "Broadcom %04X", bcm->chip_id);
  3049. assert(err == 0);
  3050. out:
  3051. return err;
  3052. err_80211_unwind:
  3053. for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
  3054. kfree(bcm->core_80211_ext[i].phy._lo_pairs);
  3055. if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
  3056. kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
  3057. }
  3058. err_chipset_detach:
  3059. bcm43xx_chipset_detach(bcm);
  3060. err_iounmap:
  3061. iounmap(bcm->mmio_addr);
  3062. err_pci_release:
  3063. pci_release_regions(pci_dev);
  3064. err_pci_disable:
  3065. pci_disable_device(pci_dev);
  3066. goto out;
  3067. }
  3068. /* Do the Hardware IO operations to send the txb */
  3069. static inline int bcm43xx_tx(struct bcm43xx_private *bcm,
  3070. struct ieee80211_txb *txb)
  3071. {
  3072. int err = -ENODEV;
  3073. if (bcm43xx_using_pio(bcm))
  3074. err = bcm43xx_pio_tx(bcm, txb);
  3075. else
  3076. err = bcm43xx_dma_tx(bcm, txb);
  3077. bcm->net_dev->trans_start = jiffies;
  3078. return err;
  3079. }
  3080. static void bcm43xx_ieee80211_set_chan(struct net_device *net_dev,
  3081. u8 channel)
  3082. {
  3083. struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
  3084. struct bcm43xx_radioinfo *radio;
  3085. unsigned long flags;
  3086. bcm43xx_lock_mmio(bcm, flags);
  3087. if (bcm->initialized) {
  3088. bcm43xx_mac_suspend(bcm);
  3089. bcm43xx_radio_selectchannel(bcm, channel, 0);
  3090. bcm43xx_mac_enable(bcm);
  3091. } else {
  3092. radio = bcm43xx_current_radio(bcm);
  3093. radio->initial_channel = channel;
  3094. }
  3095. bcm43xx_unlock_mmio(bcm, flags);
  3096. }
  3097. /* set_security() callback in struct ieee80211_device */
  3098. static void bcm43xx_ieee80211_set_security(struct net_device *net_dev,
  3099. struct ieee80211_security *sec)
  3100. {
  3101. struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
  3102. struct ieee80211_security *secinfo = &bcm->ieee->sec;
  3103. unsigned long flags;
  3104. int keyidx;
  3105. dprintk(KERN_INFO PFX "set security called\n");
  3106. bcm43xx_lock_mmio(bcm, flags);
  3107. for (keyidx = 0; keyidx<WEP_KEYS; keyidx++)
  3108. if (sec->flags & (1<<keyidx)) {
  3109. secinfo->encode_alg[keyidx] = sec->encode_alg[keyidx];
  3110. secinfo->key_sizes[keyidx] = sec->key_sizes[keyidx];
  3111. memcpy(secinfo->keys[keyidx], sec->keys[keyidx], SCM_KEY_LEN);
  3112. }
  3113. if (sec->flags & SEC_ACTIVE_KEY) {
  3114. secinfo->active_key = sec->active_key;
  3115. dprintk(KERN_INFO PFX " .active_key = %d\n", sec->active_key);
  3116. }
  3117. if (sec->flags & SEC_UNICAST_GROUP) {
  3118. secinfo->unicast_uses_group = sec->unicast_uses_group;
  3119. dprintk(KERN_INFO PFX " .unicast_uses_group = %d\n", sec->unicast_uses_group);
  3120. }
  3121. if (sec->flags & SEC_LEVEL) {
  3122. secinfo->level = sec->level;
  3123. dprintk(KERN_INFO PFX " .level = %d\n", sec->level);
  3124. }
  3125. if (sec->flags & SEC_ENABLED) {
  3126. secinfo->enabled = sec->enabled;
  3127. dprintk(KERN_INFO PFX " .enabled = %d\n", sec->enabled);
  3128. }
  3129. if (sec->flags & SEC_ENCRYPT) {
  3130. secinfo->encrypt = sec->encrypt;
  3131. dprintk(KERN_INFO PFX " .encrypt = %d\n", sec->encrypt);
  3132. }
  3133. if (bcm->initialized && !bcm->ieee->host_encrypt) {
  3134. if (secinfo->enabled) {
  3135. /* upload WEP keys to hardware */
  3136. char null_address[6] = { 0 };
  3137. u8 algorithm = 0;
  3138. for (keyidx = 0; keyidx<WEP_KEYS; keyidx++) {
  3139. if (!(sec->flags & (1<<keyidx)))
  3140. continue;
  3141. switch (sec->encode_alg[keyidx]) {
  3142. case SEC_ALG_NONE: algorithm = BCM43xx_SEC_ALGO_NONE; break;
  3143. case SEC_ALG_WEP:
  3144. algorithm = BCM43xx_SEC_ALGO_WEP;
  3145. if (secinfo->key_sizes[keyidx] == 13)
  3146. algorithm = BCM43xx_SEC_ALGO_WEP104;
  3147. break;
  3148. case SEC_ALG_TKIP:
  3149. FIXME();
  3150. algorithm = BCM43xx_SEC_ALGO_TKIP;
  3151. break;
  3152. case SEC_ALG_CCMP:
  3153. FIXME();
  3154. algorithm = BCM43xx_SEC_ALGO_AES;
  3155. break;
  3156. default:
  3157. assert(0);
  3158. break;
  3159. }
  3160. bcm43xx_key_write(bcm, keyidx, algorithm, sec->keys[keyidx], secinfo->key_sizes[keyidx], &null_address[0]);
  3161. bcm->key[keyidx].enabled = 1;
  3162. bcm->key[keyidx].algorithm = algorithm;
  3163. }
  3164. } else
  3165. bcm43xx_clear_keys(bcm);
  3166. }
  3167. bcm43xx_unlock_mmio(bcm, flags);
  3168. }
  3169. /* hard_start_xmit() callback in struct ieee80211_device */
  3170. static int bcm43xx_ieee80211_hard_start_xmit(struct ieee80211_txb *txb,
  3171. struct net_device *net_dev,
  3172. int pri)
  3173. {
  3174. struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
  3175. int err = -ENODEV;
  3176. unsigned long flags;
  3177. bcm43xx_lock_mmio(bcm, flags);
  3178. if (likely(bcm->initialized))
  3179. err = bcm43xx_tx(bcm, txb);
  3180. bcm43xx_unlock_mmio(bcm, flags);
  3181. return err;
  3182. }
  3183. static struct net_device_stats * bcm43xx_net_get_stats(struct net_device *net_dev)
  3184. {
  3185. return &(bcm43xx_priv(net_dev)->ieee->stats);
  3186. }
  3187. static void bcm43xx_net_tx_timeout(struct net_device *net_dev)
  3188. {
  3189. struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
  3190. unsigned long flags;
  3191. bcm43xx_lock_mmio(bcm, flags);
  3192. bcm43xx_controller_restart(bcm, "TX timeout");
  3193. bcm43xx_unlock_mmio(bcm, flags);
  3194. }
  3195. #ifdef CONFIG_NET_POLL_CONTROLLER
  3196. static void bcm43xx_net_poll_controller(struct net_device *net_dev)
  3197. {
  3198. struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
  3199. unsigned long flags;
  3200. local_irq_save(flags);
  3201. bcm43xx_interrupt_handler(bcm->irq, bcm, NULL);
  3202. local_irq_restore(flags);
  3203. }
  3204. #endif /* CONFIG_NET_POLL_CONTROLLER */
  3205. static int bcm43xx_net_open(struct net_device *net_dev)
  3206. {
  3207. struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
  3208. return bcm43xx_init_board(bcm);
  3209. }
  3210. static int bcm43xx_net_stop(struct net_device *net_dev)
  3211. {
  3212. struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
  3213. ieee80211softmac_stop(net_dev);
  3214. bcm43xx_disable_interrupts_sync(bcm, NULL);
  3215. bcm43xx_free_board(bcm);
  3216. return 0;
  3217. }
  3218. static int bcm43xx_init_private(struct bcm43xx_private *bcm,
  3219. struct net_device *net_dev,
  3220. struct pci_dev *pci_dev)
  3221. {
  3222. int err;
  3223. bcm->ieee = netdev_priv(net_dev);
  3224. bcm->softmac = ieee80211_priv(net_dev);
  3225. bcm->softmac->set_channel = bcm43xx_ieee80211_set_chan;
  3226. bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
  3227. bcm->pci_dev = pci_dev;
  3228. bcm->net_dev = net_dev;
  3229. bcm->bad_frames_preempt = modparam_bad_frames_preempt;
  3230. spin_lock_init(&bcm->_lock);
  3231. tasklet_init(&bcm->isr_tasklet,
  3232. (void (*)(unsigned long))bcm43xx_interrupt_tasklet,
  3233. (unsigned long)bcm);
  3234. tasklet_disable_nosync(&bcm->isr_tasklet);
  3235. if (modparam_pio) {
  3236. bcm->__using_pio = 1;
  3237. } else {
  3238. err = pci_set_dma_mask(pci_dev, DMA_30BIT_MASK);
  3239. err |= pci_set_consistent_dma_mask(pci_dev, DMA_30BIT_MASK);
  3240. if (err) {
  3241. #ifdef CONFIG_BCM43XX_PIO
  3242. printk(KERN_WARNING PFX "DMA not supported. Falling back to PIO.\n");
  3243. bcm->__using_pio = 1;
  3244. #else
  3245. printk(KERN_ERR PFX "FATAL: DMA not supported and PIO not configured. "
  3246. "Recompile the driver with PIO support, please.\n");
  3247. return -ENODEV;
  3248. #endif /* CONFIG_BCM43XX_PIO */
  3249. }
  3250. }
  3251. bcm->rts_threshold = BCM43xx_DEFAULT_RTS_THRESHOLD;
  3252. /* default to sw encryption for now */
  3253. bcm->ieee->host_build_iv = 0;
  3254. bcm->ieee->host_encrypt = 1;
  3255. bcm->ieee->host_decrypt = 1;
  3256. bcm->ieee->iw_mode = BCM43xx_INITIAL_IWMODE;
  3257. bcm->ieee->tx_headroom = sizeof(struct bcm43xx_txhdr);
  3258. bcm->ieee->set_security = bcm43xx_ieee80211_set_security;
  3259. bcm->ieee->hard_start_xmit = bcm43xx_ieee80211_hard_start_xmit;
  3260. return 0;
  3261. }
  3262. static int __devinit bcm43xx_init_one(struct pci_dev *pdev,
  3263. const struct pci_device_id *ent)
  3264. {
  3265. struct net_device *net_dev;
  3266. struct bcm43xx_private *bcm;
  3267. int err;
  3268. #ifdef CONFIG_BCM947XX
  3269. if ((pdev->bus->number == 0) && (pdev->device != 0x0800))
  3270. return -ENODEV;
  3271. #endif
  3272. #ifdef DEBUG_SINGLE_DEVICE_ONLY
  3273. if (strcmp(pci_name(pdev), DEBUG_SINGLE_DEVICE_ONLY))
  3274. return -ENODEV;
  3275. #endif
  3276. net_dev = alloc_ieee80211softmac(sizeof(*bcm));
  3277. if (!net_dev) {
  3278. printk(KERN_ERR PFX
  3279. "could not allocate ieee80211 device %s\n",
  3280. pci_name(pdev));
  3281. err = -ENOMEM;
  3282. goto out;
  3283. }
  3284. /* initialize the net_device struct */
  3285. SET_MODULE_OWNER(net_dev);
  3286. SET_NETDEV_DEV(net_dev, &pdev->dev);
  3287. net_dev->open = bcm43xx_net_open;
  3288. net_dev->stop = bcm43xx_net_stop;
  3289. net_dev->get_stats = bcm43xx_net_get_stats;
  3290. net_dev->tx_timeout = bcm43xx_net_tx_timeout;
  3291. #ifdef CONFIG_NET_POLL_CONTROLLER
  3292. net_dev->poll_controller = bcm43xx_net_poll_controller;
  3293. #endif
  3294. net_dev->wireless_handlers = &bcm43xx_wx_handlers_def;
  3295. net_dev->irq = pdev->irq;
  3296. SET_ETHTOOL_OPS(net_dev, &bcm43xx_ethtool_ops);
  3297. /* initialize the bcm43xx_private struct */
  3298. bcm = bcm43xx_priv(net_dev);
  3299. memset(bcm, 0, sizeof(*bcm));
  3300. err = bcm43xx_init_private(bcm, net_dev, pdev);
  3301. if (err)
  3302. goto err_free_netdev;
  3303. pci_set_drvdata(pdev, net_dev);
  3304. err = bcm43xx_attach_board(bcm);
  3305. if (err)
  3306. goto err_free_netdev;
  3307. err = register_netdev(net_dev);
  3308. if (err) {
  3309. printk(KERN_ERR PFX "Cannot register net device, "
  3310. "aborting.\n");
  3311. err = -ENOMEM;
  3312. goto err_detach_board;
  3313. }
  3314. bcm43xx_debugfs_add_device(bcm);
  3315. assert(err == 0);
  3316. out:
  3317. return err;
  3318. err_detach_board:
  3319. bcm43xx_detach_board(bcm);
  3320. err_free_netdev:
  3321. free_ieee80211softmac(net_dev);
  3322. goto out;
  3323. }
  3324. static void __devexit bcm43xx_remove_one(struct pci_dev *pdev)
  3325. {
  3326. struct net_device *net_dev = pci_get_drvdata(pdev);
  3327. struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
  3328. bcm43xx_debugfs_remove_device(bcm);
  3329. unregister_netdev(net_dev);
  3330. bcm43xx_detach_board(bcm);
  3331. assert(bcm->ucode == NULL);
  3332. free_ieee80211softmac(net_dev);
  3333. }
  3334. /* Hard-reset the chip. Do not call this directly.
  3335. * Use bcm43xx_controller_restart()
  3336. */
  3337. static void bcm43xx_chip_reset(void *_bcm)
  3338. {
  3339. struct bcm43xx_private *bcm = _bcm;
  3340. struct net_device *net_dev = bcm->net_dev;
  3341. struct pci_dev *pci_dev = bcm->pci_dev;
  3342. int err;
  3343. int was_initialized = bcm->initialized;
  3344. netif_stop_queue(bcm->net_dev);
  3345. tasklet_disable(&bcm->isr_tasklet);
  3346. bcm->firmware_norelease = 1;
  3347. if (was_initialized)
  3348. bcm43xx_free_board(bcm);
  3349. bcm->firmware_norelease = 0;
  3350. bcm43xx_detach_board(bcm);
  3351. err = bcm43xx_init_private(bcm, net_dev, pci_dev);
  3352. if (err)
  3353. goto failure;
  3354. err = bcm43xx_attach_board(bcm);
  3355. if (err)
  3356. goto failure;
  3357. if (was_initialized) {
  3358. err = bcm43xx_init_board(bcm);
  3359. if (err)
  3360. goto failure;
  3361. }
  3362. netif_wake_queue(bcm->net_dev);
  3363. printk(KERN_INFO PFX "Controller restarted\n");
  3364. return;
  3365. failure:
  3366. printk(KERN_ERR PFX "Controller restart failed\n");
  3367. }
  3368. /* Hard-reset the chip.
  3369. * This can be called from interrupt or process context.
  3370. * Make sure to _not_ re-enable device interrupts after this has been called.
  3371. */
  3372. void bcm43xx_controller_restart(struct bcm43xx_private *bcm, const char *reason)
  3373. {
  3374. bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
  3375. bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
  3376. printk(KERN_ERR PFX "Controller RESET (%s) ...\n", reason);
  3377. INIT_WORK(&bcm->restart_work, bcm43xx_chip_reset, bcm);
  3378. schedule_work(&bcm->restart_work);
  3379. }
  3380. #ifdef CONFIG_PM
  3381. static int bcm43xx_suspend(struct pci_dev *pdev, pm_message_t state)
  3382. {
  3383. struct net_device *net_dev = pci_get_drvdata(pdev);
  3384. struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
  3385. unsigned long flags;
  3386. int try_to_shutdown = 0, err;
  3387. dprintk(KERN_INFO PFX "Suspending...\n");
  3388. bcm43xx_lock(bcm, flags);
  3389. bcm->was_initialized = bcm->initialized;
  3390. if (bcm->initialized)
  3391. try_to_shutdown = 1;
  3392. bcm43xx_unlock(bcm, flags);
  3393. netif_device_detach(net_dev);
  3394. if (try_to_shutdown) {
  3395. ieee80211softmac_stop(net_dev);
  3396. err = bcm43xx_disable_interrupts_sync(bcm, &bcm->irq_savedstate);
  3397. if (unlikely(err)) {
  3398. dprintk(KERN_ERR PFX "Suspend failed.\n");
  3399. return -EAGAIN;
  3400. }
  3401. bcm->firmware_norelease = 1;
  3402. bcm43xx_free_board(bcm);
  3403. bcm->firmware_norelease = 0;
  3404. }
  3405. bcm43xx_chipset_detach(bcm);
  3406. pci_save_state(pdev);
  3407. pci_disable_device(pdev);
  3408. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  3409. dprintk(KERN_INFO PFX "Device suspended.\n");
  3410. return 0;
  3411. }
  3412. static int bcm43xx_resume(struct pci_dev *pdev)
  3413. {
  3414. struct net_device *net_dev = pci_get_drvdata(pdev);
  3415. struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
  3416. int err = 0;
  3417. dprintk(KERN_INFO PFX "Resuming...\n");
  3418. pci_set_power_state(pdev, 0);
  3419. pci_enable_device(pdev);
  3420. pci_restore_state(pdev);
  3421. bcm43xx_chipset_attach(bcm);
  3422. if (bcm->was_initialized) {
  3423. bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
  3424. err = bcm43xx_init_board(bcm);
  3425. }
  3426. if (err) {
  3427. printk(KERN_ERR PFX "Resume failed!\n");
  3428. return err;
  3429. }
  3430. netif_device_attach(net_dev);
  3431. /*FIXME: This should be handled by softmac instead. */
  3432. schedule_work(&bcm->softmac->associnfo.work);
  3433. dprintk(KERN_INFO PFX "Device resumed.\n");
  3434. return 0;
  3435. }
  3436. #endif /* CONFIG_PM */
  3437. static struct pci_driver bcm43xx_pci_driver = {
  3438. .name = KBUILD_MODNAME,
  3439. .id_table = bcm43xx_pci_tbl,
  3440. .probe = bcm43xx_init_one,
  3441. .remove = __devexit_p(bcm43xx_remove_one),
  3442. #ifdef CONFIG_PM
  3443. .suspend = bcm43xx_suspend,
  3444. .resume = bcm43xx_resume,
  3445. #endif /* CONFIG_PM */
  3446. };
  3447. static int __init bcm43xx_init(void)
  3448. {
  3449. printk(KERN_INFO KBUILD_MODNAME " driver\n");
  3450. bcm43xx_debugfs_init();
  3451. return pci_register_driver(&bcm43xx_pci_driver);
  3452. }
  3453. static void __exit bcm43xx_exit(void)
  3454. {
  3455. pci_unregister_driver(&bcm43xx_pci_driver);
  3456. bcm43xx_debugfs_exit();
  3457. }
  3458. module_init(bcm43xx_init)
  3459. module_exit(bcm43xx_exit)