i915_drv.h 8.0 KB

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  1. /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
  2. */
  3. /**************************************************************************
  4. *
  5. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the
  10. * "Software"), to deal in the Software without restriction, including
  11. * without limitation the rights to use, copy, modify, merge, publish,
  12. * distribute, sub license, and/or sell copies of the Software, and to
  13. * permit persons to whom the Software is furnished to do so, subject to
  14. * the following conditions:
  15. *
  16. * The above copyright notice and this permission notice (including the
  17. * next paragraph) shall be included in all copies or substantial portions
  18. * of the Software.
  19. *
  20. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27. *
  28. **************************************************************************/
  29. #ifndef _I915_DRV_H_
  30. #define _I915_DRV_H_
  31. /* General customization:
  32. */
  33. #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
  34. #define DRIVER_NAME "i915"
  35. #define DRIVER_DESC "Intel Graphics"
  36. #define DRIVER_DATE "20040405"
  37. /* Interface history:
  38. *
  39. * 1.1: Original.
  40. */
  41. #define DRIVER_MAJOR 1
  42. #define DRIVER_MINOR 1
  43. #define DRIVER_PATCHLEVEL 0
  44. /* We use our own dma mechanisms, not the drm template code. However,
  45. * the shared IRQ code is useful to us:
  46. */
  47. #define __HAVE_PM 1
  48. typedef struct _drm_i915_ring_buffer {
  49. int tail_mask;
  50. unsigned long Start;
  51. unsigned long End;
  52. unsigned long Size;
  53. u8 *virtual_start;
  54. int head;
  55. int tail;
  56. int space;
  57. drm_local_map_t map;
  58. } drm_i915_ring_buffer_t;
  59. struct mem_block {
  60. struct mem_block *next;
  61. struct mem_block *prev;
  62. int start;
  63. int size;
  64. DRMFILE filp; /* 0: free, -1: heap, other: real files */
  65. };
  66. typedef struct drm_i915_private {
  67. drm_local_map_t *sarea;
  68. drm_local_map_t *mmio_map;
  69. drm_i915_sarea_t *sarea_priv;
  70. drm_i915_ring_buffer_t ring;
  71. void *hw_status_page;
  72. unsigned long counter;
  73. dma_addr_t dma_status_page;
  74. int back_offset;
  75. int front_offset;
  76. int current_page;
  77. int page_flipping;
  78. int use_mi_batchbuffer_start;
  79. wait_queue_head_t irq_queue;
  80. atomic_t irq_received;
  81. atomic_t irq_emitted;
  82. int tex_lru_log_granularity;
  83. int allow_batchbuffer;
  84. struct mem_block *agp_heap;
  85. } drm_i915_private_t;
  86. /* i915_dma.c */
  87. extern void i915_kernel_lost_context(drm_device_t * dev);
  88. extern void i915_driver_pretakedown(drm_device_t *dev);
  89. extern void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp);
  90. /* i915_irq.c */
  91. extern int i915_irq_emit(DRM_IOCTL_ARGS);
  92. extern int i915_irq_wait(DRM_IOCTL_ARGS);
  93. extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
  94. extern void i915_driver_irq_preinstall(drm_device_t *dev);
  95. extern void i915_driver_irq_postinstall(drm_device_t *dev);
  96. extern void i915_driver_irq_uninstall(drm_device_t *dev);
  97. /* i915_mem.c */
  98. extern int i915_mem_alloc(DRM_IOCTL_ARGS);
  99. extern int i915_mem_free(DRM_IOCTL_ARGS);
  100. extern int i915_mem_init_heap(DRM_IOCTL_ARGS);
  101. extern void i915_mem_takedown(struct mem_block **heap);
  102. extern void i915_mem_release(drm_device_t * dev,
  103. DRMFILE filp, struct mem_block *heap);
  104. extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
  105. unsigned long arg);
  106. #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, reg)
  107. #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, reg, val)
  108. #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, reg)
  109. #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, reg, val)
  110. #define I915_VERBOSE 0
  111. #define RING_LOCALS unsigned int outring, ringmask, outcount; \
  112. volatile char *virt;
  113. #define BEGIN_LP_RING(n) do { \
  114. if (I915_VERBOSE) \
  115. DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", \
  116. n, __FUNCTION__); \
  117. if (dev_priv->ring.space < n*4) \
  118. i915_wait_ring(dev, n*4, __FUNCTION__); \
  119. outcount = 0; \
  120. outring = dev_priv->ring.tail; \
  121. ringmask = dev_priv->ring.tail_mask; \
  122. virt = dev_priv->ring.virtual_start; \
  123. } while (0)
  124. #define OUT_RING(n) do { \
  125. if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
  126. *(volatile unsigned int *)(virt + outring) = n; \
  127. outcount++; \
  128. outring += 4; \
  129. outring &= ringmask; \
  130. } while (0)
  131. #define ADVANCE_LP_RING() do { \
  132. if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
  133. dev_priv->ring.tail = outring; \
  134. dev_priv->ring.space -= outcount * 4; \
  135. I915_WRITE(LP_RING + RING_TAIL, outring); \
  136. } while(0)
  137. extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
  138. #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
  139. #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
  140. #define CMD_REPORT_HEAD (7<<23)
  141. #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
  142. #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
  143. #define INST_PARSER_CLIENT 0x00000000
  144. #define INST_OP_FLUSH 0x02000000
  145. #define INST_FLUSH_MAP_CACHE 0x00000001
  146. #define BB1_START_ADDR_MASK (~0x7)
  147. #define BB1_PROTECTED (1<<0)
  148. #define BB1_UNPROTECTED (0<<0)
  149. #define BB2_END_ADDR_MASK (~0x7)
  150. #define I915REG_HWSTAM 0x02098
  151. #define I915REG_INT_IDENTITY_R 0x020a4
  152. #define I915REG_INT_MASK_R 0x020a8
  153. #define I915REG_INT_ENABLE_R 0x020a0
  154. #define SRX_INDEX 0x3c4
  155. #define SRX_DATA 0x3c5
  156. #define SR01 1
  157. #define SR01_SCREEN_OFF (1<<5)
  158. #define PPCR 0x61204
  159. #define PPCR_ON (1<<0)
  160. #define ADPA 0x61100
  161. #define ADPA_DPMS_MASK (~(3<<10))
  162. #define ADPA_DPMS_ON (0<<10)
  163. #define ADPA_DPMS_SUSPEND (1<<10)
  164. #define ADPA_DPMS_STANDBY (2<<10)
  165. #define ADPA_DPMS_OFF (3<<10)
  166. #define NOPID 0x2094
  167. #define LP_RING 0x2030
  168. #define HP_RING 0x2040
  169. #define RING_TAIL 0x00
  170. #define TAIL_ADDR 0x001FFFF8
  171. #define RING_HEAD 0x04
  172. #define HEAD_WRAP_COUNT 0xFFE00000
  173. #define HEAD_WRAP_ONE 0x00200000
  174. #define HEAD_ADDR 0x001FFFFC
  175. #define RING_START 0x08
  176. #define START_ADDR 0x0xFFFFF000
  177. #define RING_LEN 0x0C
  178. #define RING_NR_PAGES 0x001FF000
  179. #define RING_REPORT_MASK 0x00000006
  180. #define RING_REPORT_64K 0x00000002
  181. #define RING_REPORT_128K 0x00000004
  182. #define RING_NO_REPORT 0x00000000
  183. #define RING_VALID_MASK 0x00000001
  184. #define RING_VALID 0x00000001
  185. #define RING_INVALID 0x00000000
  186. #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
  187. #define SC_UPDATE_SCISSOR (0x1<<1)
  188. #define SC_ENABLE_MASK (0x1<<0)
  189. #define SC_ENABLE (0x1<<0)
  190. #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
  191. #define SCI_YMIN_MASK (0xffff<<16)
  192. #define SCI_XMIN_MASK (0xffff<<0)
  193. #define SCI_YMAX_MASK (0xffff<<16)
  194. #define SCI_XMAX_MASK (0xffff<<0)
  195. #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
  196. #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
  197. #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
  198. #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
  199. #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
  200. #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
  201. #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
  202. #define MI_BATCH_BUFFER ((0x30<<23)|1)
  203. #define MI_BATCH_BUFFER_START (0x31<<23)
  204. #define MI_BATCH_BUFFER_END (0xA<<23)
  205. #define MI_BATCH_NON_SECURE (1)
  206. #define MI_WAIT_FOR_EVENT ((0x3<<23))
  207. #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
  208. #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
  209. #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
  210. #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
  211. #define ASYNC_FLIP (1<<22)
  212. #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
  213. #endif