nouveau_drv.h 46 KB

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  1. /*
  2. * Copyright 2005 Stephane Marchesin.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. */
  24. #ifndef __NOUVEAU_DRV_H__
  25. #define __NOUVEAU_DRV_H__
  26. #define DRIVER_AUTHOR "Stephane Marchesin"
  27. #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
  28. #define DRIVER_NAME "nouveau"
  29. #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
  30. #define DRIVER_DATE "20090420"
  31. #define DRIVER_MAJOR 0
  32. #define DRIVER_MINOR 0
  33. #define DRIVER_PATCHLEVEL 16
  34. #define NOUVEAU_FAMILY 0x0000FFFF
  35. #define NOUVEAU_FLAGS 0xFFFF0000
  36. #include "ttm/ttm_bo_api.h"
  37. #include "ttm/ttm_bo_driver.h"
  38. #include "ttm/ttm_placement.h"
  39. #include "ttm/ttm_memory.h"
  40. #include "ttm/ttm_module.h"
  41. struct nouveau_fpriv {
  42. struct ttm_object_file *tfile;
  43. };
  44. #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  45. #include "nouveau_drm.h"
  46. #include "nouveau_reg.h"
  47. #include "nouveau_bios.h"
  48. struct nouveau_grctx;
  49. #define MAX_NUM_DCB_ENTRIES 16
  50. #define NOUVEAU_MAX_CHANNEL_NR 128
  51. #define NOUVEAU_MAX_TILE_NR 15
  52. #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
  53. #define NV50_VM_BLOCK (512*1024*1024ULL)
  54. #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
  55. struct nouveau_tile_reg {
  56. struct nouveau_fence *fence;
  57. uint32_t addr;
  58. uint32_t size;
  59. bool used;
  60. };
  61. struct nouveau_bo {
  62. struct ttm_buffer_object bo;
  63. struct ttm_placement placement;
  64. u32 placements[3];
  65. u32 busy_placements[3];
  66. struct ttm_bo_kmap_obj kmap;
  67. struct list_head head;
  68. /* protected by ttm_bo_reserve() */
  69. struct drm_file *reserved_by;
  70. struct list_head entry;
  71. int pbbo_index;
  72. bool validate_mapped;
  73. struct nouveau_channel *channel;
  74. bool mappable;
  75. bool no_vm;
  76. uint32_t tile_mode;
  77. uint32_t tile_flags;
  78. struct nouveau_tile_reg *tile;
  79. struct drm_gem_object *gem;
  80. struct drm_file *cpu_filp;
  81. int pin_refcnt;
  82. };
  83. #define nouveau_bo_tile_layout(nvbo) \
  84. ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
  85. static inline struct nouveau_bo *
  86. nouveau_bo(struct ttm_buffer_object *bo)
  87. {
  88. return container_of(bo, struct nouveau_bo, bo);
  89. }
  90. static inline struct nouveau_bo *
  91. nouveau_gem_object(struct drm_gem_object *gem)
  92. {
  93. return gem ? gem->driver_private : NULL;
  94. }
  95. /* TODO: submit equivalent to TTM generic API upstream? */
  96. static inline void __iomem *
  97. nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
  98. {
  99. bool is_iomem;
  100. void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
  101. &nvbo->kmap, &is_iomem);
  102. WARN_ON_ONCE(ioptr && !is_iomem);
  103. return ioptr;
  104. }
  105. enum nouveau_flags {
  106. NV_NFORCE = 0x10000000,
  107. NV_NFORCE2 = 0x20000000
  108. };
  109. #define NVOBJ_ENGINE_SW 0
  110. #define NVOBJ_ENGINE_GR 1
  111. #define NVOBJ_ENGINE_DISPLAY 2
  112. #define NVOBJ_ENGINE_INT 0xdeadbeef
  113. #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
  114. #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
  115. struct nouveau_gpuobj {
  116. struct drm_device *dev;
  117. struct kref refcount;
  118. struct list_head list;
  119. struct drm_mm_node *im_pramin;
  120. struct nouveau_bo *im_backing;
  121. uint32_t *im_backing_suspend;
  122. int im_bound;
  123. uint32_t flags;
  124. u32 size;
  125. u32 pinst;
  126. u32 cinst;
  127. u64 vinst;
  128. uint32_t engine;
  129. uint32_t class;
  130. void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
  131. void *priv;
  132. };
  133. struct nouveau_channel {
  134. struct drm_device *dev;
  135. int id;
  136. /* owner of this fifo */
  137. struct drm_file *file_priv;
  138. /* mapping of the fifo itself */
  139. struct drm_local_map *map;
  140. /* mapping of the regs controling the fifo */
  141. void __iomem *user;
  142. uint32_t user_get;
  143. uint32_t user_put;
  144. /* Fencing */
  145. struct {
  146. /* lock protects the pending list only */
  147. spinlock_t lock;
  148. struct list_head pending;
  149. uint32_t sequence;
  150. uint32_t sequence_ack;
  151. atomic_t last_sequence_irq;
  152. } fence;
  153. /* DMA push buffer */
  154. struct nouveau_gpuobj *pushbuf;
  155. struct nouveau_bo *pushbuf_bo;
  156. uint32_t pushbuf_base;
  157. /* Notifier memory */
  158. struct nouveau_bo *notifier_bo;
  159. struct drm_mm notifier_heap;
  160. /* PFIFO context */
  161. struct nouveau_gpuobj *ramfc;
  162. struct nouveau_gpuobj *cache;
  163. /* PGRAPH context */
  164. /* XXX may be merge 2 pointers as private data ??? */
  165. struct nouveau_gpuobj *ramin_grctx;
  166. void *pgraph_ctx;
  167. /* NV50 VM */
  168. struct nouveau_gpuobj *vm_pd;
  169. struct nouveau_gpuobj *vm_gart_pt;
  170. struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
  171. /* Objects */
  172. struct nouveau_gpuobj *ramin; /* Private instmem */
  173. struct drm_mm ramin_heap; /* Private PRAMIN heap */
  174. struct nouveau_ramht *ramht; /* Hash table */
  175. /* GPU object info for stuff used in-kernel (mm_enabled) */
  176. uint32_t m2mf_ntfy;
  177. uint32_t vram_handle;
  178. uint32_t gart_handle;
  179. bool accel_done;
  180. /* Push buffer state (only for drm's channel on !mm_enabled) */
  181. struct {
  182. int max;
  183. int free;
  184. int cur;
  185. int put;
  186. /* access via pushbuf_bo */
  187. int ib_base;
  188. int ib_max;
  189. int ib_free;
  190. int ib_put;
  191. } dma;
  192. uint32_t sw_subchannel[8];
  193. struct {
  194. struct nouveau_gpuobj *vblsem;
  195. uint32_t vblsem_offset;
  196. uint32_t vblsem_rval;
  197. struct list_head vbl_wait;
  198. } nvsw;
  199. struct {
  200. bool active;
  201. char name[32];
  202. struct drm_info_list info;
  203. } debugfs;
  204. };
  205. struct nouveau_instmem_engine {
  206. void *priv;
  207. int (*init)(struct drm_device *dev);
  208. void (*takedown)(struct drm_device *dev);
  209. int (*suspend)(struct drm_device *dev);
  210. void (*resume)(struct drm_device *dev);
  211. int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
  212. uint32_t *size);
  213. void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
  214. int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
  215. int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
  216. void (*flush)(struct drm_device *);
  217. };
  218. struct nouveau_mc_engine {
  219. int (*init)(struct drm_device *dev);
  220. void (*takedown)(struct drm_device *dev);
  221. };
  222. struct nouveau_timer_engine {
  223. int (*init)(struct drm_device *dev);
  224. void (*takedown)(struct drm_device *dev);
  225. uint64_t (*read)(struct drm_device *dev);
  226. };
  227. struct nouveau_fb_engine {
  228. int num_tiles;
  229. int (*init)(struct drm_device *dev);
  230. void (*takedown)(struct drm_device *dev);
  231. void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
  232. uint32_t size, uint32_t pitch);
  233. };
  234. struct nouveau_fifo_engine {
  235. int channels;
  236. struct nouveau_gpuobj *playlist[2];
  237. int cur_playlist;
  238. int (*init)(struct drm_device *);
  239. void (*takedown)(struct drm_device *);
  240. void (*disable)(struct drm_device *);
  241. void (*enable)(struct drm_device *);
  242. bool (*reassign)(struct drm_device *, bool enable);
  243. bool (*cache_pull)(struct drm_device *dev, bool enable);
  244. int (*channel_id)(struct drm_device *);
  245. int (*create_context)(struct nouveau_channel *);
  246. void (*destroy_context)(struct nouveau_channel *);
  247. int (*load_context)(struct nouveau_channel *);
  248. int (*unload_context)(struct drm_device *);
  249. };
  250. struct nouveau_pgraph_object_method {
  251. int id;
  252. int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
  253. uint32_t data);
  254. };
  255. struct nouveau_pgraph_object_class {
  256. int id;
  257. bool software;
  258. struct nouveau_pgraph_object_method *methods;
  259. };
  260. struct nouveau_pgraph_engine {
  261. struct nouveau_pgraph_object_class *grclass;
  262. bool accel_blocked;
  263. int grctx_size;
  264. /* NV2x/NV3x context table (0x400780) */
  265. struct nouveau_gpuobj *ctx_table;
  266. int (*init)(struct drm_device *);
  267. void (*takedown)(struct drm_device *);
  268. void (*fifo_access)(struct drm_device *, bool);
  269. struct nouveau_channel *(*channel)(struct drm_device *);
  270. int (*create_context)(struct nouveau_channel *);
  271. void (*destroy_context)(struct nouveau_channel *);
  272. int (*load_context)(struct nouveau_channel *);
  273. int (*unload_context)(struct drm_device *);
  274. void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
  275. uint32_t size, uint32_t pitch);
  276. };
  277. struct nouveau_display_engine {
  278. int (*early_init)(struct drm_device *);
  279. void (*late_takedown)(struct drm_device *);
  280. int (*create)(struct drm_device *);
  281. int (*init)(struct drm_device *);
  282. void (*destroy)(struct drm_device *);
  283. };
  284. struct nouveau_gpio_engine {
  285. int (*init)(struct drm_device *);
  286. void (*takedown)(struct drm_device *);
  287. int (*get)(struct drm_device *, enum dcb_gpio_tag);
  288. int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
  289. void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
  290. };
  291. struct nouveau_pm_voltage_level {
  292. u8 voltage;
  293. u8 vid;
  294. };
  295. struct nouveau_pm_voltage {
  296. bool supported;
  297. u8 vid_mask;
  298. struct nouveau_pm_voltage_level *level;
  299. int nr_level;
  300. };
  301. #define NOUVEAU_PM_MAX_LEVEL 8
  302. struct nouveau_pm_level {
  303. struct device_attribute dev_attr;
  304. char name[32];
  305. int id;
  306. u32 core;
  307. u32 memory;
  308. u32 shader;
  309. u32 unk05;
  310. u8 voltage;
  311. u8 fanspeed;
  312. u16 memscript;
  313. };
  314. struct nouveau_pm_temp_sensor_constants {
  315. u16 offset_constant;
  316. s16 offset_mult;
  317. u16 offset_div;
  318. u16 slope_mult;
  319. u16 slope_div;
  320. };
  321. struct nouveau_pm_threshold_temp {
  322. s16 critical;
  323. s16 down_clock;
  324. s16 fan_boost;
  325. };
  326. struct nouveau_pm_memtiming {
  327. u32 reg_100220;
  328. u32 reg_100224;
  329. u32 reg_100228;
  330. u32 reg_10022c;
  331. u32 reg_100230;
  332. u32 reg_100234;
  333. u32 reg_100238;
  334. u32 reg_10023c;
  335. };
  336. struct nouveau_pm_memtimings {
  337. bool supported;
  338. struct nouveau_pm_memtiming *timing;
  339. int nr_timing;
  340. };
  341. struct nouveau_pm_engine {
  342. struct nouveau_pm_voltage voltage;
  343. struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
  344. int nr_perflvl;
  345. struct nouveau_pm_memtimings memtimings;
  346. struct nouveau_pm_temp_sensor_constants sensor_constants;
  347. struct nouveau_pm_threshold_temp threshold_temp;
  348. struct nouveau_pm_level boot;
  349. struct nouveau_pm_level *cur;
  350. struct device *hwmon;
  351. int (*clock_get)(struct drm_device *, u32 id);
  352. void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
  353. u32 id, int khz);
  354. void (*clock_set)(struct drm_device *, void *);
  355. int (*voltage_get)(struct drm_device *);
  356. int (*voltage_set)(struct drm_device *, int voltage);
  357. int (*fanspeed_get)(struct drm_device *);
  358. int (*fanspeed_set)(struct drm_device *, int fanspeed);
  359. int (*temp_get)(struct drm_device *);
  360. };
  361. struct nouveau_engine {
  362. struct nouveau_instmem_engine instmem;
  363. struct nouveau_mc_engine mc;
  364. struct nouveau_timer_engine timer;
  365. struct nouveau_fb_engine fb;
  366. struct nouveau_pgraph_engine graph;
  367. struct nouveau_fifo_engine fifo;
  368. struct nouveau_display_engine display;
  369. struct nouveau_gpio_engine gpio;
  370. struct nouveau_pm_engine pm;
  371. };
  372. struct nouveau_pll_vals {
  373. union {
  374. struct {
  375. #ifdef __BIG_ENDIAN
  376. uint8_t N1, M1, N2, M2;
  377. #else
  378. uint8_t M1, N1, M2, N2;
  379. #endif
  380. };
  381. struct {
  382. uint16_t NM1, NM2;
  383. } __attribute__((packed));
  384. };
  385. int log2P;
  386. int refclk;
  387. };
  388. enum nv04_fp_display_regs {
  389. FP_DISPLAY_END,
  390. FP_TOTAL,
  391. FP_CRTC,
  392. FP_SYNC_START,
  393. FP_SYNC_END,
  394. FP_VALID_START,
  395. FP_VALID_END
  396. };
  397. struct nv04_crtc_reg {
  398. unsigned char MiscOutReg;
  399. uint8_t CRTC[0xa0];
  400. uint8_t CR58[0x10];
  401. uint8_t Sequencer[5];
  402. uint8_t Graphics[9];
  403. uint8_t Attribute[21];
  404. unsigned char DAC[768];
  405. /* PCRTC regs */
  406. uint32_t fb_start;
  407. uint32_t crtc_cfg;
  408. uint32_t cursor_cfg;
  409. uint32_t gpio_ext;
  410. uint32_t crtc_830;
  411. uint32_t crtc_834;
  412. uint32_t crtc_850;
  413. uint32_t crtc_eng_ctrl;
  414. /* PRAMDAC regs */
  415. uint32_t nv10_cursync;
  416. struct nouveau_pll_vals pllvals;
  417. uint32_t ramdac_gen_ctrl;
  418. uint32_t ramdac_630;
  419. uint32_t ramdac_634;
  420. uint32_t tv_setup;
  421. uint32_t tv_vtotal;
  422. uint32_t tv_vskew;
  423. uint32_t tv_vsync_delay;
  424. uint32_t tv_htotal;
  425. uint32_t tv_hskew;
  426. uint32_t tv_hsync_delay;
  427. uint32_t tv_hsync_delay2;
  428. uint32_t fp_horiz_regs[7];
  429. uint32_t fp_vert_regs[7];
  430. uint32_t dither;
  431. uint32_t fp_control;
  432. uint32_t dither_regs[6];
  433. uint32_t fp_debug_0;
  434. uint32_t fp_debug_1;
  435. uint32_t fp_debug_2;
  436. uint32_t fp_margin_color;
  437. uint32_t ramdac_8c0;
  438. uint32_t ramdac_a20;
  439. uint32_t ramdac_a24;
  440. uint32_t ramdac_a34;
  441. uint32_t ctv_regs[38];
  442. };
  443. struct nv04_output_reg {
  444. uint32_t output;
  445. int head;
  446. };
  447. struct nv04_mode_state {
  448. struct nv04_crtc_reg crtc_reg[2];
  449. uint32_t pllsel;
  450. uint32_t sel_clk;
  451. };
  452. enum nouveau_card_type {
  453. NV_04 = 0x00,
  454. NV_10 = 0x10,
  455. NV_20 = 0x20,
  456. NV_30 = 0x30,
  457. NV_40 = 0x40,
  458. NV_50 = 0x50,
  459. NV_C0 = 0xc0,
  460. };
  461. struct drm_nouveau_private {
  462. struct drm_device *dev;
  463. /* the card type, takes NV_* as values */
  464. enum nouveau_card_type card_type;
  465. /* exact chipset, derived from NV_PMC_BOOT_0 */
  466. int chipset;
  467. int flags;
  468. void __iomem *mmio;
  469. spinlock_t ramin_lock;
  470. void __iomem *ramin;
  471. u32 ramin_size;
  472. u32 ramin_base;
  473. bool ramin_available;
  474. struct drm_mm ramin_heap;
  475. struct list_head gpuobj_list;
  476. struct nouveau_bo *vga_ram;
  477. struct workqueue_struct *wq;
  478. struct work_struct irq_work;
  479. struct work_struct hpd_work;
  480. struct list_head vbl_waiting;
  481. struct {
  482. struct drm_global_reference mem_global_ref;
  483. struct ttm_bo_global_ref bo_global_ref;
  484. struct ttm_bo_device bdev;
  485. atomic_t validate_sequence;
  486. } ttm;
  487. struct {
  488. spinlock_t lock;
  489. struct drm_mm heap;
  490. struct nouveau_bo *bo;
  491. } fence;
  492. int fifo_alloc_count;
  493. struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
  494. struct nouveau_engine engine;
  495. struct nouveau_channel *channel;
  496. /* For PFIFO and PGRAPH. */
  497. spinlock_t context_switch_lock;
  498. /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
  499. struct nouveau_ramht *ramht;
  500. struct nouveau_gpuobj *ramfc;
  501. struct nouveau_gpuobj *ramro;
  502. uint32_t ramin_rsvd_vram;
  503. struct {
  504. enum {
  505. NOUVEAU_GART_NONE = 0,
  506. NOUVEAU_GART_AGP,
  507. NOUVEAU_GART_SGDMA
  508. } type;
  509. uint64_t aper_base;
  510. uint64_t aper_size;
  511. uint64_t aper_free;
  512. struct nouveau_gpuobj *sg_ctxdma;
  513. struct page *sg_dummy_page;
  514. dma_addr_t sg_dummy_bus;
  515. } gart_info;
  516. /* nv10-nv40 tiling regions */
  517. struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR];
  518. /* VRAM/fb configuration */
  519. uint64_t vram_size;
  520. uint64_t vram_sys_base;
  521. u32 vram_rblock_size;
  522. uint64_t fb_phys;
  523. uint64_t fb_available_size;
  524. uint64_t fb_mappable_pages;
  525. uint64_t fb_aper_free;
  526. int fb_mtrr;
  527. /* G8x/G9x virtual address space */
  528. uint64_t vm_gart_base;
  529. uint64_t vm_gart_size;
  530. uint64_t vm_vram_base;
  531. uint64_t vm_vram_size;
  532. uint64_t vm_end;
  533. struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
  534. int vm_vram_pt_nr;
  535. struct nvbios vbios;
  536. struct nv04_mode_state mode_reg;
  537. struct nv04_mode_state saved_reg;
  538. uint32_t saved_vga_font[4][16384];
  539. uint32_t crtc_owner;
  540. uint32_t dac_users[4];
  541. struct nouveau_suspend_resume {
  542. uint32_t *ramin_copy;
  543. } susres;
  544. struct backlight_device *backlight;
  545. struct nouveau_channel *evo;
  546. struct {
  547. struct dcb_entry *dcb;
  548. u16 script;
  549. u32 pclk;
  550. } evo_irq;
  551. struct {
  552. struct dentry *channel_root;
  553. } debugfs;
  554. struct nouveau_fbdev *nfbdev;
  555. struct apertures_struct *apertures;
  556. };
  557. static inline struct drm_nouveau_private *
  558. nouveau_private(struct drm_device *dev)
  559. {
  560. return dev->dev_private;
  561. }
  562. static inline struct drm_nouveau_private *
  563. nouveau_bdev(struct ttm_bo_device *bd)
  564. {
  565. return container_of(bd, struct drm_nouveau_private, ttm.bdev);
  566. }
  567. static inline int
  568. nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
  569. {
  570. struct nouveau_bo *prev;
  571. if (!pnvbo)
  572. return -EINVAL;
  573. prev = *pnvbo;
  574. *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
  575. if (prev) {
  576. struct ttm_buffer_object *bo = &prev->bo;
  577. ttm_bo_unref(&bo);
  578. }
  579. return 0;
  580. }
  581. #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
  582. struct drm_nouveau_private *nv = dev->dev_private; \
  583. if (!nouveau_channel_owner(dev, (cl), (id))) { \
  584. NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
  585. DRM_CURRENTPID, (id)); \
  586. return -EPERM; \
  587. } \
  588. (ch) = nv->fifos[(id)]; \
  589. } while (0)
  590. /* nouveau_drv.c */
  591. extern int nouveau_agpmode;
  592. extern int nouveau_duallink;
  593. extern int nouveau_uscript_lvds;
  594. extern int nouveau_uscript_tmds;
  595. extern int nouveau_vram_pushbuf;
  596. extern int nouveau_vram_notify;
  597. extern int nouveau_fbpercrtc;
  598. extern int nouveau_tv_disable;
  599. extern char *nouveau_tv_norm;
  600. extern int nouveau_reg_debug;
  601. extern char *nouveau_vbios;
  602. extern int nouveau_ignorelid;
  603. extern int nouveau_nofbaccel;
  604. extern int nouveau_noaccel;
  605. extern int nouveau_force_post;
  606. extern int nouveau_override_conntype;
  607. extern char *nouveau_perflvl;
  608. extern int nouveau_perflvl_wr;
  609. extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
  610. extern int nouveau_pci_resume(struct pci_dev *pdev);
  611. /* nouveau_state.c */
  612. extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
  613. extern int nouveau_load(struct drm_device *, unsigned long flags);
  614. extern int nouveau_firstopen(struct drm_device *);
  615. extern void nouveau_lastclose(struct drm_device *);
  616. extern int nouveau_unload(struct drm_device *);
  617. extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
  618. struct drm_file *);
  619. extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
  620. struct drm_file *);
  621. extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
  622. uint32_t reg, uint32_t mask, uint32_t val);
  623. extern bool nouveau_wait_for_idle(struct drm_device *);
  624. extern int nouveau_card_init(struct drm_device *);
  625. /* nouveau_mem.c */
  626. extern int nouveau_mem_vram_init(struct drm_device *);
  627. extern void nouveau_mem_vram_fini(struct drm_device *);
  628. extern int nouveau_mem_gart_init(struct drm_device *);
  629. extern void nouveau_mem_gart_fini(struct drm_device *);
  630. extern int nouveau_mem_init_agp(struct drm_device *);
  631. extern int nouveau_mem_reset_agp(struct drm_device *);
  632. extern void nouveau_mem_close(struct drm_device *);
  633. extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
  634. uint32_t addr,
  635. uint32_t size,
  636. uint32_t pitch);
  637. extern void nv10_mem_expire_tiling(struct drm_device *dev,
  638. struct nouveau_tile_reg *tile,
  639. struct nouveau_fence *fence);
  640. extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
  641. uint32_t size, uint32_t flags,
  642. uint64_t phys);
  643. extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
  644. uint32_t size);
  645. /* nouveau_notifier.c */
  646. extern int nouveau_notifier_init_channel(struct nouveau_channel *);
  647. extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
  648. extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
  649. int cout, uint32_t *offset);
  650. extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
  651. extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
  652. struct drm_file *);
  653. extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
  654. struct drm_file *);
  655. /* nouveau_channel.c */
  656. extern struct drm_ioctl_desc nouveau_ioctls[];
  657. extern int nouveau_max_ioctl;
  658. extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
  659. extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
  660. int channel);
  661. extern int nouveau_channel_alloc(struct drm_device *dev,
  662. struct nouveau_channel **chan,
  663. struct drm_file *file_priv,
  664. uint32_t fb_ctxdma, uint32_t tt_ctxdma);
  665. extern void nouveau_channel_free(struct nouveau_channel *);
  666. /* nouveau_object.c */
  667. extern int nouveau_gpuobj_early_init(struct drm_device *);
  668. extern int nouveau_gpuobj_init(struct drm_device *);
  669. extern void nouveau_gpuobj_takedown(struct drm_device *);
  670. extern int nouveau_gpuobj_suspend(struct drm_device *dev);
  671. extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
  672. extern void nouveau_gpuobj_resume(struct drm_device *dev);
  673. extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
  674. uint32_t vram_h, uint32_t tt_h);
  675. extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
  676. extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
  677. uint32_t size, int align, uint32_t flags,
  678. struct nouveau_gpuobj **);
  679. extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
  680. struct nouveau_gpuobj **);
  681. extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
  682. u32 size, u32 flags,
  683. struct nouveau_gpuobj **);
  684. extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
  685. uint64_t offset, uint64_t size, int access,
  686. int target, struct nouveau_gpuobj **);
  687. extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
  688. uint64_t offset, uint64_t size,
  689. int access, struct nouveau_gpuobj **,
  690. uint32_t *o_ret);
  691. extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
  692. struct nouveau_gpuobj **);
  693. extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
  694. struct nouveau_gpuobj **);
  695. extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
  696. struct drm_file *);
  697. extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
  698. struct drm_file *);
  699. /* nouveau_irq.c */
  700. extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
  701. extern void nouveau_irq_preinstall(struct drm_device *);
  702. extern int nouveau_irq_postinstall(struct drm_device *);
  703. extern void nouveau_irq_uninstall(struct drm_device *);
  704. /* nouveau_sgdma.c */
  705. extern int nouveau_sgdma_init(struct drm_device *);
  706. extern void nouveau_sgdma_takedown(struct drm_device *);
  707. extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
  708. uint32_t *page);
  709. extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
  710. /* nouveau_debugfs.c */
  711. #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
  712. extern int nouveau_debugfs_init(struct drm_minor *);
  713. extern void nouveau_debugfs_takedown(struct drm_minor *);
  714. extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
  715. extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
  716. #else
  717. static inline int
  718. nouveau_debugfs_init(struct drm_minor *minor)
  719. {
  720. return 0;
  721. }
  722. static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
  723. {
  724. }
  725. static inline int
  726. nouveau_debugfs_channel_init(struct nouveau_channel *chan)
  727. {
  728. return 0;
  729. }
  730. static inline void
  731. nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
  732. {
  733. }
  734. #endif
  735. /* nouveau_dma.c */
  736. extern void nouveau_dma_pre_init(struct nouveau_channel *);
  737. extern int nouveau_dma_init(struct nouveau_channel *);
  738. extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
  739. /* nouveau_acpi.c */
  740. #define ROM_BIOS_PAGE 4096
  741. #if defined(CONFIG_ACPI)
  742. void nouveau_register_dsm_handler(void);
  743. void nouveau_unregister_dsm_handler(void);
  744. int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
  745. bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
  746. int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
  747. #else
  748. static inline void nouveau_register_dsm_handler(void) {}
  749. static inline void nouveau_unregister_dsm_handler(void) {}
  750. static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
  751. static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
  752. static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
  753. #endif
  754. /* nouveau_backlight.c */
  755. #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
  756. extern int nouveau_backlight_init(struct drm_device *);
  757. extern void nouveau_backlight_exit(struct drm_device *);
  758. #else
  759. static inline int nouveau_backlight_init(struct drm_device *dev)
  760. {
  761. return 0;
  762. }
  763. static inline void nouveau_backlight_exit(struct drm_device *dev) { }
  764. #endif
  765. /* nouveau_bios.c */
  766. extern int nouveau_bios_init(struct drm_device *);
  767. extern void nouveau_bios_takedown(struct drm_device *dev);
  768. extern int nouveau_run_vbios_init(struct drm_device *);
  769. extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
  770. struct dcb_entry *);
  771. extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
  772. enum dcb_gpio_tag);
  773. extern struct dcb_connector_table_entry *
  774. nouveau_bios_connector_entry(struct drm_device *, int index);
  775. extern u32 get_pll_register(struct drm_device *, enum pll_types);
  776. extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
  777. struct pll_lims *);
  778. extern int nouveau_bios_run_display_table(struct drm_device *,
  779. struct dcb_entry *,
  780. uint32_t script, int pxclk);
  781. extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
  782. int *length);
  783. extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
  784. extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
  785. extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
  786. bool *dl, bool *if_is_24bit);
  787. extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
  788. int head, int pxclk);
  789. extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
  790. enum LVDS_script, int pxclk);
  791. /* nouveau_ttm.c */
  792. int nouveau_ttm_global_init(struct drm_nouveau_private *);
  793. void nouveau_ttm_global_release(struct drm_nouveau_private *);
  794. int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
  795. /* nouveau_dp.c */
  796. int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
  797. uint8_t *data, int data_nr);
  798. bool nouveau_dp_detect(struct drm_encoder *);
  799. bool nouveau_dp_link_train(struct drm_encoder *);
  800. /* nv04_fb.c */
  801. extern int nv04_fb_init(struct drm_device *);
  802. extern void nv04_fb_takedown(struct drm_device *);
  803. /* nv10_fb.c */
  804. extern int nv10_fb_init(struct drm_device *);
  805. extern void nv10_fb_takedown(struct drm_device *);
  806. extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
  807. uint32_t, uint32_t);
  808. /* nv30_fb.c */
  809. extern int nv30_fb_init(struct drm_device *);
  810. extern void nv30_fb_takedown(struct drm_device *);
  811. /* nv40_fb.c */
  812. extern int nv40_fb_init(struct drm_device *);
  813. extern void nv40_fb_takedown(struct drm_device *);
  814. extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
  815. uint32_t, uint32_t);
  816. /* nv50_fb.c */
  817. extern int nv50_fb_init(struct drm_device *);
  818. extern void nv50_fb_takedown(struct drm_device *);
  819. extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
  820. /* nvc0_fb.c */
  821. extern int nvc0_fb_init(struct drm_device *);
  822. extern void nvc0_fb_takedown(struct drm_device *);
  823. /* nv04_fifo.c */
  824. extern int nv04_fifo_init(struct drm_device *);
  825. extern void nv04_fifo_disable(struct drm_device *);
  826. extern void nv04_fifo_enable(struct drm_device *);
  827. extern bool nv04_fifo_reassign(struct drm_device *, bool);
  828. extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
  829. extern int nv04_fifo_channel_id(struct drm_device *);
  830. extern int nv04_fifo_create_context(struct nouveau_channel *);
  831. extern void nv04_fifo_destroy_context(struct nouveau_channel *);
  832. extern int nv04_fifo_load_context(struct nouveau_channel *);
  833. extern int nv04_fifo_unload_context(struct drm_device *);
  834. /* nv10_fifo.c */
  835. extern int nv10_fifo_init(struct drm_device *);
  836. extern int nv10_fifo_channel_id(struct drm_device *);
  837. extern int nv10_fifo_create_context(struct nouveau_channel *);
  838. extern void nv10_fifo_destroy_context(struct nouveau_channel *);
  839. extern int nv10_fifo_load_context(struct nouveau_channel *);
  840. extern int nv10_fifo_unload_context(struct drm_device *);
  841. /* nv40_fifo.c */
  842. extern int nv40_fifo_init(struct drm_device *);
  843. extern int nv40_fifo_create_context(struct nouveau_channel *);
  844. extern void nv40_fifo_destroy_context(struct nouveau_channel *);
  845. extern int nv40_fifo_load_context(struct nouveau_channel *);
  846. extern int nv40_fifo_unload_context(struct drm_device *);
  847. /* nv50_fifo.c */
  848. extern int nv50_fifo_init(struct drm_device *);
  849. extern void nv50_fifo_takedown(struct drm_device *);
  850. extern int nv50_fifo_channel_id(struct drm_device *);
  851. extern int nv50_fifo_create_context(struct nouveau_channel *);
  852. extern void nv50_fifo_destroy_context(struct nouveau_channel *);
  853. extern int nv50_fifo_load_context(struct nouveau_channel *);
  854. extern int nv50_fifo_unload_context(struct drm_device *);
  855. /* nvc0_fifo.c */
  856. extern int nvc0_fifo_init(struct drm_device *);
  857. extern void nvc0_fifo_takedown(struct drm_device *);
  858. extern void nvc0_fifo_disable(struct drm_device *);
  859. extern void nvc0_fifo_enable(struct drm_device *);
  860. extern bool nvc0_fifo_reassign(struct drm_device *, bool);
  861. extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
  862. extern int nvc0_fifo_channel_id(struct drm_device *);
  863. extern int nvc0_fifo_create_context(struct nouveau_channel *);
  864. extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
  865. extern int nvc0_fifo_load_context(struct nouveau_channel *);
  866. extern int nvc0_fifo_unload_context(struct drm_device *);
  867. /* nv04_graph.c */
  868. extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
  869. extern int nv04_graph_init(struct drm_device *);
  870. extern void nv04_graph_takedown(struct drm_device *);
  871. extern void nv04_graph_fifo_access(struct drm_device *, bool);
  872. extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
  873. extern int nv04_graph_create_context(struct nouveau_channel *);
  874. extern void nv04_graph_destroy_context(struct nouveau_channel *);
  875. extern int nv04_graph_load_context(struct nouveau_channel *);
  876. extern int nv04_graph_unload_context(struct drm_device *);
  877. extern void nv04_graph_context_switch(struct drm_device *);
  878. /* nv10_graph.c */
  879. extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
  880. extern int nv10_graph_init(struct drm_device *);
  881. extern void nv10_graph_takedown(struct drm_device *);
  882. extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
  883. extern int nv10_graph_create_context(struct nouveau_channel *);
  884. extern void nv10_graph_destroy_context(struct nouveau_channel *);
  885. extern int nv10_graph_load_context(struct nouveau_channel *);
  886. extern int nv10_graph_unload_context(struct drm_device *);
  887. extern void nv10_graph_context_switch(struct drm_device *);
  888. extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
  889. uint32_t, uint32_t);
  890. /* nv20_graph.c */
  891. extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
  892. extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
  893. extern int nv20_graph_create_context(struct nouveau_channel *);
  894. extern void nv20_graph_destroy_context(struct nouveau_channel *);
  895. extern int nv20_graph_load_context(struct nouveau_channel *);
  896. extern int nv20_graph_unload_context(struct drm_device *);
  897. extern int nv20_graph_init(struct drm_device *);
  898. extern void nv20_graph_takedown(struct drm_device *);
  899. extern int nv30_graph_init(struct drm_device *);
  900. extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
  901. uint32_t, uint32_t);
  902. /* nv40_graph.c */
  903. extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
  904. extern int nv40_graph_init(struct drm_device *);
  905. extern void nv40_graph_takedown(struct drm_device *);
  906. extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
  907. extern int nv40_graph_create_context(struct nouveau_channel *);
  908. extern void nv40_graph_destroy_context(struct nouveau_channel *);
  909. extern int nv40_graph_load_context(struct nouveau_channel *);
  910. extern int nv40_graph_unload_context(struct drm_device *);
  911. extern void nv40_grctx_init(struct nouveau_grctx *);
  912. extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
  913. uint32_t, uint32_t);
  914. /* nv50_graph.c */
  915. extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
  916. extern int nv50_graph_init(struct drm_device *);
  917. extern void nv50_graph_takedown(struct drm_device *);
  918. extern void nv50_graph_fifo_access(struct drm_device *, bool);
  919. extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
  920. extern int nv50_graph_create_context(struct nouveau_channel *);
  921. extern void nv50_graph_destroy_context(struct nouveau_channel *);
  922. extern int nv50_graph_load_context(struct nouveau_channel *);
  923. extern int nv50_graph_unload_context(struct drm_device *);
  924. extern void nv50_graph_context_switch(struct drm_device *);
  925. extern int nv50_grctx_init(struct nouveau_grctx *);
  926. /* nvc0_graph.c */
  927. extern int nvc0_graph_init(struct drm_device *);
  928. extern void nvc0_graph_takedown(struct drm_device *);
  929. extern void nvc0_graph_fifo_access(struct drm_device *, bool);
  930. extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
  931. extern int nvc0_graph_create_context(struct nouveau_channel *);
  932. extern void nvc0_graph_destroy_context(struct nouveau_channel *);
  933. extern int nvc0_graph_load_context(struct nouveau_channel *);
  934. extern int nvc0_graph_unload_context(struct drm_device *);
  935. /* nv04_instmem.c */
  936. extern int nv04_instmem_init(struct drm_device *);
  937. extern void nv04_instmem_takedown(struct drm_device *);
  938. extern int nv04_instmem_suspend(struct drm_device *);
  939. extern void nv04_instmem_resume(struct drm_device *);
  940. extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
  941. uint32_t *size);
  942. extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
  943. extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
  944. extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
  945. extern void nv04_instmem_flush(struct drm_device *);
  946. /* nv50_instmem.c */
  947. extern int nv50_instmem_init(struct drm_device *);
  948. extern void nv50_instmem_takedown(struct drm_device *);
  949. extern int nv50_instmem_suspend(struct drm_device *);
  950. extern void nv50_instmem_resume(struct drm_device *);
  951. extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
  952. uint32_t *size);
  953. extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
  954. extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
  955. extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
  956. extern void nv50_instmem_flush(struct drm_device *);
  957. extern void nv84_instmem_flush(struct drm_device *);
  958. extern void nv50_vm_flush(struct drm_device *, int engine);
  959. /* nvc0_instmem.c */
  960. extern int nvc0_instmem_init(struct drm_device *);
  961. extern void nvc0_instmem_takedown(struct drm_device *);
  962. extern int nvc0_instmem_suspend(struct drm_device *);
  963. extern void nvc0_instmem_resume(struct drm_device *);
  964. extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
  965. uint32_t *size);
  966. extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
  967. extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
  968. extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
  969. extern void nvc0_instmem_flush(struct drm_device *);
  970. /* nv04_mc.c */
  971. extern int nv04_mc_init(struct drm_device *);
  972. extern void nv04_mc_takedown(struct drm_device *);
  973. /* nv40_mc.c */
  974. extern int nv40_mc_init(struct drm_device *);
  975. extern void nv40_mc_takedown(struct drm_device *);
  976. /* nv50_mc.c */
  977. extern int nv50_mc_init(struct drm_device *);
  978. extern void nv50_mc_takedown(struct drm_device *);
  979. /* nv04_timer.c */
  980. extern int nv04_timer_init(struct drm_device *);
  981. extern uint64_t nv04_timer_read(struct drm_device *);
  982. extern void nv04_timer_takedown(struct drm_device *);
  983. extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
  984. unsigned long arg);
  985. /* nv04_dac.c */
  986. extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
  987. extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
  988. extern int nv04_dac_output_offset(struct drm_encoder *encoder);
  989. extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
  990. extern bool nv04_dac_in_use(struct drm_encoder *encoder);
  991. /* nv04_dfp.c */
  992. extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
  993. extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
  994. extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
  995. int head, bool dl);
  996. extern void nv04_dfp_disable(struct drm_device *dev, int head);
  997. extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
  998. /* nv04_tv.c */
  999. extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
  1000. extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
  1001. /* nv17_tv.c */
  1002. extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
  1003. /* nv04_display.c */
  1004. extern int nv04_display_early_init(struct drm_device *);
  1005. extern void nv04_display_late_takedown(struct drm_device *);
  1006. extern int nv04_display_create(struct drm_device *);
  1007. extern int nv04_display_init(struct drm_device *);
  1008. extern void nv04_display_destroy(struct drm_device *);
  1009. /* nv04_crtc.c */
  1010. extern int nv04_crtc_create(struct drm_device *, int index);
  1011. /* nouveau_bo.c */
  1012. extern struct ttm_bo_driver nouveau_bo_driver;
  1013. extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
  1014. int size, int align, uint32_t flags,
  1015. uint32_t tile_mode, uint32_t tile_flags,
  1016. bool no_vm, bool mappable, struct nouveau_bo **);
  1017. extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
  1018. extern int nouveau_bo_unpin(struct nouveau_bo *);
  1019. extern int nouveau_bo_map(struct nouveau_bo *);
  1020. extern void nouveau_bo_unmap(struct nouveau_bo *);
  1021. extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
  1022. uint32_t busy);
  1023. extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
  1024. extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
  1025. extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
  1026. extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
  1027. /* nouveau_fence.c */
  1028. struct nouveau_fence;
  1029. extern int nouveau_fence_init(struct drm_device *);
  1030. extern void nouveau_fence_fini(struct drm_device *);
  1031. extern int nouveau_fence_channel_init(struct nouveau_channel *);
  1032. extern void nouveau_fence_channel_fini(struct nouveau_channel *);
  1033. extern void nouveau_fence_update(struct nouveau_channel *);
  1034. extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
  1035. bool emit);
  1036. extern int nouveau_fence_emit(struct nouveau_fence *);
  1037. extern void nouveau_fence_work(struct nouveau_fence *fence,
  1038. void (*work)(void *priv, bool signalled),
  1039. void *priv);
  1040. struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
  1041. extern bool nouveau_fence_signalled(void *obj, void *arg);
  1042. extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
  1043. extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
  1044. extern int nouveau_fence_flush(void *obj, void *arg);
  1045. extern void nouveau_fence_unref(void **obj);
  1046. extern void *nouveau_fence_ref(void *obj);
  1047. /* nouveau_gem.c */
  1048. extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
  1049. int size, int align, uint32_t flags,
  1050. uint32_t tile_mode, uint32_t tile_flags,
  1051. bool no_vm, bool mappable, struct nouveau_bo **);
  1052. extern int nouveau_gem_object_new(struct drm_gem_object *);
  1053. extern void nouveau_gem_object_del(struct drm_gem_object *);
  1054. extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
  1055. struct drm_file *);
  1056. extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
  1057. struct drm_file *);
  1058. extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
  1059. struct drm_file *);
  1060. extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
  1061. struct drm_file *);
  1062. extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
  1063. struct drm_file *);
  1064. /* nv10_gpio.c */
  1065. int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
  1066. int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
  1067. /* nv50_gpio.c */
  1068. int nv50_gpio_init(struct drm_device *dev);
  1069. int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
  1070. int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
  1071. void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
  1072. /* nv50_calc. */
  1073. int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
  1074. int *N1, int *M1, int *N2, int *M2, int *P);
  1075. int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
  1076. int clk, int *N, int *fN, int *M, int *P);
  1077. #ifndef ioread32_native
  1078. #ifdef __BIG_ENDIAN
  1079. #define ioread16_native ioread16be
  1080. #define iowrite16_native iowrite16be
  1081. #define ioread32_native ioread32be
  1082. #define iowrite32_native iowrite32be
  1083. #else /* def __BIG_ENDIAN */
  1084. #define ioread16_native ioread16
  1085. #define iowrite16_native iowrite16
  1086. #define ioread32_native ioread32
  1087. #define iowrite32_native iowrite32
  1088. #endif /* def __BIG_ENDIAN else */
  1089. #endif /* !ioread32_native */
  1090. /* channel control reg access */
  1091. static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
  1092. {
  1093. return ioread32_native(chan->user + reg);
  1094. }
  1095. static inline void nvchan_wr32(struct nouveau_channel *chan,
  1096. unsigned reg, u32 val)
  1097. {
  1098. iowrite32_native(val, chan->user + reg);
  1099. }
  1100. /* register access */
  1101. static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
  1102. {
  1103. struct drm_nouveau_private *dev_priv = dev->dev_private;
  1104. return ioread32_native(dev_priv->mmio + reg);
  1105. }
  1106. static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
  1107. {
  1108. struct drm_nouveau_private *dev_priv = dev->dev_private;
  1109. iowrite32_native(val, dev_priv->mmio + reg);
  1110. }
  1111. static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
  1112. {
  1113. u32 tmp = nv_rd32(dev, reg);
  1114. nv_wr32(dev, reg, (tmp & ~mask) | val);
  1115. return tmp;
  1116. }
  1117. static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
  1118. {
  1119. struct drm_nouveau_private *dev_priv = dev->dev_private;
  1120. return ioread8(dev_priv->mmio + reg);
  1121. }
  1122. static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
  1123. {
  1124. struct drm_nouveau_private *dev_priv = dev->dev_private;
  1125. iowrite8(val, dev_priv->mmio + reg);
  1126. }
  1127. #define nv_wait(dev, reg, mask, val) \
  1128. nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
  1129. /* PRAMIN access */
  1130. static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
  1131. {
  1132. struct drm_nouveau_private *dev_priv = dev->dev_private;
  1133. return ioread32_native(dev_priv->ramin + offset);
  1134. }
  1135. static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
  1136. {
  1137. struct drm_nouveau_private *dev_priv = dev->dev_private;
  1138. iowrite32_native(val, dev_priv->ramin + offset);
  1139. }
  1140. /* object access */
  1141. extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
  1142. extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
  1143. /*
  1144. * Logging
  1145. * Argument d is (struct drm_device *).
  1146. */
  1147. #define NV_PRINTK(level, d, fmt, arg...) \
  1148. printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
  1149. pci_name(d->pdev), ##arg)
  1150. #ifndef NV_DEBUG_NOTRACE
  1151. #define NV_DEBUG(d, fmt, arg...) do { \
  1152. if (drm_debug & DRM_UT_DRIVER) { \
  1153. NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
  1154. __LINE__, ##arg); \
  1155. } \
  1156. } while (0)
  1157. #define NV_DEBUG_KMS(d, fmt, arg...) do { \
  1158. if (drm_debug & DRM_UT_KMS) { \
  1159. NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
  1160. __LINE__, ##arg); \
  1161. } \
  1162. } while (0)
  1163. #else
  1164. #define NV_DEBUG(d, fmt, arg...) do { \
  1165. if (drm_debug & DRM_UT_DRIVER) \
  1166. NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
  1167. } while (0)
  1168. #define NV_DEBUG_KMS(d, fmt, arg...) do { \
  1169. if (drm_debug & DRM_UT_KMS) \
  1170. NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
  1171. } while (0)
  1172. #endif
  1173. #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
  1174. #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
  1175. #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
  1176. #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
  1177. #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
  1178. /* nouveau_reg_debug bitmask */
  1179. enum {
  1180. NOUVEAU_REG_DEBUG_MC = 0x1,
  1181. NOUVEAU_REG_DEBUG_VIDEO = 0x2,
  1182. NOUVEAU_REG_DEBUG_FB = 0x4,
  1183. NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
  1184. NOUVEAU_REG_DEBUG_CRTC = 0x10,
  1185. NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
  1186. NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
  1187. NOUVEAU_REG_DEBUG_RMVIO = 0x80,
  1188. NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
  1189. NOUVEAU_REG_DEBUG_EVO = 0x200,
  1190. };
  1191. #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
  1192. if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
  1193. NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
  1194. } while (0)
  1195. static inline bool
  1196. nv_two_heads(struct drm_device *dev)
  1197. {
  1198. struct drm_nouveau_private *dev_priv = dev->dev_private;
  1199. const int impl = dev->pci_device & 0x0ff0;
  1200. if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
  1201. impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
  1202. return true;
  1203. return false;
  1204. }
  1205. static inline bool
  1206. nv_gf4_disp_arch(struct drm_device *dev)
  1207. {
  1208. return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
  1209. }
  1210. static inline bool
  1211. nv_two_reg_pll(struct drm_device *dev)
  1212. {
  1213. struct drm_nouveau_private *dev_priv = dev->dev_private;
  1214. const int impl = dev->pci_device & 0x0ff0;
  1215. if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
  1216. return true;
  1217. return false;
  1218. }
  1219. static inline bool
  1220. nv_match_device(struct drm_device *dev, unsigned device,
  1221. unsigned sub_vendor, unsigned sub_device)
  1222. {
  1223. return dev->pdev->device == device &&
  1224. dev->pdev->subsystem_vendor == sub_vendor &&
  1225. dev->pdev->subsystem_device == sub_device;
  1226. }
  1227. #define NV_SW 0x0000506e
  1228. #define NV_SW_DMA_SEMAPHORE 0x00000060
  1229. #define NV_SW_SEMAPHORE_OFFSET 0x00000064
  1230. #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
  1231. #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
  1232. #define NV_SW_YIELD 0x00000080
  1233. #define NV_SW_DMA_VBLSEM 0x0000018c
  1234. #define NV_SW_VBLSEM_OFFSET 0x00000400
  1235. #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
  1236. #define NV_SW_VBLSEM_RELEASE 0x00000408
  1237. #endif /* __NOUVEAU_DRV_H__ */