r8169.c 72 KB

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  1. /*
  2. =========================================================================
  3. r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
  4. --------------------------------------------------------------------
  5. History:
  6. Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
  7. May 20 2002 - Add link status force-mode and TBI mode support.
  8. 2004 - Massive updates. See kernel SCM system for details.
  9. =========================================================================
  10. 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
  11. Command: 'insmod r8169 media = SET_MEDIA'
  12. Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
  13. SET_MEDIA can be:
  14. _10_Half = 0x01
  15. _10_Full = 0x02
  16. _100_Half = 0x04
  17. _100_Full = 0x08
  18. _1000_Full = 0x10
  19. 2. Support TBI mode.
  20. =========================================================================
  21. VERSION 1.1 <2002/10/4>
  22. The bit4:0 of MII register 4 is called "selector field", and have to be
  23. 00001b to indicate support of IEEE std 802.3 during NWay process of
  24. exchanging Link Code Word (FLP).
  25. VERSION 1.2 <2002/11/30>
  26. - Large style cleanup
  27. - Use ether_crc in stock kernel (linux/crc32.h)
  28. - Copy mc_filter setup code from 8139cp
  29. (includes an optimization, and avoids set_bit use)
  30. VERSION 1.6LK <2004/04/14>
  31. - Merge of Realtek's version 1.6
  32. - Conversion to DMA API
  33. - Suspend/resume
  34. - Endianness
  35. - Misc Rx/Tx bugs
  36. VERSION 2.2LK <2005/01/25>
  37. - RX csum, TX csum/SG, TSO
  38. - VLAN
  39. - baby (< 7200) Jumbo frames support
  40. - Merge of Realtek's version 2.2 (new phy)
  41. */
  42. #include <linux/module.h>
  43. #include <linux/moduleparam.h>
  44. #include <linux/pci.h>
  45. #include <linux/netdevice.h>
  46. #include <linux/etherdevice.h>
  47. #include <linux/delay.h>
  48. #include <linux/ethtool.h>
  49. #include <linux/mii.h>
  50. #include <linux/if_vlan.h>
  51. #include <linux/crc32.h>
  52. #include <linux/in.h>
  53. #include <linux/ip.h>
  54. #include <linux/tcp.h>
  55. #include <linux/init.h>
  56. #include <linux/dma-mapping.h>
  57. #include <asm/io.h>
  58. #include <asm/irq.h>
  59. #ifdef CONFIG_R8169_NAPI
  60. #define NAPI_SUFFIX "-NAPI"
  61. #else
  62. #define NAPI_SUFFIX ""
  63. #endif
  64. #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
  65. #define MODULENAME "r8169"
  66. #define PFX MODULENAME ": "
  67. #ifdef RTL8169_DEBUG
  68. #define assert(expr) \
  69. if (!(expr)) { \
  70. printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  71. #expr,__FILE__,__FUNCTION__,__LINE__); \
  72. }
  73. #define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
  74. #else
  75. #define assert(expr) do {} while (0)
  76. #define dprintk(fmt, args...) do {} while (0)
  77. #endif /* RTL8169_DEBUG */
  78. #define R8169_MSG_DEFAULT \
  79. (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  80. #define TX_BUFFS_AVAIL(tp) \
  81. (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  82. #ifdef CONFIG_R8169_NAPI
  83. #define rtl8169_rx_skb netif_receive_skb
  84. #define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
  85. #define rtl8169_rx_quota(count, quota) min(count, quota)
  86. #else
  87. #define rtl8169_rx_skb netif_rx
  88. #define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
  89. #define rtl8169_rx_quota(count, quota) count
  90. #endif
  91. /* media options */
  92. #define MAX_UNITS 8
  93. static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
  94. static int num_media = 0;
  95. /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
  96. static const int max_interrupt_work = 20;
  97. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  98. The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  99. static const int multicast_filter_limit = 32;
  100. /* MAC address length */
  101. #define MAC_ADDR_LEN 6
  102. #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  103. #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
  104. #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
  105. #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
  106. #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
  107. #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
  108. #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
  109. #define R8169_REGS_SIZE 256
  110. #define R8169_NAPI_WEIGHT 64
  111. #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
  112. #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
  113. #define RX_BUF_SIZE 1536 /* Rx Buffer size */
  114. #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
  115. #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
  116. #define RTL8169_TX_TIMEOUT (6*HZ)
  117. #define RTL8169_PHY_TIMEOUT (10*HZ)
  118. /* write/read MMIO register */
  119. #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
  120. #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
  121. #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
  122. #define RTL_R8(reg) readb (ioaddr + (reg))
  123. #define RTL_R16(reg) readw (ioaddr + (reg))
  124. #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
  125. enum mac_version {
  126. RTL_GIGA_MAC_VER_01 = 0x00,
  127. RTL_GIGA_MAC_VER_02 = 0x01,
  128. RTL_GIGA_MAC_VER_03 = 0x02,
  129. RTL_GIGA_MAC_VER_04 = 0x03,
  130. RTL_GIGA_MAC_VER_05 = 0x04,
  131. RTL_GIGA_MAC_VER_11 = 0x0b,
  132. RTL_GIGA_MAC_VER_12 = 0x0c,
  133. RTL_GIGA_MAC_VER_13 = 0x0d,
  134. RTL_GIGA_MAC_VER_14 = 0x0e,
  135. RTL_GIGA_MAC_VER_15 = 0x0f
  136. };
  137. enum phy_version {
  138. RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
  139. RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
  140. RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
  141. RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
  142. RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
  143. RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
  144. };
  145. #define _R(NAME,MAC,MASK) \
  146. { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
  147. static const struct {
  148. const char *name;
  149. u8 mac_version;
  150. u32 RxConfigMask; /* Clears the bits supported by this chip */
  151. } rtl_chip_info[] = {
  152. _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880),
  153. _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_02, 0xff7e1880),
  154. _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880),
  155. _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880),
  156. _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880),
  157. _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
  158. _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
  159. _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
  160. _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
  161. _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
  162. };
  163. #undef _R
  164. enum cfg_version {
  165. RTL_CFG_0 = 0x00,
  166. RTL_CFG_1,
  167. RTL_CFG_2
  168. };
  169. static const struct {
  170. unsigned int region;
  171. unsigned int align;
  172. } rtl_cfg_info[] = {
  173. [RTL_CFG_0] = { 1, NET_IP_ALIGN },
  174. [RTL_CFG_1] = { 2, NET_IP_ALIGN },
  175. [RTL_CFG_2] = { 2, 8 }
  176. };
  177. static struct pci_device_id rtl8169_pci_tbl[] = {
  178. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
  179. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
  180. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
  181. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_2 },
  182. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
  183. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
  184. { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 },
  185. { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
  186. { PCI_VENDOR_ID_LINKSYS, 0x1032,
  187. PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
  188. {0,},
  189. };
  190. MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
  191. static int rx_copybreak = 200;
  192. static int use_dac;
  193. static struct {
  194. u32 msg_enable;
  195. } debug = { -1 };
  196. enum RTL8169_registers {
  197. MAC0 = 0, /* Ethernet hardware address. */
  198. MAR0 = 8, /* Multicast filter. */
  199. CounterAddrLow = 0x10,
  200. CounterAddrHigh = 0x14,
  201. TxDescStartAddrLow = 0x20,
  202. TxDescStartAddrHigh = 0x24,
  203. TxHDescStartAddrLow = 0x28,
  204. TxHDescStartAddrHigh = 0x2c,
  205. FLASH = 0x30,
  206. ERSR = 0x36,
  207. ChipCmd = 0x37,
  208. TxPoll = 0x38,
  209. IntrMask = 0x3C,
  210. IntrStatus = 0x3E,
  211. TxConfig = 0x40,
  212. RxConfig = 0x44,
  213. RxMissed = 0x4C,
  214. Cfg9346 = 0x50,
  215. Config0 = 0x51,
  216. Config1 = 0x52,
  217. Config2 = 0x53,
  218. Config3 = 0x54,
  219. Config4 = 0x55,
  220. Config5 = 0x56,
  221. MultiIntr = 0x5C,
  222. PHYAR = 0x60,
  223. TBICSR = 0x64,
  224. TBI_ANAR = 0x68,
  225. TBI_LPAR = 0x6A,
  226. PHYstatus = 0x6C,
  227. RxMaxSize = 0xDA,
  228. CPlusCmd = 0xE0,
  229. IntrMitigate = 0xE2,
  230. RxDescAddrLow = 0xE4,
  231. RxDescAddrHigh = 0xE8,
  232. EarlyTxThres = 0xEC,
  233. FuncEvent = 0xF0,
  234. FuncEventMask = 0xF4,
  235. FuncPresetState = 0xF8,
  236. FuncForceEvent = 0xFC,
  237. };
  238. enum RTL8169_register_content {
  239. /* InterruptStatusBits */
  240. SYSErr = 0x8000,
  241. PCSTimeout = 0x4000,
  242. SWInt = 0x0100,
  243. TxDescUnavail = 0x80,
  244. RxFIFOOver = 0x40,
  245. LinkChg = 0x20,
  246. RxOverflow = 0x10,
  247. TxErr = 0x08,
  248. TxOK = 0x04,
  249. RxErr = 0x02,
  250. RxOK = 0x01,
  251. /* RxStatusDesc */
  252. RxFOVF = (1 << 23),
  253. RxRWT = (1 << 22),
  254. RxRES = (1 << 21),
  255. RxRUNT = (1 << 20),
  256. RxCRC = (1 << 19),
  257. /* ChipCmdBits */
  258. CmdReset = 0x10,
  259. CmdRxEnb = 0x08,
  260. CmdTxEnb = 0x04,
  261. RxBufEmpty = 0x01,
  262. /* Cfg9346Bits */
  263. Cfg9346_Lock = 0x00,
  264. Cfg9346_Unlock = 0xC0,
  265. /* rx_mode_bits */
  266. AcceptErr = 0x20,
  267. AcceptRunt = 0x10,
  268. AcceptBroadcast = 0x08,
  269. AcceptMulticast = 0x04,
  270. AcceptMyPhys = 0x02,
  271. AcceptAllPhys = 0x01,
  272. /* RxConfigBits */
  273. RxCfgFIFOShift = 13,
  274. RxCfgDMAShift = 8,
  275. /* TxConfigBits */
  276. TxInterFrameGapShift = 24,
  277. TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
  278. /* Config1 register p.24 */
  279. PMEnable = (1 << 0), /* Power Management Enable */
  280. /* Config3 register p.25 */
  281. MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
  282. LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
  283. /* Config5 register p.27 */
  284. BWF = (1 << 6), /* Accept Broadcast wakeup frame */
  285. MWF = (1 << 5), /* Accept Multicast wakeup frame */
  286. UWF = (1 << 4), /* Accept Unicast wakeup frame */
  287. LanWake = (1 << 1), /* LanWake enable/disable */
  288. PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
  289. /* TBICSR p.28 */
  290. TBIReset = 0x80000000,
  291. TBILoopback = 0x40000000,
  292. TBINwEnable = 0x20000000,
  293. TBINwRestart = 0x10000000,
  294. TBILinkOk = 0x02000000,
  295. TBINwComplete = 0x01000000,
  296. /* CPlusCmd p.31 */
  297. RxVlan = (1 << 6),
  298. RxChkSum = (1 << 5),
  299. PCIDAC = (1 << 4),
  300. PCIMulRW = (1 << 3),
  301. /* rtl8169_PHYstatus */
  302. TBI_Enable = 0x80,
  303. TxFlowCtrl = 0x40,
  304. RxFlowCtrl = 0x20,
  305. _1000bpsF = 0x10,
  306. _100bps = 0x08,
  307. _10bps = 0x04,
  308. LinkStatus = 0x02,
  309. FullDup = 0x01,
  310. /* _MediaType */
  311. _10_Half = 0x01,
  312. _10_Full = 0x02,
  313. _100_Half = 0x04,
  314. _100_Full = 0x08,
  315. _1000_Full = 0x10,
  316. /* _TBICSRBit */
  317. TBILinkOK = 0x02000000,
  318. /* DumpCounterCommand */
  319. CounterDump = 0x8,
  320. };
  321. enum _DescStatusBit {
  322. DescOwn = (1 << 31), /* Descriptor is owned by NIC */
  323. RingEnd = (1 << 30), /* End of descriptor ring */
  324. FirstFrag = (1 << 29), /* First segment of a packet */
  325. LastFrag = (1 << 28), /* Final segment of a packet */
  326. /* Tx private */
  327. LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
  328. MSSShift = 16, /* MSS value position */
  329. MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
  330. IPCS = (1 << 18), /* Calculate IP checksum */
  331. UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
  332. TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
  333. TxVlanTag = (1 << 17), /* Add VLAN tag */
  334. /* Rx private */
  335. PID1 = (1 << 18), /* Protocol ID bit 1/2 */
  336. PID0 = (1 << 17), /* Protocol ID bit 2/2 */
  337. #define RxProtoUDP (PID1)
  338. #define RxProtoTCP (PID0)
  339. #define RxProtoIP (PID1 | PID0)
  340. #define RxProtoMask RxProtoIP
  341. IPFail = (1 << 16), /* IP checksum failed */
  342. UDPFail = (1 << 15), /* UDP/IP checksum failed */
  343. TCPFail = (1 << 14), /* TCP/IP checksum failed */
  344. RxVlanTag = (1 << 16), /* VLAN tag available */
  345. };
  346. #define RsvdMask 0x3fffc000
  347. struct TxDesc {
  348. u32 opts1;
  349. u32 opts2;
  350. u64 addr;
  351. };
  352. struct RxDesc {
  353. u32 opts1;
  354. u32 opts2;
  355. u64 addr;
  356. };
  357. struct ring_info {
  358. struct sk_buff *skb;
  359. u32 len;
  360. u8 __pad[sizeof(void *) - sizeof(u32)];
  361. };
  362. struct rtl8169_private {
  363. void __iomem *mmio_addr; /* memory map physical address */
  364. struct pci_dev *pci_dev; /* Index of PCI device */
  365. struct net_device_stats stats; /* statistics of net device */
  366. spinlock_t lock; /* spin lock flag */
  367. u32 msg_enable;
  368. int chipset;
  369. int mac_version;
  370. int phy_version;
  371. u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
  372. u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
  373. u32 dirty_rx;
  374. u32 dirty_tx;
  375. struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
  376. struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
  377. dma_addr_t TxPhyAddr;
  378. dma_addr_t RxPhyAddr;
  379. struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
  380. struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
  381. unsigned align;
  382. unsigned rx_buf_sz;
  383. struct timer_list timer;
  384. u16 cp_cmd;
  385. u16 intr_mask;
  386. int phy_auto_nego_reg;
  387. int phy_1000_ctrl_reg;
  388. #ifdef CONFIG_R8169_VLAN
  389. struct vlan_group *vlgrp;
  390. #endif
  391. int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
  392. void (*get_settings)(struct net_device *, struct ethtool_cmd *);
  393. void (*phy_reset_enable)(void __iomem *);
  394. unsigned int (*phy_reset_pending)(void __iomem *);
  395. unsigned int (*link_ok)(void __iomem *);
  396. struct work_struct task;
  397. unsigned wol_enabled : 1;
  398. };
  399. MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
  400. MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
  401. module_param_array(media, int, &num_media, 0);
  402. MODULE_PARM_DESC(media, "force phy operation. Deprecated by ethtool (8).");
  403. module_param(rx_copybreak, int, 0);
  404. MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
  405. module_param(use_dac, int, 0);
  406. MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
  407. module_param_named(debug, debug.msg_enable, int, 0);
  408. MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
  409. MODULE_LICENSE("GPL");
  410. MODULE_VERSION(RTL8169_VERSION);
  411. static int rtl8169_open(struct net_device *dev);
  412. static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
  413. static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
  414. static int rtl8169_init_ring(struct net_device *dev);
  415. static void rtl8169_hw_start(struct net_device *dev);
  416. static int rtl8169_close(struct net_device *dev);
  417. static void rtl8169_set_rx_mode(struct net_device *dev);
  418. static void rtl8169_tx_timeout(struct net_device *dev);
  419. static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
  420. static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
  421. void __iomem *);
  422. static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
  423. static void rtl8169_down(struct net_device *dev);
  424. #ifdef CONFIG_R8169_NAPI
  425. static int rtl8169_poll(struct net_device *dev, int *budget);
  426. #endif
  427. static const u16 rtl8169_intr_mask =
  428. SYSErr | LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
  429. static const u16 rtl8169_napi_event =
  430. RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr;
  431. static const unsigned int rtl8169_rx_config =
  432. (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
  433. static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
  434. {
  435. int i;
  436. RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
  437. for (i = 20; i > 0; i--) {
  438. /* Check if the RTL8169 has completed writing to the specified MII register */
  439. if (!(RTL_R32(PHYAR) & 0x80000000))
  440. break;
  441. udelay(25);
  442. }
  443. }
  444. static int mdio_read(void __iomem *ioaddr, int RegAddr)
  445. {
  446. int i, value = -1;
  447. RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
  448. for (i = 20; i > 0; i--) {
  449. /* Check if the RTL8169 has completed retrieving data from the specified MII register */
  450. if (RTL_R32(PHYAR) & 0x80000000) {
  451. value = (int) (RTL_R32(PHYAR) & 0xFFFF);
  452. break;
  453. }
  454. udelay(25);
  455. }
  456. return value;
  457. }
  458. static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
  459. {
  460. RTL_W16(IntrMask, 0x0000);
  461. RTL_W16(IntrStatus, 0xffff);
  462. }
  463. static void rtl8169_asic_down(void __iomem *ioaddr)
  464. {
  465. RTL_W8(ChipCmd, 0x00);
  466. rtl8169_irq_mask_and_ack(ioaddr);
  467. RTL_R16(CPlusCmd);
  468. }
  469. static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
  470. {
  471. return RTL_R32(TBICSR) & TBIReset;
  472. }
  473. static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
  474. {
  475. return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
  476. }
  477. static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
  478. {
  479. return RTL_R32(TBICSR) & TBILinkOk;
  480. }
  481. static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
  482. {
  483. return RTL_R8(PHYstatus) & LinkStatus;
  484. }
  485. static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
  486. {
  487. RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
  488. }
  489. static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
  490. {
  491. unsigned int val;
  492. val = (mdio_read(ioaddr, MII_BMCR) | BMCR_RESET) & 0xffff;
  493. mdio_write(ioaddr, MII_BMCR, val);
  494. }
  495. static void rtl8169_check_link_status(struct net_device *dev,
  496. struct rtl8169_private *tp, void __iomem *ioaddr)
  497. {
  498. unsigned long flags;
  499. spin_lock_irqsave(&tp->lock, flags);
  500. if (tp->link_ok(ioaddr)) {
  501. netif_carrier_on(dev);
  502. if (netif_msg_ifup(tp))
  503. printk(KERN_INFO PFX "%s: link up\n", dev->name);
  504. } else {
  505. if (netif_msg_ifdown(tp))
  506. printk(KERN_INFO PFX "%s: link down\n", dev->name);
  507. netif_carrier_off(dev);
  508. }
  509. spin_unlock_irqrestore(&tp->lock, flags);
  510. }
  511. static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
  512. {
  513. struct {
  514. u16 speed;
  515. u8 duplex;
  516. u8 autoneg;
  517. u8 media;
  518. } link_settings[] = {
  519. { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
  520. { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
  521. { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
  522. { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
  523. { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
  524. /* Make TBI happy */
  525. { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
  526. }, *p;
  527. unsigned char option;
  528. option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
  529. if ((option != 0xff) && !idx && netif_msg_drv(&debug))
  530. printk(KERN_WARNING PFX "media option is deprecated.\n");
  531. for (p = link_settings; p->media != 0xff; p++) {
  532. if (p->media == option)
  533. break;
  534. }
  535. *autoneg = p->autoneg;
  536. *speed = p->speed;
  537. *duplex = p->duplex;
  538. }
  539. static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  540. {
  541. struct rtl8169_private *tp = netdev_priv(dev);
  542. void __iomem *ioaddr = tp->mmio_addr;
  543. u8 options;
  544. wol->wolopts = 0;
  545. #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
  546. wol->supported = WAKE_ANY;
  547. spin_lock_irq(&tp->lock);
  548. options = RTL_R8(Config1);
  549. if (!(options & PMEnable))
  550. goto out_unlock;
  551. options = RTL_R8(Config3);
  552. if (options & LinkUp)
  553. wol->wolopts |= WAKE_PHY;
  554. if (options & MagicPacket)
  555. wol->wolopts |= WAKE_MAGIC;
  556. options = RTL_R8(Config5);
  557. if (options & UWF)
  558. wol->wolopts |= WAKE_UCAST;
  559. if (options & BWF)
  560. wol->wolopts |= WAKE_BCAST;
  561. if (options & MWF)
  562. wol->wolopts |= WAKE_MCAST;
  563. out_unlock:
  564. spin_unlock_irq(&tp->lock);
  565. }
  566. static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  567. {
  568. struct rtl8169_private *tp = netdev_priv(dev);
  569. void __iomem *ioaddr = tp->mmio_addr;
  570. int i;
  571. static struct {
  572. u32 opt;
  573. u16 reg;
  574. u8 mask;
  575. } cfg[] = {
  576. { WAKE_ANY, Config1, PMEnable },
  577. { WAKE_PHY, Config3, LinkUp },
  578. { WAKE_MAGIC, Config3, MagicPacket },
  579. { WAKE_UCAST, Config5, UWF },
  580. { WAKE_BCAST, Config5, BWF },
  581. { WAKE_MCAST, Config5, MWF },
  582. { WAKE_ANY, Config5, LanWake }
  583. };
  584. spin_lock_irq(&tp->lock);
  585. RTL_W8(Cfg9346, Cfg9346_Unlock);
  586. for (i = 0; i < ARRAY_SIZE(cfg); i++) {
  587. u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
  588. if (wol->wolopts & cfg[i].opt)
  589. options |= cfg[i].mask;
  590. RTL_W8(cfg[i].reg, options);
  591. }
  592. RTL_W8(Cfg9346, Cfg9346_Lock);
  593. tp->wol_enabled = (wol->wolopts) ? 1 : 0;
  594. spin_unlock_irq(&tp->lock);
  595. return 0;
  596. }
  597. static void rtl8169_get_drvinfo(struct net_device *dev,
  598. struct ethtool_drvinfo *info)
  599. {
  600. struct rtl8169_private *tp = netdev_priv(dev);
  601. strcpy(info->driver, MODULENAME);
  602. strcpy(info->version, RTL8169_VERSION);
  603. strcpy(info->bus_info, pci_name(tp->pci_dev));
  604. }
  605. static int rtl8169_get_regs_len(struct net_device *dev)
  606. {
  607. return R8169_REGS_SIZE;
  608. }
  609. static int rtl8169_set_speed_tbi(struct net_device *dev,
  610. u8 autoneg, u16 speed, u8 duplex)
  611. {
  612. struct rtl8169_private *tp = netdev_priv(dev);
  613. void __iomem *ioaddr = tp->mmio_addr;
  614. int ret = 0;
  615. u32 reg;
  616. reg = RTL_R32(TBICSR);
  617. if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
  618. (duplex == DUPLEX_FULL)) {
  619. RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
  620. } else if (autoneg == AUTONEG_ENABLE)
  621. RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
  622. else {
  623. if (netif_msg_link(tp)) {
  624. printk(KERN_WARNING "%s: "
  625. "incorrect speed setting refused in TBI mode\n",
  626. dev->name);
  627. }
  628. ret = -EOPNOTSUPP;
  629. }
  630. return ret;
  631. }
  632. static int rtl8169_set_speed_xmii(struct net_device *dev,
  633. u8 autoneg, u16 speed, u8 duplex)
  634. {
  635. struct rtl8169_private *tp = netdev_priv(dev);
  636. void __iomem *ioaddr = tp->mmio_addr;
  637. int auto_nego, giga_ctrl;
  638. auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
  639. auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  640. ADVERTISE_100HALF | ADVERTISE_100FULL);
  641. giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
  642. giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  643. if (autoneg == AUTONEG_ENABLE) {
  644. auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
  645. ADVERTISE_100HALF | ADVERTISE_100FULL);
  646. giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  647. } else {
  648. if (speed == SPEED_10)
  649. auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  650. else if (speed == SPEED_100)
  651. auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  652. else if (speed == SPEED_1000)
  653. giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  654. if (duplex == DUPLEX_HALF)
  655. auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
  656. if (duplex == DUPLEX_FULL)
  657. auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
  658. /* This tweak comes straight from Realtek's driver. */
  659. if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
  660. (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
  661. auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
  662. }
  663. }
  664. /* The 8100e/8101e do Fast Ethernet only. */
  665. if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
  666. (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
  667. (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
  668. if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
  669. netif_msg_link(tp)) {
  670. printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
  671. dev->name);
  672. }
  673. giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  674. }
  675. auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  676. tp->phy_auto_nego_reg = auto_nego;
  677. tp->phy_1000_ctrl_reg = giga_ctrl;
  678. mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
  679. mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
  680. mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
  681. return 0;
  682. }
  683. static int rtl8169_set_speed(struct net_device *dev,
  684. u8 autoneg, u16 speed, u8 duplex)
  685. {
  686. struct rtl8169_private *tp = netdev_priv(dev);
  687. int ret;
  688. ret = tp->set_speed(dev, autoneg, speed, duplex);
  689. if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
  690. mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
  691. return ret;
  692. }
  693. static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  694. {
  695. struct rtl8169_private *tp = netdev_priv(dev);
  696. unsigned long flags;
  697. int ret;
  698. spin_lock_irqsave(&tp->lock, flags);
  699. ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
  700. spin_unlock_irqrestore(&tp->lock, flags);
  701. return ret;
  702. }
  703. static u32 rtl8169_get_rx_csum(struct net_device *dev)
  704. {
  705. struct rtl8169_private *tp = netdev_priv(dev);
  706. return tp->cp_cmd & RxChkSum;
  707. }
  708. static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
  709. {
  710. struct rtl8169_private *tp = netdev_priv(dev);
  711. void __iomem *ioaddr = tp->mmio_addr;
  712. unsigned long flags;
  713. spin_lock_irqsave(&tp->lock, flags);
  714. if (data)
  715. tp->cp_cmd |= RxChkSum;
  716. else
  717. tp->cp_cmd &= ~RxChkSum;
  718. RTL_W16(CPlusCmd, tp->cp_cmd);
  719. RTL_R16(CPlusCmd);
  720. spin_unlock_irqrestore(&tp->lock, flags);
  721. return 0;
  722. }
  723. #ifdef CONFIG_R8169_VLAN
  724. static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
  725. struct sk_buff *skb)
  726. {
  727. return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
  728. TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
  729. }
  730. static void rtl8169_vlan_rx_register(struct net_device *dev,
  731. struct vlan_group *grp)
  732. {
  733. struct rtl8169_private *tp = netdev_priv(dev);
  734. void __iomem *ioaddr = tp->mmio_addr;
  735. unsigned long flags;
  736. spin_lock_irqsave(&tp->lock, flags);
  737. tp->vlgrp = grp;
  738. if (tp->vlgrp)
  739. tp->cp_cmd |= RxVlan;
  740. else
  741. tp->cp_cmd &= ~RxVlan;
  742. RTL_W16(CPlusCmd, tp->cp_cmd);
  743. RTL_R16(CPlusCmd);
  744. spin_unlock_irqrestore(&tp->lock, flags);
  745. }
  746. static void rtl8169_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
  747. {
  748. struct rtl8169_private *tp = netdev_priv(dev);
  749. unsigned long flags;
  750. spin_lock_irqsave(&tp->lock, flags);
  751. if (tp->vlgrp)
  752. tp->vlgrp->vlan_devices[vid] = NULL;
  753. spin_unlock_irqrestore(&tp->lock, flags);
  754. }
  755. static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
  756. struct sk_buff *skb)
  757. {
  758. u32 opts2 = le32_to_cpu(desc->opts2);
  759. int ret;
  760. if (tp->vlgrp && (opts2 & RxVlanTag)) {
  761. rtl8169_rx_hwaccel_skb(skb, tp->vlgrp,
  762. swab16(opts2 & 0xffff));
  763. ret = 0;
  764. } else
  765. ret = -1;
  766. desc->opts2 = 0;
  767. return ret;
  768. }
  769. #else /* !CONFIG_R8169_VLAN */
  770. static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
  771. struct sk_buff *skb)
  772. {
  773. return 0;
  774. }
  775. static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
  776. struct sk_buff *skb)
  777. {
  778. return -1;
  779. }
  780. #endif
  781. static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
  782. {
  783. struct rtl8169_private *tp = netdev_priv(dev);
  784. void __iomem *ioaddr = tp->mmio_addr;
  785. u32 status;
  786. cmd->supported =
  787. SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
  788. cmd->port = PORT_FIBRE;
  789. cmd->transceiver = XCVR_INTERNAL;
  790. status = RTL_R32(TBICSR);
  791. cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
  792. cmd->autoneg = !!(status & TBINwEnable);
  793. cmd->speed = SPEED_1000;
  794. cmd->duplex = DUPLEX_FULL; /* Always set */
  795. }
  796. static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
  797. {
  798. struct rtl8169_private *tp = netdev_priv(dev);
  799. void __iomem *ioaddr = tp->mmio_addr;
  800. u8 status;
  801. cmd->supported = SUPPORTED_10baseT_Half |
  802. SUPPORTED_10baseT_Full |
  803. SUPPORTED_100baseT_Half |
  804. SUPPORTED_100baseT_Full |
  805. SUPPORTED_1000baseT_Full |
  806. SUPPORTED_Autoneg |
  807. SUPPORTED_TP;
  808. cmd->autoneg = 1;
  809. cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
  810. if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
  811. cmd->advertising |= ADVERTISED_10baseT_Half;
  812. if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
  813. cmd->advertising |= ADVERTISED_10baseT_Full;
  814. if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
  815. cmd->advertising |= ADVERTISED_100baseT_Half;
  816. if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
  817. cmd->advertising |= ADVERTISED_100baseT_Full;
  818. if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
  819. cmd->advertising |= ADVERTISED_1000baseT_Full;
  820. status = RTL_R8(PHYstatus);
  821. if (status & _1000bpsF)
  822. cmd->speed = SPEED_1000;
  823. else if (status & _100bps)
  824. cmd->speed = SPEED_100;
  825. else if (status & _10bps)
  826. cmd->speed = SPEED_10;
  827. if (status & TxFlowCtrl)
  828. cmd->advertising |= ADVERTISED_Asym_Pause;
  829. if (status & RxFlowCtrl)
  830. cmd->advertising |= ADVERTISED_Pause;
  831. cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
  832. DUPLEX_FULL : DUPLEX_HALF;
  833. }
  834. static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  835. {
  836. struct rtl8169_private *tp = netdev_priv(dev);
  837. unsigned long flags;
  838. spin_lock_irqsave(&tp->lock, flags);
  839. tp->get_settings(dev, cmd);
  840. spin_unlock_irqrestore(&tp->lock, flags);
  841. return 0;
  842. }
  843. static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
  844. void *p)
  845. {
  846. struct rtl8169_private *tp = netdev_priv(dev);
  847. unsigned long flags;
  848. if (regs->len > R8169_REGS_SIZE)
  849. regs->len = R8169_REGS_SIZE;
  850. spin_lock_irqsave(&tp->lock, flags);
  851. memcpy_fromio(p, tp->mmio_addr, regs->len);
  852. spin_unlock_irqrestore(&tp->lock, flags);
  853. }
  854. static u32 rtl8169_get_msglevel(struct net_device *dev)
  855. {
  856. struct rtl8169_private *tp = netdev_priv(dev);
  857. return tp->msg_enable;
  858. }
  859. static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
  860. {
  861. struct rtl8169_private *tp = netdev_priv(dev);
  862. tp->msg_enable = value;
  863. }
  864. static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
  865. "tx_packets",
  866. "rx_packets",
  867. "tx_errors",
  868. "rx_errors",
  869. "rx_missed",
  870. "align_errors",
  871. "tx_single_collisions",
  872. "tx_multi_collisions",
  873. "unicast",
  874. "broadcast",
  875. "multicast",
  876. "tx_aborted",
  877. "tx_underrun",
  878. };
  879. struct rtl8169_counters {
  880. u64 tx_packets;
  881. u64 rx_packets;
  882. u64 tx_errors;
  883. u32 rx_errors;
  884. u16 rx_missed;
  885. u16 align_errors;
  886. u32 tx_one_collision;
  887. u32 tx_multi_collision;
  888. u64 rx_unicast;
  889. u64 rx_broadcast;
  890. u32 rx_multicast;
  891. u16 tx_aborted;
  892. u16 tx_underun;
  893. };
  894. static int rtl8169_get_stats_count(struct net_device *dev)
  895. {
  896. return ARRAY_SIZE(rtl8169_gstrings);
  897. }
  898. static void rtl8169_get_ethtool_stats(struct net_device *dev,
  899. struct ethtool_stats *stats, u64 *data)
  900. {
  901. struct rtl8169_private *tp = netdev_priv(dev);
  902. void __iomem *ioaddr = tp->mmio_addr;
  903. struct rtl8169_counters *counters;
  904. dma_addr_t paddr;
  905. u32 cmd;
  906. ASSERT_RTNL();
  907. counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
  908. if (!counters)
  909. return;
  910. RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
  911. cmd = (u64)paddr & DMA_32BIT_MASK;
  912. RTL_W32(CounterAddrLow, cmd);
  913. RTL_W32(CounterAddrLow, cmd | CounterDump);
  914. while (RTL_R32(CounterAddrLow) & CounterDump) {
  915. if (msleep_interruptible(1))
  916. break;
  917. }
  918. RTL_W32(CounterAddrLow, 0);
  919. RTL_W32(CounterAddrHigh, 0);
  920. data[0] = le64_to_cpu(counters->tx_packets);
  921. data[1] = le64_to_cpu(counters->rx_packets);
  922. data[2] = le64_to_cpu(counters->tx_errors);
  923. data[3] = le32_to_cpu(counters->rx_errors);
  924. data[4] = le16_to_cpu(counters->rx_missed);
  925. data[5] = le16_to_cpu(counters->align_errors);
  926. data[6] = le32_to_cpu(counters->tx_one_collision);
  927. data[7] = le32_to_cpu(counters->tx_multi_collision);
  928. data[8] = le64_to_cpu(counters->rx_unicast);
  929. data[9] = le64_to_cpu(counters->rx_broadcast);
  930. data[10] = le32_to_cpu(counters->rx_multicast);
  931. data[11] = le16_to_cpu(counters->tx_aborted);
  932. data[12] = le16_to_cpu(counters->tx_underun);
  933. pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
  934. }
  935. static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  936. {
  937. switch(stringset) {
  938. case ETH_SS_STATS:
  939. memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
  940. break;
  941. }
  942. }
  943. static const struct ethtool_ops rtl8169_ethtool_ops = {
  944. .get_drvinfo = rtl8169_get_drvinfo,
  945. .get_regs_len = rtl8169_get_regs_len,
  946. .get_link = ethtool_op_get_link,
  947. .get_settings = rtl8169_get_settings,
  948. .set_settings = rtl8169_set_settings,
  949. .get_msglevel = rtl8169_get_msglevel,
  950. .set_msglevel = rtl8169_set_msglevel,
  951. .get_rx_csum = rtl8169_get_rx_csum,
  952. .set_rx_csum = rtl8169_set_rx_csum,
  953. .get_tx_csum = ethtool_op_get_tx_csum,
  954. .set_tx_csum = ethtool_op_set_tx_csum,
  955. .get_sg = ethtool_op_get_sg,
  956. .set_sg = ethtool_op_set_sg,
  957. .get_tso = ethtool_op_get_tso,
  958. .set_tso = ethtool_op_set_tso,
  959. .get_regs = rtl8169_get_regs,
  960. .get_wol = rtl8169_get_wol,
  961. .set_wol = rtl8169_set_wol,
  962. .get_strings = rtl8169_get_strings,
  963. .get_stats_count = rtl8169_get_stats_count,
  964. .get_ethtool_stats = rtl8169_get_ethtool_stats,
  965. .get_perm_addr = ethtool_op_get_perm_addr,
  966. };
  967. static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum,
  968. int bitval)
  969. {
  970. int val;
  971. val = mdio_read(ioaddr, reg);
  972. val = (bitval == 1) ?
  973. val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
  974. mdio_write(ioaddr, reg, val & 0xffff);
  975. }
  976. static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr)
  977. {
  978. const struct {
  979. u32 mask;
  980. int mac_version;
  981. } mac_info[] = {
  982. { 0x38800000, RTL_GIGA_MAC_VER_15 },
  983. { 0x38000000, RTL_GIGA_MAC_VER_12 },
  984. { 0x34000000, RTL_GIGA_MAC_VER_13 },
  985. { 0x30800000, RTL_GIGA_MAC_VER_14 },
  986. { 0x30000000, RTL_GIGA_MAC_VER_11 },
  987. { 0x18000000, RTL_GIGA_MAC_VER_05 },
  988. { 0x10000000, RTL_GIGA_MAC_VER_04 },
  989. { 0x04000000, RTL_GIGA_MAC_VER_03 },
  990. { 0x00800000, RTL_GIGA_MAC_VER_02 },
  991. { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
  992. }, *p = mac_info;
  993. u32 reg;
  994. reg = RTL_R32(TxConfig) & 0x7c800000;
  995. while ((reg & p->mask) != p->mask)
  996. p++;
  997. tp->mac_version = p->mac_version;
  998. }
  999. static void rtl8169_print_mac_version(struct rtl8169_private *tp)
  1000. {
  1001. dprintk("mac_version = 0x%02x\n", tp->mac_version);
  1002. }
  1003. static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)
  1004. {
  1005. const struct {
  1006. u16 mask;
  1007. u16 set;
  1008. int phy_version;
  1009. } phy_info[] = {
  1010. { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
  1011. { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
  1012. { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
  1013. { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
  1014. }, *p = phy_info;
  1015. u16 reg;
  1016. reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
  1017. while ((reg & p->mask) != p->set)
  1018. p++;
  1019. tp->phy_version = p->phy_version;
  1020. }
  1021. static void rtl8169_print_phy_version(struct rtl8169_private *tp)
  1022. {
  1023. struct {
  1024. int version;
  1025. char *msg;
  1026. u32 reg;
  1027. } phy_print[] = {
  1028. { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
  1029. { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
  1030. { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
  1031. { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
  1032. { 0, NULL, 0x0000 }
  1033. }, *p;
  1034. for (p = phy_print; p->msg; p++) {
  1035. if (tp->phy_version == p->version) {
  1036. dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
  1037. return;
  1038. }
  1039. }
  1040. dprintk("phy_version == Unknown\n");
  1041. }
  1042. static void rtl8169_hw_phy_config(struct net_device *dev)
  1043. {
  1044. struct rtl8169_private *tp = netdev_priv(dev);
  1045. void __iomem *ioaddr = tp->mmio_addr;
  1046. struct {
  1047. u16 regs[5]; /* Beware of bit-sign propagation */
  1048. } phy_magic[5] = { {
  1049. { 0x0000, //w 4 15 12 0
  1050. 0x00a1, //w 3 15 0 00a1
  1051. 0x0008, //w 2 15 0 0008
  1052. 0x1020, //w 1 15 0 1020
  1053. 0x1000 } },{ //w 0 15 0 1000
  1054. { 0x7000, //w 4 15 12 7
  1055. 0xff41, //w 3 15 0 ff41
  1056. 0xde60, //w 2 15 0 de60
  1057. 0x0140, //w 1 15 0 0140
  1058. 0x0077 } },{ //w 0 15 0 0077
  1059. { 0xa000, //w 4 15 12 a
  1060. 0xdf01, //w 3 15 0 df01
  1061. 0xdf20, //w 2 15 0 df20
  1062. 0xff95, //w 1 15 0 ff95
  1063. 0xfa00 } },{ //w 0 15 0 fa00
  1064. { 0xb000, //w 4 15 12 b
  1065. 0xff41, //w 3 15 0 ff41
  1066. 0xde20, //w 2 15 0 de20
  1067. 0x0140, //w 1 15 0 0140
  1068. 0x00bb } },{ //w 0 15 0 00bb
  1069. { 0xf000, //w 4 15 12 f
  1070. 0xdf01, //w 3 15 0 df01
  1071. 0xdf20, //w 2 15 0 df20
  1072. 0xff95, //w 1 15 0 ff95
  1073. 0xbf00 } //w 0 15 0 bf00
  1074. }
  1075. }, *p = phy_magic;
  1076. int i;
  1077. rtl8169_print_mac_version(tp);
  1078. rtl8169_print_phy_version(tp);
  1079. if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
  1080. return;
  1081. if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
  1082. return;
  1083. dprintk("MAC version != 0 && PHY version == 0 or 1\n");
  1084. dprintk("Do final_reg2.cfg\n");
  1085. /* Shazam ! */
  1086. if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
  1087. mdio_write(ioaddr, 31, 0x0001);
  1088. mdio_write(ioaddr, 9, 0x273a);
  1089. mdio_write(ioaddr, 14, 0x7bfb);
  1090. mdio_write(ioaddr, 27, 0x841e);
  1091. mdio_write(ioaddr, 31, 0x0002);
  1092. mdio_write(ioaddr, 1, 0x90d0);
  1093. mdio_write(ioaddr, 31, 0x0000);
  1094. return;
  1095. }
  1096. /* phy config for RTL8169s mac_version C chip */
  1097. mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
  1098. mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
  1099. mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
  1100. rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
  1101. for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
  1102. int val, pos = 4;
  1103. val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
  1104. mdio_write(ioaddr, pos, val);
  1105. while (--pos >= 0)
  1106. mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
  1107. rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
  1108. rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
  1109. }
  1110. mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
  1111. }
  1112. static void rtl8169_phy_timer(unsigned long __opaque)
  1113. {
  1114. struct net_device *dev = (struct net_device *)__opaque;
  1115. struct rtl8169_private *tp = netdev_priv(dev);
  1116. struct timer_list *timer = &tp->timer;
  1117. void __iomem *ioaddr = tp->mmio_addr;
  1118. unsigned long timeout = RTL8169_PHY_TIMEOUT;
  1119. assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
  1120. assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
  1121. if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
  1122. return;
  1123. spin_lock_irq(&tp->lock);
  1124. if (tp->phy_reset_pending(ioaddr)) {
  1125. /*
  1126. * A busy loop could burn quite a few cycles on nowadays CPU.
  1127. * Let's delay the execution of the timer for a few ticks.
  1128. */
  1129. timeout = HZ/10;
  1130. goto out_mod_timer;
  1131. }
  1132. if (tp->link_ok(ioaddr))
  1133. goto out_unlock;
  1134. if (netif_msg_link(tp))
  1135. printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
  1136. tp->phy_reset_enable(ioaddr);
  1137. out_mod_timer:
  1138. mod_timer(timer, jiffies + timeout);
  1139. out_unlock:
  1140. spin_unlock_irq(&tp->lock);
  1141. }
  1142. static inline void rtl8169_delete_timer(struct net_device *dev)
  1143. {
  1144. struct rtl8169_private *tp = netdev_priv(dev);
  1145. struct timer_list *timer = &tp->timer;
  1146. if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
  1147. (tp->phy_version >= RTL_GIGA_PHY_VER_H))
  1148. return;
  1149. del_timer_sync(timer);
  1150. }
  1151. static inline void rtl8169_request_timer(struct net_device *dev)
  1152. {
  1153. struct rtl8169_private *tp = netdev_priv(dev);
  1154. struct timer_list *timer = &tp->timer;
  1155. if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
  1156. (tp->phy_version >= RTL_GIGA_PHY_VER_H))
  1157. return;
  1158. init_timer(timer);
  1159. timer->expires = jiffies + RTL8169_PHY_TIMEOUT;
  1160. timer->data = (unsigned long)(dev);
  1161. timer->function = rtl8169_phy_timer;
  1162. add_timer(timer);
  1163. }
  1164. #ifdef CONFIG_NET_POLL_CONTROLLER
  1165. /*
  1166. * Polling 'interrupt' - used by things like netconsole to send skbs
  1167. * without having to re-enable interrupts. It's not called while
  1168. * the interrupt routine is executing.
  1169. */
  1170. static void rtl8169_netpoll(struct net_device *dev)
  1171. {
  1172. struct rtl8169_private *tp = netdev_priv(dev);
  1173. struct pci_dev *pdev = tp->pci_dev;
  1174. disable_irq(pdev->irq);
  1175. rtl8169_interrupt(pdev->irq, dev);
  1176. enable_irq(pdev->irq);
  1177. }
  1178. #endif
  1179. static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
  1180. void __iomem *ioaddr)
  1181. {
  1182. iounmap(ioaddr);
  1183. pci_release_regions(pdev);
  1184. pci_disable_device(pdev);
  1185. free_netdev(dev);
  1186. }
  1187. static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
  1188. {
  1189. void __iomem *ioaddr = tp->mmio_addr;
  1190. static int board_idx = -1;
  1191. u8 autoneg, duplex;
  1192. u16 speed;
  1193. board_idx++;
  1194. rtl8169_hw_phy_config(dev);
  1195. dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
  1196. RTL_W8(0x82, 0x01);
  1197. if (tp->mac_version < RTL_GIGA_MAC_VER_03) {
  1198. dprintk("Set PCI Latency=0x40\n");
  1199. pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
  1200. }
  1201. if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
  1202. dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
  1203. RTL_W8(0x82, 0x01);
  1204. dprintk("Set PHY Reg 0x0bh = 0x00h\n");
  1205. mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
  1206. }
  1207. rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
  1208. rtl8169_set_speed(dev, autoneg, speed, duplex);
  1209. if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
  1210. printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
  1211. }
  1212. static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1213. {
  1214. struct rtl8169_private *tp = netdev_priv(dev);
  1215. struct mii_ioctl_data *data = if_mii(ifr);
  1216. if (!netif_running(dev))
  1217. return -ENODEV;
  1218. switch (cmd) {
  1219. case SIOCGMIIPHY:
  1220. data->phy_id = 32; /* Internal PHY */
  1221. return 0;
  1222. case SIOCGMIIREG:
  1223. data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
  1224. return 0;
  1225. case SIOCSMIIREG:
  1226. if (!capable(CAP_NET_ADMIN))
  1227. return -EPERM;
  1228. mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
  1229. return 0;
  1230. }
  1231. return -EOPNOTSUPP;
  1232. }
  1233. static int __devinit
  1234. rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  1235. {
  1236. const unsigned int region = rtl_cfg_info[ent->driver_data].region;
  1237. struct rtl8169_private *tp;
  1238. struct net_device *dev;
  1239. void __iomem *ioaddr;
  1240. unsigned int i, pm_cap;
  1241. int rc;
  1242. if (netif_msg_drv(&debug)) {
  1243. printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
  1244. MODULENAME, RTL8169_VERSION);
  1245. }
  1246. dev = alloc_etherdev(sizeof (*tp));
  1247. if (!dev) {
  1248. if (netif_msg_drv(&debug))
  1249. dev_err(&pdev->dev, "unable to alloc new ethernet\n");
  1250. rc = -ENOMEM;
  1251. goto out;
  1252. }
  1253. SET_MODULE_OWNER(dev);
  1254. SET_NETDEV_DEV(dev, &pdev->dev);
  1255. tp = netdev_priv(dev);
  1256. tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
  1257. /* enable device (incl. PCI PM wakeup and hotplug setup) */
  1258. rc = pci_enable_device(pdev);
  1259. if (rc < 0) {
  1260. if (netif_msg_probe(tp))
  1261. dev_err(&pdev->dev, "enable failure\n");
  1262. goto err_out_free_dev_1;
  1263. }
  1264. rc = pci_set_mwi(pdev);
  1265. if (rc < 0)
  1266. goto err_out_disable_2;
  1267. /* save power state before pci_enable_device overwrites it */
  1268. pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
  1269. if (pm_cap) {
  1270. u16 pwr_command, acpi_idle_state;
  1271. pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
  1272. acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
  1273. } else {
  1274. if (netif_msg_probe(tp)) {
  1275. dev_err(&pdev->dev,
  1276. "PowerManagement capability not found.\n");
  1277. }
  1278. }
  1279. /* make sure PCI base addr 1 is MMIO */
  1280. if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
  1281. if (netif_msg_probe(tp)) {
  1282. dev_err(&pdev->dev,
  1283. "region #%d not an MMIO resource, aborting\n",
  1284. region);
  1285. }
  1286. rc = -ENODEV;
  1287. goto err_out_mwi_3;
  1288. }
  1289. /* check for weird/broken PCI region reporting */
  1290. if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
  1291. if (netif_msg_probe(tp)) {
  1292. dev_err(&pdev->dev,
  1293. "Invalid PCI region size(s), aborting\n");
  1294. }
  1295. rc = -ENODEV;
  1296. goto err_out_mwi_3;
  1297. }
  1298. rc = pci_request_regions(pdev, MODULENAME);
  1299. if (rc < 0) {
  1300. if (netif_msg_probe(tp))
  1301. dev_err(&pdev->dev, "could not request regions.\n");
  1302. goto err_out_mwi_3;
  1303. }
  1304. tp->cp_cmd = PCIMulRW | RxChkSum;
  1305. if ((sizeof(dma_addr_t) > 4) &&
  1306. !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
  1307. tp->cp_cmd |= PCIDAC;
  1308. dev->features |= NETIF_F_HIGHDMA;
  1309. } else {
  1310. rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  1311. if (rc < 0) {
  1312. if (netif_msg_probe(tp)) {
  1313. dev_err(&pdev->dev,
  1314. "DMA configuration failed.\n");
  1315. }
  1316. goto err_out_free_res_4;
  1317. }
  1318. }
  1319. pci_set_master(pdev);
  1320. /* ioremap MMIO region */
  1321. ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
  1322. if (!ioaddr) {
  1323. if (netif_msg_probe(tp))
  1324. dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
  1325. rc = -EIO;
  1326. goto err_out_free_res_4;
  1327. }
  1328. /* Unneeded ? Don't mess with Mrs. Murphy. */
  1329. rtl8169_irq_mask_and_ack(ioaddr);
  1330. /* Soft reset the chip. */
  1331. RTL_W8(ChipCmd, CmdReset);
  1332. /* Check that the chip has finished the reset. */
  1333. for (i = 100; i > 0; i--) {
  1334. if ((RTL_R8(ChipCmd) & CmdReset) == 0)
  1335. break;
  1336. msleep_interruptible(1);
  1337. }
  1338. /* Identify chip attached to board */
  1339. rtl8169_get_mac_version(tp, ioaddr);
  1340. rtl8169_get_phy_version(tp, ioaddr);
  1341. rtl8169_print_mac_version(tp);
  1342. rtl8169_print_phy_version(tp);
  1343. for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
  1344. if (tp->mac_version == rtl_chip_info[i].mac_version)
  1345. break;
  1346. }
  1347. if (i < 0) {
  1348. /* Unknown chip: assume array element #0, original RTL-8169 */
  1349. if (netif_msg_probe(tp)) {
  1350. dev_printk(KERN_DEBUG, &pdev->dev,
  1351. "unknown chip version, assuming %s\n",
  1352. rtl_chip_info[0].name);
  1353. }
  1354. i++;
  1355. }
  1356. tp->chipset = i;
  1357. RTL_W8(Cfg9346, Cfg9346_Unlock);
  1358. RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
  1359. RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
  1360. RTL_W8(Cfg9346, Cfg9346_Lock);
  1361. if (RTL_R8(PHYstatus) & TBI_Enable) {
  1362. tp->set_speed = rtl8169_set_speed_tbi;
  1363. tp->get_settings = rtl8169_gset_tbi;
  1364. tp->phy_reset_enable = rtl8169_tbi_reset_enable;
  1365. tp->phy_reset_pending = rtl8169_tbi_reset_pending;
  1366. tp->link_ok = rtl8169_tbi_link_ok;
  1367. tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
  1368. } else {
  1369. tp->set_speed = rtl8169_set_speed_xmii;
  1370. tp->get_settings = rtl8169_gset_xmii;
  1371. tp->phy_reset_enable = rtl8169_xmii_reset_enable;
  1372. tp->phy_reset_pending = rtl8169_xmii_reset_pending;
  1373. tp->link_ok = rtl8169_xmii_link_ok;
  1374. dev->do_ioctl = rtl8169_ioctl;
  1375. }
  1376. /* Get MAC address. FIXME: read EEPROM */
  1377. for (i = 0; i < MAC_ADDR_LEN; i++)
  1378. dev->dev_addr[i] = RTL_R8(MAC0 + i);
  1379. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  1380. dev->open = rtl8169_open;
  1381. dev->hard_start_xmit = rtl8169_start_xmit;
  1382. dev->get_stats = rtl8169_get_stats;
  1383. SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
  1384. dev->stop = rtl8169_close;
  1385. dev->tx_timeout = rtl8169_tx_timeout;
  1386. dev->set_multicast_list = rtl8169_set_rx_mode;
  1387. dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
  1388. dev->irq = pdev->irq;
  1389. dev->base_addr = (unsigned long) ioaddr;
  1390. dev->change_mtu = rtl8169_change_mtu;
  1391. #ifdef CONFIG_R8169_NAPI
  1392. dev->poll = rtl8169_poll;
  1393. dev->weight = R8169_NAPI_WEIGHT;
  1394. #endif
  1395. #ifdef CONFIG_R8169_VLAN
  1396. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  1397. dev->vlan_rx_register = rtl8169_vlan_rx_register;
  1398. dev->vlan_rx_kill_vid = rtl8169_vlan_rx_kill_vid;
  1399. #endif
  1400. #ifdef CONFIG_NET_POLL_CONTROLLER
  1401. dev->poll_controller = rtl8169_netpoll;
  1402. #endif
  1403. tp->intr_mask = 0xffff;
  1404. tp->pci_dev = pdev;
  1405. tp->mmio_addr = ioaddr;
  1406. tp->align = rtl_cfg_info[ent->driver_data].align;
  1407. spin_lock_init(&tp->lock);
  1408. rc = register_netdev(dev);
  1409. if (rc < 0)
  1410. goto err_out_unmap_5;
  1411. pci_set_drvdata(pdev, dev);
  1412. if (netif_msg_probe(tp)) {
  1413. printk(KERN_INFO "%s: %s at 0x%lx, "
  1414. "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
  1415. "IRQ %d\n",
  1416. dev->name,
  1417. rtl_chip_info[tp->chipset].name,
  1418. dev->base_addr,
  1419. dev->dev_addr[0], dev->dev_addr[1],
  1420. dev->dev_addr[2], dev->dev_addr[3],
  1421. dev->dev_addr[4], dev->dev_addr[5], dev->irq);
  1422. }
  1423. rtl8169_init_phy(dev, tp);
  1424. out:
  1425. return rc;
  1426. err_out_unmap_5:
  1427. iounmap(ioaddr);
  1428. err_out_free_res_4:
  1429. pci_release_regions(pdev);
  1430. err_out_mwi_3:
  1431. pci_clear_mwi(pdev);
  1432. err_out_disable_2:
  1433. pci_disable_device(pdev);
  1434. err_out_free_dev_1:
  1435. free_netdev(dev);
  1436. goto out;
  1437. }
  1438. static void __devexit
  1439. rtl8169_remove_one(struct pci_dev *pdev)
  1440. {
  1441. struct net_device *dev = pci_get_drvdata(pdev);
  1442. struct rtl8169_private *tp = netdev_priv(dev);
  1443. assert(dev != NULL);
  1444. assert(tp != NULL);
  1445. unregister_netdev(dev);
  1446. rtl8169_release_board(pdev, dev, tp->mmio_addr);
  1447. pci_set_drvdata(pdev, NULL);
  1448. }
  1449. static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
  1450. struct net_device *dev)
  1451. {
  1452. unsigned int mtu = dev->mtu;
  1453. tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
  1454. }
  1455. static int rtl8169_open(struct net_device *dev)
  1456. {
  1457. struct rtl8169_private *tp = netdev_priv(dev);
  1458. struct pci_dev *pdev = tp->pci_dev;
  1459. int retval;
  1460. rtl8169_set_rxbufsize(tp, dev);
  1461. retval =
  1462. request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED, dev->name, dev);
  1463. if (retval < 0)
  1464. goto out;
  1465. retval = -ENOMEM;
  1466. /*
  1467. * Rx and Tx desscriptors needs 256 bytes alignment.
  1468. * pci_alloc_consistent provides more.
  1469. */
  1470. tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
  1471. &tp->TxPhyAddr);
  1472. if (!tp->TxDescArray)
  1473. goto err_free_irq;
  1474. tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
  1475. &tp->RxPhyAddr);
  1476. if (!tp->RxDescArray)
  1477. goto err_free_tx;
  1478. retval = rtl8169_init_ring(dev);
  1479. if (retval < 0)
  1480. goto err_free_rx;
  1481. INIT_WORK(&tp->task, NULL, dev);
  1482. rtl8169_hw_start(dev);
  1483. rtl8169_request_timer(dev);
  1484. rtl8169_check_link_status(dev, tp, tp->mmio_addr);
  1485. out:
  1486. return retval;
  1487. err_free_rx:
  1488. pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
  1489. tp->RxPhyAddr);
  1490. err_free_tx:
  1491. pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
  1492. tp->TxPhyAddr);
  1493. err_free_irq:
  1494. free_irq(dev->irq, dev);
  1495. goto out;
  1496. }
  1497. static void rtl8169_hw_reset(void __iomem *ioaddr)
  1498. {
  1499. /* Disable interrupts */
  1500. rtl8169_irq_mask_and_ack(ioaddr);
  1501. /* Reset the chipset */
  1502. RTL_W8(ChipCmd, CmdReset);
  1503. /* PCI commit */
  1504. RTL_R8(ChipCmd);
  1505. }
  1506. static void
  1507. rtl8169_hw_start(struct net_device *dev)
  1508. {
  1509. struct rtl8169_private *tp = netdev_priv(dev);
  1510. void __iomem *ioaddr = tp->mmio_addr;
  1511. struct pci_dev *pdev = tp->pci_dev;
  1512. u32 i;
  1513. /* Soft reset the chip. */
  1514. RTL_W8(ChipCmd, CmdReset);
  1515. /* Check that the chip has finished the reset. */
  1516. for (i = 100; i > 0; i--) {
  1517. if ((RTL_R8(ChipCmd) & CmdReset) == 0)
  1518. break;
  1519. msleep_interruptible(1);
  1520. }
  1521. if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
  1522. pci_write_config_word(pdev, 0x68, 0x00);
  1523. pci_write_config_word(pdev, 0x69, 0x08);
  1524. }
  1525. /* Undocumented stuff. */
  1526. if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
  1527. u16 cmd;
  1528. /* Realtek's r1000_n.c driver uses '&& 0x01' here. Well... */
  1529. if ((RTL_R8(Config2) & 0x07) & 0x01)
  1530. RTL_W32(0x7c, 0x0007ffff);
  1531. RTL_W32(0x7c, 0x0007ff00);
  1532. pci_read_config_word(pdev, PCI_COMMAND, &cmd);
  1533. cmd = cmd & 0xef;
  1534. pci_write_config_word(pdev, PCI_COMMAND, cmd);
  1535. }
  1536. RTL_W8(Cfg9346, Cfg9346_Unlock);
  1537. RTL_W8(EarlyTxThres, EarlyTxThld);
  1538. /* Low hurts. Let's disable the filtering. */
  1539. RTL_W16(RxMaxSize, 16383);
  1540. /* Set Rx Config register */
  1541. i = rtl8169_rx_config |
  1542. (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
  1543. RTL_W32(RxConfig, i);
  1544. /* Set DMA burst size and Interframe Gap Time */
  1545. RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
  1546. (InterFrameGap << TxInterFrameGapShift));
  1547. tp->cp_cmd |= RTL_R16(CPlusCmd) | PCIMulRW;
  1548. if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
  1549. (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
  1550. dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
  1551. "Bit-3 and bit-14 MUST be 1\n");
  1552. tp->cp_cmd |= (1 << 14);
  1553. }
  1554. RTL_W16(CPlusCmd, tp->cp_cmd);
  1555. /*
  1556. * Undocumented corner. Supposedly:
  1557. * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
  1558. */
  1559. RTL_W16(IntrMitigate, 0x0000);
  1560. /*
  1561. * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
  1562. * register to be written before TxDescAddrLow to work.
  1563. * Switching from MMIO to I/O access fixes the issue as well.
  1564. */
  1565. RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
  1566. RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
  1567. RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
  1568. RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
  1569. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  1570. RTL_W8(Cfg9346, Cfg9346_Lock);
  1571. /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
  1572. RTL_R8(IntrMask);
  1573. RTL_W32(RxMissed, 0);
  1574. rtl8169_set_rx_mode(dev);
  1575. /* no early-rx interrupts */
  1576. RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
  1577. /* Enable all known interrupts by setting the interrupt mask. */
  1578. RTL_W16(IntrMask, rtl8169_intr_mask);
  1579. netif_start_queue(dev);
  1580. }
  1581. static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
  1582. {
  1583. struct rtl8169_private *tp = netdev_priv(dev);
  1584. int ret = 0;
  1585. if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
  1586. return -EINVAL;
  1587. dev->mtu = new_mtu;
  1588. if (!netif_running(dev))
  1589. goto out;
  1590. rtl8169_down(dev);
  1591. rtl8169_set_rxbufsize(tp, dev);
  1592. ret = rtl8169_init_ring(dev);
  1593. if (ret < 0)
  1594. goto out;
  1595. netif_poll_enable(dev);
  1596. rtl8169_hw_start(dev);
  1597. rtl8169_request_timer(dev);
  1598. out:
  1599. return ret;
  1600. }
  1601. static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
  1602. {
  1603. desc->addr = 0x0badbadbadbadbadull;
  1604. desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
  1605. }
  1606. static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
  1607. struct sk_buff **sk_buff, struct RxDesc *desc)
  1608. {
  1609. struct pci_dev *pdev = tp->pci_dev;
  1610. pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
  1611. PCI_DMA_FROMDEVICE);
  1612. dev_kfree_skb(*sk_buff);
  1613. *sk_buff = NULL;
  1614. rtl8169_make_unusable_by_asic(desc);
  1615. }
  1616. static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
  1617. {
  1618. u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
  1619. desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
  1620. }
  1621. static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
  1622. u32 rx_buf_sz)
  1623. {
  1624. desc->addr = cpu_to_le64(mapping);
  1625. wmb();
  1626. rtl8169_mark_to_asic(desc, rx_buf_sz);
  1627. }
  1628. static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
  1629. struct RxDesc *desc, int rx_buf_sz,
  1630. unsigned int align)
  1631. {
  1632. struct sk_buff *skb;
  1633. dma_addr_t mapping;
  1634. int ret = 0;
  1635. skb = dev_alloc_skb(rx_buf_sz + align);
  1636. if (!skb)
  1637. goto err_out;
  1638. skb_reserve(skb, align);
  1639. *sk_buff = skb;
  1640. mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
  1641. PCI_DMA_FROMDEVICE);
  1642. rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
  1643. out:
  1644. return ret;
  1645. err_out:
  1646. ret = -ENOMEM;
  1647. rtl8169_make_unusable_by_asic(desc);
  1648. goto out;
  1649. }
  1650. static void rtl8169_rx_clear(struct rtl8169_private *tp)
  1651. {
  1652. int i;
  1653. for (i = 0; i < NUM_RX_DESC; i++) {
  1654. if (tp->Rx_skbuff[i]) {
  1655. rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
  1656. tp->RxDescArray + i);
  1657. }
  1658. }
  1659. }
  1660. static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
  1661. u32 start, u32 end)
  1662. {
  1663. u32 cur;
  1664. for (cur = start; end - cur > 0; cur++) {
  1665. int ret, i = cur % NUM_RX_DESC;
  1666. if (tp->Rx_skbuff[i])
  1667. continue;
  1668. ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
  1669. tp->RxDescArray + i, tp->rx_buf_sz, tp->align);
  1670. if (ret < 0)
  1671. break;
  1672. }
  1673. return cur - start;
  1674. }
  1675. static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
  1676. {
  1677. desc->opts1 |= cpu_to_le32(RingEnd);
  1678. }
  1679. static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
  1680. {
  1681. tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
  1682. }
  1683. static int rtl8169_init_ring(struct net_device *dev)
  1684. {
  1685. struct rtl8169_private *tp = netdev_priv(dev);
  1686. rtl8169_init_ring_indexes(tp);
  1687. memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
  1688. memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
  1689. if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
  1690. goto err_out;
  1691. rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
  1692. return 0;
  1693. err_out:
  1694. rtl8169_rx_clear(tp);
  1695. return -ENOMEM;
  1696. }
  1697. static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
  1698. struct TxDesc *desc)
  1699. {
  1700. unsigned int len = tx_skb->len;
  1701. pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
  1702. desc->opts1 = 0x00;
  1703. desc->opts2 = 0x00;
  1704. desc->addr = 0x00;
  1705. tx_skb->len = 0;
  1706. }
  1707. static void rtl8169_tx_clear(struct rtl8169_private *tp)
  1708. {
  1709. unsigned int i;
  1710. for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
  1711. unsigned int entry = i % NUM_TX_DESC;
  1712. struct ring_info *tx_skb = tp->tx_skb + entry;
  1713. unsigned int len = tx_skb->len;
  1714. if (len) {
  1715. struct sk_buff *skb = tx_skb->skb;
  1716. rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
  1717. tp->TxDescArray + entry);
  1718. if (skb) {
  1719. dev_kfree_skb(skb);
  1720. tx_skb->skb = NULL;
  1721. }
  1722. tp->stats.tx_dropped++;
  1723. }
  1724. }
  1725. tp->cur_tx = tp->dirty_tx = 0;
  1726. }
  1727. static void rtl8169_schedule_work(struct net_device *dev, void (*task)(void *))
  1728. {
  1729. struct rtl8169_private *tp = netdev_priv(dev);
  1730. PREPARE_WORK(&tp->task, task, dev);
  1731. schedule_delayed_work(&tp->task, 4);
  1732. }
  1733. static void rtl8169_wait_for_quiescence(struct net_device *dev)
  1734. {
  1735. struct rtl8169_private *tp = netdev_priv(dev);
  1736. void __iomem *ioaddr = tp->mmio_addr;
  1737. synchronize_irq(dev->irq);
  1738. /* Wait for any pending NAPI task to complete */
  1739. netif_poll_disable(dev);
  1740. rtl8169_irq_mask_and_ack(ioaddr);
  1741. netif_poll_enable(dev);
  1742. }
  1743. static void rtl8169_reinit_task(void *_data)
  1744. {
  1745. struct net_device *dev = _data;
  1746. int ret;
  1747. if (netif_running(dev)) {
  1748. rtl8169_wait_for_quiescence(dev);
  1749. rtl8169_close(dev);
  1750. }
  1751. ret = rtl8169_open(dev);
  1752. if (unlikely(ret < 0)) {
  1753. if (net_ratelimit()) {
  1754. struct rtl8169_private *tp = netdev_priv(dev);
  1755. if (netif_msg_drv(tp)) {
  1756. printk(PFX KERN_ERR
  1757. "%s: reinit failure (status = %d)."
  1758. " Rescheduling.\n", dev->name, ret);
  1759. }
  1760. }
  1761. rtl8169_schedule_work(dev, rtl8169_reinit_task);
  1762. }
  1763. }
  1764. static void rtl8169_reset_task(void *_data)
  1765. {
  1766. struct net_device *dev = _data;
  1767. struct rtl8169_private *tp = netdev_priv(dev);
  1768. if (!netif_running(dev))
  1769. return;
  1770. rtl8169_wait_for_quiescence(dev);
  1771. rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
  1772. rtl8169_tx_clear(tp);
  1773. if (tp->dirty_rx == tp->cur_rx) {
  1774. rtl8169_init_ring_indexes(tp);
  1775. rtl8169_hw_start(dev);
  1776. netif_wake_queue(dev);
  1777. } else {
  1778. if (net_ratelimit()) {
  1779. struct rtl8169_private *tp = netdev_priv(dev);
  1780. if (netif_msg_intr(tp)) {
  1781. printk(PFX KERN_EMERG
  1782. "%s: Rx buffers shortage\n", dev->name);
  1783. }
  1784. }
  1785. rtl8169_schedule_work(dev, rtl8169_reset_task);
  1786. }
  1787. }
  1788. static void rtl8169_tx_timeout(struct net_device *dev)
  1789. {
  1790. struct rtl8169_private *tp = netdev_priv(dev);
  1791. rtl8169_hw_reset(tp->mmio_addr);
  1792. /* Let's wait a bit while any (async) irq lands on */
  1793. rtl8169_schedule_work(dev, rtl8169_reset_task);
  1794. }
  1795. static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
  1796. u32 opts1)
  1797. {
  1798. struct skb_shared_info *info = skb_shinfo(skb);
  1799. unsigned int cur_frag, entry;
  1800. struct TxDesc *txd;
  1801. entry = tp->cur_tx;
  1802. for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
  1803. skb_frag_t *frag = info->frags + cur_frag;
  1804. dma_addr_t mapping;
  1805. u32 status, len;
  1806. void *addr;
  1807. entry = (entry + 1) % NUM_TX_DESC;
  1808. txd = tp->TxDescArray + entry;
  1809. len = frag->size;
  1810. addr = ((void *) page_address(frag->page)) + frag->page_offset;
  1811. mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
  1812. /* anti gcc 2.95.3 bugware (sic) */
  1813. status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
  1814. txd->opts1 = cpu_to_le32(status);
  1815. txd->addr = cpu_to_le64(mapping);
  1816. tp->tx_skb[entry].len = len;
  1817. }
  1818. if (cur_frag) {
  1819. tp->tx_skb[entry].skb = skb;
  1820. txd->opts1 |= cpu_to_le32(LastFrag);
  1821. }
  1822. return cur_frag;
  1823. }
  1824. static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
  1825. {
  1826. if (dev->features & NETIF_F_TSO) {
  1827. u32 mss = skb_shinfo(skb)->gso_size;
  1828. if (mss)
  1829. return LargeSend | ((mss & MSSMask) << MSSShift);
  1830. }
  1831. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1832. const struct iphdr *ip = skb->nh.iph;
  1833. if (ip->protocol == IPPROTO_TCP)
  1834. return IPCS | TCPCS;
  1835. else if (ip->protocol == IPPROTO_UDP)
  1836. return IPCS | UDPCS;
  1837. WARN_ON(1); /* we need a WARN() */
  1838. }
  1839. return 0;
  1840. }
  1841. static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1842. {
  1843. struct rtl8169_private *tp = netdev_priv(dev);
  1844. unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
  1845. struct TxDesc *txd = tp->TxDescArray + entry;
  1846. void __iomem *ioaddr = tp->mmio_addr;
  1847. dma_addr_t mapping;
  1848. u32 status, len;
  1849. u32 opts1;
  1850. int ret = NETDEV_TX_OK;
  1851. if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
  1852. if (netif_msg_drv(tp)) {
  1853. printk(KERN_ERR
  1854. "%s: BUG! Tx Ring full when queue awake!\n",
  1855. dev->name);
  1856. }
  1857. goto err_stop;
  1858. }
  1859. if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
  1860. goto err_stop;
  1861. opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
  1862. frags = rtl8169_xmit_frags(tp, skb, opts1);
  1863. if (frags) {
  1864. len = skb_headlen(skb);
  1865. opts1 |= FirstFrag;
  1866. } else {
  1867. len = skb->len;
  1868. if (unlikely(len < ETH_ZLEN)) {
  1869. if (skb_padto(skb, ETH_ZLEN))
  1870. goto err_update_stats;
  1871. len = ETH_ZLEN;
  1872. }
  1873. opts1 |= FirstFrag | LastFrag;
  1874. tp->tx_skb[entry].skb = skb;
  1875. }
  1876. mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
  1877. tp->tx_skb[entry].len = len;
  1878. txd->addr = cpu_to_le64(mapping);
  1879. txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
  1880. wmb();
  1881. /* anti gcc 2.95.3 bugware (sic) */
  1882. status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
  1883. txd->opts1 = cpu_to_le32(status);
  1884. dev->trans_start = jiffies;
  1885. tp->cur_tx += frags + 1;
  1886. smp_wmb();
  1887. RTL_W8(TxPoll, 0x40); /* set polling bit */
  1888. if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
  1889. netif_stop_queue(dev);
  1890. smp_rmb();
  1891. if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
  1892. netif_wake_queue(dev);
  1893. }
  1894. out:
  1895. return ret;
  1896. err_stop:
  1897. netif_stop_queue(dev);
  1898. ret = NETDEV_TX_BUSY;
  1899. err_update_stats:
  1900. tp->stats.tx_dropped++;
  1901. goto out;
  1902. }
  1903. static void rtl8169_pcierr_interrupt(struct net_device *dev)
  1904. {
  1905. struct rtl8169_private *tp = netdev_priv(dev);
  1906. struct pci_dev *pdev = tp->pci_dev;
  1907. void __iomem *ioaddr = tp->mmio_addr;
  1908. u16 pci_status, pci_cmd;
  1909. pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
  1910. pci_read_config_word(pdev, PCI_STATUS, &pci_status);
  1911. if (netif_msg_intr(tp)) {
  1912. printk(KERN_ERR
  1913. "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
  1914. dev->name, pci_cmd, pci_status);
  1915. }
  1916. /*
  1917. * The recovery sequence below admits a very elaborated explanation:
  1918. * - it seems to work;
  1919. * - I did not see what else could be done.
  1920. *
  1921. * Feel free to adjust to your needs.
  1922. */
  1923. pci_write_config_word(pdev, PCI_COMMAND,
  1924. pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
  1925. pci_write_config_word(pdev, PCI_STATUS,
  1926. pci_status & (PCI_STATUS_DETECTED_PARITY |
  1927. PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
  1928. PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
  1929. /* The infamous DAC f*ckup only happens at boot time */
  1930. if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
  1931. if (netif_msg_intr(tp))
  1932. printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
  1933. tp->cp_cmd &= ~PCIDAC;
  1934. RTL_W16(CPlusCmd, tp->cp_cmd);
  1935. dev->features &= ~NETIF_F_HIGHDMA;
  1936. rtl8169_schedule_work(dev, rtl8169_reinit_task);
  1937. }
  1938. rtl8169_hw_reset(ioaddr);
  1939. }
  1940. static void
  1941. rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
  1942. void __iomem *ioaddr)
  1943. {
  1944. unsigned int dirty_tx, tx_left;
  1945. assert(dev != NULL);
  1946. assert(tp != NULL);
  1947. assert(ioaddr != NULL);
  1948. dirty_tx = tp->dirty_tx;
  1949. smp_rmb();
  1950. tx_left = tp->cur_tx - dirty_tx;
  1951. while (tx_left > 0) {
  1952. unsigned int entry = dirty_tx % NUM_TX_DESC;
  1953. struct ring_info *tx_skb = tp->tx_skb + entry;
  1954. u32 len = tx_skb->len;
  1955. u32 status;
  1956. rmb();
  1957. status = le32_to_cpu(tp->TxDescArray[entry].opts1);
  1958. if (status & DescOwn)
  1959. break;
  1960. tp->stats.tx_bytes += len;
  1961. tp->stats.tx_packets++;
  1962. rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
  1963. if (status & LastFrag) {
  1964. dev_kfree_skb_irq(tx_skb->skb);
  1965. tx_skb->skb = NULL;
  1966. }
  1967. dirty_tx++;
  1968. tx_left--;
  1969. }
  1970. if (tp->dirty_tx != dirty_tx) {
  1971. tp->dirty_tx = dirty_tx;
  1972. smp_wmb();
  1973. if (netif_queue_stopped(dev) &&
  1974. (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
  1975. netif_wake_queue(dev);
  1976. }
  1977. }
  1978. }
  1979. static inline int rtl8169_fragmented_frame(u32 status)
  1980. {
  1981. return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
  1982. }
  1983. static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
  1984. {
  1985. u32 opts1 = le32_to_cpu(desc->opts1);
  1986. u32 status = opts1 & RxProtoMask;
  1987. if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
  1988. ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
  1989. ((status == RxProtoIP) && !(opts1 & IPFail)))
  1990. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1991. else
  1992. skb->ip_summed = CHECKSUM_NONE;
  1993. }
  1994. static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
  1995. struct RxDesc *desc, int rx_buf_sz,
  1996. unsigned int align)
  1997. {
  1998. int ret = -1;
  1999. if (pkt_size < rx_copybreak) {
  2000. struct sk_buff *skb;
  2001. skb = dev_alloc_skb(pkt_size + align);
  2002. if (skb) {
  2003. skb_reserve(skb, align);
  2004. eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0);
  2005. *sk_buff = skb;
  2006. rtl8169_mark_to_asic(desc, rx_buf_sz);
  2007. ret = 0;
  2008. }
  2009. }
  2010. return ret;
  2011. }
  2012. static int
  2013. rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
  2014. void __iomem *ioaddr)
  2015. {
  2016. unsigned int cur_rx, rx_left;
  2017. unsigned int delta, count;
  2018. assert(dev != NULL);
  2019. assert(tp != NULL);
  2020. assert(ioaddr != NULL);
  2021. cur_rx = tp->cur_rx;
  2022. rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
  2023. rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
  2024. for (; rx_left > 0; rx_left--, cur_rx++) {
  2025. unsigned int entry = cur_rx % NUM_RX_DESC;
  2026. struct RxDesc *desc = tp->RxDescArray + entry;
  2027. u32 status;
  2028. rmb();
  2029. status = le32_to_cpu(desc->opts1);
  2030. if (status & DescOwn)
  2031. break;
  2032. if (unlikely(status & RxRES)) {
  2033. if (netif_msg_rx_err(tp)) {
  2034. printk(KERN_INFO
  2035. "%s: Rx ERROR. status = %08x\n",
  2036. dev->name, status);
  2037. }
  2038. tp->stats.rx_errors++;
  2039. if (status & (RxRWT | RxRUNT))
  2040. tp->stats.rx_length_errors++;
  2041. if (status & RxCRC)
  2042. tp->stats.rx_crc_errors++;
  2043. if (status & RxFOVF) {
  2044. rtl8169_schedule_work(dev, rtl8169_reset_task);
  2045. tp->stats.rx_fifo_errors++;
  2046. }
  2047. rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
  2048. } else {
  2049. struct sk_buff *skb = tp->Rx_skbuff[entry];
  2050. int pkt_size = (status & 0x00001FFF) - 4;
  2051. void (*pci_action)(struct pci_dev *, dma_addr_t,
  2052. size_t, int) = pci_dma_sync_single_for_device;
  2053. /*
  2054. * The driver does not support incoming fragmented
  2055. * frames. They are seen as a symptom of over-mtu
  2056. * sized frames.
  2057. */
  2058. if (unlikely(rtl8169_fragmented_frame(status))) {
  2059. tp->stats.rx_dropped++;
  2060. tp->stats.rx_length_errors++;
  2061. rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
  2062. continue;
  2063. }
  2064. rtl8169_rx_csum(skb, desc);
  2065. pci_dma_sync_single_for_cpu(tp->pci_dev,
  2066. le64_to_cpu(desc->addr), tp->rx_buf_sz,
  2067. PCI_DMA_FROMDEVICE);
  2068. if (rtl8169_try_rx_copy(&skb, pkt_size, desc,
  2069. tp->rx_buf_sz, tp->align)) {
  2070. pci_action = pci_unmap_single;
  2071. tp->Rx_skbuff[entry] = NULL;
  2072. }
  2073. pci_action(tp->pci_dev, le64_to_cpu(desc->addr),
  2074. tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
  2075. skb->dev = dev;
  2076. skb_put(skb, pkt_size);
  2077. skb->protocol = eth_type_trans(skb, dev);
  2078. if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
  2079. rtl8169_rx_skb(skb);
  2080. dev->last_rx = jiffies;
  2081. tp->stats.rx_bytes += pkt_size;
  2082. tp->stats.rx_packets++;
  2083. }
  2084. }
  2085. count = cur_rx - tp->cur_rx;
  2086. tp->cur_rx = cur_rx;
  2087. delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
  2088. if (!delta && count && netif_msg_intr(tp))
  2089. printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
  2090. tp->dirty_rx += delta;
  2091. /*
  2092. * FIXME: until there is periodic timer to try and refill the ring,
  2093. * a temporary shortage may definitely kill the Rx process.
  2094. * - disable the asic to try and avoid an overflow and kick it again
  2095. * after refill ?
  2096. * - how do others driver handle this condition (Uh oh...).
  2097. */
  2098. if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
  2099. printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
  2100. return count;
  2101. }
  2102. /* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
  2103. static irqreturn_t
  2104. rtl8169_interrupt(int irq, void *dev_instance)
  2105. {
  2106. struct net_device *dev = (struct net_device *) dev_instance;
  2107. struct rtl8169_private *tp = netdev_priv(dev);
  2108. int boguscnt = max_interrupt_work;
  2109. void __iomem *ioaddr = tp->mmio_addr;
  2110. int status;
  2111. int handled = 0;
  2112. do {
  2113. status = RTL_R16(IntrStatus);
  2114. /* hotplug/major error/no more work/shared irq */
  2115. if ((status == 0xFFFF) || !status)
  2116. break;
  2117. handled = 1;
  2118. if (unlikely(!netif_running(dev))) {
  2119. rtl8169_asic_down(ioaddr);
  2120. goto out;
  2121. }
  2122. status &= tp->intr_mask;
  2123. RTL_W16(IntrStatus,
  2124. (status & RxFIFOOver) ? (status | RxOverflow) : status);
  2125. if (!(status & rtl8169_intr_mask))
  2126. break;
  2127. if (unlikely(status & SYSErr)) {
  2128. rtl8169_pcierr_interrupt(dev);
  2129. break;
  2130. }
  2131. if (status & LinkChg)
  2132. rtl8169_check_link_status(dev, tp, ioaddr);
  2133. #ifdef CONFIG_R8169_NAPI
  2134. RTL_W16(IntrMask, rtl8169_intr_mask & ~rtl8169_napi_event);
  2135. tp->intr_mask = ~rtl8169_napi_event;
  2136. if (likely(netif_rx_schedule_prep(dev)))
  2137. __netif_rx_schedule(dev);
  2138. else if (netif_msg_intr(tp)) {
  2139. printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
  2140. dev->name, status);
  2141. }
  2142. break;
  2143. #else
  2144. /* Rx interrupt */
  2145. if (status & (RxOK | RxOverflow | RxFIFOOver)) {
  2146. rtl8169_rx_interrupt(dev, tp, ioaddr);
  2147. }
  2148. /* Tx interrupt */
  2149. if (status & (TxOK | TxErr))
  2150. rtl8169_tx_interrupt(dev, tp, ioaddr);
  2151. #endif
  2152. boguscnt--;
  2153. } while (boguscnt > 0);
  2154. if (boguscnt <= 0) {
  2155. if (netif_msg_intr(tp) && net_ratelimit() ) {
  2156. printk(KERN_WARNING
  2157. "%s: Too much work at interrupt!\n", dev->name);
  2158. }
  2159. /* Clear all interrupt sources. */
  2160. RTL_W16(IntrStatus, 0xffff);
  2161. }
  2162. out:
  2163. return IRQ_RETVAL(handled);
  2164. }
  2165. #ifdef CONFIG_R8169_NAPI
  2166. static int rtl8169_poll(struct net_device *dev, int *budget)
  2167. {
  2168. unsigned int work_done, work_to_do = min(*budget, dev->quota);
  2169. struct rtl8169_private *tp = netdev_priv(dev);
  2170. void __iomem *ioaddr = tp->mmio_addr;
  2171. work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
  2172. rtl8169_tx_interrupt(dev, tp, ioaddr);
  2173. *budget -= work_done;
  2174. dev->quota -= work_done;
  2175. if (work_done < work_to_do) {
  2176. netif_rx_complete(dev);
  2177. tp->intr_mask = 0xffff;
  2178. /*
  2179. * 20040426: the barrier is not strictly required but the
  2180. * behavior of the irq handler could be less predictable
  2181. * without it. Btw, the lack of flush for the posted pci
  2182. * write is safe - FR
  2183. */
  2184. smp_wmb();
  2185. RTL_W16(IntrMask, rtl8169_intr_mask);
  2186. }
  2187. return (work_done >= work_to_do);
  2188. }
  2189. #endif
  2190. static void rtl8169_down(struct net_device *dev)
  2191. {
  2192. struct rtl8169_private *tp = netdev_priv(dev);
  2193. void __iomem *ioaddr = tp->mmio_addr;
  2194. unsigned int poll_locked = 0;
  2195. unsigned int intrmask;
  2196. rtl8169_delete_timer(dev);
  2197. netif_stop_queue(dev);
  2198. flush_scheduled_work();
  2199. core_down:
  2200. spin_lock_irq(&tp->lock);
  2201. rtl8169_asic_down(ioaddr);
  2202. /* Update the error counts. */
  2203. tp->stats.rx_missed_errors += RTL_R32(RxMissed);
  2204. RTL_W32(RxMissed, 0);
  2205. spin_unlock_irq(&tp->lock);
  2206. synchronize_irq(dev->irq);
  2207. if (!poll_locked) {
  2208. netif_poll_disable(dev);
  2209. poll_locked++;
  2210. }
  2211. /* Give a racing hard_start_xmit a few cycles to complete. */
  2212. synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
  2213. /*
  2214. * And now for the 50k$ question: are IRQ disabled or not ?
  2215. *
  2216. * Two paths lead here:
  2217. * 1) dev->close
  2218. * -> netif_running() is available to sync the current code and the
  2219. * IRQ handler. See rtl8169_interrupt for details.
  2220. * 2) dev->change_mtu
  2221. * -> rtl8169_poll can not be issued again and re-enable the
  2222. * interruptions. Let's simply issue the IRQ down sequence again.
  2223. *
  2224. * No loop if hotpluged or major error (0xffff).
  2225. */
  2226. intrmask = RTL_R16(IntrMask);
  2227. if (intrmask && (intrmask != 0xffff))
  2228. goto core_down;
  2229. rtl8169_tx_clear(tp);
  2230. rtl8169_rx_clear(tp);
  2231. }
  2232. static int rtl8169_close(struct net_device *dev)
  2233. {
  2234. struct rtl8169_private *tp = netdev_priv(dev);
  2235. struct pci_dev *pdev = tp->pci_dev;
  2236. rtl8169_down(dev);
  2237. free_irq(dev->irq, dev);
  2238. netif_poll_enable(dev);
  2239. pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
  2240. tp->RxPhyAddr);
  2241. pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
  2242. tp->TxPhyAddr);
  2243. tp->TxDescArray = NULL;
  2244. tp->RxDescArray = NULL;
  2245. return 0;
  2246. }
  2247. static void
  2248. rtl8169_set_rx_mode(struct net_device *dev)
  2249. {
  2250. struct rtl8169_private *tp = netdev_priv(dev);
  2251. void __iomem *ioaddr = tp->mmio_addr;
  2252. unsigned long flags;
  2253. u32 mc_filter[2]; /* Multicast hash filter */
  2254. int i, rx_mode;
  2255. u32 tmp = 0;
  2256. if (dev->flags & IFF_PROMISC) {
  2257. /* Unconditionally log net taps. */
  2258. if (netif_msg_link(tp)) {
  2259. printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
  2260. dev->name);
  2261. }
  2262. rx_mode =
  2263. AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
  2264. AcceptAllPhys;
  2265. mc_filter[1] = mc_filter[0] = 0xffffffff;
  2266. } else if ((dev->mc_count > multicast_filter_limit)
  2267. || (dev->flags & IFF_ALLMULTI)) {
  2268. /* Too many to filter perfectly -- accept all multicasts. */
  2269. rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
  2270. mc_filter[1] = mc_filter[0] = 0xffffffff;
  2271. } else {
  2272. struct dev_mc_list *mclist;
  2273. rx_mode = AcceptBroadcast | AcceptMyPhys;
  2274. mc_filter[1] = mc_filter[0] = 0;
  2275. for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
  2276. i++, mclist = mclist->next) {
  2277. int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
  2278. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  2279. rx_mode |= AcceptMulticast;
  2280. }
  2281. }
  2282. spin_lock_irqsave(&tp->lock, flags);
  2283. tmp = rtl8169_rx_config | rx_mode |
  2284. (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
  2285. if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
  2286. (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
  2287. (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
  2288. (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
  2289. (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
  2290. mc_filter[0] = 0xffffffff;
  2291. mc_filter[1] = 0xffffffff;
  2292. }
  2293. RTL_W32(RxConfig, tmp);
  2294. RTL_W32(MAR0 + 0, mc_filter[0]);
  2295. RTL_W32(MAR0 + 4, mc_filter[1]);
  2296. spin_unlock_irqrestore(&tp->lock, flags);
  2297. }
  2298. /**
  2299. * rtl8169_get_stats - Get rtl8169 read/write statistics
  2300. * @dev: The Ethernet Device to get statistics for
  2301. *
  2302. * Get TX/RX statistics for rtl8169
  2303. */
  2304. static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
  2305. {
  2306. struct rtl8169_private *tp = netdev_priv(dev);
  2307. void __iomem *ioaddr = tp->mmio_addr;
  2308. unsigned long flags;
  2309. if (netif_running(dev)) {
  2310. spin_lock_irqsave(&tp->lock, flags);
  2311. tp->stats.rx_missed_errors += RTL_R32(RxMissed);
  2312. RTL_W32(RxMissed, 0);
  2313. spin_unlock_irqrestore(&tp->lock, flags);
  2314. }
  2315. return &tp->stats;
  2316. }
  2317. #ifdef CONFIG_PM
  2318. static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
  2319. {
  2320. struct net_device *dev = pci_get_drvdata(pdev);
  2321. struct rtl8169_private *tp = netdev_priv(dev);
  2322. void __iomem *ioaddr = tp->mmio_addr;
  2323. if (!netif_running(dev))
  2324. goto out;
  2325. netif_device_detach(dev);
  2326. netif_stop_queue(dev);
  2327. spin_lock_irq(&tp->lock);
  2328. rtl8169_asic_down(ioaddr);
  2329. tp->stats.rx_missed_errors += RTL_R32(RxMissed);
  2330. RTL_W32(RxMissed, 0);
  2331. spin_unlock_irq(&tp->lock);
  2332. pci_save_state(pdev);
  2333. pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
  2334. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  2335. out:
  2336. return 0;
  2337. }
  2338. static int rtl8169_resume(struct pci_dev *pdev)
  2339. {
  2340. struct net_device *dev = pci_get_drvdata(pdev);
  2341. if (!netif_running(dev))
  2342. goto out;
  2343. netif_device_attach(dev);
  2344. pci_set_power_state(pdev, PCI_D0);
  2345. pci_restore_state(pdev);
  2346. pci_enable_wake(pdev, PCI_D0, 0);
  2347. rtl8169_schedule_work(dev, rtl8169_reset_task);
  2348. out:
  2349. return 0;
  2350. }
  2351. #endif /* CONFIG_PM */
  2352. static struct pci_driver rtl8169_pci_driver = {
  2353. .name = MODULENAME,
  2354. .id_table = rtl8169_pci_tbl,
  2355. .probe = rtl8169_init_one,
  2356. .remove = __devexit_p(rtl8169_remove_one),
  2357. #ifdef CONFIG_PM
  2358. .suspend = rtl8169_suspend,
  2359. .resume = rtl8169_resume,
  2360. #endif
  2361. };
  2362. static int __init
  2363. rtl8169_init_module(void)
  2364. {
  2365. return pci_register_driver(&rtl8169_pci_driver);
  2366. }
  2367. static void __exit
  2368. rtl8169_cleanup_module(void)
  2369. {
  2370. pci_unregister_driver(&rtl8169_pci_driver);
  2371. }
  2372. module_init(rtl8169_init_module);
  2373. module_exit(rtl8169_cleanup_module);