cputable.c 34 KB

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  1. /*
  2. * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
  3. *
  4. * Modifications for ppc64:
  5. * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/string.h>
  13. #include <linux/sched.h>
  14. #include <linux/threads.h>
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <asm/oprofile_impl.h>
  18. #include <asm/cputable.h>
  19. #include <asm/prom.h> /* for PTRRELOC on ARCH=ppc */
  20. struct cpu_spec* cur_cpu_spec = NULL;
  21. EXPORT_SYMBOL(cur_cpu_spec);
  22. /* NOTE:
  23. * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  24. * the responsibility of the appropriate CPU save/restore functions to
  25. * eventually copy these settings over. Those save/restore aren't yet
  26. * part of the cputable though. That has to be fixed for both ppc32
  27. * and ppc64
  28. */
  29. #ifdef CONFIG_PPC32
  30. extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
  31. extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
  32. extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
  33. extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
  34. extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
  35. extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
  36. extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
  37. extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
  38. #endif /* CONFIG_PPC32 */
  39. #ifdef CONFIG_PPC64
  40. extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  41. extern void __restore_cpu_ppc970(void);
  42. #endif /* CONFIG_PPC64 */
  43. /* This table only contains "desktop" CPUs, it need to be filled with embedded
  44. * ones as well...
  45. */
  46. #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  47. PPC_FEATURE_HAS_MMU)
  48. #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
  49. #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4)
  50. #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5 |\
  51. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  52. #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\
  53. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  54. #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\
  55. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  56. PPC_FEATURE_TRUE_LE)
  57. #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
  58. PPC_FEATURE_TRUE_LE | \
  59. PPC_FEATURE_HAS_ALTIVEC_COMP)
  60. #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
  61. PPC_FEATURE_BOOKE)
  62. /* We only set the spe features if the kernel was compiled with
  63. * spe support
  64. */
  65. #ifdef CONFIG_SPE
  66. #define PPC_FEATURE_SPE_COMP PPC_FEATURE_HAS_SPE
  67. #else
  68. #define PPC_FEATURE_SPE_COMP 0
  69. #endif
  70. static struct cpu_spec cpu_specs[] = {
  71. #ifdef CONFIG_PPC64
  72. { /* Power3 */
  73. .pvr_mask = 0xffff0000,
  74. .pvr_value = 0x00400000,
  75. .cpu_name = "POWER3 (630)",
  76. .cpu_features = CPU_FTRS_POWER3,
  77. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  78. .icache_bsize = 128,
  79. .dcache_bsize = 128,
  80. .num_pmcs = 8,
  81. .oprofile_cpu_type = "ppc64/power3",
  82. .oprofile_type = PPC_OPROFILE_RS64,
  83. .platform = "power3",
  84. },
  85. { /* Power3+ */
  86. .pvr_mask = 0xffff0000,
  87. .pvr_value = 0x00410000,
  88. .cpu_name = "POWER3 (630+)",
  89. .cpu_features = CPU_FTRS_POWER3,
  90. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  91. .icache_bsize = 128,
  92. .dcache_bsize = 128,
  93. .num_pmcs = 8,
  94. .oprofile_cpu_type = "ppc64/power3",
  95. .oprofile_type = PPC_OPROFILE_RS64,
  96. .platform = "power3",
  97. },
  98. { /* Northstar */
  99. .pvr_mask = 0xffff0000,
  100. .pvr_value = 0x00330000,
  101. .cpu_name = "RS64-II (northstar)",
  102. .cpu_features = CPU_FTRS_RS64,
  103. .cpu_user_features = COMMON_USER_PPC64,
  104. .icache_bsize = 128,
  105. .dcache_bsize = 128,
  106. .num_pmcs = 8,
  107. .oprofile_cpu_type = "ppc64/rs64",
  108. .oprofile_type = PPC_OPROFILE_RS64,
  109. .platform = "rs64",
  110. },
  111. { /* Pulsar */
  112. .pvr_mask = 0xffff0000,
  113. .pvr_value = 0x00340000,
  114. .cpu_name = "RS64-III (pulsar)",
  115. .cpu_features = CPU_FTRS_RS64,
  116. .cpu_user_features = COMMON_USER_PPC64,
  117. .icache_bsize = 128,
  118. .dcache_bsize = 128,
  119. .num_pmcs = 8,
  120. .oprofile_cpu_type = "ppc64/rs64",
  121. .oprofile_type = PPC_OPROFILE_RS64,
  122. .platform = "rs64",
  123. },
  124. { /* I-star */
  125. .pvr_mask = 0xffff0000,
  126. .pvr_value = 0x00360000,
  127. .cpu_name = "RS64-III (icestar)",
  128. .cpu_features = CPU_FTRS_RS64,
  129. .cpu_user_features = COMMON_USER_PPC64,
  130. .icache_bsize = 128,
  131. .dcache_bsize = 128,
  132. .num_pmcs = 8,
  133. .oprofile_cpu_type = "ppc64/rs64",
  134. .oprofile_type = PPC_OPROFILE_RS64,
  135. .platform = "rs64",
  136. },
  137. { /* S-star */
  138. .pvr_mask = 0xffff0000,
  139. .pvr_value = 0x00370000,
  140. .cpu_name = "RS64-IV (sstar)",
  141. .cpu_features = CPU_FTRS_RS64,
  142. .cpu_user_features = COMMON_USER_PPC64,
  143. .icache_bsize = 128,
  144. .dcache_bsize = 128,
  145. .num_pmcs = 8,
  146. .oprofile_cpu_type = "ppc64/rs64",
  147. .oprofile_type = PPC_OPROFILE_RS64,
  148. .platform = "rs64",
  149. },
  150. { /* Power4 */
  151. .pvr_mask = 0xffff0000,
  152. .pvr_value = 0x00350000,
  153. .cpu_name = "POWER4 (gp)",
  154. .cpu_features = CPU_FTRS_POWER4,
  155. .cpu_user_features = COMMON_USER_POWER4,
  156. .icache_bsize = 128,
  157. .dcache_bsize = 128,
  158. .num_pmcs = 8,
  159. .oprofile_cpu_type = "ppc64/power4",
  160. .oprofile_type = PPC_OPROFILE_POWER4,
  161. .platform = "power4",
  162. },
  163. { /* Power4+ */
  164. .pvr_mask = 0xffff0000,
  165. .pvr_value = 0x00380000,
  166. .cpu_name = "POWER4+ (gq)",
  167. .cpu_features = CPU_FTRS_POWER4,
  168. .cpu_user_features = COMMON_USER_POWER4,
  169. .icache_bsize = 128,
  170. .dcache_bsize = 128,
  171. .num_pmcs = 8,
  172. .oprofile_cpu_type = "ppc64/power4",
  173. .oprofile_type = PPC_OPROFILE_POWER4,
  174. .platform = "power4",
  175. },
  176. { /* PPC970 */
  177. .pvr_mask = 0xffff0000,
  178. .pvr_value = 0x00390000,
  179. .cpu_name = "PPC970",
  180. .cpu_features = CPU_FTRS_PPC970,
  181. .cpu_user_features = COMMON_USER_POWER4 |
  182. PPC_FEATURE_HAS_ALTIVEC_COMP,
  183. .icache_bsize = 128,
  184. .dcache_bsize = 128,
  185. .num_pmcs = 8,
  186. .cpu_setup = __setup_cpu_ppc970,
  187. .cpu_restore = __restore_cpu_ppc970,
  188. .oprofile_cpu_type = "ppc64/970",
  189. .oprofile_type = PPC_OPROFILE_POWER4,
  190. .platform = "ppc970",
  191. },
  192. { /* PPC970FX */
  193. .pvr_mask = 0xffff0000,
  194. .pvr_value = 0x003c0000,
  195. .cpu_name = "PPC970FX",
  196. .cpu_features = CPU_FTRS_PPC970,
  197. .cpu_user_features = COMMON_USER_POWER4 |
  198. PPC_FEATURE_HAS_ALTIVEC_COMP,
  199. .icache_bsize = 128,
  200. .dcache_bsize = 128,
  201. .num_pmcs = 8,
  202. .cpu_setup = __setup_cpu_ppc970,
  203. .cpu_restore = __restore_cpu_ppc970,
  204. .oprofile_cpu_type = "ppc64/970",
  205. .oprofile_type = PPC_OPROFILE_POWER4,
  206. .platform = "ppc970",
  207. },
  208. { /* PPC970MP */
  209. .pvr_mask = 0xffff0000,
  210. .pvr_value = 0x00440000,
  211. .cpu_name = "PPC970MP",
  212. .cpu_features = CPU_FTRS_PPC970,
  213. .cpu_user_features = COMMON_USER_POWER4 |
  214. PPC_FEATURE_HAS_ALTIVEC_COMP,
  215. .icache_bsize = 128,
  216. .dcache_bsize = 128,
  217. .num_pmcs = 8,
  218. .cpu_setup = __setup_cpu_ppc970,
  219. .cpu_restore = __restore_cpu_ppc970,
  220. .oprofile_cpu_type = "ppc64/970",
  221. .oprofile_type = PPC_OPROFILE_POWER4,
  222. .platform = "ppc970",
  223. },
  224. { /* PPC970GX */
  225. .pvr_mask = 0xffff0000,
  226. .pvr_value = 0x00450000,
  227. .cpu_name = "PPC970GX",
  228. .cpu_features = CPU_FTRS_PPC970,
  229. .cpu_user_features = COMMON_USER_POWER4 |
  230. PPC_FEATURE_HAS_ALTIVEC_COMP,
  231. .icache_bsize = 128,
  232. .dcache_bsize = 128,
  233. .num_pmcs = 8,
  234. .cpu_setup = __setup_cpu_ppc970,
  235. .oprofile_cpu_type = "ppc64/970",
  236. .oprofile_type = PPC_OPROFILE_POWER4,
  237. .platform = "ppc970",
  238. },
  239. { /* Power5 GR */
  240. .pvr_mask = 0xffff0000,
  241. .pvr_value = 0x003a0000,
  242. .cpu_name = "POWER5 (gr)",
  243. .cpu_features = CPU_FTRS_POWER5,
  244. .cpu_user_features = COMMON_USER_POWER5,
  245. .icache_bsize = 128,
  246. .dcache_bsize = 128,
  247. .num_pmcs = 6,
  248. .oprofile_cpu_type = "ppc64/power5",
  249. .oprofile_type = PPC_OPROFILE_POWER4,
  250. /* SIHV / SIPR bits are implemented on POWER4+ (GQ)
  251. * and above but only works on POWER5 and above
  252. */
  253. .oprofile_mmcra_sihv = MMCRA_SIHV,
  254. .oprofile_mmcra_sipr = MMCRA_SIPR,
  255. .platform = "power5",
  256. },
  257. { /* Power5 GS */
  258. .pvr_mask = 0xffff0000,
  259. .pvr_value = 0x003b0000,
  260. .cpu_name = "POWER5+ (gs)",
  261. .cpu_features = CPU_FTRS_POWER5,
  262. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  263. .icache_bsize = 128,
  264. .dcache_bsize = 128,
  265. .num_pmcs = 6,
  266. .oprofile_cpu_type = "ppc64/power5+",
  267. .oprofile_type = PPC_OPROFILE_POWER4,
  268. .oprofile_mmcra_sihv = MMCRA_SIHV,
  269. .oprofile_mmcra_sipr = MMCRA_SIPR,
  270. .platform = "power5+",
  271. },
  272. { /* Power6 */
  273. .pvr_mask = 0xffff0000,
  274. .pvr_value = 0x003e0000,
  275. .cpu_name = "POWER6",
  276. .cpu_features = CPU_FTRS_POWER6,
  277. .cpu_user_features = COMMON_USER_POWER6,
  278. .icache_bsize = 128,
  279. .dcache_bsize = 128,
  280. .num_pmcs = 6,
  281. .oprofile_cpu_type = "ppc64/power6",
  282. .oprofile_type = PPC_OPROFILE_POWER4,
  283. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  284. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  285. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  286. POWER6_MMCRA_OTHER,
  287. .platform = "power6",
  288. },
  289. { /* Cell Broadband Engine */
  290. .pvr_mask = 0xffff0000,
  291. .pvr_value = 0x00700000,
  292. .cpu_name = "Cell Broadband Engine",
  293. .cpu_features = CPU_FTRS_CELL,
  294. .cpu_user_features = COMMON_USER_PPC64 |
  295. PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
  296. PPC_FEATURE_SMT,
  297. .icache_bsize = 128,
  298. .dcache_bsize = 128,
  299. .platform = "ppc-cell-be",
  300. },
  301. { /* PA Semi PA6T */
  302. .pvr_mask = 0x7fff0000,
  303. .pvr_value = 0x00900000,
  304. .cpu_name = "PA6T",
  305. .cpu_features = CPU_FTRS_PA6T,
  306. .cpu_user_features = COMMON_USER_PA6T,
  307. .icache_bsize = 64,
  308. .dcache_bsize = 64,
  309. .num_pmcs = 6,
  310. .platform = "pa6t",
  311. },
  312. { /* default match */
  313. .pvr_mask = 0x00000000,
  314. .pvr_value = 0x00000000,
  315. .cpu_name = "POWER4 (compatible)",
  316. .cpu_features = CPU_FTRS_COMPATIBLE,
  317. .cpu_user_features = COMMON_USER_PPC64,
  318. .icache_bsize = 128,
  319. .dcache_bsize = 128,
  320. .num_pmcs = 6,
  321. .platform = "power4",
  322. }
  323. #endif /* CONFIG_PPC64 */
  324. #ifdef CONFIG_PPC32
  325. #if CLASSIC_PPC
  326. { /* 601 */
  327. .pvr_mask = 0xffff0000,
  328. .pvr_value = 0x00010000,
  329. .cpu_name = "601",
  330. .cpu_features = CPU_FTRS_PPC601,
  331. .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
  332. PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
  333. .icache_bsize = 32,
  334. .dcache_bsize = 32,
  335. .platform = "ppc601",
  336. },
  337. { /* 603 */
  338. .pvr_mask = 0xffff0000,
  339. .pvr_value = 0x00030000,
  340. .cpu_name = "603",
  341. .cpu_features = CPU_FTRS_603,
  342. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  343. .icache_bsize = 32,
  344. .dcache_bsize = 32,
  345. .cpu_setup = __setup_cpu_603,
  346. .platform = "ppc603",
  347. },
  348. { /* 603e */
  349. .pvr_mask = 0xffff0000,
  350. .pvr_value = 0x00060000,
  351. .cpu_name = "603e",
  352. .cpu_features = CPU_FTRS_603,
  353. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  354. .icache_bsize = 32,
  355. .dcache_bsize = 32,
  356. .cpu_setup = __setup_cpu_603,
  357. .platform = "ppc603",
  358. },
  359. { /* 603ev */
  360. .pvr_mask = 0xffff0000,
  361. .pvr_value = 0x00070000,
  362. .cpu_name = "603ev",
  363. .cpu_features = CPU_FTRS_603,
  364. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  365. .icache_bsize = 32,
  366. .dcache_bsize = 32,
  367. .cpu_setup = __setup_cpu_603,
  368. .platform = "ppc603",
  369. },
  370. { /* 604 */
  371. .pvr_mask = 0xffff0000,
  372. .pvr_value = 0x00040000,
  373. .cpu_name = "604",
  374. .cpu_features = CPU_FTRS_604,
  375. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  376. .icache_bsize = 32,
  377. .dcache_bsize = 32,
  378. .num_pmcs = 2,
  379. .cpu_setup = __setup_cpu_604,
  380. .platform = "ppc604",
  381. },
  382. { /* 604e */
  383. .pvr_mask = 0xfffff000,
  384. .pvr_value = 0x00090000,
  385. .cpu_name = "604e",
  386. .cpu_features = CPU_FTRS_604,
  387. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  388. .icache_bsize = 32,
  389. .dcache_bsize = 32,
  390. .num_pmcs = 4,
  391. .cpu_setup = __setup_cpu_604,
  392. .platform = "ppc604",
  393. },
  394. { /* 604r */
  395. .pvr_mask = 0xffff0000,
  396. .pvr_value = 0x00090000,
  397. .cpu_name = "604r",
  398. .cpu_features = CPU_FTRS_604,
  399. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  400. .icache_bsize = 32,
  401. .dcache_bsize = 32,
  402. .num_pmcs = 4,
  403. .cpu_setup = __setup_cpu_604,
  404. .platform = "ppc604",
  405. },
  406. { /* 604ev */
  407. .pvr_mask = 0xffff0000,
  408. .pvr_value = 0x000a0000,
  409. .cpu_name = "604ev",
  410. .cpu_features = CPU_FTRS_604,
  411. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  412. .icache_bsize = 32,
  413. .dcache_bsize = 32,
  414. .num_pmcs = 4,
  415. .cpu_setup = __setup_cpu_604,
  416. .platform = "ppc604",
  417. },
  418. { /* 740/750 (0x4202, don't support TAU ?) */
  419. .pvr_mask = 0xffffffff,
  420. .pvr_value = 0x00084202,
  421. .cpu_name = "740/750",
  422. .cpu_features = CPU_FTRS_740_NOTAU,
  423. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  424. .icache_bsize = 32,
  425. .dcache_bsize = 32,
  426. .num_pmcs = 4,
  427. .cpu_setup = __setup_cpu_750,
  428. .platform = "ppc750",
  429. },
  430. { /* 750CX (80100 and 8010x?) */
  431. .pvr_mask = 0xfffffff0,
  432. .pvr_value = 0x00080100,
  433. .cpu_name = "750CX",
  434. .cpu_features = CPU_FTRS_750,
  435. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  436. .icache_bsize = 32,
  437. .dcache_bsize = 32,
  438. .num_pmcs = 4,
  439. .cpu_setup = __setup_cpu_750cx,
  440. .platform = "ppc750",
  441. },
  442. { /* 750CX (82201 and 82202) */
  443. .pvr_mask = 0xfffffff0,
  444. .pvr_value = 0x00082200,
  445. .cpu_name = "750CX",
  446. .cpu_features = CPU_FTRS_750,
  447. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  448. .icache_bsize = 32,
  449. .dcache_bsize = 32,
  450. .num_pmcs = 4,
  451. .cpu_setup = __setup_cpu_750cx,
  452. .platform = "ppc750",
  453. },
  454. { /* 750CXe (82214) */
  455. .pvr_mask = 0xfffffff0,
  456. .pvr_value = 0x00082210,
  457. .cpu_name = "750CXe",
  458. .cpu_features = CPU_FTRS_750,
  459. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  460. .icache_bsize = 32,
  461. .dcache_bsize = 32,
  462. .num_pmcs = 4,
  463. .cpu_setup = __setup_cpu_750cx,
  464. .platform = "ppc750",
  465. },
  466. { /* 750CXe "Gekko" (83214) */
  467. .pvr_mask = 0xffffffff,
  468. .pvr_value = 0x00083214,
  469. .cpu_name = "750CXe",
  470. .cpu_features = CPU_FTRS_750,
  471. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  472. .icache_bsize = 32,
  473. .dcache_bsize = 32,
  474. .num_pmcs = 4,
  475. .cpu_setup = __setup_cpu_750cx,
  476. .platform = "ppc750",
  477. },
  478. { /* 745/755 */
  479. .pvr_mask = 0xfffff000,
  480. .pvr_value = 0x00083000,
  481. .cpu_name = "745/755",
  482. .cpu_features = CPU_FTRS_750,
  483. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  484. .icache_bsize = 32,
  485. .dcache_bsize = 32,
  486. .num_pmcs = 4,
  487. .cpu_setup = __setup_cpu_750,
  488. .platform = "ppc750",
  489. },
  490. { /* 750FX rev 1.x */
  491. .pvr_mask = 0xffffff00,
  492. .pvr_value = 0x70000100,
  493. .cpu_name = "750FX",
  494. .cpu_features = CPU_FTRS_750FX1,
  495. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  496. .icache_bsize = 32,
  497. .dcache_bsize = 32,
  498. .num_pmcs = 4,
  499. .cpu_setup = __setup_cpu_750,
  500. .platform = "ppc750",
  501. },
  502. { /* 750FX rev 2.0 must disable HID0[DPM] */
  503. .pvr_mask = 0xffffffff,
  504. .pvr_value = 0x70000200,
  505. .cpu_name = "750FX",
  506. .cpu_features = CPU_FTRS_750FX2,
  507. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  508. .icache_bsize = 32,
  509. .dcache_bsize = 32,
  510. .num_pmcs = 4,
  511. .cpu_setup = __setup_cpu_750,
  512. .platform = "ppc750",
  513. },
  514. { /* 750FX (All revs except 2.0) */
  515. .pvr_mask = 0xffff0000,
  516. .pvr_value = 0x70000000,
  517. .cpu_name = "750FX",
  518. .cpu_features = CPU_FTRS_750FX,
  519. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  520. .icache_bsize = 32,
  521. .dcache_bsize = 32,
  522. .num_pmcs = 4,
  523. .cpu_setup = __setup_cpu_750fx,
  524. .platform = "ppc750",
  525. },
  526. { /* 750GX */
  527. .pvr_mask = 0xffff0000,
  528. .pvr_value = 0x70020000,
  529. .cpu_name = "750GX",
  530. .cpu_features = CPU_FTRS_750GX,
  531. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  532. .icache_bsize = 32,
  533. .dcache_bsize = 32,
  534. .num_pmcs = 4,
  535. .cpu_setup = __setup_cpu_750fx,
  536. .platform = "ppc750",
  537. },
  538. { /* 740/750 (L2CR bit need fixup for 740) */
  539. .pvr_mask = 0xffff0000,
  540. .pvr_value = 0x00080000,
  541. .cpu_name = "740/750",
  542. .cpu_features = CPU_FTRS_740,
  543. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  544. .icache_bsize = 32,
  545. .dcache_bsize = 32,
  546. .num_pmcs = 4,
  547. .cpu_setup = __setup_cpu_750,
  548. .platform = "ppc750",
  549. },
  550. { /* 7400 rev 1.1 ? (no TAU) */
  551. .pvr_mask = 0xffffffff,
  552. .pvr_value = 0x000c1101,
  553. .cpu_name = "7400 (1.1)",
  554. .cpu_features = CPU_FTRS_7400_NOTAU,
  555. .cpu_user_features = COMMON_USER |
  556. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  557. .icache_bsize = 32,
  558. .dcache_bsize = 32,
  559. .num_pmcs = 4,
  560. .cpu_setup = __setup_cpu_7400,
  561. .platform = "ppc7400",
  562. },
  563. { /* 7400 */
  564. .pvr_mask = 0xffff0000,
  565. .pvr_value = 0x000c0000,
  566. .cpu_name = "7400",
  567. .cpu_features = CPU_FTRS_7400,
  568. .cpu_user_features = COMMON_USER |
  569. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  570. .icache_bsize = 32,
  571. .dcache_bsize = 32,
  572. .num_pmcs = 4,
  573. .cpu_setup = __setup_cpu_7400,
  574. .platform = "ppc7400",
  575. },
  576. { /* 7410 */
  577. .pvr_mask = 0xffff0000,
  578. .pvr_value = 0x800c0000,
  579. .cpu_name = "7410",
  580. .cpu_features = CPU_FTRS_7400,
  581. .cpu_user_features = COMMON_USER |
  582. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  583. .icache_bsize = 32,
  584. .dcache_bsize = 32,
  585. .num_pmcs = 4,
  586. .cpu_setup = __setup_cpu_7410,
  587. .platform = "ppc7400",
  588. },
  589. { /* 7450 2.0 - no doze/nap */
  590. .pvr_mask = 0xffffffff,
  591. .pvr_value = 0x80000200,
  592. .cpu_name = "7450",
  593. .cpu_features = CPU_FTRS_7450_20,
  594. .cpu_user_features = COMMON_USER |
  595. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  596. .icache_bsize = 32,
  597. .dcache_bsize = 32,
  598. .num_pmcs = 6,
  599. .cpu_setup = __setup_cpu_745x,
  600. .oprofile_cpu_type = "ppc/7450",
  601. .oprofile_type = PPC_OPROFILE_G4,
  602. .platform = "ppc7450",
  603. },
  604. { /* 7450 2.1 */
  605. .pvr_mask = 0xffffffff,
  606. .pvr_value = 0x80000201,
  607. .cpu_name = "7450",
  608. .cpu_features = CPU_FTRS_7450_21,
  609. .cpu_user_features = COMMON_USER |
  610. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  611. .icache_bsize = 32,
  612. .dcache_bsize = 32,
  613. .num_pmcs = 6,
  614. .cpu_setup = __setup_cpu_745x,
  615. .oprofile_cpu_type = "ppc/7450",
  616. .oprofile_type = PPC_OPROFILE_G4,
  617. .platform = "ppc7450",
  618. },
  619. { /* 7450 2.3 and newer */
  620. .pvr_mask = 0xffff0000,
  621. .pvr_value = 0x80000000,
  622. .cpu_name = "7450",
  623. .cpu_features = CPU_FTRS_7450_23,
  624. .cpu_user_features = COMMON_USER |
  625. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  626. .icache_bsize = 32,
  627. .dcache_bsize = 32,
  628. .num_pmcs = 6,
  629. .cpu_setup = __setup_cpu_745x,
  630. .oprofile_cpu_type = "ppc/7450",
  631. .oprofile_type = PPC_OPROFILE_G4,
  632. .platform = "ppc7450",
  633. },
  634. { /* 7455 rev 1.x */
  635. .pvr_mask = 0xffffff00,
  636. .pvr_value = 0x80010100,
  637. .cpu_name = "7455",
  638. .cpu_features = CPU_FTRS_7455_1,
  639. .cpu_user_features = COMMON_USER |
  640. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  641. .icache_bsize = 32,
  642. .dcache_bsize = 32,
  643. .num_pmcs = 6,
  644. .cpu_setup = __setup_cpu_745x,
  645. .oprofile_cpu_type = "ppc/7450",
  646. .oprofile_type = PPC_OPROFILE_G4,
  647. .platform = "ppc7450",
  648. },
  649. { /* 7455 rev 2.0 */
  650. .pvr_mask = 0xffffffff,
  651. .pvr_value = 0x80010200,
  652. .cpu_name = "7455",
  653. .cpu_features = CPU_FTRS_7455_20,
  654. .cpu_user_features = COMMON_USER |
  655. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  656. .icache_bsize = 32,
  657. .dcache_bsize = 32,
  658. .num_pmcs = 6,
  659. .cpu_setup = __setup_cpu_745x,
  660. .oprofile_cpu_type = "ppc/7450",
  661. .oprofile_type = PPC_OPROFILE_G4,
  662. .platform = "ppc7450",
  663. },
  664. { /* 7455 others */
  665. .pvr_mask = 0xffff0000,
  666. .pvr_value = 0x80010000,
  667. .cpu_name = "7455",
  668. .cpu_features = CPU_FTRS_7455,
  669. .cpu_user_features = COMMON_USER |
  670. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  671. .icache_bsize = 32,
  672. .dcache_bsize = 32,
  673. .num_pmcs = 6,
  674. .cpu_setup = __setup_cpu_745x,
  675. .oprofile_cpu_type = "ppc/7450",
  676. .oprofile_type = PPC_OPROFILE_G4,
  677. .platform = "ppc7450",
  678. },
  679. { /* 7447/7457 Rev 1.0 */
  680. .pvr_mask = 0xffffffff,
  681. .pvr_value = 0x80020100,
  682. .cpu_name = "7447/7457",
  683. .cpu_features = CPU_FTRS_7447_10,
  684. .cpu_user_features = COMMON_USER |
  685. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  686. .icache_bsize = 32,
  687. .dcache_bsize = 32,
  688. .num_pmcs = 6,
  689. .cpu_setup = __setup_cpu_745x,
  690. .oprofile_cpu_type = "ppc/7450",
  691. .oprofile_type = PPC_OPROFILE_G4,
  692. .platform = "ppc7450",
  693. },
  694. { /* 7447/7457 Rev 1.1 */
  695. .pvr_mask = 0xffffffff,
  696. .pvr_value = 0x80020101,
  697. .cpu_name = "7447/7457",
  698. .cpu_features = CPU_FTRS_7447_10,
  699. .cpu_user_features = COMMON_USER |
  700. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  701. .icache_bsize = 32,
  702. .dcache_bsize = 32,
  703. .num_pmcs = 6,
  704. .cpu_setup = __setup_cpu_745x,
  705. .oprofile_cpu_type = "ppc/7450",
  706. .oprofile_type = PPC_OPROFILE_G4,
  707. .platform = "ppc7450",
  708. },
  709. { /* 7447/7457 Rev 1.2 and later */
  710. .pvr_mask = 0xffff0000,
  711. .pvr_value = 0x80020000,
  712. .cpu_name = "7447/7457",
  713. .cpu_features = CPU_FTRS_7447,
  714. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  715. .icache_bsize = 32,
  716. .dcache_bsize = 32,
  717. .num_pmcs = 6,
  718. .cpu_setup = __setup_cpu_745x,
  719. .oprofile_cpu_type = "ppc/7450",
  720. .oprofile_type = PPC_OPROFILE_G4,
  721. .platform = "ppc7450",
  722. },
  723. { /* 7447A */
  724. .pvr_mask = 0xffff0000,
  725. .pvr_value = 0x80030000,
  726. .cpu_name = "7447A",
  727. .cpu_features = CPU_FTRS_7447A,
  728. .cpu_user_features = COMMON_USER |
  729. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  730. .icache_bsize = 32,
  731. .dcache_bsize = 32,
  732. .num_pmcs = 6,
  733. .cpu_setup = __setup_cpu_745x,
  734. .oprofile_cpu_type = "ppc/7450",
  735. .oprofile_type = PPC_OPROFILE_G4,
  736. .platform = "ppc7450",
  737. },
  738. { /* 7448 */
  739. .pvr_mask = 0xffff0000,
  740. .pvr_value = 0x80040000,
  741. .cpu_name = "7448",
  742. .cpu_features = CPU_FTRS_7447A,
  743. .cpu_user_features = COMMON_USER |
  744. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  745. .icache_bsize = 32,
  746. .dcache_bsize = 32,
  747. .num_pmcs = 6,
  748. .cpu_setup = __setup_cpu_745x,
  749. .oprofile_cpu_type = "ppc/7450",
  750. .oprofile_type = PPC_OPROFILE_G4,
  751. .platform = "ppc7450",
  752. },
  753. { /* 82xx (8240, 8245, 8260 are all 603e cores) */
  754. .pvr_mask = 0x7fff0000,
  755. .pvr_value = 0x00810000,
  756. .cpu_name = "82xx",
  757. .cpu_features = CPU_FTRS_82XX,
  758. .cpu_user_features = COMMON_USER,
  759. .icache_bsize = 32,
  760. .dcache_bsize = 32,
  761. .cpu_setup = __setup_cpu_603,
  762. .platform = "ppc603",
  763. },
  764. { /* All G2_LE (603e core, plus some) have the same pvr */
  765. .pvr_mask = 0x7fff0000,
  766. .pvr_value = 0x00820000,
  767. .cpu_name = "G2_LE",
  768. .cpu_features = CPU_FTRS_G2_LE,
  769. .cpu_user_features = COMMON_USER,
  770. .icache_bsize = 32,
  771. .dcache_bsize = 32,
  772. .cpu_setup = __setup_cpu_603,
  773. .platform = "ppc603",
  774. },
  775. { /* e300c1 (a 603e core, plus some) on 83xx */
  776. .pvr_mask = 0x7fff0000,
  777. .pvr_value = 0x00830000,
  778. .cpu_name = "e300c1",
  779. .cpu_features = CPU_FTRS_E300,
  780. .cpu_user_features = COMMON_USER,
  781. .icache_bsize = 32,
  782. .dcache_bsize = 32,
  783. .cpu_setup = __setup_cpu_603,
  784. .platform = "ppc603",
  785. },
  786. { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */
  787. .pvr_mask = 0x7fff0000,
  788. .pvr_value = 0x00840000,
  789. .cpu_name = "e300c2",
  790. .cpu_features = CPU_FTRS_E300,
  791. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  792. .icache_bsize = 32,
  793. .dcache_bsize = 32,
  794. .cpu_setup = __setup_cpu_603,
  795. .platform = "ppc603",
  796. },
  797. { /* default match, we assume split I/D cache & TB (non-601)... */
  798. .pvr_mask = 0x00000000,
  799. .pvr_value = 0x00000000,
  800. .cpu_name = "(generic PPC)",
  801. .cpu_features = CPU_FTRS_CLASSIC32,
  802. .cpu_user_features = COMMON_USER,
  803. .icache_bsize = 32,
  804. .dcache_bsize = 32,
  805. .platform = "ppc603",
  806. },
  807. #endif /* CLASSIC_PPC */
  808. #ifdef CONFIG_8xx
  809. { /* 8xx */
  810. .pvr_mask = 0xffff0000,
  811. .pvr_value = 0x00500000,
  812. .cpu_name = "8xx",
  813. /* CPU_FTR_MAYBE_CAN_DOZE is possible,
  814. * if the 8xx code is there.... */
  815. .cpu_features = CPU_FTRS_8XX,
  816. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  817. .icache_bsize = 16,
  818. .dcache_bsize = 16,
  819. .platform = "ppc823",
  820. },
  821. #endif /* CONFIG_8xx */
  822. #ifdef CONFIG_40x
  823. { /* 403GC */
  824. .pvr_mask = 0xffffff00,
  825. .pvr_value = 0x00200200,
  826. .cpu_name = "403GC",
  827. .cpu_features = CPU_FTRS_40X,
  828. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  829. .icache_bsize = 16,
  830. .dcache_bsize = 16,
  831. .platform = "ppc403",
  832. },
  833. { /* 403GCX */
  834. .pvr_mask = 0xffffff00,
  835. .pvr_value = 0x00201400,
  836. .cpu_name = "403GCX",
  837. .cpu_features = CPU_FTRS_40X,
  838. .cpu_user_features = PPC_FEATURE_32 |
  839. PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
  840. .icache_bsize = 16,
  841. .dcache_bsize = 16,
  842. .platform = "ppc403",
  843. },
  844. { /* 403G ?? */
  845. .pvr_mask = 0xffff0000,
  846. .pvr_value = 0x00200000,
  847. .cpu_name = "403G ??",
  848. .cpu_features = CPU_FTRS_40X,
  849. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  850. .icache_bsize = 16,
  851. .dcache_bsize = 16,
  852. .platform = "ppc403",
  853. },
  854. { /* 405GP */
  855. .pvr_mask = 0xffff0000,
  856. .pvr_value = 0x40110000,
  857. .cpu_name = "405GP",
  858. .cpu_features = CPU_FTRS_40X,
  859. .cpu_user_features = PPC_FEATURE_32 |
  860. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  861. .icache_bsize = 32,
  862. .dcache_bsize = 32,
  863. .platform = "ppc405",
  864. },
  865. { /* STB 03xxx */
  866. .pvr_mask = 0xffff0000,
  867. .pvr_value = 0x40130000,
  868. .cpu_name = "STB03xxx",
  869. .cpu_features = CPU_FTRS_40X,
  870. .cpu_user_features = PPC_FEATURE_32 |
  871. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  872. .icache_bsize = 32,
  873. .dcache_bsize = 32,
  874. .platform = "ppc405",
  875. },
  876. { /* STB 04xxx */
  877. .pvr_mask = 0xffff0000,
  878. .pvr_value = 0x41810000,
  879. .cpu_name = "STB04xxx",
  880. .cpu_features = CPU_FTRS_40X,
  881. .cpu_user_features = PPC_FEATURE_32 |
  882. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  883. .icache_bsize = 32,
  884. .dcache_bsize = 32,
  885. .platform = "ppc405",
  886. },
  887. { /* NP405L */
  888. .pvr_mask = 0xffff0000,
  889. .pvr_value = 0x41610000,
  890. .cpu_name = "NP405L",
  891. .cpu_features = CPU_FTRS_40X,
  892. .cpu_user_features = PPC_FEATURE_32 |
  893. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  894. .icache_bsize = 32,
  895. .dcache_bsize = 32,
  896. .platform = "ppc405",
  897. },
  898. { /* NP4GS3 */
  899. .pvr_mask = 0xffff0000,
  900. .pvr_value = 0x40B10000,
  901. .cpu_name = "NP4GS3",
  902. .cpu_features = CPU_FTRS_40X,
  903. .cpu_user_features = PPC_FEATURE_32 |
  904. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  905. .icache_bsize = 32,
  906. .dcache_bsize = 32,
  907. .platform = "ppc405",
  908. },
  909. { /* NP405H */
  910. .pvr_mask = 0xffff0000,
  911. .pvr_value = 0x41410000,
  912. .cpu_name = "NP405H",
  913. .cpu_features = CPU_FTRS_40X,
  914. .cpu_user_features = PPC_FEATURE_32 |
  915. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  916. .icache_bsize = 32,
  917. .dcache_bsize = 32,
  918. .platform = "ppc405",
  919. },
  920. { /* 405GPr */
  921. .pvr_mask = 0xffff0000,
  922. .pvr_value = 0x50910000,
  923. .cpu_name = "405GPr",
  924. .cpu_features = CPU_FTRS_40X,
  925. .cpu_user_features = PPC_FEATURE_32 |
  926. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  927. .icache_bsize = 32,
  928. .dcache_bsize = 32,
  929. .platform = "ppc405",
  930. },
  931. { /* STBx25xx */
  932. .pvr_mask = 0xffff0000,
  933. .pvr_value = 0x51510000,
  934. .cpu_name = "STBx25xx",
  935. .cpu_features = CPU_FTRS_40X,
  936. .cpu_user_features = PPC_FEATURE_32 |
  937. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  938. .icache_bsize = 32,
  939. .dcache_bsize = 32,
  940. .platform = "ppc405",
  941. },
  942. { /* 405LP */
  943. .pvr_mask = 0xffff0000,
  944. .pvr_value = 0x41F10000,
  945. .cpu_name = "405LP",
  946. .cpu_features = CPU_FTRS_40X,
  947. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  948. .icache_bsize = 32,
  949. .dcache_bsize = 32,
  950. .platform = "ppc405",
  951. },
  952. { /* Xilinx Virtex-II Pro */
  953. .pvr_mask = 0xfffff000,
  954. .pvr_value = 0x20010000,
  955. .cpu_name = "Virtex-II Pro",
  956. .cpu_features = CPU_FTRS_40X,
  957. .cpu_user_features = PPC_FEATURE_32 |
  958. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  959. .icache_bsize = 32,
  960. .dcache_bsize = 32,
  961. .platform = "ppc405",
  962. },
  963. { /* Xilinx Virtex-4 FX */
  964. .pvr_mask = 0xfffff000,
  965. .pvr_value = 0x20011000,
  966. .cpu_name = "Virtex-4 FX",
  967. .cpu_features = CPU_FTRS_40X,
  968. .cpu_user_features = PPC_FEATURE_32 |
  969. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  970. .icache_bsize = 32,
  971. .dcache_bsize = 32,
  972. .platform = "ppc405",
  973. },
  974. { /* 405EP */
  975. .pvr_mask = 0xffff0000,
  976. .pvr_value = 0x51210000,
  977. .cpu_name = "405EP",
  978. .cpu_features = CPU_FTRS_40X,
  979. .cpu_user_features = PPC_FEATURE_32 |
  980. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  981. .icache_bsize = 32,
  982. .dcache_bsize = 32,
  983. .platform = "ppc405",
  984. },
  985. #endif /* CONFIG_40x */
  986. #ifdef CONFIG_44x
  987. {
  988. .pvr_mask = 0xf0000fff,
  989. .pvr_value = 0x40000850,
  990. .cpu_name = "440EP Rev. A",
  991. .cpu_features = CPU_FTRS_44X,
  992. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  993. .icache_bsize = 32,
  994. .dcache_bsize = 32,
  995. .platform = "ppc440",
  996. },
  997. {
  998. .pvr_mask = 0xf0000fff,
  999. .pvr_value = 0x400008d3,
  1000. .cpu_name = "440EP Rev. B",
  1001. .cpu_features = CPU_FTRS_44X,
  1002. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1003. .icache_bsize = 32,
  1004. .dcache_bsize = 32,
  1005. .platform = "ppc440",
  1006. },
  1007. { /* 440GP Rev. B */
  1008. .pvr_mask = 0xf0000fff,
  1009. .pvr_value = 0x40000440,
  1010. .cpu_name = "440GP Rev. B",
  1011. .cpu_features = CPU_FTRS_44X,
  1012. .cpu_user_features = COMMON_USER_BOOKE,
  1013. .icache_bsize = 32,
  1014. .dcache_bsize = 32,
  1015. .platform = "ppc440gp",
  1016. },
  1017. { /* 440GP Rev. C */
  1018. .pvr_mask = 0xf0000fff,
  1019. .pvr_value = 0x40000481,
  1020. .cpu_name = "440GP Rev. C",
  1021. .cpu_features = CPU_FTRS_44X,
  1022. .cpu_user_features = COMMON_USER_BOOKE,
  1023. .icache_bsize = 32,
  1024. .dcache_bsize = 32,
  1025. .platform = "ppc440gp",
  1026. },
  1027. { /* 440GX Rev. A */
  1028. .pvr_mask = 0xf0000fff,
  1029. .pvr_value = 0x50000850,
  1030. .cpu_name = "440GX Rev. A",
  1031. .cpu_features = CPU_FTRS_44X,
  1032. .cpu_user_features = COMMON_USER_BOOKE,
  1033. .icache_bsize = 32,
  1034. .dcache_bsize = 32,
  1035. .platform = "ppc440",
  1036. },
  1037. { /* 440GX Rev. B */
  1038. .pvr_mask = 0xf0000fff,
  1039. .pvr_value = 0x50000851,
  1040. .cpu_name = "440GX Rev. B",
  1041. .cpu_features = CPU_FTRS_44X,
  1042. .cpu_user_features = COMMON_USER_BOOKE,
  1043. .icache_bsize = 32,
  1044. .dcache_bsize = 32,
  1045. .platform = "ppc440",
  1046. },
  1047. { /* 440GX Rev. C */
  1048. .pvr_mask = 0xf0000fff,
  1049. .pvr_value = 0x50000892,
  1050. .cpu_name = "440GX Rev. C",
  1051. .cpu_features = CPU_FTRS_44X,
  1052. .cpu_user_features = COMMON_USER_BOOKE,
  1053. .icache_bsize = 32,
  1054. .dcache_bsize = 32,
  1055. .platform = "ppc440",
  1056. },
  1057. { /* 440GX Rev. F */
  1058. .pvr_mask = 0xf0000fff,
  1059. .pvr_value = 0x50000894,
  1060. .cpu_name = "440GX Rev. F",
  1061. .cpu_features = CPU_FTRS_44X,
  1062. .cpu_user_features = COMMON_USER_BOOKE,
  1063. .icache_bsize = 32,
  1064. .dcache_bsize = 32,
  1065. .platform = "ppc440",
  1066. },
  1067. { /* 440SP Rev. A */
  1068. .pvr_mask = 0xff000fff,
  1069. .pvr_value = 0x53000891,
  1070. .cpu_name = "440SP Rev. A",
  1071. .cpu_features = CPU_FTRS_44X,
  1072. .cpu_user_features = COMMON_USER_BOOKE,
  1073. .icache_bsize = 32,
  1074. .dcache_bsize = 32,
  1075. .platform = "ppc440",
  1076. },
  1077. { /* 440SPe Rev. A */
  1078. .pvr_mask = 0xff000fff,
  1079. .pvr_value = 0x53000890,
  1080. .cpu_name = "440SPe Rev. A",
  1081. .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
  1082. CPU_FTR_USE_TB,
  1083. .cpu_user_features = COMMON_USER_BOOKE,
  1084. .icache_bsize = 32,
  1085. .dcache_bsize = 32,
  1086. .platform = "ppc440",
  1087. },
  1088. #endif /* CONFIG_44x */
  1089. #ifdef CONFIG_FSL_BOOKE
  1090. { /* e200z5 */
  1091. .pvr_mask = 0xfff00000,
  1092. .pvr_value = 0x81000000,
  1093. .cpu_name = "e200z5",
  1094. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1095. .cpu_features = CPU_FTRS_E200,
  1096. .cpu_user_features = COMMON_USER_BOOKE |
  1097. PPC_FEATURE_HAS_EFP_SINGLE |
  1098. PPC_FEATURE_UNIFIED_CACHE,
  1099. .dcache_bsize = 32,
  1100. .platform = "ppc5554",
  1101. },
  1102. { /* e200z6 */
  1103. .pvr_mask = 0xfff00000,
  1104. .pvr_value = 0x81100000,
  1105. .cpu_name = "e200z6",
  1106. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1107. .cpu_features = CPU_FTRS_E200,
  1108. .cpu_user_features = COMMON_USER_BOOKE |
  1109. PPC_FEATURE_SPE_COMP |
  1110. PPC_FEATURE_HAS_EFP_SINGLE |
  1111. PPC_FEATURE_UNIFIED_CACHE,
  1112. .dcache_bsize = 32,
  1113. .platform = "ppc5554",
  1114. },
  1115. { /* e500 */
  1116. .pvr_mask = 0xffff0000,
  1117. .pvr_value = 0x80200000,
  1118. .cpu_name = "e500",
  1119. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1120. .cpu_features = CPU_FTRS_E500,
  1121. .cpu_user_features = COMMON_USER_BOOKE |
  1122. PPC_FEATURE_SPE_COMP |
  1123. PPC_FEATURE_HAS_EFP_SINGLE,
  1124. .icache_bsize = 32,
  1125. .dcache_bsize = 32,
  1126. .num_pmcs = 4,
  1127. .oprofile_cpu_type = "ppc/e500",
  1128. .oprofile_type = PPC_OPROFILE_BOOKE,
  1129. .platform = "ppc8540",
  1130. },
  1131. { /* e500v2 */
  1132. .pvr_mask = 0xffff0000,
  1133. .pvr_value = 0x80210000,
  1134. .cpu_name = "e500v2",
  1135. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1136. .cpu_features = CPU_FTRS_E500_2,
  1137. .cpu_user_features = COMMON_USER_BOOKE |
  1138. PPC_FEATURE_SPE_COMP |
  1139. PPC_FEATURE_HAS_EFP_SINGLE |
  1140. PPC_FEATURE_HAS_EFP_DOUBLE,
  1141. .icache_bsize = 32,
  1142. .dcache_bsize = 32,
  1143. .num_pmcs = 4,
  1144. .oprofile_cpu_type = "ppc/e500",
  1145. .oprofile_type = PPC_OPROFILE_BOOKE,
  1146. .platform = "ppc8548",
  1147. },
  1148. #endif
  1149. #if !CLASSIC_PPC
  1150. { /* default match */
  1151. .pvr_mask = 0x00000000,
  1152. .pvr_value = 0x00000000,
  1153. .cpu_name = "(generic PPC)",
  1154. .cpu_features = CPU_FTRS_GENERIC_32,
  1155. .cpu_user_features = PPC_FEATURE_32,
  1156. .icache_bsize = 32,
  1157. .dcache_bsize = 32,
  1158. .platform = "powerpc",
  1159. }
  1160. #endif /* !CLASSIC_PPC */
  1161. #endif /* CONFIG_PPC32 */
  1162. };
  1163. struct cpu_spec *identify_cpu(unsigned long offset)
  1164. {
  1165. struct cpu_spec *s = cpu_specs;
  1166. struct cpu_spec **cur = &cur_cpu_spec;
  1167. unsigned int pvr = mfspr(SPRN_PVR);
  1168. int i;
  1169. s = PTRRELOC(s);
  1170. cur = PTRRELOC(cur);
  1171. if (*cur != NULL)
  1172. return PTRRELOC(*cur);
  1173. for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++)
  1174. if ((pvr & s->pvr_mask) == s->pvr_value) {
  1175. *cur = cpu_specs + i;
  1176. #ifdef CONFIG_PPC64
  1177. /* ppc64 expects identify_cpu to also call setup_cpu
  1178. * for that processor. I will consolidate that at a
  1179. * later time, for now, just use our friend #ifdef.
  1180. * we also don't need to PTRRELOC the function pointer
  1181. * on ppc64 as we are running at 0 in real mode.
  1182. */
  1183. if (s->cpu_setup) {
  1184. s->cpu_setup(offset, s);
  1185. }
  1186. #endif /* CONFIG_PPC64 */
  1187. return s;
  1188. }
  1189. BUG();
  1190. return NULL;
  1191. }
  1192. void do_feature_fixups(unsigned long value, void *fixup_start, void *fixup_end)
  1193. {
  1194. struct fixup_entry {
  1195. unsigned long mask;
  1196. unsigned long value;
  1197. long start_off;
  1198. long end_off;
  1199. } *fcur, *fend;
  1200. fcur = fixup_start;
  1201. fend = fixup_end;
  1202. for (; fcur < fend; fcur++) {
  1203. unsigned int *pstart, *pend, *p;
  1204. if ((value & fcur->mask) == fcur->value)
  1205. continue;
  1206. /* These PTRRELOCs will disappear once the new scheme for
  1207. * modules and vdso is implemented
  1208. */
  1209. pstart = ((unsigned int *)fcur) + (fcur->start_off / 4);
  1210. pend = ((unsigned int *)fcur) + (fcur->end_off / 4);
  1211. for (p = pstart; p < pend; p++) {
  1212. *p = 0x60000000u;
  1213. asm volatile ("dcbst 0, %0" : : "r" (p));
  1214. }
  1215. asm volatile ("sync" : : : "memory");
  1216. for (p = pstart; p < pend; p++)
  1217. asm volatile ("icbi 0,%0" : : "r" (p));
  1218. asm volatile ("sync; isync" : : : "memory");
  1219. }
  1220. }