netdev.c 197 KB

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  1. /*******************************************************************************
  2. Intel PRO/1000 Linux driver
  3. Copyright(c) 1999 - 2013 Intel Corporation.
  4. This program is free software; you can redistribute it and/or modify it
  5. under the terms and conditions of the GNU General Public License,
  6. version 2, as published by the Free Software Foundation.
  7. This program is distributed in the hope it will be useful, but WITHOUT
  8. ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  9. FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  10. more details.
  11. You should have received a copy of the GNU General Public License along with
  12. this program; if not, write to the Free Software Foundation, Inc.,
  13. 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  14. The full GNU General Public License is included in this distribution in
  15. the file called "COPYING".
  16. Contact Information:
  17. Linux NICS <linux.nics@intel.com>
  18. e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  19. Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  20. *******************************************************************************/
  21. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  22. #include <linux/module.h>
  23. #include <linux/types.h>
  24. #include <linux/init.h>
  25. #include <linux/pci.h>
  26. #include <linux/vmalloc.h>
  27. #include <linux/pagemap.h>
  28. #include <linux/delay.h>
  29. #include <linux/netdevice.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/tcp.h>
  32. #include <linux/ipv6.h>
  33. #include <linux/slab.h>
  34. #include <net/checksum.h>
  35. #include <net/ip6_checksum.h>
  36. #include <linux/ethtool.h>
  37. #include <linux/if_vlan.h>
  38. #include <linux/cpu.h>
  39. #include <linux/smp.h>
  40. #include <linux/pm_qos.h>
  41. #include <linux/pm_runtime.h>
  42. #include <linux/aer.h>
  43. #include <linux/prefetch.h>
  44. #include "e1000.h"
  45. #define DRV_EXTRAVERSION "-k"
  46. #define DRV_VERSION "2.2.14" DRV_EXTRAVERSION
  47. char e1000e_driver_name[] = "e1000e";
  48. const char e1000e_driver_version[] = DRV_VERSION;
  49. #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
  50. static int debug = -1;
  51. module_param(debug, int, 0);
  52. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  53. static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
  54. static const struct e1000_info *e1000_info_tbl[] = {
  55. [board_82571] = &e1000_82571_info,
  56. [board_82572] = &e1000_82572_info,
  57. [board_82573] = &e1000_82573_info,
  58. [board_82574] = &e1000_82574_info,
  59. [board_82583] = &e1000_82583_info,
  60. [board_80003es2lan] = &e1000_es2_info,
  61. [board_ich8lan] = &e1000_ich8_info,
  62. [board_ich9lan] = &e1000_ich9_info,
  63. [board_ich10lan] = &e1000_ich10_info,
  64. [board_pchlan] = &e1000_pch_info,
  65. [board_pch2lan] = &e1000_pch2_info,
  66. [board_pch_lpt] = &e1000_pch_lpt_info,
  67. };
  68. struct e1000_reg_info {
  69. u32 ofs;
  70. char *name;
  71. };
  72. static const struct e1000_reg_info e1000_reg_info_tbl[] = {
  73. /* General Registers */
  74. {E1000_CTRL, "CTRL"},
  75. {E1000_STATUS, "STATUS"},
  76. {E1000_CTRL_EXT, "CTRL_EXT"},
  77. /* Interrupt Registers */
  78. {E1000_ICR, "ICR"},
  79. /* Rx Registers */
  80. {E1000_RCTL, "RCTL"},
  81. {E1000_RDLEN(0), "RDLEN"},
  82. {E1000_RDH(0), "RDH"},
  83. {E1000_RDT(0), "RDT"},
  84. {E1000_RDTR, "RDTR"},
  85. {E1000_RXDCTL(0), "RXDCTL"},
  86. {E1000_ERT, "ERT"},
  87. {E1000_RDBAL(0), "RDBAL"},
  88. {E1000_RDBAH(0), "RDBAH"},
  89. {E1000_RDFH, "RDFH"},
  90. {E1000_RDFT, "RDFT"},
  91. {E1000_RDFHS, "RDFHS"},
  92. {E1000_RDFTS, "RDFTS"},
  93. {E1000_RDFPC, "RDFPC"},
  94. /* Tx Registers */
  95. {E1000_TCTL, "TCTL"},
  96. {E1000_TDBAL(0), "TDBAL"},
  97. {E1000_TDBAH(0), "TDBAH"},
  98. {E1000_TDLEN(0), "TDLEN"},
  99. {E1000_TDH(0), "TDH"},
  100. {E1000_TDT(0), "TDT"},
  101. {E1000_TIDV, "TIDV"},
  102. {E1000_TXDCTL(0), "TXDCTL"},
  103. {E1000_TADV, "TADV"},
  104. {E1000_TARC(0), "TARC"},
  105. {E1000_TDFH, "TDFH"},
  106. {E1000_TDFT, "TDFT"},
  107. {E1000_TDFHS, "TDFHS"},
  108. {E1000_TDFTS, "TDFTS"},
  109. {E1000_TDFPC, "TDFPC"},
  110. /* List Terminator */
  111. {0, NULL}
  112. };
  113. /**
  114. * e1000_regdump - register printout routine
  115. * @hw: pointer to the HW structure
  116. * @reginfo: pointer to the register info table
  117. **/
  118. static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
  119. {
  120. int n = 0;
  121. char rname[16];
  122. u32 regs[8];
  123. switch (reginfo->ofs) {
  124. case E1000_RXDCTL(0):
  125. for (n = 0; n < 2; n++)
  126. regs[n] = __er32(hw, E1000_RXDCTL(n));
  127. break;
  128. case E1000_TXDCTL(0):
  129. for (n = 0; n < 2; n++)
  130. regs[n] = __er32(hw, E1000_TXDCTL(n));
  131. break;
  132. case E1000_TARC(0):
  133. for (n = 0; n < 2; n++)
  134. regs[n] = __er32(hw, E1000_TARC(n));
  135. break;
  136. default:
  137. pr_info("%-15s %08x\n",
  138. reginfo->name, __er32(hw, reginfo->ofs));
  139. return;
  140. }
  141. snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
  142. pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
  143. }
  144. static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
  145. struct e1000_buffer *bi)
  146. {
  147. int i;
  148. struct e1000_ps_page *ps_page;
  149. for (i = 0; i < adapter->rx_ps_pages; i++) {
  150. ps_page = &bi->ps_pages[i];
  151. if (ps_page->page) {
  152. pr_info("packet dump for ps_page %d:\n", i);
  153. print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
  154. 16, 1, page_address(ps_page->page),
  155. PAGE_SIZE, true);
  156. }
  157. }
  158. }
  159. /**
  160. * e1000e_dump - Print registers, Tx-ring and Rx-ring
  161. * @adapter: board private structure
  162. **/
  163. static void e1000e_dump(struct e1000_adapter *adapter)
  164. {
  165. struct net_device *netdev = adapter->netdev;
  166. struct e1000_hw *hw = &adapter->hw;
  167. struct e1000_reg_info *reginfo;
  168. struct e1000_ring *tx_ring = adapter->tx_ring;
  169. struct e1000_tx_desc *tx_desc;
  170. struct my_u0 {
  171. __le64 a;
  172. __le64 b;
  173. } *u0;
  174. struct e1000_buffer *buffer_info;
  175. struct e1000_ring *rx_ring = adapter->rx_ring;
  176. union e1000_rx_desc_packet_split *rx_desc_ps;
  177. union e1000_rx_desc_extended *rx_desc;
  178. struct my_u1 {
  179. __le64 a;
  180. __le64 b;
  181. __le64 c;
  182. __le64 d;
  183. } *u1;
  184. u32 staterr;
  185. int i = 0;
  186. if (!netif_msg_hw(adapter))
  187. return;
  188. /* Print netdevice Info */
  189. if (netdev) {
  190. dev_info(&adapter->pdev->dev, "Net device Info\n");
  191. pr_info("Device Name state trans_start last_rx\n");
  192. pr_info("%-15s %016lX %016lX %016lX\n",
  193. netdev->name, netdev->state, netdev->trans_start,
  194. netdev->last_rx);
  195. }
  196. /* Print Registers */
  197. dev_info(&adapter->pdev->dev, "Register Dump\n");
  198. pr_info(" Register Name Value\n");
  199. for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
  200. reginfo->name; reginfo++) {
  201. e1000_regdump(hw, reginfo);
  202. }
  203. /* Print Tx Ring Summary */
  204. if (!netdev || !netif_running(netdev))
  205. return;
  206. dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
  207. pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
  208. buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
  209. pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
  210. 0, tx_ring->next_to_use, tx_ring->next_to_clean,
  211. (unsigned long long)buffer_info->dma,
  212. buffer_info->length,
  213. buffer_info->next_to_watch,
  214. (unsigned long long)buffer_info->time_stamp);
  215. /* Print Tx Ring */
  216. if (!netif_msg_tx_done(adapter))
  217. goto rx_ring_summary;
  218. dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
  219. /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
  220. *
  221. * Legacy Transmit Descriptor
  222. * +--------------------------------------------------------------+
  223. * 0 | Buffer Address [63:0] (Reserved on Write Back) |
  224. * +--------------------------------------------------------------+
  225. * 8 | Special | CSS | Status | CMD | CSO | Length |
  226. * +--------------------------------------------------------------+
  227. * 63 48 47 36 35 32 31 24 23 16 15 0
  228. *
  229. * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
  230. * 63 48 47 40 39 32 31 16 15 8 7 0
  231. * +----------------------------------------------------------------+
  232. * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
  233. * +----------------------------------------------------------------+
  234. * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
  235. * +----------------------------------------------------------------+
  236. * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
  237. *
  238. * Extended Data Descriptor (DTYP=0x1)
  239. * +----------------------------------------------------------------+
  240. * 0 | Buffer Address [63:0] |
  241. * +----------------------------------------------------------------+
  242. * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
  243. * +----------------------------------------------------------------+
  244. * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
  245. */
  246. pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
  247. pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
  248. pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
  249. for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
  250. const char *next_desc;
  251. tx_desc = E1000_TX_DESC(*tx_ring, i);
  252. buffer_info = &tx_ring->buffer_info[i];
  253. u0 = (struct my_u0 *)tx_desc;
  254. if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
  255. next_desc = " NTC/U";
  256. else if (i == tx_ring->next_to_use)
  257. next_desc = " NTU";
  258. else if (i == tx_ring->next_to_clean)
  259. next_desc = " NTC";
  260. else
  261. next_desc = "";
  262. pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
  263. (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
  264. ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
  265. i,
  266. (unsigned long long)le64_to_cpu(u0->a),
  267. (unsigned long long)le64_to_cpu(u0->b),
  268. (unsigned long long)buffer_info->dma,
  269. buffer_info->length, buffer_info->next_to_watch,
  270. (unsigned long long)buffer_info->time_stamp,
  271. buffer_info->skb, next_desc);
  272. if (netif_msg_pktdata(adapter) && buffer_info->skb)
  273. print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
  274. 16, 1, buffer_info->skb->data,
  275. buffer_info->skb->len, true);
  276. }
  277. /* Print Rx Ring Summary */
  278. rx_ring_summary:
  279. dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
  280. pr_info("Queue [NTU] [NTC]\n");
  281. pr_info(" %5d %5X %5X\n",
  282. 0, rx_ring->next_to_use, rx_ring->next_to_clean);
  283. /* Print Rx Ring */
  284. if (!netif_msg_rx_status(adapter))
  285. return;
  286. dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
  287. switch (adapter->rx_ps_pages) {
  288. case 1:
  289. case 2:
  290. case 3:
  291. /* [Extended] Packet Split Receive Descriptor Format
  292. *
  293. * +-----------------------------------------------------+
  294. * 0 | Buffer Address 0 [63:0] |
  295. * +-----------------------------------------------------+
  296. * 8 | Buffer Address 1 [63:0] |
  297. * +-----------------------------------------------------+
  298. * 16 | Buffer Address 2 [63:0] |
  299. * +-----------------------------------------------------+
  300. * 24 | Buffer Address 3 [63:0] |
  301. * +-----------------------------------------------------+
  302. */
  303. pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
  304. /* [Extended] Receive Descriptor (Write-Back) Format
  305. *
  306. * 63 48 47 32 31 13 12 8 7 4 3 0
  307. * +------------------------------------------------------+
  308. * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
  309. * | Checksum | Ident | | Queue | | Type |
  310. * +------------------------------------------------------+
  311. * 8 | VLAN Tag | Length | Extended Error | Extended Status |
  312. * +------------------------------------------------------+
  313. * 63 48 47 32 31 20 19 0
  314. */
  315. pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
  316. for (i = 0; i < rx_ring->count; i++) {
  317. const char *next_desc;
  318. buffer_info = &rx_ring->buffer_info[i];
  319. rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
  320. u1 = (struct my_u1 *)rx_desc_ps;
  321. staterr =
  322. le32_to_cpu(rx_desc_ps->wb.middle.status_error);
  323. if (i == rx_ring->next_to_use)
  324. next_desc = " NTU";
  325. else if (i == rx_ring->next_to_clean)
  326. next_desc = " NTC";
  327. else
  328. next_desc = "";
  329. if (staterr & E1000_RXD_STAT_DD) {
  330. /* Descriptor Done */
  331. pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
  332. "RWB", i,
  333. (unsigned long long)le64_to_cpu(u1->a),
  334. (unsigned long long)le64_to_cpu(u1->b),
  335. (unsigned long long)le64_to_cpu(u1->c),
  336. (unsigned long long)le64_to_cpu(u1->d),
  337. buffer_info->skb, next_desc);
  338. } else {
  339. pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
  340. "R ", i,
  341. (unsigned long long)le64_to_cpu(u1->a),
  342. (unsigned long long)le64_to_cpu(u1->b),
  343. (unsigned long long)le64_to_cpu(u1->c),
  344. (unsigned long long)le64_to_cpu(u1->d),
  345. (unsigned long long)buffer_info->dma,
  346. buffer_info->skb, next_desc);
  347. if (netif_msg_pktdata(adapter))
  348. e1000e_dump_ps_pages(adapter,
  349. buffer_info);
  350. }
  351. }
  352. break;
  353. default:
  354. case 0:
  355. /* Extended Receive Descriptor (Read) Format
  356. *
  357. * +-----------------------------------------------------+
  358. * 0 | Buffer Address [63:0] |
  359. * +-----------------------------------------------------+
  360. * 8 | Reserved |
  361. * +-----------------------------------------------------+
  362. */
  363. pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
  364. /* Extended Receive Descriptor (Write-Back) Format
  365. *
  366. * 63 48 47 32 31 24 23 4 3 0
  367. * +------------------------------------------------------+
  368. * | RSS Hash | | | |
  369. * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
  370. * | Packet | IP | | | Type |
  371. * | Checksum | Ident | | | |
  372. * +------------------------------------------------------+
  373. * 8 | VLAN Tag | Length | Extended Error | Extended Status |
  374. * +------------------------------------------------------+
  375. * 63 48 47 32 31 20 19 0
  376. */
  377. pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
  378. for (i = 0; i < rx_ring->count; i++) {
  379. const char *next_desc;
  380. buffer_info = &rx_ring->buffer_info[i];
  381. rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
  382. u1 = (struct my_u1 *)rx_desc;
  383. staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
  384. if (i == rx_ring->next_to_use)
  385. next_desc = " NTU";
  386. else if (i == rx_ring->next_to_clean)
  387. next_desc = " NTC";
  388. else
  389. next_desc = "";
  390. if (staterr & E1000_RXD_STAT_DD) {
  391. /* Descriptor Done */
  392. pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
  393. "RWB", i,
  394. (unsigned long long)le64_to_cpu(u1->a),
  395. (unsigned long long)le64_to_cpu(u1->b),
  396. buffer_info->skb, next_desc);
  397. } else {
  398. pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
  399. "R ", i,
  400. (unsigned long long)le64_to_cpu(u1->a),
  401. (unsigned long long)le64_to_cpu(u1->b),
  402. (unsigned long long)buffer_info->dma,
  403. buffer_info->skb, next_desc);
  404. if (netif_msg_pktdata(adapter) &&
  405. buffer_info->skb)
  406. print_hex_dump(KERN_INFO, "",
  407. DUMP_PREFIX_ADDRESS, 16,
  408. 1,
  409. buffer_info->skb->data,
  410. adapter->rx_buffer_len,
  411. true);
  412. }
  413. }
  414. }
  415. }
  416. /**
  417. * e1000_desc_unused - calculate if we have unused descriptors
  418. **/
  419. static int e1000_desc_unused(struct e1000_ring *ring)
  420. {
  421. if (ring->next_to_clean > ring->next_to_use)
  422. return ring->next_to_clean - ring->next_to_use - 1;
  423. return ring->count + ring->next_to_clean - ring->next_to_use - 1;
  424. }
  425. /**
  426. * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
  427. * @adapter: board private structure
  428. * @hwtstamps: time stamp structure to update
  429. * @systim: unsigned 64bit system time value.
  430. *
  431. * Convert the system time value stored in the RX/TXSTMP registers into a
  432. * hwtstamp which can be used by the upper level time stamping functions.
  433. *
  434. * The 'systim_lock' spinlock is used to protect the consistency of the
  435. * system time value. This is needed because reading the 64 bit time
  436. * value involves reading two 32 bit registers. The first read latches the
  437. * value.
  438. **/
  439. static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
  440. struct skb_shared_hwtstamps *hwtstamps,
  441. u64 systim)
  442. {
  443. u64 ns;
  444. unsigned long flags;
  445. spin_lock_irqsave(&adapter->systim_lock, flags);
  446. ns = timecounter_cyc2time(&adapter->tc, systim);
  447. spin_unlock_irqrestore(&adapter->systim_lock, flags);
  448. memset(hwtstamps, 0, sizeof(*hwtstamps));
  449. hwtstamps->hwtstamp = ns_to_ktime(ns);
  450. }
  451. /**
  452. * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
  453. * @adapter: board private structure
  454. * @status: descriptor extended error and status field
  455. * @skb: particular skb to include time stamp
  456. *
  457. * If the time stamp is valid, convert it into the timecounter ns value
  458. * and store that result into the shhwtstamps structure which is passed
  459. * up the network stack.
  460. **/
  461. static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
  462. struct sk_buff *skb)
  463. {
  464. struct e1000_hw *hw = &adapter->hw;
  465. u64 rxstmp;
  466. if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
  467. !(status & E1000_RXDEXT_STATERR_TST) ||
  468. !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
  469. return;
  470. /* The Rx time stamp registers contain the time stamp. No other
  471. * received packet will be time stamped until the Rx time stamp
  472. * registers are read. Because only one packet can be time stamped
  473. * at a time, the register values must belong to this packet and
  474. * therefore none of the other additional attributes need to be
  475. * compared.
  476. */
  477. rxstmp = (u64)er32(RXSTMPL);
  478. rxstmp |= (u64)er32(RXSTMPH) << 32;
  479. e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
  480. adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
  481. }
  482. /**
  483. * e1000_receive_skb - helper function to handle Rx indications
  484. * @adapter: board private structure
  485. * @staterr: descriptor extended error and status field as written by hardware
  486. * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
  487. * @skb: pointer to sk_buff to be indicated to stack
  488. **/
  489. static void e1000_receive_skb(struct e1000_adapter *adapter,
  490. struct net_device *netdev, struct sk_buff *skb,
  491. u32 staterr, __le16 vlan)
  492. {
  493. u16 tag = le16_to_cpu(vlan);
  494. e1000e_rx_hwtstamp(adapter, staterr, skb);
  495. skb->protocol = eth_type_trans(skb, netdev);
  496. if (staterr & E1000_RXD_STAT_VP)
  497. __vlan_hwaccel_put_tag(skb, tag);
  498. napi_gro_receive(&adapter->napi, skb);
  499. }
  500. /**
  501. * e1000_rx_checksum - Receive Checksum Offload
  502. * @adapter: board private structure
  503. * @status_err: receive descriptor status and error fields
  504. * @csum: receive descriptor csum field
  505. * @sk_buff: socket buffer with received data
  506. **/
  507. static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
  508. struct sk_buff *skb)
  509. {
  510. u16 status = (u16)status_err;
  511. u8 errors = (u8)(status_err >> 24);
  512. skb_checksum_none_assert(skb);
  513. /* Rx checksum disabled */
  514. if (!(adapter->netdev->features & NETIF_F_RXCSUM))
  515. return;
  516. /* Ignore Checksum bit is set */
  517. if (status & E1000_RXD_STAT_IXSM)
  518. return;
  519. /* TCP/UDP checksum error bit or IP checksum error bit is set */
  520. if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
  521. /* let the stack verify checksum errors */
  522. adapter->hw_csum_err++;
  523. return;
  524. }
  525. /* TCP/UDP Checksum has not been calculated */
  526. if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
  527. return;
  528. /* It must be a TCP or UDP packet with a valid checksum */
  529. skb->ip_summed = CHECKSUM_UNNECESSARY;
  530. adapter->hw_csum_good++;
  531. }
  532. static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
  533. {
  534. struct e1000_adapter *adapter = rx_ring->adapter;
  535. struct e1000_hw *hw = &adapter->hw;
  536. s32 ret_val = __ew32_prepare(hw);
  537. writel(i, rx_ring->tail);
  538. if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
  539. u32 rctl = er32(RCTL);
  540. ew32(RCTL, rctl & ~E1000_RCTL_EN);
  541. e_err("ME firmware caused invalid RDT - resetting\n");
  542. schedule_work(&adapter->reset_task);
  543. }
  544. }
  545. static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
  546. {
  547. struct e1000_adapter *adapter = tx_ring->adapter;
  548. struct e1000_hw *hw = &adapter->hw;
  549. s32 ret_val = __ew32_prepare(hw);
  550. writel(i, tx_ring->tail);
  551. if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
  552. u32 tctl = er32(TCTL);
  553. ew32(TCTL, tctl & ~E1000_TCTL_EN);
  554. e_err("ME firmware caused invalid TDT - resetting\n");
  555. schedule_work(&adapter->reset_task);
  556. }
  557. }
  558. /**
  559. * e1000_alloc_rx_buffers - Replace used receive buffers
  560. * @rx_ring: Rx descriptor ring
  561. **/
  562. static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
  563. int cleaned_count, gfp_t gfp)
  564. {
  565. struct e1000_adapter *adapter = rx_ring->adapter;
  566. struct net_device *netdev = adapter->netdev;
  567. struct pci_dev *pdev = adapter->pdev;
  568. union e1000_rx_desc_extended *rx_desc;
  569. struct e1000_buffer *buffer_info;
  570. struct sk_buff *skb;
  571. unsigned int i;
  572. unsigned int bufsz = adapter->rx_buffer_len;
  573. i = rx_ring->next_to_use;
  574. buffer_info = &rx_ring->buffer_info[i];
  575. while (cleaned_count--) {
  576. skb = buffer_info->skb;
  577. if (skb) {
  578. skb_trim(skb, 0);
  579. goto map_skb;
  580. }
  581. skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
  582. if (!skb) {
  583. /* Better luck next round */
  584. adapter->alloc_rx_buff_failed++;
  585. break;
  586. }
  587. buffer_info->skb = skb;
  588. map_skb:
  589. buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
  590. adapter->rx_buffer_len,
  591. DMA_FROM_DEVICE);
  592. if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
  593. dev_err(&pdev->dev, "Rx DMA map failed\n");
  594. adapter->rx_dma_failed++;
  595. break;
  596. }
  597. rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
  598. rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
  599. if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
  600. /* Force memory writes to complete before letting h/w
  601. * know there are new descriptors to fetch. (Only
  602. * applicable for weak-ordered memory model archs,
  603. * such as IA-64).
  604. */
  605. wmb();
  606. if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
  607. e1000e_update_rdt_wa(rx_ring, i);
  608. else
  609. writel(i, rx_ring->tail);
  610. }
  611. i++;
  612. if (i == rx_ring->count)
  613. i = 0;
  614. buffer_info = &rx_ring->buffer_info[i];
  615. }
  616. rx_ring->next_to_use = i;
  617. }
  618. /**
  619. * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
  620. * @rx_ring: Rx descriptor ring
  621. **/
  622. static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
  623. int cleaned_count, gfp_t gfp)
  624. {
  625. struct e1000_adapter *adapter = rx_ring->adapter;
  626. struct net_device *netdev = adapter->netdev;
  627. struct pci_dev *pdev = adapter->pdev;
  628. union e1000_rx_desc_packet_split *rx_desc;
  629. struct e1000_buffer *buffer_info;
  630. struct e1000_ps_page *ps_page;
  631. struct sk_buff *skb;
  632. unsigned int i, j;
  633. i = rx_ring->next_to_use;
  634. buffer_info = &rx_ring->buffer_info[i];
  635. while (cleaned_count--) {
  636. rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
  637. for (j = 0; j < PS_PAGE_BUFFERS; j++) {
  638. ps_page = &buffer_info->ps_pages[j];
  639. if (j >= adapter->rx_ps_pages) {
  640. /* all unused desc entries get hw null ptr */
  641. rx_desc->read.buffer_addr[j + 1] =
  642. ~cpu_to_le64(0);
  643. continue;
  644. }
  645. if (!ps_page->page) {
  646. ps_page->page = alloc_page(gfp);
  647. if (!ps_page->page) {
  648. adapter->alloc_rx_buff_failed++;
  649. goto no_buffers;
  650. }
  651. ps_page->dma = dma_map_page(&pdev->dev,
  652. ps_page->page,
  653. 0, PAGE_SIZE,
  654. DMA_FROM_DEVICE);
  655. if (dma_mapping_error(&pdev->dev,
  656. ps_page->dma)) {
  657. dev_err(&adapter->pdev->dev,
  658. "Rx DMA page map failed\n");
  659. adapter->rx_dma_failed++;
  660. goto no_buffers;
  661. }
  662. }
  663. /* Refresh the desc even if buffer_addrs
  664. * didn't change because each write-back
  665. * erases this info.
  666. */
  667. rx_desc->read.buffer_addr[j + 1] =
  668. cpu_to_le64(ps_page->dma);
  669. }
  670. skb = __netdev_alloc_skb_ip_align(netdev,
  671. adapter->rx_ps_bsize0,
  672. gfp);
  673. if (!skb) {
  674. adapter->alloc_rx_buff_failed++;
  675. break;
  676. }
  677. buffer_info->skb = skb;
  678. buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
  679. adapter->rx_ps_bsize0,
  680. DMA_FROM_DEVICE);
  681. if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
  682. dev_err(&pdev->dev, "Rx DMA map failed\n");
  683. adapter->rx_dma_failed++;
  684. /* cleanup skb */
  685. dev_kfree_skb_any(skb);
  686. buffer_info->skb = NULL;
  687. break;
  688. }
  689. rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
  690. if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
  691. /* Force memory writes to complete before letting h/w
  692. * know there are new descriptors to fetch. (Only
  693. * applicable for weak-ordered memory model archs,
  694. * such as IA-64).
  695. */
  696. wmb();
  697. if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
  698. e1000e_update_rdt_wa(rx_ring, i << 1);
  699. else
  700. writel(i << 1, rx_ring->tail);
  701. }
  702. i++;
  703. if (i == rx_ring->count)
  704. i = 0;
  705. buffer_info = &rx_ring->buffer_info[i];
  706. }
  707. no_buffers:
  708. rx_ring->next_to_use = i;
  709. }
  710. /**
  711. * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
  712. * @rx_ring: Rx descriptor ring
  713. * @cleaned_count: number of buffers to allocate this pass
  714. **/
  715. static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
  716. int cleaned_count, gfp_t gfp)
  717. {
  718. struct e1000_adapter *adapter = rx_ring->adapter;
  719. struct net_device *netdev = adapter->netdev;
  720. struct pci_dev *pdev = adapter->pdev;
  721. union e1000_rx_desc_extended *rx_desc;
  722. struct e1000_buffer *buffer_info;
  723. struct sk_buff *skb;
  724. unsigned int i;
  725. unsigned int bufsz = 256 - 16; /* for skb_reserve */
  726. i = rx_ring->next_to_use;
  727. buffer_info = &rx_ring->buffer_info[i];
  728. while (cleaned_count--) {
  729. skb = buffer_info->skb;
  730. if (skb) {
  731. skb_trim(skb, 0);
  732. goto check_page;
  733. }
  734. skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
  735. if (unlikely(!skb)) {
  736. /* Better luck next round */
  737. adapter->alloc_rx_buff_failed++;
  738. break;
  739. }
  740. buffer_info->skb = skb;
  741. check_page:
  742. /* allocate a new page if necessary */
  743. if (!buffer_info->page) {
  744. buffer_info->page = alloc_page(gfp);
  745. if (unlikely(!buffer_info->page)) {
  746. adapter->alloc_rx_buff_failed++;
  747. break;
  748. }
  749. }
  750. if (!buffer_info->dma)
  751. buffer_info->dma = dma_map_page(&pdev->dev,
  752. buffer_info->page, 0,
  753. PAGE_SIZE,
  754. DMA_FROM_DEVICE);
  755. rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
  756. rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
  757. if (unlikely(++i == rx_ring->count))
  758. i = 0;
  759. buffer_info = &rx_ring->buffer_info[i];
  760. }
  761. if (likely(rx_ring->next_to_use != i)) {
  762. rx_ring->next_to_use = i;
  763. if (unlikely(i-- == 0))
  764. i = (rx_ring->count - 1);
  765. /* Force memory writes to complete before letting h/w
  766. * know there are new descriptors to fetch. (Only
  767. * applicable for weak-ordered memory model archs,
  768. * such as IA-64).
  769. */
  770. wmb();
  771. if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
  772. e1000e_update_rdt_wa(rx_ring, i);
  773. else
  774. writel(i, rx_ring->tail);
  775. }
  776. }
  777. static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
  778. struct sk_buff *skb)
  779. {
  780. if (netdev->features & NETIF_F_RXHASH)
  781. skb->rxhash = le32_to_cpu(rss);
  782. }
  783. /**
  784. * e1000_clean_rx_irq - Send received data up the network stack
  785. * @rx_ring: Rx descriptor ring
  786. *
  787. * the return value indicates whether actual cleaning was done, there
  788. * is no guarantee that everything was cleaned
  789. **/
  790. static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
  791. int work_to_do)
  792. {
  793. struct e1000_adapter *adapter = rx_ring->adapter;
  794. struct net_device *netdev = adapter->netdev;
  795. struct pci_dev *pdev = adapter->pdev;
  796. struct e1000_hw *hw = &adapter->hw;
  797. union e1000_rx_desc_extended *rx_desc, *next_rxd;
  798. struct e1000_buffer *buffer_info, *next_buffer;
  799. u32 length, staterr;
  800. unsigned int i;
  801. int cleaned_count = 0;
  802. bool cleaned = false;
  803. unsigned int total_rx_bytes = 0, total_rx_packets = 0;
  804. i = rx_ring->next_to_clean;
  805. rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
  806. staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
  807. buffer_info = &rx_ring->buffer_info[i];
  808. while (staterr & E1000_RXD_STAT_DD) {
  809. struct sk_buff *skb;
  810. if (*work_done >= work_to_do)
  811. break;
  812. (*work_done)++;
  813. rmb(); /* read descriptor and rx_buffer_info after status DD */
  814. skb = buffer_info->skb;
  815. buffer_info->skb = NULL;
  816. prefetch(skb->data - NET_IP_ALIGN);
  817. i++;
  818. if (i == rx_ring->count)
  819. i = 0;
  820. next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
  821. prefetch(next_rxd);
  822. next_buffer = &rx_ring->buffer_info[i];
  823. cleaned = true;
  824. cleaned_count++;
  825. dma_unmap_single(&pdev->dev,
  826. buffer_info->dma,
  827. adapter->rx_buffer_len,
  828. DMA_FROM_DEVICE);
  829. buffer_info->dma = 0;
  830. length = le16_to_cpu(rx_desc->wb.upper.length);
  831. /* !EOP means multiple descriptors were used to store a single
  832. * packet, if that's the case we need to toss it. In fact, we
  833. * need to toss every packet with the EOP bit clear and the
  834. * next frame that _does_ have the EOP bit set, as it is by
  835. * definition only a frame fragment
  836. */
  837. if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
  838. adapter->flags2 |= FLAG2_IS_DISCARDING;
  839. if (adapter->flags2 & FLAG2_IS_DISCARDING) {
  840. /* All receives must fit into a single buffer */
  841. e_dbg("Receive packet consumed multiple buffers\n");
  842. /* recycle */
  843. buffer_info->skb = skb;
  844. if (staterr & E1000_RXD_STAT_EOP)
  845. adapter->flags2 &= ~FLAG2_IS_DISCARDING;
  846. goto next_desc;
  847. }
  848. if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
  849. !(netdev->features & NETIF_F_RXALL))) {
  850. /* recycle */
  851. buffer_info->skb = skb;
  852. goto next_desc;
  853. }
  854. /* adjust length to remove Ethernet CRC */
  855. if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
  856. /* If configured to store CRC, don't subtract FCS,
  857. * but keep the FCS bytes out of the total_rx_bytes
  858. * counter
  859. */
  860. if (netdev->features & NETIF_F_RXFCS)
  861. total_rx_bytes -= 4;
  862. else
  863. length -= 4;
  864. }
  865. total_rx_bytes += length;
  866. total_rx_packets++;
  867. /* code added for copybreak, this should improve
  868. * performance for small packets with large amounts
  869. * of reassembly being done in the stack
  870. */
  871. if (length < copybreak) {
  872. struct sk_buff *new_skb =
  873. netdev_alloc_skb_ip_align(netdev, length);
  874. if (new_skb) {
  875. skb_copy_to_linear_data_offset(new_skb,
  876. -NET_IP_ALIGN,
  877. (skb->data -
  878. NET_IP_ALIGN),
  879. (length +
  880. NET_IP_ALIGN));
  881. /* save the skb in buffer_info as good */
  882. buffer_info->skb = skb;
  883. skb = new_skb;
  884. }
  885. /* else just continue with the old one */
  886. }
  887. /* end copybreak code */
  888. skb_put(skb, length);
  889. /* Receive Checksum Offload */
  890. e1000_rx_checksum(adapter, staterr, skb);
  891. e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
  892. e1000_receive_skb(adapter, netdev, skb, staterr,
  893. rx_desc->wb.upper.vlan);
  894. next_desc:
  895. rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
  896. /* return some buffers to hardware, one at a time is too slow */
  897. if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
  898. adapter->alloc_rx_buf(rx_ring, cleaned_count,
  899. GFP_ATOMIC);
  900. cleaned_count = 0;
  901. }
  902. /* use prefetched values */
  903. rx_desc = next_rxd;
  904. buffer_info = next_buffer;
  905. staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
  906. }
  907. rx_ring->next_to_clean = i;
  908. cleaned_count = e1000_desc_unused(rx_ring);
  909. if (cleaned_count)
  910. adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
  911. adapter->total_rx_bytes += total_rx_bytes;
  912. adapter->total_rx_packets += total_rx_packets;
  913. return cleaned;
  914. }
  915. static void e1000_put_txbuf(struct e1000_ring *tx_ring,
  916. struct e1000_buffer *buffer_info)
  917. {
  918. struct e1000_adapter *adapter = tx_ring->adapter;
  919. if (buffer_info->dma) {
  920. if (buffer_info->mapped_as_page)
  921. dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
  922. buffer_info->length, DMA_TO_DEVICE);
  923. else
  924. dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
  925. buffer_info->length, DMA_TO_DEVICE);
  926. buffer_info->dma = 0;
  927. }
  928. if (buffer_info->skb) {
  929. dev_kfree_skb_any(buffer_info->skb);
  930. buffer_info->skb = NULL;
  931. }
  932. buffer_info->time_stamp = 0;
  933. }
  934. static void e1000_print_hw_hang(struct work_struct *work)
  935. {
  936. struct e1000_adapter *adapter = container_of(work,
  937. struct e1000_adapter,
  938. print_hang_task);
  939. struct net_device *netdev = adapter->netdev;
  940. struct e1000_ring *tx_ring = adapter->tx_ring;
  941. unsigned int i = tx_ring->next_to_clean;
  942. unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
  943. struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
  944. struct e1000_hw *hw = &adapter->hw;
  945. u16 phy_status, phy_1000t_status, phy_ext_status;
  946. u16 pci_status;
  947. if (test_bit(__E1000_DOWN, &adapter->state))
  948. return;
  949. if (!adapter->tx_hang_recheck &&
  950. (adapter->flags2 & FLAG2_DMA_BURST)) {
  951. /* May be block on write-back, flush and detect again
  952. * flush pending descriptor writebacks to memory
  953. */
  954. ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
  955. /* execute the writes immediately */
  956. e1e_flush();
  957. /* Due to rare timing issues, write to TIDV again to ensure
  958. * the write is successful
  959. */
  960. ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
  961. /* execute the writes immediately */
  962. e1e_flush();
  963. adapter->tx_hang_recheck = true;
  964. return;
  965. }
  966. /* Real hang detected */
  967. adapter->tx_hang_recheck = false;
  968. netif_stop_queue(netdev);
  969. e1e_rphy(hw, MII_BMSR, &phy_status);
  970. e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
  971. e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
  972. pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
  973. /* detected Hardware unit hang */
  974. e_err("Detected Hardware Unit Hang:\n"
  975. " TDH <%x>\n"
  976. " TDT <%x>\n"
  977. " next_to_use <%x>\n"
  978. " next_to_clean <%x>\n"
  979. "buffer_info[next_to_clean]:\n"
  980. " time_stamp <%lx>\n"
  981. " next_to_watch <%x>\n"
  982. " jiffies <%lx>\n"
  983. " next_to_watch.status <%x>\n"
  984. "MAC Status <%x>\n"
  985. "PHY Status <%x>\n"
  986. "PHY 1000BASE-T Status <%x>\n"
  987. "PHY Extended Status <%x>\n"
  988. "PCI Status <%x>\n",
  989. readl(tx_ring->head),
  990. readl(tx_ring->tail),
  991. tx_ring->next_to_use,
  992. tx_ring->next_to_clean,
  993. tx_ring->buffer_info[eop].time_stamp,
  994. eop,
  995. jiffies,
  996. eop_desc->upper.fields.status,
  997. er32(STATUS),
  998. phy_status,
  999. phy_1000t_status,
  1000. phy_ext_status,
  1001. pci_status);
  1002. /* Suggest workaround for known h/w issue */
  1003. if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
  1004. e_err("Try turning off Tx pause (flow control) via ethtool\n");
  1005. }
  1006. /**
  1007. * e1000e_tx_hwtstamp_work - check for Tx time stamp
  1008. * @work: pointer to work struct
  1009. *
  1010. * This work function polls the TSYNCTXCTL valid bit to determine when a
  1011. * timestamp has been taken for the current stored skb. The timestamp must
  1012. * be for this skb because only one such packet is allowed in the queue.
  1013. */
  1014. static void e1000e_tx_hwtstamp_work(struct work_struct *work)
  1015. {
  1016. struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
  1017. tx_hwtstamp_work);
  1018. struct e1000_hw *hw = &adapter->hw;
  1019. if (!adapter->tx_hwtstamp_skb)
  1020. return;
  1021. if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
  1022. struct skb_shared_hwtstamps shhwtstamps;
  1023. u64 txstmp;
  1024. txstmp = er32(TXSTMPL);
  1025. txstmp |= (u64)er32(TXSTMPH) << 32;
  1026. e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
  1027. skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps);
  1028. dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
  1029. adapter->tx_hwtstamp_skb = NULL;
  1030. } else {
  1031. /* reschedule to check later */
  1032. schedule_work(&adapter->tx_hwtstamp_work);
  1033. }
  1034. }
  1035. /**
  1036. * e1000_clean_tx_irq - Reclaim resources after transmit completes
  1037. * @tx_ring: Tx descriptor ring
  1038. *
  1039. * the return value indicates whether actual cleaning was done, there
  1040. * is no guarantee that everything was cleaned
  1041. **/
  1042. static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
  1043. {
  1044. struct e1000_adapter *adapter = tx_ring->adapter;
  1045. struct net_device *netdev = adapter->netdev;
  1046. struct e1000_hw *hw = &adapter->hw;
  1047. struct e1000_tx_desc *tx_desc, *eop_desc;
  1048. struct e1000_buffer *buffer_info;
  1049. unsigned int i, eop;
  1050. unsigned int count = 0;
  1051. unsigned int total_tx_bytes = 0, total_tx_packets = 0;
  1052. unsigned int bytes_compl = 0, pkts_compl = 0;
  1053. i = tx_ring->next_to_clean;
  1054. eop = tx_ring->buffer_info[i].next_to_watch;
  1055. eop_desc = E1000_TX_DESC(*tx_ring, eop);
  1056. while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
  1057. (count < tx_ring->count)) {
  1058. bool cleaned = false;
  1059. rmb(); /* read buffer_info after eop_desc */
  1060. for (; !cleaned; count++) {
  1061. tx_desc = E1000_TX_DESC(*tx_ring, i);
  1062. buffer_info = &tx_ring->buffer_info[i];
  1063. cleaned = (i == eop);
  1064. if (cleaned) {
  1065. total_tx_packets += buffer_info->segs;
  1066. total_tx_bytes += buffer_info->bytecount;
  1067. if (buffer_info->skb) {
  1068. bytes_compl += buffer_info->skb->len;
  1069. pkts_compl++;
  1070. }
  1071. }
  1072. e1000_put_txbuf(tx_ring, buffer_info);
  1073. tx_desc->upper.data = 0;
  1074. i++;
  1075. if (i == tx_ring->count)
  1076. i = 0;
  1077. }
  1078. if (i == tx_ring->next_to_use)
  1079. break;
  1080. eop = tx_ring->buffer_info[i].next_to_watch;
  1081. eop_desc = E1000_TX_DESC(*tx_ring, eop);
  1082. }
  1083. tx_ring->next_to_clean = i;
  1084. netdev_completed_queue(netdev, pkts_compl, bytes_compl);
  1085. #define TX_WAKE_THRESHOLD 32
  1086. if (count && netif_carrier_ok(netdev) &&
  1087. e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
  1088. /* Make sure that anybody stopping the queue after this
  1089. * sees the new next_to_clean.
  1090. */
  1091. smp_mb();
  1092. if (netif_queue_stopped(netdev) &&
  1093. !(test_bit(__E1000_DOWN, &adapter->state))) {
  1094. netif_wake_queue(netdev);
  1095. ++adapter->restart_queue;
  1096. }
  1097. }
  1098. if (adapter->detect_tx_hung) {
  1099. /* Detect a transmit hang in hardware, this serializes the
  1100. * check with the clearing of time_stamp and movement of i
  1101. */
  1102. adapter->detect_tx_hung = false;
  1103. if (tx_ring->buffer_info[i].time_stamp &&
  1104. time_after(jiffies, tx_ring->buffer_info[i].time_stamp
  1105. + (adapter->tx_timeout_factor * HZ)) &&
  1106. !(er32(STATUS) & E1000_STATUS_TXOFF))
  1107. schedule_work(&adapter->print_hang_task);
  1108. else
  1109. adapter->tx_hang_recheck = false;
  1110. }
  1111. adapter->total_tx_bytes += total_tx_bytes;
  1112. adapter->total_tx_packets += total_tx_packets;
  1113. return count < tx_ring->count;
  1114. }
  1115. /**
  1116. * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
  1117. * @rx_ring: Rx descriptor ring
  1118. *
  1119. * the return value indicates whether actual cleaning was done, there
  1120. * is no guarantee that everything was cleaned
  1121. **/
  1122. static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
  1123. int work_to_do)
  1124. {
  1125. struct e1000_adapter *adapter = rx_ring->adapter;
  1126. struct e1000_hw *hw = &adapter->hw;
  1127. union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
  1128. struct net_device *netdev = adapter->netdev;
  1129. struct pci_dev *pdev = adapter->pdev;
  1130. struct e1000_buffer *buffer_info, *next_buffer;
  1131. struct e1000_ps_page *ps_page;
  1132. struct sk_buff *skb;
  1133. unsigned int i, j;
  1134. u32 length, staterr;
  1135. int cleaned_count = 0;
  1136. bool cleaned = false;
  1137. unsigned int total_rx_bytes = 0, total_rx_packets = 0;
  1138. i = rx_ring->next_to_clean;
  1139. rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
  1140. staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
  1141. buffer_info = &rx_ring->buffer_info[i];
  1142. while (staterr & E1000_RXD_STAT_DD) {
  1143. if (*work_done >= work_to_do)
  1144. break;
  1145. (*work_done)++;
  1146. skb = buffer_info->skb;
  1147. rmb(); /* read descriptor and rx_buffer_info after status DD */
  1148. /* in the packet split case this is header only */
  1149. prefetch(skb->data - NET_IP_ALIGN);
  1150. i++;
  1151. if (i == rx_ring->count)
  1152. i = 0;
  1153. next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
  1154. prefetch(next_rxd);
  1155. next_buffer = &rx_ring->buffer_info[i];
  1156. cleaned = true;
  1157. cleaned_count++;
  1158. dma_unmap_single(&pdev->dev, buffer_info->dma,
  1159. adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
  1160. buffer_info->dma = 0;
  1161. /* see !EOP comment in other Rx routine */
  1162. if (!(staterr & E1000_RXD_STAT_EOP))
  1163. adapter->flags2 |= FLAG2_IS_DISCARDING;
  1164. if (adapter->flags2 & FLAG2_IS_DISCARDING) {
  1165. e_dbg("Packet Split buffers didn't pick up the full packet\n");
  1166. dev_kfree_skb_irq(skb);
  1167. if (staterr & E1000_RXD_STAT_EOP)
  1168. adapter->flags2 &= ~FLAG2_IS_DISCARDING;
  1169. goto next_desc;
  1170. }
  1171. if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
  1172. !(netdev->features & NETIF_F_RXALL))) {
  1173. dev_kfree_skb_irq(skb);
  1174. goto next_desc;
  1175. }
  1176. length = le16_to_cpu(rx_desc->wb.middle.length0);
  1177. if (!length) {
  1178. e_dbg("Last part of the packet spanning multiple descriptors\n");
  1179. dev_kfree_skb_irq(skb);
  1180. goto next_desc;
  1181. }
  1182. /* Good Receive */
  1183. skb_put(skb, length);
  1184. {
  1185. /* this looks ugly, but it seems compiler issues make
  1186. * it more efficient than reusing j
  1187. */
  1188. int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
  1189. /* page alloc/put takes too long and effects small
  1190. * packet throughput, so unsplit small packets and
  1191. * save the alloc/put only valid in softirq (napi)
  1192. * context to call kmap_*
  1193. */
  1194. if (l1 && (l1 <= copybreak) &&
  1195. ((length + l1) <= adapter->rx_ps_bsize0)) {
  1196. u8 *vaddr;
  1197. ps_page = &buffer_info->ps_pages[0];
  1198. /* there is no documentation about how to call
  1199. * kmap_atomic, so we can't hold the mapping
  1200. * very long
  1201. */
  1202. dma_sync_single_for_cpu(&pdev->dev,
  1203. ps_page->dma,
  1204. PAGE_SIZE,
  1205. DMA_FROM_DEVICE);
  1206. vaddr = kmap_atomic(ps_page->page);
  1207. memcpy(skb_tail_pointer(skb), vaddr, l1);
  1208. kunmap_atomic(vaddr);
  1209. dma_sync_single_for_device(&pdev->dev,
  1210. ps_page->dma,
  1211. PAGE_SIZE,
  1212. DMA_FROM_DEVICE);
  1213. /* remove the CRC */
  1214. if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
  1215. if (!(netdev->features & NETIF_F_RXFCS))
  1216. l1 -= 4;
  1217. }
  1218. skb_put(skb, l1);
  1219. goto copydone;
  1220. } /* if */
  1221. }
  1222. for (j = 0; j < PS_PAGE_BUFFERS; j++) {
  1223. length = le16_to_cpu(rx_desc->wb.upper.length[j]);
  1224. if (!length)
  1225. break;
  1226. ps_page = &buffer_info->ps_pages[j];
  1227. dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
  1228. DMA_FROM_DEVICE);
  1229. ps_page->dma = 0;
  1230. skb_fill_page_desc(skb, j, ps_page->page, 0, length);
  1231. ps_page->page = NULL;
  1232. skb->len += length;
  1233. skb->data_len += length;
  1234. skb->truesize += PAGE_SIZE;
  1235. }
  1236. /* strip the ethernet crc, problem is we're using pages now so
  1237. * this whole operation can get a little cpu intensive
  1238. */
  1239. if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
  1240. if (!(netdev->features & NETIF_F_RXFCS))
  1241. pskb_trim(skb, skb->len - 4);
  1242. }
  1243. copydone:
  1244. total_rx_bytes += skb->len;
  1245. total_rx_packets++;
  1246. e1000_rx_checksum(adapter, staterr, skb);
  1247. e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
  1248. if (rx_desc->wb.upper.header_status &
  1249. cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
  1250. adapter->rx_hdr_split++;
  1251. e1000_receive_skb(adapter, netdev, skb, staterr,
  1252. rx_desc->wb.middle.vlan);
  1253. next_desc:
  1254. rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
  1255. buffer_info->skb = NULL;
  1256. /* return some buffers to hardware, one at a time is too slow */
  1257. if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
  1258. adapter->alloc_rx_buf(rx_ring, cleaned_count,
  1259. GFP_ATOMIC);
  1260. cleaned_count = 0;
  1261. }
  1262. /* use prefetched values */
  1263. rx_desc = next_rxd;
  1264. buffer_info = next_buffer;
  1265. staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
  1266. }
  1267. rx_ring->next_to_clean = i;
  1268. cleaned_count = e1000_desc_unused(rx_ring);
  1269. if (cleaned_count)
  1270. adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
  1271. adapter->total_rx_bytes += total_rx_bytes;
  1272. adapter->total_rx_packets += total_rx_packets;
  1273. return cleaned;
  1274. }
  1275. /**
  1276. * e1000_consume_page - helper function
  1277. **/
  1278. static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
  1279. u16 length)
  1280. {
  1281. bi->page = NULL;
  1282. skb->len += length;
  1283. skb->data_len += length;
  1284. skb->truesize += PAGE_SIZE;
  1285. }
  1286. /**
  1287. * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
  1288. * @adapter: board private structure
  1289. *
  1290. * the return value indicates whether actual cleaning was done, there
  1291. * is no guarantee that everything was cleaned
  1292. **/
  1293. static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
  1294. int work_to_do)
  1295. {
  1296. struct e1000_adapter *adapter = rx_ring->adapter;
  1297. struct net_device *netdev = adapter->netdev;
  1298. struct pci_dev *pdev = adapter->pdev;
  1299. union e1000_rx_desc_extended *rx_desc, *next_rxd;
  1300. struct e1000_buffer *buffer_info, *next_buffer;
  1301. u32 length, staterr;
  1302. unsigned int i;
  1303. int cleaned_count = 0;
  1304. bool cleaned = false;
  1305. unsigned int total_rx_bytes=0, total_rx_packets=0;
  1306. i = rx_ring->next_to_clean;
  1307. rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
  1308. staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
  1309. buffer_info = &rx_ring->buffer_info[i];
  1310. while (staterr & E1000_RXD_STAT_DD) {
  1311. struct sk_buff *skb;
  1312. if (*work_done >= work_to_do)
  1313. break;
  1314. (*work_done)++;
  1315. rmb(); /* read descriptor and rx_buffer_info after status DD */
  1316. skb = buffer_info->skb;
  1317. buffer_info->skb = NULL;
  1318. ++i;
  1319. if (i == rx_ring->count)
  1320. i = 0;
  1321. next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
  1322. prefetch(next_rxd);
  1323. next_buffer = &rx_ring->buffer_info[i];
  1324. cleaned = true;
  1325. cleaned_count++;
  1326. dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
  1327. DMA_FROM_DEVICE);
  1328. buffer_info->dma = 0;
  1329. length = le16_to_cpu(rx_desc->wb.upper.length);
  1330. /* errors is only valid for DD + EOP descriptors */
  1331. if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
  1332. ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
  1333. !(netdev->features & NETIF_F_RXALL)))) {
  1334. /* recycle both page and skb */
  1335. buffer_info->skb = skb;
  1336. /* an error means any chain goes out the window too */
  1337. if (rx_ring->rx_skb_top)
  1338. dev_kfree_skb_irq(rx_ring->rx_skb_top);
  1339. rx_ring->rx_skb_top = NULL;
  1340. goto next_desc;
  1341. }
  1342. #define rxtop (rx_ring->rx_skb_top)
  1343. if (!(staterr & E1000_RXD_STAT_EOP)) {
  1344. /* this descriptor is only the beginning (or middle) */
  1345. if (!rxtop) {
  1346. /* this is the beginning of a chain */
  1347. rxtop = skb;
  1348. skb_fill_page_desc(rxtop, 0, buffer_info->page,
  1349. 0, length);
  1350. } else {
  1351. /* this is the middle of a chain */
  1352. skb_fill_page_desc(rxtop,
  1353. skb_shinfo(rxtop)->nr_frags,
  1354. buffer_info->page, 0, length);
  1355. /* re-use the skb, only consumed the page */
  1356. buffer_info->skb = skb;
  1357. }
  1358. e1000_consume_page(buffer_info, rxtop, length);
  1359. goto next_desc;
  1360. } else {
  1361. if (rxtop) {
  1362. /* end of the chain */
  1363. skb_fill_page_desc(rxtop,
  1364. skb_shinfo(rxtop)->nr_frags,
  1365. buffer_info->page, 0, length);
  1366. /* re-use the current skb, we only consumed the
  1367. * page
  1368. */
  1369. buffer_info->skb = skb;
  1370. skb = rxtop;
  1371. rxtop = NULL;
  1372. e1000_consume_page(buffer_info, skb, length);
  1373. } else {
  1374. /* no chain, got EOP, this buf is the packet
  1375. * copybreak to save the put_page/alloc_page
  1376. */
  1377. if (length <= copybreak &&
  1378. skb_tailroom(skb) >= length) {
  1379. u8 *vaddr;
  1380. vaddr = kmap_atomic(buffer_info->page);
  1381. memcpy(skb_tail_pointer(skb), vaddr,
  1382. length);
  1383. kunmap_atomic(vaddr);
  1384. /* re-use the page, so don't erase
  1385. * buffer_info->page
  1386. */
  1387. skb_put(skb, length);
  1388. } else {
  1389. skb_fill_page_desc(skb, 0,
  1390. buffer_info->page, 0,
  1391. length);
  1392. e1000_consume_page(buffer_info, skb,
  1393. length);
  1394. }
  1395. }
  1396. }
  1397. /* Receive Checksum Offload */
  1398. e1000_rx_checksum(adapter, staterr, skb);
  1399. e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
  1400. /* probably a little skewed due to removing CRC */
  1401. total_rx_bytes += skb->len;
  1402. total_rx_packets++;
  1403. /* eth type trans needs skb->data to point to something */
  1404. if (!pskb_may_pull(skb, ETH_HLEN)) {
  1405. e_err("pskb_may_pull failed.\n");
  1406. dev_kfree_skb_irq(skb);
  1407. goto next_desc;
  1408. }
  1409. e1000_receive_skb(adapter, netdev, skb, staterr,
  1410. rx_desc->wb.upper.vlan);
  1411. next_desc:
  1412. rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
  1413. /* return some buffers to hardware, one at a time is too slow */
  1414. if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
  1415. adapter->alloc_rx_buf(rx_ring, cleaned_count,
  1416. GFP_ATOMIC);
  1417. cleaned_count = 0;
  1418. }
  1419. /* use prefetched values */
  1420. rx_desc = next_rxd;
  1421. buffer_info = next_buffer;
  1422. staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
  1423. }
  1424. rx_ring->next_to_clean = i;
  1425. cleaned_count = e1000_desc_unused(rx_ring);
  1426. if (cleaned_count)
  1427. adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
  1428. adapter->total_rx_bytes += total_rx_bytes;
  1429. adapter->total_rx_packets += total_rx_packets;
  1430. return cleaned;
  1431. }
  1432. /**
  1433. * e1000_clean_rx_ring - Free Rx Buffers per Queue
  1434. * @rx_ring: Rx descriptor ring
  1435. **/
  1436. static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
  1437. {
  1438. struct e1000_adapter *adapter = rx_ring->adapter;
  1439. struct e1000_buffer *buffer_info;
  1440. struct e1000_ps_page *ps_page;
  1441. struct pci_dev *pdev = adapter->pdev;
  1442. unsigned int i, j;
  1443. /* Free all the Rx ring sk_buffs */
  1444. for (i = 0; i < rx_ring->count; i++) {
  1445. buffer_info = &rx_ring->buffer_info[i];
  1446. if (buffer_info->dma) {
  1447. if (adapter->clean_rx == e1000_clean_rx_irq)
  1448. dma_unmap_single(&pdev->dev, buffer_info->dma,
  1449. adapter->rx_buffer_len,
  1450. DMA_FROM_DEVICE);
  1451. else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
  1452. dma_unmap_page(&pdev->dev, buffer_info->dma,
  1453. PAGE_SIZE, DMA_FROM_DEVICE);
  1454. else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
  1455. dma_unmap_single(&pdev->dev, buffer_info->dma,
  1456. adapter->rx_ps_bsize0,
  1457. DMA_FROM_DEVICE);
  1458. buffer_info->dma = 0;
  1459. }
  1460. if (buffer_info->page) {
  1461. put_page(buffer_info->page);
  1462. buffer_info->page = NULL;
  1463. }
  1464. if (buffer_info->skb) {
  1465. dev_kfree_skb(buffer_info->skb);
  1466. buffer_info->skb = NULL;
  1467. }
  1468. for (j = 0; j < PS_PAGE_BUFFERS; j++) {
  1469. ps_page = &buffer_info->ps_pages[j];
  1470. if (!ps_page->page)
  1471. break;
  1472. dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
  1473. DMA_FROM_DEVICE);
  1474. ps_page->dma = 0;
  1475. put_page(ps_page->page);
  1476. ps_page->page = NULL;
  1477. }
  1478. }
  1479. /* there also may be some cached data from a chained receive */
  1480. if (rx_ring->rx_skb_top) {
  1481. dev_kfree_skb(rx_ring->rx_skb_top);
  1482. rx_ring->rx_skb_top = NULL;
  1483. }
  1484. /* Zero out the descriptor ring */
  1485. memset(rx_ring->desc, 0, rx_ring->size);
  1486. rx_ring->next_to_clean = 0;
  1487. rx_ring->next_to_use = 0;
  1488. adapter->flags2 &= ~FLAG2_IS_DISCARDING;
  1489. writel(0, rx_ring->head);
  1490. if (rx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
  1491. e1000e_update_rdt_wa(rx_ring, 0);
  1492. else
  1493. writel(0, rx_ring->tail);
  1494. }
  1495. static void e1000e_downshift_workaround(struct work_struct *work)
  1496. {
  1497. struct e1000_adapter *adapter = container_of(work,
  1498. struct e1000_adapter, downshift_task);
  1499. if (test_bit(__E1000_DOWN, &adapter->state))
  1500. return;
  1501. e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
  1502. }
  1503. /**
  1504. * e1000_intr_msi - Interrupt Handler
  1505. * @irq: interrupt number
  1506. * @data: pointer to a network interface device structure
  1507. **/
  1508. static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
  1509. {
  1510. struct net_device *netdev = data;
  1511. struct e1000_adapter *adapter = netdev_priv(netdev);
  1512. struct e1000_hw *hw = &adapter->hw;
  1513. u32 icr = er32(ICR);
  1514. /* read ICR disables interrupts using IAM */
  1515. if (icr & E1000_ICR_LSC) {
  1516. hw->mac.get_link_status = true;
  1517. /* ICH8 workaround-- Call gig speed drop workaround on cable
  1518. * disconnect (LSC) before accessing any PHY registers
  1519. */
  1520. if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
  1521. (!(er32(STATUS) & E1000_STATUS_LU)))
  1522. schedule_work(&adapter->downshift_task);
  1523. /* 80003ES2LAN workaround-- For packet buffer work-around on
  1524. * link down event; disable receives here in the ISR and reset
  1525. * adapter in watchdog
  1526. */
  1527. if (netif_carrier_ok(netdev) &&
  1528. adapter->flags & FLAG_RX_NEEDS_RESTART) {
  1529. /* disable receives */
  1530. u32 rctl = er32(RCTL);
  1531. ew32(RCTL, rctl & ~E1000_RCTL_EN);
  1532. adapter->flags |= FLAG_RESTART_NOW;
  1533. }
  1534. /* guard against interrupt when we're going down */
  1535. if (!test_bit(__E1000_DOWN, &adapter->state))
  1536. mod_timer(&adapter->watchdog_timer, jiffies + 1);
  1537. }
  1538. /* Reset on uncorrectable ECC error */
  1539. if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
  1540. u32 pbeccsts = er32(PBECCSTS);
  1541. adapter->corr_errors +=
  1542. pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
  1543. adapter->uncorr_errors +=
  1544. (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
  1545. E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
  1546. /* Do the reset outside of interrupt context */
  1547. schedule_work(&adapter->reset_task);
  1548. /* return immediately since reset is imminent */
  1549. return IRQ_HANDLED;
  1550. }
  1551. if (napi_schedule_prep(&adapter->napi)) {
  1552. adapter->total_tx_bytes = 0;
  1553. adapter->total_tx_packets = 0;
  1554. adapter->total_rx_bytes = 0;
  1555. adapter->total_rx_packets = 0;
  1556. __napi_schedule(&adapter->napi);
  1557. }
  1558. return IRQ_HANDLED;
  1559. }
  1560. /**
  1561. * e1000_intr - Interrupt Handler
  1562. * @irq: interrupt number
  1563. * @data: pointer to a network interface device structure
  1564. **/
  1565. static irqreturn_t e1000_intr(int __always_unused irq, void *data)
  1566. {
  1567. struct net_device *netdev = data;
  1568. struct e1000_adapter *adapter = netdev_priv(netdev);
  1569. struct e1000_hw *hw = &adapter->hw;
  1570. u32 rctl, icr = er32(ICR);
  1571. if (!icr || test_bit(__E1000_DOWN, &adapter->state))
  1572. return IRQ_NONE; /* Not our interrupt */
  1573. /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
  1574. * not set, then the adapter didn't send an interrupt
  1575. */
  1576. if (!(icr & E1000_ICR_INT_ASSERTED))
  1577. return IRQ_NONE;
  1578. /* Interrupt Auto-Mask...upon reading ICR,
  1579. * interrupts are masked. No need for the
  1580. * IMC write
  1581. */
  1582. if (icr & E1000_ICR_LSC) {
  1583. hw->mac.get_link_status = true;
  1584. /* ICH8 workaround-- Call gig speed drop workaround on cable
  1585. * disconnect (LSC) before accessing any PHY registers
  1586. */
  1587. if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
  1588. (!(er32(STATUS) & E1000_STATUS_LU)))
  1589. schedule_work(&adapter->downshift_task);
  1590. /* 80003ES2LAN workaround--
  1591. * For packet buffer work-around on link down event;
  1592. * disable receives here in the ISR and
  1593. * reset adapter in watchdog
  1594. */
  1595. if (netif_carrier_ok(netdev) &&
  1596. (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
  1597. /* disable receives */
  1598. rctl = er32(RCTL);
  1599. ew32(RCTL, rctl & ~E1000_RCTL_EN);
  1600. adapter->flags |= FLAG_RESTART_NOW;
  1601. }
  1602. /* guard against interrupt when we're going down */
  1603. if (!test_bit(__E1000_DOWN, &adapter->state))
  1604. mod_timer(&adapter->watchdog_timer, jiffies + 1);
  1605. }
  1606. /* Reset on uncorrectable ECC error */
  1607. if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
  1608. u32 pbeccsts = er32(PBECCSTS);
  1609. adapter->corr_errors +=
  1610. pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
  1611. adapter->uncorr_errors +=
  1612. (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
  1613. E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
  1614. /* Do the reset outside of interrupt context */
  1615. schedule_work(&adapter->reset_task);
  1616. /* return immediately since reset is imminent */
  1617. return IRQ_HANDLED;
  1618. }
  1619. if (napi_schedule_prep(&adapter->napi)) {
  1620. adapter->total_tx_bytes = 0;
  1621. adapter->total_tx_packets = 0;
  1622. adapter->total_rx_bytes = 0;
  1623. adapter->total_rx_packets = 0;
  1624. __napi_schedule(&adapter->napi);
  1625. }
  1626. return IRQ_HANDLED;
  1627. }
  1628. static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
  1629. {
  1630. struct net_device *netdev = data;
  1631. struct e1000_adapter *adapter = netdev_priv(netdev);
  1632. struct e1000_hw *hw = &adapter->hw;
  1633. u32 icr = er32(ICR);
  1634. if (!(icr & E1000_ICR_INT_ASSERTED)) {
  1635. if (!test_bit(__E1000_DOWN, &adapter->state))
  1636. ew32(IMS, E1000_IMS_OTHER);
  1637. return IRQ_NONE;
  1638. }
  1639. if (icr & adapter->eiac_mask)
  1640. ew32(ICS, (icr & adapter->eiac_mask));
  1641. if (icr & E1000_ICR_OTHER) {
  1642. if (!(icr & E1000_ICR_LSC))
  1643. goto no_link_interrupt;
  1644. hw->mac.get_link_status = true;
  1645. /* guard against interrupt when we're going down */
  1646. if (!test_bit(__E1000_DOWN, &adapter->state))
  1647. mod_timer(&adapter->watchdog_timer, jiffies + 1);
  1648. }
  1649. no_link_interrupt:
  1650. if (!test_bit(__E1000_DOWN, &adapter->state))
  1651. ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
  1652. return IRQ_HANDLED;
  1653. }
  1654. static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
  1655. {
  1656. struct net_device *netdev = data;
  1657. struct e1000_adapter *adapter = netdev_priv(netdev);
  1658. struct e1000_hw *hw = &adapter->hw;
  1659. struct e1000_ring *tx_ring = adapter->tx_ring;
  1660. adapter->total_tx_bytes = 0;
  1661. adapter->total_tx_packets = 0;
  1662. if (!e1000_clean_tx_irq(tx_ring))
  1663. /* Ring was not completely cleaned, so fire another interrupt */
  1664. ew32(ICS, tx_ring->ims_val);
  1665. return IRQ_HANDLED;
  1666. }
  1667. static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
  1668. {
  1669. struct net_device *netdev = data;
  1670. struct e1000_adapter *adapter = netdev_priv(netdev);
  1671. struct e1000_ring *rx_ring = adapter->rx_ring;
  1672. /* Write the ITR value calculated at the end of the
  1673. * previous interrupt.
  1674. */
  1675. if (rx_ring->set_itr) {
  1676. writel(1000000000 / (rx_ring->itr_val * 256),
  1677. rx_ring->itr_register);
  1678. rx_ring->set_itr = 0;
  1679. }
  1680. if (napi_schedule_prep(&adapter->napi)) {
  1681. adapter->total_rx_bytes = 0;
  1682. adapter->total_rx_packets = 0;
  1683. __napi_schedule(&adapter->napi);
  1684. }
  1685. return IRQ_HANDLED;
  1686. }
  1687. /**
  1688. * e1000_configure_msix - Configure MSI-X hardware
  1689. *
  1690. * e1000_configure_msix sets up the hardware to properly
  1691. * generate MSI-X interrupts.
  1692. **/
  1693. static void e1000_configure_msix(struct e1000_adapter *adapter)
  1694. {
  1695. struct e1000_hw *hw = &adapter->hw;
  1696. struct e1000_ring *rx_ring = adapter->rx_ring;
  1697. struct e1000_ring *tx_ring = adapter->tx_ring;
  1698. int vector = 0;
  1699. u32 ctrl_ext, ivar = 0;
  1700. adapter->eiac_mask = 0;
  1701. /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
  1702. if (hw->mac.type == e1000_82574) {
  1703. u32 rfctl = er32(RFCTL);
  1704. rfctl |= E1000_RFCTL_ACK_DIS;
  1705. ew32(RFCTL, rfctl);
  1706. }
  1707. #define E1000_IVAR_INT_ALLOC_VALID 0x8
  1708. /* Configure Rx vector */
  1709. rx_ring->ims_val = E1000_IMS_RXQ0;
  1710. adapter->eiac_mask |= rx_ring->ims_val;
  1711. if (rx_ring->itr_val)
  1712. writel(1000000000 / (rx_ring->itr_val * 256),
  1713. rx_ring->itr_register);
  1714. else
  1715. writel(1, rx_ring->itr_register);
  1716. ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
  1717. /* Configure Tx vector */
  1718. tx_ring->ims_val = E1000_IMS_TXQ0;
  1719. vector++;
  1720. if (tx_ring->itr_val)
  1721. writel(1000000000 / (tx_ring->itr_val * 256),
  1722. tx_ring->itr_register);
  1723. else
  1724. writel(1, tx_ring->itr_register);
  1725. adapter->eiac_mask |= tx_ring->ims_val;
  1726. ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
  1727. /* set vector for Other Causes, e.g. link changes */
  1728. vector++;
  1729. ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
  1730. if (rx_ring->itr_val)
  1731. writel(1000000000 / (rx_ring->itr_val * 256),
  1732. hw->hw_addr + E1000_EITR_82574(vector));
  1733. else
  1734. writel(1, hw->hw_addr + E1000_EITR_82574(vector));
  1735. /* Cause Tx interrupts on every write back */
  1736. ivar |= (1 << 31);
  1737. ew32(IVAR, ivar);
  1738. /* enable MSI-X PBA support */
  1739. ctrl_ext = er32(CTRL_EXT);
  1740. ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
  1741. /* Auto-Mask Other interrupts upon ICR read */
  1742. ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
  1743. ctrl_ext |= E1000_CTRL_EXT_EIAME;
  1744. ew32(CTRL_EXT, ctrl_ext);
  1745. e1e_flush();
  1746. }
  1747. void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
  1748. {
  1749. if (adapter->msix_entries) {
  1750. pci_disable_msix(adapter->pdev);
  1751. kfree(adapter->msix_entries);
  1752. adapter->msix_entries = NULL;
  1753. } else if (adapter->flags & FLAG_MSI_ENABLED) {
  1754. pci_disable_msi(adapter->pdev);
  1755. adapter->flags &= ~FLAG_MSI_ENABLED;
  1756. }
  1757. }
  1758. /**
  1759. * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
  1760. *
  1761. * Attempt to configure interrupts using the best available
  1762. * capabilities of the hardware and kernel.
  1763. **/
  1764. void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
  1765. {
  1766. int err;
  1767. int i;
  1768. switch (adapter->int_mode) {
  1769. case E1000E_INT_MODE_MSIX:
  1770. if (adapter->flags & FLAG_HAS_MSIX) {
  1771. adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
  1772. adapter->msix_entries = kcalloc(adapter->num_vectors,
  1773. sizeof(struct msix_entry),
  1774. GFP_KERNEL);
  1775. if (adapter->msix_entries) {
  1776. for (i = 0; i < adapter->num_vectors; i++)
  1777. adapter->msix_entries[i].entry = i;
  1778. err = pci_enable_msix(adapter->pdev,
  1779. adapter->msix_entries,
  1780. adapter->num_vectors);
  1781. if (err == 0)
  1782. return;
  1783. }
  1784. /* MSI-X failed, so fall through and try MSI */
  1785. e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
  1786. e1000e_reset_interrupt_capability(adapter);
  1787. }
  1788. adapter->int_mode = E1000E_INT_MODE_MSI;
  1789. /* Fall through */
  1790. case E1000E_INT_MODE_MSI:
  1791. if (!pci_enable_msi(adapter->pdev)) {
  1792. adapter->flags |= FLAG_MSI_ENABLED;
  1793. } else {
  1794. adapter->int_mode = E1000E_INT_MODE_LEGACY;
  1795. e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
  1796. }
  1797. /* Fall through */
  1798. case E1000E_INT_MODE_LEGACY:
  1799. /* Don't do anything; this is the system default */
  1800. break;
  1801. }
  1802. /* store the number of vectors being used */
  1803. adapter->num_vectors = 1;
  1804. }
  1805. /**
  1806. * e1000_request_msix - Initialize MSI-X interrupts
  1807. *
  1808. * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
  1809. * kernel.
  1810. **/
  1811. static int e1000_request_msix(struct e1000_adapter *adapter)
  1812. {
  1813. struct net_device *netdev = adapter->netdev;
  1814. int err = 0, vector = 0;
  1815. if (strlen(netdev->name) < (IFNAMSIZ - 5))
  1816. snprintf(adapter->rx_ring->name,
  1817. sizeof(adapter->rx_ring->name) - 1,
  1818. "%s-rx-0", netdev->name);
  1819. else
  1820. memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
  1821. err = request_irq(adapter->msix_entries[vector].vector,
  1822. e1000_intr_msix_rx, 0, adapter->rx_ring->name,
  1823. netdev);
  1824. if (err)
  1825. return err;
  1826. adapter->rx_ring->itr_register = adapter->hw.hw_addr +
  1827. E1000_EITR_82574(vector);
  1828. adapter->rx_ring->itr_val = adapter->itr;
  1829. vector++;
  1830. if (strlen(netdev->name) < (IFNAMSIZ - 5))
  1831. snprintf(adapter->tx_ring->name,
  1832. sizeof(adapter->tx_ring->name) - 1,
  1833. "%s-tx-0", netdev->name);
  1834. else
  1835. memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
  1836. err = request_irq(adapter->msix_entries[vector].vector,
  1837. e1000_intr_msix_tx, 0, adapter->tx_ring->name,
  1838. netdev);
  1839. if (err)
  1840. return err;
  1841. adapter->tx_ring->itr_register = adapter->hw.hw_addr +
  1842. E1000_EITR_82574(vector);
  1843. adapter->tx_ring->itr_val = adapter->itr;
  1844. vector++;
  1845. err = request_irq(adapter->msix_entries[vector].vector,
  1846. e1000_msix_other, 0, netdev->name, netdev);
  1847. if (err)
  1848. return err;
  1849. e1000_configure_msix(adapter);
  1850. return 0;
  1851. }
  1852. /**
  1853. * e1000_request_irq - initialize interrupts
  1854. *
  1855. * Attempts to configure interrupts using the best available
  1856. * capabilities of the hardware and kernel.
  1857. **/
  1858. static int e1000_request_irq(struct e1000_adapter *adapter)
  1859. {
  1860. struct net_device *netdev = adapter->netdev;
  1861. int err;
  1862. if (adapter->msix_entries) {
  1863. err = e1000_request_msix(adapter);
  1864. if (!err)
  1865. return err;
  1866. /* fall back to MSI */
  1867. e1000e_reset_interrupt_capability(adapter);
  1868. adapter->int_mode = E1000E_INT_MODE_MSI;
  1869. e1000e_set_interrupt_capability(adapter);
  1870. }
  1871. if (adapter->flags & FLAG_MSI_ENABLED) {
  1872. err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
  1873. netdev->name, netdev);
  1874. if (!err)
  1875. return err;
  1876. /* fall back to legacy interrupt */
  1877. e1000e_reset_interrupt_capability(adapter);
  1878. adapter->int_mode = E1000E_INT_MODE_LEGACY;
  1879. }
  1880. err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
  1881. netdev->name, netdev);
  1882. if (err)
  1883. e_err("Unable to allocate interrupt, Error: %d\n", err);
  1884. return err;
  1885. }
  1886. static void e1000_free_irq(struct e1000_adapter *adapter)
  1887. {
  1888. struct net_device *netdev = adapter->netdev;
  1889. if (adapter->msix_entries) {
  1890. int vector = 0;
  1891. free_irq(adapter->msix_entries[vector].vector, netdev);
  1892. vector++;
  1893. free_irq(adapter->msix_entries[vector].vector, netdev);
  1894. vector++;
  1895. /* Other Causes interrupt vector */
  1896. free_irq(adapter->msix_entries[vector].vector, netdev);
  1897. return;
  1898. }
  1899. free_irq(adapter->pdev->irq, netdev);
  1900. }
  1901. /**
  1902. * e1000_irq_disable - Mask off interrupt generation on the NIC
  1903. **/
  1904. static void e1000_irq_disable(struct e1000_adapter *adapter)
  1905. {
  1906. struct e1000_hw *hw = &adapter->hw;
  1907. ew32(IMC, ~0);
  1908. if (adapter->msix_entries)
  1909. ew32(EIAC_82574, 0);
  1910. e1e_flush();
  1911. if (adapter->msix_entries) {
  1912. int i;
  1913. for (i = 0; i < adapter->num_vectors; i++)
  1914. synchronize_irq(adapter->msix_entries[i].vector);
  1915. } else {
  1916. synchronize_irq(adapter->pdev->irq);
  1917. }
  1918. }
  1919. /**
  1920. * e1000_irq_enable - Enable default interrupt generation settings
  1921. **/
  1922. static void e1000_irq_enable(struct e1000_adapter *adapter)
  1923. {
  1924. struct e1000_hw *hw = &adapter->hw;
  1925. if (adapter->msix_entries) {
  1926. ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
  1927. ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
  1928. } else if (hw->mac.type == e1000_pch_lpt) {
  1929. ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
  1930. } else {
  1931. ew32(IMS, IMS_ENABLE_MASK);
  1932. }
  1933. e1e_flush();
  1934. }
  1935. /**
  1936. * e1000e_get_hw_control - get control of the h/w from f/w
  1937. * @adapter: address of board private structure
  1938. *
  1939. * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
  1940. * For ASF and Pass Through versions of f/w this means that
  1941. * the driver is loaded. For AMT version (only with 82573)
  1942. * of the f/w this means that the network i/f is open.
  1943. **/
  1944. void e1000e_get_hw_control(struct e1000_adapter *adapter)
  1945. {
  1946. struct e1000_hw *hw = &adapter->hw;
  1947. u32 ctrl_ext;
  1948. u32 swsm;
  1949. /* Let firmware know the driver has taken over */
  1950. if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
  1951. swsm = er32(SWSM);
  1952. ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
  1953. } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
  1954. ctrl_ext = er32(CTRL_EXT);
  1955. ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
  1956. }
  1957. }
  1958. /**
  1959. * e1000e_release_hw_control - release control of the h/w to f/w
  1960. * @adapter: address of board private structure
  1961. *
  1962. * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
  1963. * For ASF and Pass Through versions of f/w this means that the
  1964. * driver is no longer loaded. For AMT version (only with 82573) i
  1965. * of the f/w this means that the network i/f is closed.
  1966. *
  1967. **/
  1968. void e1000e_release_hw_control(struct e1000_adapter *adapter)
  1969. {
  1970. struct e1000_hw *hw = &adapter->hw;
  1971. u32 ctrl_ext;
  1972. u32 swsm;
  1973. /* Let firmware taken over control of h/w */
  1974. if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
  1975. swsm = er32(SWSM);
  1976. ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
  1977. } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
  1978. ctrl_ext = er32(CTRL_EXT);
  1979. ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
  1980. }
  1981. }
  1982. /**
  1983. * e1000_alloc_ring_dma - allocate memory for a ring structure
  1984. **/
  1985. static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
  1986. struct e1000_ring *ring)
  1987. {
  1988. struct pci_dev *pdev = adapter->pdev;
  1989. ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
  1990. GFP_KERNEL);
  1991. if (!ring->desc)
  1992. return -ENOMEM;
  1993. return 0;
  1994. }
  1995. /**
  1996. * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
  1997. * @tx_ring: Tx descriptor ring
  1998. *
  1999. * Return 0 on success, negative on failure
  2000. **/
  2001. int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
  2002. {
  2003. struct e1000_adapter *adapter = tx_ring->adapter;
  2004. int err = -ENOMEM, size;
  2005. size = sizeof(struct e1000_buffer) * tx_ring->count;
  2006. tx_ring->buffer_info = vzalloc(size);
  2007. if (!tx_ring->buffer_info)
  2008. goto err;
  2009. /* round up to nearest 4K */
  2010. tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
  2011. tx_ring->size = ALIGN(tx_ring->size, 4096);
  2012. err = e1000_alloc_ring_dma(adapter, tx_ring);
  2013. if (err)
  2014. goto err;
  2015. tx_ring->next_to_use = 0;
  2016. tx_ring->next_to_clean = 0;
  2017. return 0;
  2018. err:
  2019. vfree(tx_ring->buffer_info);
  2020. e_err("Unable to allocate memory for the transmit descriptor ring\n");
  2021. return err;
  2022. }
  2023. /**
  2024. * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
  2025. * @rx_ring: Rx descriptor ring
  2026. *
  2027. * Returns 0 on success, negative on failure
  2028. **/
  2029. int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
  2030. {
  2031. struct e1000_adapter *adapter = rx_ring->adapter;
  2032. struct e1000_buffer *buffer_info;
  2033. int i, size, desc_len, err = -ENOMEM;
  2034. size = sizeof(struct e1000_buffer) * rx_ring->count;
  2035. rx_ring->buffer_info = vzalloc(size);
  2036. if (!rx_ring->buffer_info)
  2037. goto err;
  2038. for (i = 0; i < rx_ring->count; i++) {
  2039. buffer_info = &rx_ring->buffer_info[i];
  2040. buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
  2041. sizeof(struct e1000_ps_page),
  2042. GFP_KERNEL);
  2043. if (!buffer_info->ps_pages)
  2044. goto err_pages;
  2045. }
  2046. desc_len = sizeof(union e1000_rx_desc_packet_split);
  2047. /* Round up to nearest 4K */
  2048. rx_ring->size = rx_ring->count * desc_len;
  2049. rx_ring->size = ALIGN(rx_ring->size, 4096);
  2050. err = e1000_alloc_ring_dma(adapter, rx_ring);
  2051. if (err)
  2052. goto err_pages;
  2053. rx_ring->next_to_clean = 0;
  2054. rx_ring->next_to_use = 0;
  2055. rx_ring->rx_skb_top = NULL;
  2056. return 0;
  2057. err_pages:
  2058. for (i = 0; i < rx_ring->count; i++) {
  2059. buffer_info = &rx_ring->buffer_info[i];
  2060. kfree(buffer_info->ps_pages);
  2061. }
  2062. err:
  2063. vfree(rx_ring->buffer_info);
  2064. e_err("Unable to allocate memory for the receive descriptor ring\n");
  2065. return err;
  2066. }
  2067. /**
  2068. * e1000_clean_tx_ring - Free Tx Buffers
  2069. * @tx_ring: Tx descriptor ring
  2070. **/
  2071. static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
  2072. {
  2073. struct e1000_adapter *adapter = tx_ring->adapter;
  2074. struct e1000_buffer *buffer_info;
  2075. unsigned long size;
  2076. unsigned int i;
  2077. for (i = 0; i < tx_ring->count; i++) {
  2078. buffer_info = &tx_ring->buffer_info[i];
  2079. e1000_put_txbuf(tx_ring, buffer_info);
  2080. }
  2081. netdev_reset_queue(adapter->netdev);
  2082. size = sizeof(struct e1000_buffer) * tx_ring->count;
  2083. memset(tx_ring->buffer_info, 0, size);
  2084. memset(tx_ring->desc, 0, tx_ring->size);
  2085. tx_ring->next_to_use = 0;
  2086. tx_ring->next_to_clean = 0;
  2087. writel(0, tx_ring->head);
  2088. if (tx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
  2089. e1000e_update_tdt_wa(tx_ring, 0);
  2090. else
  2091. writel(0, tx_ring->tail);
  2092. }
  2093. /**
  2094. * e1000e_free_tx_resources - Free Tx Resources per Queue
  2095. * @tx_ring: Tx descriptor ring
  2096. *
  2097. * Free all transmit software resources
  2098. **/
  2099. void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
  2100. {
  2101. struct e1000_adapter *adapter = tx_ring->adapter;
  2102. struct pci_dev *pdev = adapter->pdev;
  2103. e1000_clean_tx_ring(tx_ring);
  2104. vfree(tx_ring->buffer_info);
  2105. tx_ring->buffer_info = NULL;
  2106. dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
  2107. tx_ring->dma);
  2108. tx_ring->desc = NULL;
  2109. }
  2110. /**
  2111. * e1000e_free_rx_resources - Free Rx Resources
  2112. * @rx_ring: Rx descriptor ring
  2113. *
  2114. * Free all receive software resources
  2115. **/
  2116. void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
  2117. {
  2118. struct e1000_adapter *adapter = rx_ring->adapter;
  2119. struct pci_dev *pdev = adapter->pdev;
  2120. int i;
  2121. e1000_clean_rx_ring(rx_ring);
  2122. for (i = 0; i < rx_ring->count; i++)
  2123. kfree(rx_ring->buffer_info[i].ps_pages);
  2124. vfree(rx_ring->buffer_info);
  2125. rx_ring->buffer_info = NULL;
  2126. dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
  2127. rx_ring->dma);
  2128. rx_ring->desc = NULL;
  2129. }
  2130. /**
  2131. * e1000_update_itr - update the dynamic ITR value based on statistics
  2132. * @adapter: pointer to adapter
  2133. * @itr_setting: current adapter->itr
  2134. * @packets: the number of packets during this measurement interval
  2135. * @bytes: the number of bytes during this measurement interval
  2136. *
  2137. * Stores a new ITR value based on packets and byte
  2138. * counts during the last interrupt. The advantage of per interrupt
  2139. * computation is faster updates and more accurate ITR for the current
  2140. * traffic pattern. Constants in this function were computed
  2141. * based on theoretical maximum wire speed and thresholds were set based
  2142. * on testing data as well as attempting to minimize response time
  2143. * while increasing bulk throughput. This functionality is controlled
  2144. * by the InterruptThrottleRate module parameter.
  2145. **/
  2146. static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
  2147. {
  2148. unsigned int retval = itr_setting;
  2149. if (packets == 0)
  2150. return itr_setting;
  2151. switch (itr_setting) {
  2152. case lowest_latency:
  2153. /* handle TSO and jumbo frames */
  2154. if (bytes/packets > 8000)
  2155. retval = bulk_latency;
  2156. else if ((packets < 5) && (bytes > 512))
  2157. retval = low_latency;
  2158. break;
  2159. case low_latency: /* 50 usec aka 20000 ints/s */
  2160. if (bytes > 10000) {
  2161. /* this if handles the TSO accounting */
  2162. if (bytes/packets > 8000)
  2163. retval = bulk_latency;
  2164. else if ((packets < 10) || ((bytes/packets) > 1200))
  2165. retval = bulk_latency;
  2166. else if ((packets > 35))
  2167. retval = lowest_latency;
  2168. } else if (bytes/packets > 2000) {
  2169. retval = bulk_latency;
  2170. } else if (packets <= 2 && bytes < 512) {
  2171. retval = lowest_latency;
  2172. }
  2173. break;
  2174. case bulk_latency: /* 250 usec aka 4000 ints/s */
  2175. if (bytes > 25000) {
  2176. if (packets > 35)
  2177. retval = low_latency;
  2178. } else if (bytes < 6000) {
  2179. retval = low_latency;
  2180. }
  2181. break;
  2182. }
  2183. return retval;
  2184. }
  2185. static void e1000_set_itr(struct e1000_adapter *adapter)
  2186. {
  2187. u16 current_itr;
  2188. u32 new_itr = adapter->itr;
  2189. /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
  2190. if (adapter->link_speed != SPEED_1000) {
  2191. current_itr = 0;
  2192. new_itr = 4000;
  2193. goto set_itr_now;
  2194. }
  2195. if (adapter->flags2 & FLAG2_DISABLE_AIM) {
  2196. new_itr = 0;
  2197. goto set_itr_now;
  2198. }
  2199. adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
  2200. adapter->total_tx_packets,
  2201. adapter->total_tx_bytes);
  2202. /* conservative mode (itr 3) eliminates the lowest_latency setting */
  2203. if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
  2204. adapter->tx_itr = low_latency;
  2205. adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
  2206. adapter->total_rx_packets,
  2207. adapter->total_rx_bytes);
  2208. /* conservative mode (itr 3) eliminates the lowest_latency setting */
  2209. if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
  2210. adapter->rx_itr = low_latency;
  2211. current_itr = max(adapter->rx_itr, adapter->tx_itr);
  2212. switch (current_itr) {
  2213. /* counts and packets in update_itr are dependent on these numbers */
  2214. case lowest_latency:
  2215. new_itr = 70000;
  2216. break;
  2217. case low_latency:
  2218. new_itr = 20000; /* aka hwitr = ~200 */
  2219. break;
  2220. case bulk_latency:
  2221. new_itr = 4000;
  2222. break;
  2223. default:
  2224. break;
  2225. }
  2226. set_itr_now:
  2227. if (new_itr != adapter->itr) {
  2228. /* this attempts to bias the interrupt rate towards Bulk
  2229. * by adding intermediate steps when interrupt rate is
  2230. * increasing
  2231. */
  2232. new_itr = new_itr > adapter->itr ?
  2233. min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
  2234. adapter->itr = new_itr;
  2235. adapter->rx_ring->itr_val = new_itr;
  2236. if (adapter->msix_entries)
  2237. adapter->rx_ring->set_itr = 1;
  2238. else
  2239. e1000e_write_itr(adapter, new_itr);
  2240. }
  2241. }
  2242. /**
  2243. * e1000e_write_itr - write the ITR value to the appropriate registers
  2244. * @adapter: address of board private structure
  2245. * @itr: new ITR value to program
  2246. *
  2247. * e1000e_write_itr determines if the adapter is in MSI-X mode
  2248. * and, if so, writes the EITR registers with the ITR value.
  2249. * Otherwise, it writes the ITR value into the ITR register.
  2250. **/
  2251. void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
  2252. {
  2253. struct e1000_hw *hw = &adapter->hw;
  2254. u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
  2255. if (adapter->msix_entries) {
  2256. int vector;
  2257. for (vector = 0; vector < adapter->num_vectors; vector++)
  2258. writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
  2259. } else {
  2260. ew32(ITR, new_itr);
  2261. }
  2262. }
  2263. /**
  2264. * e1000_alloc_queues - Allocate memory for all rings
  2265. * @adapter: board private structure to initialize
  2266. **/
  2267. static int e1000_alloc_queues(struct e1000_adapter *adapter)
  2268. {
  2269. int size = sizeof(struct e1000_ring);
  2270. adapter->tx_ring = kzalloc(size, GFP_KERNEL);
  2271. if (!adapter->tx_ring)
  2272. goto err;
  2273. adapter->tx_ring->count = adapter->tx_ring_count;
  2274. adapter->tx_ring->adapter = adapter;
  2275. adapter->rx_ring = kzalloc(size, GFP_KERNEL);
  2276. if (!adapter->rx_ring)
  2277. goto err;
  2278. adapter->rx_ring->count = adapter->rx_ring_count;
  2279. adapter->rx_ring->adapter = adapter;
  2280. return 0;
  2281. err:
  2282. e_err("Unable to allocate memory for queues\n");
  2283. kfree(adapter->rx_ring);
  2284. kfree(adapter->tx_ring);
  2285. return -ENOMEM;
  2286. }
  2287. /**
  2288. * e1000e_poll - NAPI Rx polling callback
  2289. * @napi: struct associated with this polling callback
  2290. * @weight: number of packets driver is allowed to process this poll
  2291. **/
  2292. static int e1000e_poll(struct napi_struct *napi, int weight)
  2293. {
  2294. struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
  2295. napi);
  2296. struct e1000_hw *hw = &adapter->hw;
  2297. struct net_device *poll_dev = adapter->netdev;
  2298. int tx_cleaned = 1, work_done = 0;
  2299. adapter = netdev_priv(poll_dev);
  2300. if (!adapter->msix_entries ||
  2301. (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
  2302. tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
  2303. adapter->clean_rx(adapter->rx_ring, &work_done, weight);
  2304. if (!tx_cleaned)
  2305. work_done = weight;
  2306. /* If weight not fully consumed, exit the polling mode */
  2307. if (work_done < weight) {
  2308. if (adapter->itr_setting & 3)
  2309. e1000_set_itr(adapter);
  2310. napi_complete(napi);
  2311. if (!test_bit(__E1000_DOWN, &adapter->state)) {
  2312. if (adapter->msix_entries)
  2313. ew32(IMS, adapter->rx_ring->ims_val);
  2314. else
  2315. e1000_irq_enable(adapter);
  2316. }
  2317. }
  2318. return work_done;
  2319. }
  2320. static int e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
  2321. {
  2322. struct e1000_adapter *adapter = netdev_priv(netdev);
  2323. struct e1000_hw *hw = &adapter->hw;
  2324. u32 vfta, index;
  2325. /* don't update vlan cookie if already programmed */
  2326. if ((adapter->hw.mng_cookie.status &
  2327. E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
  2328. (vid == adapter->mng_vlan_id))
  2329. return 0;
  2330. /* add VID to filter table */
  2331. if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
  2332. index = (vid >> 5) & 0x7F;
  2333. vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
  2334. vfta |= (1 << (vid & 0x1F));
  2335. hw->mac.ops.write_vfta(hw, index, vfta);
  2336. }
  2337. set_bit(vid, adapter->active_vlans);
  2338. return 0;
  2339. }
  2340. static int e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
  2341. {
  2342. struct e1000_adapter *adapter = netdev_priv(netdev);
  2343. struct e1000_hw *hw = &adapter->hw;
  2344. u32 vfta, index;
  2345. if ((adapter->hw.mng_cookie.status &
  2346. E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
  2347. (vid == adapter->mng_vlan_id)) {
  2348. /* release control to f/w */
  2349. e1000e_release_hw_control(adapter);
  2350. return 0;
  2351. }
  2352. /* remove VID from filter table */
  2353. if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
  2354. index = (vid >> 5) & 0x7F;
  2355. vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
  2356. vfta &= ~(1 << (vid & 0x1F));
  2357. hw->mac.ops.write_vfta(hw, index, vfta);
  2358. }
  2359. clear_bit(vid, adapter->active_vlans);
  2360. return 0;
  2361. }
  2362. /**
  2363. * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
  2364. * @adapter: board private structure to initialize
  2365. **/
  2366. static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
  2367. {
  2368. struct net_device *netdev = adapter->netdev;
  2369. struct e1000_hw *hw = &adapter->hw;
  2370. u32 rctl;
  2371. if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
  2372. /* disable VLAN receive filtering */
  2373. rctl = er32(RCTL);
  2374. rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
  2375. ew32(RCTL, rctl);
  2376. if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
  2377. e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
  2378. adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
  2379. }
  2380. }
  2381. }
  2382. /**
  2383. * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
  2384. * @adapter: board private structure to initialize
  2385. **/
  2386. static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
  2387. {
  2388. struct e1000_hw *hw = &adapter->hw;
  2389. u32 rctl;
  2390. if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
  2391. /* enable VLAN receive filtering */
  2392. rctl = er32(RCTL);
  2393. rctl |= E1000_RCTL_VFE;
  2394. rctl &= ~E1000_RCTL_CFIEN;
  2395. ew32(RCTL, rctl);
  2396. }
  2397. }
  2398. /**
  2399. * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
  2400. * @adapter: board private structure to initialize
  2401. **/
  2402. static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
  2403. {
  2404. struct e1000_hw *hw = &adapter->hw;
  2405. u32 ctrl;
  2406. /* disable VLAN tag insert/strip */
  2407. ctrl = er32(CTRL);
  2408. ctrl &= ~E1000_CTRL_VME;
  2409. ew32(CTRL, ctrl);
  2410. }
  2411. /**
  2412. * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
  2413. * @adapter: board private structure to initialize
  2414. **/
  2415. static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
  2416. {
  2417. struct e1000_hw *hw = &adapter->hw;
  2418. u32 ctrl;
  2419. /* enable VLAN tag insert/strip */
  2420. ctrl = er32(CTRL);
  2421. ctrl |= E1000_CTRL_VME;
  2422. ew32(CTRL, ctrl);
  2423. }
  2424. static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
  2425. {
  2426. struct net_device *netdev = adapter->netdev;
  2427. u16 vid = adapter->hw.mng_cookie.vlan_id;
  2428. u16 old_vid = adapter->mng_vlan_id;
  2429. if (adapter->hw.mng_cookie.status &
  2430. E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
  2431. e1000_vlan_rx_add_vid(netdev, vid);
  2432. adapter->mng_vlan_id = vid;
  2433. }
  2434. if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
  2435. e1000_vlan_rx_kill_vid(netdev, old_vid);
  2436. }
  2437. static void e1000_restore_vlan(struct e1000_adapter *adapter)
  2438. {
  2439. u16 vid;
  2440. e1000_vlan_rx_add_vid(adapter->netdev, 0);
  2441. for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
  2442. e1000_vlan_rx_add_vid(adapter->netdev, vid);
  2443. }
  2444. static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
  2445. {
  2446. struct e1000_hw *hw = &adapter->hw;
  2447. u32 manc, manc2h, mdef, i, j;
  2448. if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
  2449. return;
  2450. manc = er32(MANC);
  2451. /* enable receiving management packets to the host. this will probably
  2452. * generate destination unreachable messages from the host OS, but
  2453. * the packets will be handled on SMBUS
  2454. */
  2455. manc |= E1000_MANC_EN_MNG2HOST;
  2456. manc2h = er32(MANC2H);
  2457. switch (hw->mac.type) {
  2458. default:
  2459. manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
  2460. break;
  2461. case e1000_82574:
  2462. case e1000_82583:
  2463. /* Check if IPMI pass-through decision filter already exists;
  2464. * if so, enable it.
  2465. */
  2466. for (i = 0, j = 0; i < 8; i++) {
  2467. mdef = er32(MDEF(i));
  2468. /* Ignore filters with anything other than IPMI ports */
  2469. if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
  2470. continue;
  2471. /* Enable this decision filter in MANC2H */
  2472. if (mdef)
  2473. manc2h |= (1 << i);
  2474. j |= mdef;
  2475. }
  2476. if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
  2477. break;
  2478. /* Create new decision filter in an empty filter */
  2479. for (i = 0, j = 0; i < 8; i++)
  2480. if (er32(MDEF(i)) == 0) {
  2481. ew32(MDEF(i), (E1000_MDEF_PORT_623 |
  2482. E1000_MDEF_PORT_664));
  2483. manc2h |= (1 << 1);
  2484. j++;
  2485. break;
  2486. }
  2487. if (!j)
  2488. e_warn("Unable to create IPMI pass-through filter\n");
  2489. break;
  2490. }
  2491. ew32(MANC2H, manc2h);
  2492. ew32(MANC, manc);
  2493. }
  2494. /**
  2495. * e1000_configure_tx - Configure Transmit Unit after Reset
  2496. * @adapter: board private structure
  2497. *
  2498. * Configure the Tx unit of the MAC after a reset.
  2499. **/
  2500. static void e1000_configure_tx(struct e1000_adapter *adapter)
  2501. {
  2502. struct e1000_hw *hw = &adapter->hw;
  2503. struct e1000_ring *tx_ring = adapter->tx_ring;
  2504. u64 tdba;
  2505. u32 tdlen, tarc;
  2506. /* Setup the HW Tx Head and Tail descriptor pointers */
  2507. tdba = tx_ring->dma;
  2508. tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
  2509. ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
  2510. ew32(TDBAH(0), (tdba >> 32));
  2511. ew32(TDLEN(0), tdlen);
  2512. ew32(TDH(0), 0);
  2513. ew32(TDT(0), 0);
  2514. tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
  2515. tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
  2516. /* Set the Tx Interrupt Delay register */
  2517. ew32(TIDV, adapter->tx_int_delay);
  2518. /* Tx irq moderation */
  2519. ew32(TADV, adapter->tx_abs_int_delay);
  2520. if (adapter->flags2 & FLAG2_DMA_BURST) {
  2521. u32 txdctl = er32(TXDCTL(0));
  2522. txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
  2523. E1000_TXDCTL_WTHRESH);
  2524. /* set up some performance related parameters to encourage the
  2525. * hardware to use the bus more efficiently in bursts, depends
  2526. * on the tx_int_delay to be enabled,
  2527. * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
  2528. * hthresh = 1 ==> prefetch when one or more available
  2529. * pthresh = 0x1f ==> prefetch if internal cache 31 or less
  2530. * BEWARE: this seems to work but should be considered first if
  2531. * there are Tx hangs or other Tx related bugs
  2532. */
  2533. txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
  2534. ew32(TXDCTL(0), txdctl);
  2535. }
  2536. /* erratum work around: set txdctl the same for both queues */
  2537. ew32(TXDCTL(1), er32(TXDCTL(0)));
  2538. if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
  2539. tarc = er32(TARC(0));
  2540. /* set the speed mode bit, we'll clear it if we're not at
  2541. * gigabit link later
  2542. */
  2543. #define SPEED_MODE_BIT (1 << 21)
  2544. tarc |= SPEED_MODE_BIT;
  2545. ew32(TARC(0), tarc);
  2546. }
  2547. /* errata: program both queues to unweighted RR */
  2548. if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
  2549. tarc = er32(TARC(0));
  2550. tarc |= 1;
  2551. ew32(TARC(0), tarc);
  2552. tarc = er32(TARC(1));
  2553. tarc |= 1;
  2554. ew32(TARC(1), tarc);
  2555. }
  2556. /* Setup Transmit Descriptor Settings for eop descriptor */
  2557. adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
  2558. /* only set IDE if we are delaying interrupts using the timers */
  2559. if (adapter->tx_int_delay)
  2560. adapter->txd_cmd |= E1000_TXD_CMD_IDE;
  2561. /* enable Report Status bit */
  2562. adapter->txd_cmd |= E1000_TXD_CMD_RS;
  2563. hw->mac.ops.config_collision_dist(hw);
  2564. }
  2565. /**
  2566. * e1000_setup_rctl - configure the receive control registers
  2567. * @adapter: Board private structure
  2568. **/
  2569. #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
  2570. (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
  2571. static void e1000_setup_rctl(struct e1000_adapter *adapter)
  2572. {
  2573. struct e1000_hw *hw = &adapter->hw;
  2574. u32 rctl, rfctl;
  2575. u32 pages = 0;
  2576. /* Workaround Si errata on PCHx - configure jumbo frame flow */
  2577. if (hw->mac.type >= e1000_pch2lan) {
  2578. s32 ret_val;
  2579. if (adapter->netdev->mtu > ETH_DATA_LEN)
  2580. ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
  2581. else
  2582. ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
  2583. if (ret_val)
  2584. e_dbg("failed to enable jumbo frame workaround mode\n");
  2585. }
  2586. /* Program MC offset vector base */
  2587. rctl = er32(RCTL);
  2588. rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
  2589. rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
  2590. E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
  2591. (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
  2592. /* Do not Store bad packets */
  2593. rctl &= ~E1000_RCTL_SBP;
  2594. /* Enable Long Packet receive */
  2595. if (adapter->netdev->mtu <= ETH_DATA_LEN)
  2596. rctl &= ~E1000_RCTL_LPE;
  2597. else
  2598. rctl |= E1000_RCTL_LPE;
  2599. /* Some systems expect that the CRC is included in SMBUS traffic. The
  2600. * hardware strips the CRC before sending to both SMBUS (BMC) and to
  2601. * host memory when this is enabled
  2602. */
  2603. if (adapter->flags2 & FLAG2_CRC_STRIPPING)
  2604. rctl |= E1000_RCTL_SECRC;
  2605. /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
  2606. if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
  2607. u16 phy_data;
  2608. e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
  2609. phy_data &= 0xfff8;
  2610. phy_data |= (1 << 2);
  2611. e1e_wphy(hw, PHY_REG(770, 26), phy_data);
  2612. e1e_rphy(hw, 22, &phy_data);
  2613. phy_data &= 0x0fff;
  2614. phy_data |= (1 << 14);
  2615. e1e_wphy(hw, 0x10, 0x2823);
  2616. e1e_wphy(hw, 0x11, 0x0003);
  2617. e1e_wphy(hw, 22, phy_data);
  2618. }
  2619. /* Setup buffer sizes */
  2620. rctl &= ~E1000_RCTL_SZ_4096;
  2621. rctl |= E1000_RCTL_BSEX;
  2622. switch (adapter->rx_buffer_len) {
  2623. case 2048:
  2624. default:
  2625. rctl |= E1000_RCTL_SZ_2048;
  2626. rctl &= ~E1000_RCTL_BSEX;
  2627. break;
  2628. case 4096:
  2629. rctl |= E1000_RCTL_SZ_4096;
  2630. break;
  2631. case 8192:
  2632. rctl |= E1000_RCTL_SZ_8192;
  2633. break;
  2634. case 16384:
  2635. rctl |= E1000_RCTL_SZ_16384;
  2636. break;
  2637. }
  2638. /* Enable Extended Status in all Receive Descriptors */
  2639. rfctl = er32(RFCTL);
  2640. rfctl |= E1000_RFCTL_EXTEN;
  2641. ew32(RFCTL, rfctl);
  2642. /* 82571 and greater support packet-split where the protocol
  2643. * header is placed in skb->data and the packet data is
  2644. * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
  2645. * In the case of a non-split, skb->data is linearly filled,
  2646. * followed by the page buffers. Therefore, skb->data is
  2647. * sized to hold the largest protocol header.
  2648. *
  2649. * allocations using alloc_page take too long for regular MTU
  2650. * so only enable packet split for jumbo frames
  2651. *
  2652. * Using pages when the page size is greater than 16k wastes
  2653. * a lot of memory, since we allocate 3 pages at all times
  2654. * per packet.
  2655. */
  2656. pages = PAGE_USE_COUNT(adapter->netdev->mtu);
  2657. if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
  2658. adapter->rx_ps_pages = pages;
  2659. else
  2660. adapter->rx_ps_pages = 0;
  2661. if (adapter->rx_ps_pages) {
  2662. u32 psrctl = 0;
  2663. /* Enable Packet split descriptors */
  2664. rctl |= E1000_RCTL_DTYP_PS;
  2665. psrctl |= adapter->rx_ps_bsize0 >>
  2666. E1000_PSRCTL_BSIZE0_SHIFT;
  2667. switch (adapter->rx_ps_pages) {
  2668. case 3:
  2669. psrctl |= PAGE_SIZE <<
  2670. E1000_PSRCTL_BSIZE3_SHIFT;
  2671. case 2:
  2672. psrctl |= PAGE_SIZE <<
  2673. E1000_PSRCTL_BSIZE2_SHIFT;
  2674. case 1:
  2675. psrctl |= PAGE_SIZE >>
  2676. E1000_PSRCTL_BSIZE1_SHIFT;
  2677. break;
  2678. }
  2679. ew32(PSRCTL, psrctl);
  2680. }
  2681. /* This is useful for sniffing bad packets. */
  2682. if (adapter->netdev->features & NETIF_F_RXALL) {
  2683. /* UPE and MPE will be handled by normal PROMISC logic
  2684. * in e1000e_set_rx_mode
  2685. */
  2686. rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
  2687. E1000_RCTL_BAM | /* RX All Bcast Pkts */
  2688. E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
  2689. rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
  2690. E1000_RCTL_DPF | /* Allow filtered pause */
  2691. E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
  2692. /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
  2693. * and that breaks VLANs.
  2694. */
  2695. }
  2696. ew32(RCTL, rctl);
  2697. /* just started the receive unit, no need to restart */
  2698. adapter->flags &= ~FLAG_RESTART_NOW;
  2699. }
  2700. /**
  2701. * e1000_configure_rx - Configure Receive Unit after Reset
  2702. * @adapter: board private structure
  2703. *
  2704. * Configure the Rx unit of the MAC after a reset.
  2705. **/
  2706. static void e1000_configure_rx(struct e1000_adapter *adapter)
  2707. {
  2708. struct e1000_hw *hw = &adapter->hw;
  2709. struct e1000_ring *rx_ring = adapter->rx_ring;
  2710. u64 rdba;
  2711. u32 rdlen, rctl, rxcsum, ctrl_ext;
  2712. if (adapter->rx_ps_pages) {
  2713. /* this is a 32 byte descriptor */
  2714. rdlen = rx_ring->count *
  2715. sizeof(union e1000_rx_desc_packet_split);
  2716. adapter->clean_rx = e1000_clean_rx_irq_ps;
  2717. adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
  2718. } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
  2719. rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
  2720. adapter->clean_rx = e1000_clean_jumbo_rx_irq;
  2721. adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
  2722. } else {
  2723. rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
  2724. adapter->clean_rx = e1000_clean_rx_irq;
  2725. adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
  2726. }
  2727. /* disable receives while setting up the descriptors */
  2728. rctl = er32(RCTL);
  2729. if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
  2730. ew32(RCTL, rctl & ~E1000_RCTL_EN);
  2731. e1e_flush();
  2732. usleep_range(10000, 20000);
  2733. if (adapter->flags2 & FLAG2_DMA_BURST) {
  2734. /* set the writeback threshold (only takes effect if the RDTR
  2735. * is set). set GRAN=1 and write back up to 0x4 worth, and
  2736. * enable prefetching of 0x20 Rx descriptors
  2737. * granularity = 01
  2738. * wthresh = 04,
  2739. * hthresh = 04,
  2740. * pthresh = 0x20
  2741. */
  2742. ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
  2743. ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
  2744. /* override the delay timers for enabling bursting, only if
  2745. * the value was not set by the user via module options
  2746. */
  2747. if (adapter->rx_int_delay == DEFAULT_RDTR)
  2748. adapter->rx_int_delay = BURST_RDTR;
  2749. if (adapter->rx_abs_int_delay == DEFAULT_RADV)
  2750. adapter->rx_abs_int_delay = BURST_RADV;
  2751. }
  2752. /* set the Receive Delay Timer Register */
  2753. ew32(RDTR, adapter->rx_int_delay);
  2754. /* irq moderation */
  2755. ew32(RADV, adapter->rx_abs_int_delay);
  2756. if ((adapter->itr_setting != 0) && (adapter->itr != 0))
  2757. e1000e_write_itr(adapter, adapter->itr);
  2758. ctrl_ext = er32(CTRL_EXT);
  2759. /* Auto-Mask interrupts upon ICR access */
  2760. ctrl_ext |= E1000_CTRL_EXT_IAME;
  2761. ew32(IAM, 0xffffffff);
  2762. ew32(CTRL_EXT, ctrl_ext);
  2763. e1e_flush();
  2764. /* Setup the HW Rx Head and Tail Descriptor Pointers and
  2765. * the Base and Length of the Rx Descriptor Ring
  2766. */
  2767. rdba = rx_ring->dma;
  2768. ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
  2769. ew32(RDBAH(0), (rdba >> 32));
  2770. ew32(RDLEN(0), rdlen);
  2771. ew32(RDH(0), 0);
  2772. ew32(RDT(0), 0);
  2773. rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
  2774. rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
  2775. /* Enable Receive Checksum Offload for TCP and UDP */
  2776. rxcsum = er32(RXCSUM);
  2777. if (adapter->netdev->features & NETIF_F_RXCSUM)
  2778. rxcsum |= E1000_RXCSUM_TUOFL;
  2779. else
  2780. rxcsum &= ~E1000_RXCSUM_TUOFL;
  2781. ew32(RXCSUM, rxcsum);
  2782. /* With jumbo frames, excessive C-state transition latencies result
  2783. * in dropped transactions.
  2784. */
  2785. if (adapter->netdev->mtu > ETH_DATA_LEN) {
  2786. u32 lat =
  2787. ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
  2788. adapter->max_frame_size) * 8 / 1000;
  2789. if (adapter->flags & FLAG_IS_ICH) {
  2790. u32 rxdctl = er32(RXDCTL(0));
  2791. ew32(RXDCTL(0), rxdctl | 0x3);
  2792. }
  2793. pm_qos_update_request(&adapter->netdev->pm_qos_req, lat);
  2794. } else {
  2795. pm_qos_update_request(&adapter->netdev->pm_qos_req,
  2796. PM_QOS_DEFAULT_VALUE);
  2797. }
  2798. /* Enable Receives */
  2799. ew32(RCTL, rctl);
  2800. }
  2801. /**
  2802. * e1000e_write_mc_addr_list - write multicast addresses to MTA
  2803. * @netdev: network interface device structure
  2804. *
  2805. * Writes multicast address list to the MTA hash table.
  2806. * Returns: -ENOMEM on failure
  2807. * 0 on no addresses written
  2808. * X on writing X addresses to MTA
  2809. */
  2810. static int e1000e_write_mc_addr_list(struct net_device *netdev)
  2811. {
  2812. struct e1000_adapter *adapter = netdev_priv(netdev);
  2813. struct e1000_hw *hw = &adapter->hw;
  2814. struct netdev_hw_addr *ha;
  2815. u8 *mta_list;
  2816. int i;
  2817. if (netdev_mc_empty(netdev)) {
  2818. /* nothing to program, so clear mc list */
  2819. hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
  2820. return 0;
  2821. }
  2822. mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
  2823. if (!mta_list)
  2824. return -ENOMEM;
  2825. /* update_mc_addr_list expects a packed array of only addresses. */
  2826. i = 0;
  2827. netdev_for_each_mc_addr(ha, netdev)
  2828. memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
  2829. hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
  2830. kfree(mta_list);
  2831. return netdev_mc_count(netdev);
  2832. }
  2833. /**
  2834. * e1000e_write_uc_addr_list - write unicast addresses to RAR table
  2835. * @netdev: network interface device structure
  2836. *
  2837. * Writes unicast address list to the RAR table.
  2838. * Returns: -ENOMEM on failure/insufficient address space
  2839. * 0 on no addresses written
  2840. * X on writing X addresses to the RAR table
  2841. **/
  2842. static int e1000e_write_uc_addr_list(struct net_device *netdev)
  2843. {
  2844. struct e1000_adapter *adapter = netdev_priv(netdev);
  2845. struct e1000_hw *hw = &adapter->hw;
  2846. unsigned int rar_entries = hw->mac.rar_entry_count;
  2847. int count = 0;
  2848. /* save a rar entry for our hardware address */
  2849. rar_entries--;
  2850. /* save a rar entry for the LAA workaround */
  2851. if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
  2852. rar_entries--;
  2853. /* return ENOMEM indicating insufficient memory for addresses */
  2854. if (netdev_uc_count(netdev) > rar_entries)
  2855. return -ENOMEM;
  2856. if (!netdev_uc_empty(netdev) && rar_entries) {
  2857. struct netdev_hw_addr *ha;
  2858. /* write the addresses in reverse order to avoid write
  2859. * combining
  2860. */
  2861. netdev_for_each_uc_addr(ha, netdev) {
  2862. if (!rar_entries)
  2863. break;
  2864. hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
  2865. count++;
  2866. }
  2867. }
  2868. /* zero out the remaining RAR entries not used above */
  2869. for (; rar_entries > 0; rar_entries--) {
  2870. ew32(RAH(rar_entries), 0);
  2871. ew32(RAL(rar_entries), 0);
  2872. }
  2873. e1e_flush();
  2874. return count;
  2875. }
  2876. /**
  2877. * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
  2878. * @netdev: network interface device structure
  2879. *
  2880. * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
  2881. * address list or the network interface flags are updated. This routine is
  2882. * responsible for configuring the hardware for proper unicast, multicast,
  2883. * promiscuous mode, and all-multi behavior.
  2884. **/
  2885. static void e1000e_set_rx_mode(struct net_device *netdev)
  2886. {
  2887. struct e1000_adapter *adapter = netdev_priv(netdev);
  2888. struct e1000_hw *hw = &adapter->hw;
  2889. u32 rctl;
  2890. /* Check for Promiscuous and All Multicast modes */
  2891. rctl = er32(RCTL);
  2892. /* clear the affected bits */
  2893. rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
  2894. if (netdev->flags & IFF_PROMISC) {
  2895. rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
  2896. /* Do not hardware filter VLANs in promisc mode */
  2897. e1000e_vlan_filter_disable(adapter);
  2898. } else {
  2899. int count;
  2900. if (netdev->flags & IFF_ALLMULTI) {
  2901. rctl |= E1000_RCTL_MPE;
  2902. } else {
  2903. /* Write addresses to the MTA, if the attempt fails
  2904. * then we should just turn on promiscuous mode so
  2905. * that we can at least receive multicast traffic
  2906. */
  2907. count = e1000e_write_mc_addr_list(netdev);
  2908. if (count < 0)
  2909. rctl |= E1000_RCTL_MPE;
  2910. }
  2911. e1000e_vlan_filter_enable(adapter);
  2912. /* Write addresses to available RAR registers, if there is not
  2913. * sufficient space to store all the addresses then enable
  2914. * unicast promiscuous mode
  2915. */
  2916. count = e1000e_write_uc_addr_list(netdev);
  2917. if (count < 0)
  2918. rctl |= E1000_RCTL_UPE;
  2919. }
  2920. ew32(RCTL, rctl);
  2921. if (netdev->features & NETIF_F_HW_VLAN_RX)
  2922. e1000e_vlan_strip_enable(adapter);
  2923. else
  2924. e1000e_vlan_strip_disable(adapter);
  2925. }
  2926. static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
  2927. {
  2928. struct e1000_hw *hw = &adapter->hw;
  2929. u32 mrqc, rxcsum;
  2930. int i;
  2931. static const u32 rsskey[10] = {
  2932. 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
  2933. 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
  2934. };
  2935. /* Fill out hash function seed */
  2936. for (i = 0; i < 10; i++)
  2937. ew32(RSSRK(i), rsskey[i]);
  2938. /* Direct all traffic to queue 0 */
  2939. for (i = 0; i < 32; i++)
  2940. ew32(RETA(i), 0);
  2941. /* Disable raw packet checksumming so that RSS hash is placed in
  2942. * descriptor on writeback.
  2943. */
  2944. rxcsum = er32(RXCSUM);
  2945. rxcsum |= E1000_RXCSUM_PCSD;
  2946. ew32(RXCSUM, rxcsum);
  2947. mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
  2948. E1000_MRQC_RSS_FIELD_IPV4_TCP |
  2949. E1000_MRQC_RSS_FIELD_IPV6 |
  2950. E1000_MRQC_RSS_FIELD_IPV6_TCP |
  2951. E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
  2952. ew32(MRQC, mrqc);
  2953. }
  2954. /**
  2955. * e1000e_get_base_timinca - get default SYSTIM time increment attributes
  2956. * @adapter: board private structure
  2957. * @timinca: pointer to returned time increment attributes
  2958. *
  2959. * Get attributes for incrementing the System Time Register SYSTIML/H at
  2960. * the default base frequency, and set the cyclecounter shift value.
  2961. **/
  2962. s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
  2963. {
  2964. struct e1000_hw *hw = &adapter->hw;
  2965. u32 incvalue, incperiod, shift;
  2966. /* Make sure clock is enabled on I217 before checking the frequency */
  2967. if ((hw->mac.type == e1000_pch_lpt) &&
  2968. !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
  2969. !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
  2970. u32 fextnvm7 = er32(FEXTNVM7);
  2971. if (!(fextnvm7 & (1 << 0))) {
  2972. ew32(FEXTNVM7, fextnvm7 | (1 << 0));
  2973. e1e_flush();
  2974. }
  2975. }
  2976. switch (hw->mac.type) {
  2977. case e1000_pch2lan:
  2978. case e1000_pch_lpt:
  2979. /* On I217, the clock frequency is 25MHz or 96MHz as
  2980. * indicated by the System Clock Frequency Indication
  2981. */
  2982. if ((hw->mac.type != e1000_pch_lpt) ||
  2983. (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) {
  2984. /* Stable 96MHz frequency */
  2985. incperiod = INCPERIOD_96MHz;
  2986. incvalue = INCVALUE_96MHz;
  2987. shift = INCVALUE_SHIFT_96MHz;
  2988. adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHz;
  2989. break;
  2990. }
  2991. /* fall-through */
  2992. case e1000_82574:
  2993. case e1000_82583:
  2994. /* Stable 25MHz frequency */
  2995. incperiod = INCPERIOD_25MHz;
  2996. incvalue = INCVALUE_25MHz;
  2997. shift = INCVALUE_SHIFT_25MHz;
  2998. adapter->cc.shift = shift;
  2999. break;
  3000. default:
  3001. return -EINVAL;
  3002. }
  3003. *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
  3004. ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
  3005. return 0;
  3006. }
  3007. /**
  3008. * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
  3009. * @adapter: board private structure
  3010. *
  3011. * Outgoing time stamping can be enabled and disabled. Play nice and
  3012. * disable it when requested, although it shouldn't cause any overhead
  3013. * when no packet needs it. At most one packet in the queue may be
  3014. * marked for time stamping, otherwise it would be impossible to tell
  3015. * for sure to which packet the hardware time stamp belongs.
  3016. *
  3017. * Incoming time stamping has to be configured via the hardware filters.
  3018. * Not all combinations are supported, in particular event type has to be
  3019. * specified. Matching the kind of event packet is not supported, with the
  3020. * exception of "all V2 events regardless of level 2 or 4".
  3021. **/
  3022. static int e1000e_config_hwtstamp(struct e1000_adapter *adapter)
  3023. {
  3024. struct e1000_hw *hw = &adapter->hw;
  3025. struct hwtstamp_config *config = &adapter->hwtstamp_config;
  3026. u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
  3027. u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
  3028. u32 rxmtrl = 0;
  3029. u16 rxudp = 0;
  3030. bool is_l4 = false;
  3031. bool is_l2 = false;
  3032. u32 regval;
  3033. s32 ret_val;
  3034. if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
  3035. return -EINVAL;
  3036. /* flags reserved for future extensions - must be zero */
  3037. if (config->flags)
  3038. return -EINVAL;
  3039. switch (config->tx_type) {
  3040. case HWTSTAMP_TX_OFF:
  3041. tsync_tx_ctl = 0;
  3042. break;
  3043. case HWTSTAMP_TX_ON:
  3044. break;
  3045. default:
  3046. return -ERANGE;
  3047. }
  3048. switch (config->rx_filter) {
  3049. case HWTSTAMP_FILTER_NONE:
  3050. tsync_rx_ctl = 0;
  3051. break;
  3052. case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
  3053. tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
  3054. rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
  3055. is_l4 = true;
  3056. break;
  3057. case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
  3058. tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
  3059. rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
  3060. is_l4 = true;
  3061. break;
  3062. case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
  3063. /* Also time stamps V2 L2 Path Delay Request/Response */
  3064. tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
  3065. rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
  3066. is_l2 = true;
  3067. break;
  3068. case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
  3069. /* Also time stamps V2 L2 Path Delay Request/Response. */
  3070. tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
  3071. rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
  3072. is_l2 = true;
  3073. break;
  3074. case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
  3075. /* Hardware cannot filter just V2 L4 Sync messages;
  3076. * fall-through to V2 (both L2 and L4) Sync.
  3077. */
  3078. case HWTSTAMP_FILTER_PTP_V2_SYNC:
  3079. /* Also time stamps V2 Path Delay Request/Response. */
  3080. tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
  3081. rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
  3082. is_l2 = true;
  3083. is_l4 = true;
  3084. break;
  3085. case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
  3086. /* Hardware cannot filter just V2 L4 Delay Request messages;
  3087. * fall-through to V2 (both L2 and L4) Delay Request.
  3088. */
  3089. case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
  3090. /* Also time stamps V2 Path Delay Request/Response. */
  3091. tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
  3092. rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
  3093. is_l2 = true;
  3094. is_l4 = true;
  3095. break;
  3096. case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
  3097. case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
  3098. /* Hardware cannot filter just V2 L4 or L2 Event messages;
  3099. * fall-through to all V2 (both L2 and L4) Events.
  3100. */
  3101. case HWTSTAMP_FILTER_PTP_V2_EVENT:
  3102. tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
  3103. config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
  3104. is_l2 = true;
  3105. is_l4 = true;
  3106. break;
  3107. case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
  3108. /* For V1, the hardware can only filter Sync messages or
  3109. * Delay Request messages but not both so fall-through to
  3110. * time stamp all packets.
  3111. */
  3112. case HWTSTAMP_FILTER_ALL:
  3113. is_l2 = true;
  3114. is_l4 = true;
  3115. tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
  3116. config->rx_filter = HWTSTAMP_FILTER_ALL;
  3117. break;
  3118. default:
  3119. return -ERANGE;
  3120. }
  3121. /* enable/disable Tx h/w time stamping */
  3122. regval = er32(TSYNCTXCTL);
  3123. regval &= ~E1000_TSYNCTXCTL_ENABLED;
  3124. regval |= tsync_tx_ctl;
  3125. ew32(TSYNCTXCTL, regval);
  3126. if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
  3127. (regval & E1000_TSYNCTXCTL_ENABLED)) {
  3128. e_err("Timesync Tx Control register not set as expected\n");
  3129. return -EAGAIN;
  3130. }
  3131. /* enable/disable Rx h/w time stamping */
  3132. regval = er32(TSYNCRXCTL);
  3133. regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
  3134. regval |= tsync_rx_ctl;
  3135. ew32(TSYNCRXCTL, regval);
  3136. if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
  3137. E1000_TSYNCRXCTL_TYPE_MASK)) !=
  3138. (regval & (E1000_TSYNCRXCTL_ENABLED |
  3139. E1000_TSYNCRXCTL_TYPE_MASK))) {
  3140. e_err("Timesync Rx Control register not set as expected\n");
  3141. return -EAGAIN;
  3142. }
  3143. /* L2: define ethertype filter for time stamped packets */
  3144. if (is_l2)
  3145. rxmtrl |= ETH_P_1588;
  3146. /* define which PTP packets get time stamped */
  3147. ew32(RXMTRL, rxmtrl);
  3148. /* Filter by destination port */
  3149. if (is_l4) {
  3150. rxudp = PTP_EV_PORT;
  3151. cpu_to_be16s(&rxudp);
  3152. }
  3153. ew32(RXUDP, rxudp);
  3154. e1e_flush();
  3155. /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
  3156. er32(RXSTMPH);
  3157. er32(TXSTMPH);
  3158. /* Get and set the System Time Register SYSTIM base frequency */
  3159. ret_val = e1000e_get_base_timinca(adapter, &regval);
  3160. if (ret_val)
  3161. return ret_val;
  3162. ew32(TIMINCA, regval);
  3163. /* reset the ns time counter */
  3164. timecounter_init(&adapter->tc, &adapter->cc,
  3165. ktime_to_ns(ktime_get_real()));
  3166. return 0;
  3167. }
  3168. /**
  3169. * e1000_configure - configure the hardware for Rx and Tx
  3170. * @adapter: private board structure
  3171. **/
  3172. static void e1000_configure(struct e1000_adapter *adapter)
  3173. {
  3174. struct e1000_ring *rx_ring = adapter->rx_ring;
  3175. e1000e_set_rx_mode(adapter->netdev);
  3176. e1000_restore_vlan(adapter);
  3177. e1000_init_manageability_pt(adapter);
  3178. e1000_configure_tx(adapter);
  3179. if (adapter->netdev->features & NETIF_F_RXHASH)
  3180. e1000e_setup_rss_hash(adapter);
  3181. e1000_setup_rctl(adapter);
  3182. e1000_configure_rx(adapter);
  3183. adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
  3184. }
  3185. /**
  3186. * e1000e_power_up_phy - restore link in case the phy was powered down
  3187. * @adapter: address of board private structure
  3188. *
  3189. * The phy may be powered down to save power and turn off link when the
  3190. * driver is unloaded and wake on lan is not enabled (among others)
  3191. * *** this routine MUST be followed by a call to e1000e_reset ***
  3192. **/
  3193. void e1000e_power_up_phy(struct e1000_adapter *adapter)
  3194. {
  3195. if (adapter->hw.phy.ops.power_up)
  3196. adapter->hw.phy.ops.power_up(&adapter->hw);
  3197. adapter->hw.mac.ops.setup_link(&adapter->hw);
  3198. }
  3199. /**
  3200. * e1000_power_down_phy - Power down the PHY
  3201. *
  3202. * Power down the PHY so no link is implied when interface is down.
  3203. * The PHY cannot be powered down if management or WoL is active.
  3204. */
  3205. static void e1000_power_down_phy(struct e1000_adapter *adapter)
  3206. {
  3207. /* WoL is enabled */
  3208. if (adapter->wol)
  3209. return;
  3210. if (adapter->hw.phy.ops.power_down)
  3211. adapter->hw.phy.ops.power_down(&adapter->hw);
  3212. }
  3213. /**
  3214. * e1000e_reset - bring the hardware into a known good state
  3215. *
  3216. * This function boots the hardware and enables some settings that
  3217. * require a configuration cycle of the hardware - those cannot be
  3218. * set/changed during runtime. After reset the device needs to be
  3219. * properly configured for Rx, Tx etc.
  3220. */
  3221. void e1000e_reset(struct e1000_adapter *adapter)
  3222. {
  3223. struct e1000_mac_info *mac = &adapter->hw.mac;
  3224. struct e1000_fc_info *fc = &adapter->hw.fc;
  3225. struct e1000_hw *hw = &adapter->hw;
  3226. u32 tx_space, min_tx_space, min_rx_space;
  3227. u32 pba = adapter->pba;
  3228. u16 hwm;
  3229. /* reset Packet Buffer Allocation to default */
  3230. ew32(PBA, pba);
  3231. if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
  3232. /* To maintain wire speed transmits, the Tx FIFO should be
  3233. * large enough to accommodate two full transmit packets,
  3234. * rounded up to the next 1KB and expressed in KB. Likewise,
  3235. * the Rx FIFO should be large enough to accommodate at least
  3236. * one full receive packet and is similarly rounded up and
  3237. * expressed in KB.
  3238. */
  3239. pba = er32(PBA);
  3240. /* upper 16 bits has Tx packet buffer allocation size in KB */
  3241. tx_space = pba >> 16;
  3242. /* lower 16 bits has Rx packet buffer allocation size in KB */
  3243. pba &= 0xffff;
  3244. /* the Tx fifo also stores 16 bytes of information about the Tx
  3245. * but don't include ethernet FCS because hardware appends it
  3246. */
  3247. min_tx_space = (adapter->max_frame_size +
  3248. sizeof(struct e1000_tx_desc) -
  3249. ETH_FCS_LEN) * 2;
  3250. min_tx_space = ALIGN(min_tx_space, 1024);
  3251. min_tx_space >>= 10;
  3252. /* software strips receive CRC, so leave room for it */
  3253. min_rx_space = adapter->max_frame_size;
  3254. min_rx_space = ALIGN(min_rx_space, 1024);
  3255. min_rx_space >>= 10;
  3256. /* If current Tx allocation is less than the min Tx FIFO size,
  3257. * and the min Tx FIFO size is less than the current Rx FIFO
  3258. * allocation, take space away from current Rx allocation
  3259. */
  3260. if ((tx_space < min_tx_space) &&
  3261. ((min_tx_space - tx_space) < pba)) {
  3262. pba -= min_tx_space - tx_space;
  3263. /* if short on Rx space, Rx wins and must trump Tx
  3264. * adjustment
  3265. */
  3266. if (pba < min_rx_space)
  3267. pba = min_rx_space;
  3268. }
  3269. ew32(PBA, pba);
  3270. }
  3271. /* flow control settings
  3272. *
  3273. * The high water mark must be low enough to fit one full frame
  3274. * (or the size used for early receive) above it in the Rx FIFO.
  3275. * Set it to the lower of:
  3276. * - 90% of the Rx FIFO size, and
  3277. * - the full Rx FIFO size minus one full frame
  3278. */
  3279. if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
  3280. fc->pause_time = 0xFFFF;
  3281. else
  3282. fc->pause_time = E1000_FC_PAUSE_TIME;
  3283. fc->send_xon = true;
  3284. fc->current_mode = fc->requested_mode;
  3285. switch (hw->mac.type) {
  3286. case e1000_ich9lan:
  3287. case e1000_ich10lan:
  3288. if (adapter->netdev->mtu > ETH_DATA_LEN) {
  3289. pba = 14;
  3290. ew32(PBA, pba);
  3291. fc->high_water = 0x2800;
  3292. fc->low_water = fc->high_water - 8;
  3293. break;
  3294. }
  3295. /* fall-through */
  3296. default:
  3297. hwm = min(((pba << 10) * 9 / 10),
  3298. ((pba << 10) - adapter->max_frame_size));
  3299. fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
  3300. fc->low_water = fc->high_water - 8;
  3301. break;
  3302. case e1000_pchlan:
  3303. /* Workaround PCH LOM adapter hangs with certain network
  3304. * loads. If hangs persist, try disabling Tx flow control.
  3305. */
  3306. if (adapter->netdev->mtu > ETH_DATA_LEN) {
  3307. fc->high_water = 0x3500;
  3308. fc->low_water = 0x1500;
  3309. } else {
  3310. fc->high_water = 0x5000;
  3311. fc->low_water = 0x3000;
  3312. }
  3313. fc->refresh_time = 0x1000;
  3314. break;
  3315. case e1000_pch2lan:
  3316. case e1000_pch_lpt:
  3317. fc->refresh_time = 0x0400;
  3318. if (adapter->netdev->mtu <= ETH_DATA_LEN) {
  3319. fc->high_water = 0x05C20;
  3320. fc->low_water = 0x05048;
  3321. fc->pause_time = 0x0650;
  3322. break;
  3323. }
  3324. fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
  3325. fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
  3326. break;
  3327. }
  3328. /* Alignment of Tx data is on an arbitrary byte boundary with the
  3329. * maximum size per Tx descriptor limited only to the transmit
  3330. * allocation of the packet buffer minus 96 bytes with an upper
  3331. * limit of 24KB due to receive synchronization limitations.
  3332. */
  3333. adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
  3334. 24 << 10);
  3335. /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
  3336. * fit in receive buffer.
  3337. */
  3338. if (adapter->itr_setting & 0x3) {
  3339. if ((adapter->max_frame_size * 2) > (pba << 10)) {
  3340. if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
  3341. dev_info(&adapter->pdev->dev,
  3342. "Interrupt Throttle Rate turned off\n");
  3343. adapter->flags2 |= FLAG2_DISABLE_AIM;
  3344. e1000e_write_itr(adapter, 0);
  3345. }
  3346. } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
  3347. dev_info(&adapter->pdev->dev,
  3348. "Interrupt Throttle Rate turned on\n");
  3349. adapter->flags2 &= ~FLAG2_DISABLE_AIM;
  3350. adapter->itr = 20000;
  3351. e1000e_write_itr(adapter, adapter->itr);
  3352. }
  3353. }
  3354. /* Allow time for pending master requests to run */
  3355. mac->ops.reset_hw(hw);
  3356. /* For parts with AMT enabled, let the firmware know
  3357. * that the network interface is in control
  3358. */
  3359. if (adapter->flags & FLAG_HAS_AMT)
  3360. e1000e_get_hw_control(adapter);
  3361. ew32(WUC, 0);
  3362. if (mac->ops.init_hw(hw))
  3363. e_err("Hardware Error\n");
  3364. e1000_update_mng_vlan(adapter);
  3365. /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
  3366. ew32(VET, ETH_P_8021Q);
  3367. e1000e_reset_adaptive(hw);
  3368. /* initialize systim and reset the ns time counter */
  3369. e1000e_config_hwtstamp(adapter);
  3370. if (!netif_running(adapter->netdev) &&
  3371. !test_bit(__E1000_TESTING, &adapter->state)) {
  3372. e1000_power_down_phy(adapter);
  3373. return;
  3374. }
  3375. e1000_get_phy_info(hw);
  3376. if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
  3377. !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
  3378. u16 phy_data = 0;
  3379. /* speed up time to link by disabling smart power down, ignore
  3380. * the return value of this function because there is nothing
  3381. * different we would do if it failed
  3382. */
  3383. e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
  3384. phy_data &= ~IGP02E1000_PM_SPD;
  3385. e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
  3386. }
  3387. }
  3388. int e1000e_up(struct e1000_adapter *adapter)
  3389. {
  3390. struct e1000_hw *hw = &adapter->hw;
  3391. /* hardware has been reset, we need to reload some things */
  3392. e1000_configure(adapter);
  3393. clear_bit(__E1000_DOWN, &adapter->state);
  3394. if (adapter->msix_entries)
  3395. e1000_configure_msix(adapter);
  3396. e1000_irq_enable(adapter);
  3397. netif_start_queue(adapter->netdev);
  3398. /* fire a link change interrupt to start the watchdog */
  3399. if (adapter->msix_entries)
  3400. ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
  3401. else
  3402. ew32(ICS, E1000_ICS_LSC);
  3403. return 0;
  3404. }
  3405. static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
  3406. {
  3407. struct e1000_hw *hw = &adapter->hw;
  3408. if (!(adapter->flags2 & FLAG2_DMA_BURST))
  3409. return;
  3410. /* flush pending descriptor writebacks to memory */
  3411. ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
  3412. ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
  3413. /* execute the writes immediately */
  3414. e1e_flush();
  3415. /* due to rare timing issues, write to TIDV/RDTR again to ensure the
  3416. * write is successful
  3417. */
  3418. ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
  3419. ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
  3420. /* execute the writes immediately */
  3421. e1e_flush();
  3422. }
  3423. static void e1000e_update_stats(struct e1000_adapter *adapter);
  3424. void e1000e_down(struct e1000_adapter *adapter)
  3425. {
  3426. struct net_device *netdev = adapter->netdev;
  3427. struct e1000_hw *hw = &adapter->hw;
  3428. u32 tctl, rctl;
  3429. /* signal that we're down so the interrupt handler does not
  3430. * reschedule our watchdog timer
  3431. */
  3432. set_bit(__E1000_DOWN, &adapter->state);
  3433. /* disable receives in the hardware */
  3434. rctl = er32(RCTL);
  3435. if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
  3436. ew32(RCTL, rctl & ~E1000_RCTL_EN);
  3437. /* flush and sleep below */
  3438. netif_stop_queue(netdev);
  3439. /* disable transmits in the hardware */
  3440. tctl = er32(TCTL);
  3441. tctl &= ~E1000_TCTL_EN;
  3442. ew32(TCTL, tctl);
  3443. /* flush both disables and wait for them to finish */
  3444. e1e_flush();
  3445. usleep_range(10000, 20000);
  3446. e1000_irq_disable(adapter);
  3447. del_timer_sync(&adapter->watchdog_timer);
  3448. del_timer_sync(&adapter->phy_info_timer);
  3449. netif_carrier_off(netdev);
  3450. spin_lock(&adapter->stats64_lock);
  3451. e1000e_update_stats(adapter);
  3452. spin_unlock(&adapter->stats64_lock);
  3453. e1000e_flush_descriptors(adapter);
  3454. e1000_clean_tx_ring(adapter->tx_ring);
  3455. e1000_clean_rx_ring(adapter->rx_ring);
  3456. adapter->link_speed = 0;
  3457. adapter->link_duplex = 0;
  3458. if (!pci_channel_offline(adapter->pdev))
  3459. e1000e_reset(adapter);
  3460. /* TODO: for power management, we could drop the link and
  3461. * pci_disable_device here.
  3462. */
  3463. }
  3464. void e1000e_reinit_locked(struct e1000_adapter *adapter)
  3465. {
  3466. might_sleep();
  3467. while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
  3468. usleep_range(1000, 2000);
  3469. e1000e_down(adapter);
  3470. e1000e_up(adapter);
  3471. clear_bit(__E1000_RESETTING, &adapter->state);
  3472. }
  3473. /**
  3474. * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
  3475. * @cc: cyclecounter structure
  3476. **/
  3477. static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc)
  3478. {
  3479. struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
  3480. cc);
  3481. struct e1000_hw *hw = &adapter->hw;
  3482. cycle_t systim;
  3483. /* latch SYSTIMH on read of SYSTIML */
  3484. systim = (cycle_t)er32(SYSTIML);
  3485. systim |= (cycle_t)er32(SYSTIMH) << 32;
  3486. return systim;
  3487. }
  3488. /**
  3489. * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
  3490. * @adapter: board private structure to initialize
  3491. *
  3492. * e1000_sw_init initializes the Adapter private data structure.
  3493. * Fields are initialized based on PCI device information and
  3494. * OS network device settings (MTU size).
  3495. **/
  3496. static int e1000_sw_init(struct e1000_adapter *adapter)
  3497. {
  3498. struct net_device *netdev = adapter->netdev;
  3499. adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
  3500. adapter->rx_ps_bsize0 = 128;
  3501. adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
  3502. adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
  3503. adapter->tx_ring_count = E1000_DEFAULT_TXD;
  3504. adapter->rx_ring_count = E1000_DEFAULT_RXD;
  3505. spin_lock_init(&adapter->stats64_lock);
  3506. e1000e_set_interrupt_capability(adapter);
  3507. if (e1000_alloc_queues(adapter))
  3508. return -ENOMEM;
  3509. /* Setup hardware time stamping cyclecounter */
  3510. if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
  3511. adapter->cc.read = e1000e_cyclecounter_read;
  3512. adapter->cc.mask = CLOCKSOURCE_MASK(64);
  3513. adapter->cc.mult = 1;
  3514. /* cc.shift set in e1000e_get_base_tininca() */
  3515. spin_lock_init(&adapter->systim_lock);
  3516. INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
  3517. }
  3518. /* Explicitly disable IRQ since the NIC can be in any state. */
  3519. e1000_irq_disable(adapter);
  3520. set_bit(__E1000_DOWN, &adapter->state);
  3521. return 0;
  3522. }
  3523. /**
  3524. * e1000_intr_msi_test - Interrupt Handler
  3525. * @irq: interrupt number
  3526. * @data: pointer to a network interface device structure
  3527. **/
  3528. static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
  3529. {
  3530. struct net_device *netdev = data;
  3531. struct e1000_adapter *adapter = netdev_priv(netdev);
  3532. struct e1000_hw *hw = &adapter->hw;
  3533. u32 icr = er32(ICR);
  3534. e_dbg("icr is %08X\n", icr);
  3535. if (icr & E1000_ICR_RXSEQ) {
  3536. adapter->flags &= ~FLAG_MSI_TEST_FAILED;
  3537. /* Force memory writes to complete before acknowledging the
  3538. * interrupt is handled.
  3539. */
  3540. wmb();
  3541. }
  3542. return IRQ_HANDLED;
  3543. }
  3544. /**
  3545. * e1000_test_msi_interrupt - Returns 0 for successful test
  3546. * @adapter: board private struct
  3547. *
  3548. * code flow taken from tg3.c
  3549. **/
  3550. static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
  3551. {
  3552. struct net_device *netdev = adapter->netdev;
  3553. struct e1000_hw *hw = &adapter->hw;
  3554. int err;
  3555. /* poll_enable hasn't been called yet, so don't need disable */
  3556. /* clear any pending events */
  3557. er32(ICR);
  3558. /* free the real vector and request a test handler */
  3559. e1000_free_irq(adapter);
  3560. e1000e_reset_interrupt_capability(adapter);
  3561. /* Assume that the test fails, if it succeeds then the test
  3562. * MSI irq handler will unset this flag
  3563. */
  3564. adapter->flags |= FLAG_MSI_TEST_FAILED;
  3565. err = pci_enable_msi(adapter->pdev);
  3566. if (err)
  3567. goto msi_test_failed;
  3568. err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
  3569. netdev->name, netdev);
  3570. if (err) {
  3571. pci_disable_msi(adapter->pdev);
  3572. goto msi_test_failed;
  3573. }
  3574. /* Force memory writes to complete before enabling and firing an
  3575. * interrupt.
  3576. */
  3577. wmb();
  3578. e1000_irq_enable(adapter);
  3579. /* fire an unusual interrupt on the test handler */
  3580. ew32(ICS, E1000_ICS_RXSEQ);
  3581. e1e_flush();
  3582. msleep(100);
  3583. e1000_irq_disable(adapter);
  3584. rmb(); /* read flags after interrupt has been fired */
  3585. if (adapter->flags & FLAG_MSI_TEST_FAILED) {
  3586. adapter->int_mode = E1000E_INT_MODE_LEGACY;
  3587. e_info("MSI interrupt test failed, using legacy interrupt.\n");
  3588. } else {
  3589. e_dbg("MSI interrupt test succeeded!\n");
  3590. }
  3591. free_irq(adapter->pdev->irq, netdev);
  3592. pci_disable_msi(adapter->pdev);
  3593. msi_test_failed:
  3594. e1000e_set_interrupt_capability(adapter);
  3595. return e1000_request_irq(adapter);
  3596. }
  3597. /**
  3598. * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
  3599. * @adapter: board private struct
  3600. *
  3601. * code flow taken from tg3.c, called with e1000 interrupts disabled.
  3602. **/
  3603. static int e1000_test_msi(struct e1000_adapter *adapter)
  3604. {
  3605. int err;
  3606. u16 pci_cmd;
  3607. if (!(adapter->flags & FLAG_MSI_ENABLED))
  3608. return 0;
  3609. /* disable SERR in case the MSI write causes a master abort */
  3610. pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
  3611. if (pci_cmd & PCI_COMMAND_SERR)
  3612. pci_write_config_word(adapter->pdev, PCI_COMMAND,
  3613. pci_cmd & ~PCI_COMMAND_SERR);
  3614. err = e1000_test_msi_interrupt(adapter);
  3615. /* re-enable SERR */
  3616. if (pci_cmd & PCI_COMMAND_SERR) {
  3617. pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
  3618. pci_cmd |= PCI_COMMAND_SERR;
  3619. pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
  3620. }
  3621. return err;
  3622. }
  3623. /**
  3624. * e1000_open - Called when a network interface is made active
  3625. * @netdev: network interface device structure
  3626. *
  3627. * Returns 0 on success, negative value on failure
  3628. *
  3629. * The open entry point is called when a network interface is made
  3630. * active by the system (IFF_UP). At this point all resources needed
  3631. * for transmit and receive operations are allocated, the interrupt
  3632. * handler is registered with the OS, the watchdog timer is started,
  3633. * and the stack is notified that the interface is ready.
  3634. **/
  3635. static int e1000_open(struct net_device *netdev)
  3636. {
  3637. struct e1000_adapter *adapter = netdev_priv(netdev);
  3638. struct e1000_hw *hw = &adapter->hw;
  3639. struct pci_dev *pdev = adapter->pdev;
  3640. int err;
  3641. /* disallow open during test */
  3642. if (test_bit(__E1000_TESTING, &adapter->state))
  3643. return -EBUSY;
  3644. pm_runtime_get_sync(&pdev->dev);
  3645. netif_carrier_off(netdev);
  3646. /* allocate transmit descriptors */
  3647. err = e1000e_setup_tx_resources(adapter->tx_ring);
  3648. if (err)
  3649. goto err_setup_tx;
  3650. /* allocate receive descriptors */
  3651. err = e1000e_setup_rx_resources(adapter->rx_ring);
  3652. if (err)
  3653. goto err_setup_rx;
  3654. /* If AMT is enabled, let the firmware know that the network
  3655. * interface is now open and reset the part to a known state.
  3656. */
  3657. if (adapter->flags & FLAG_HAS_AMT) {
  3658. e1000e_get_hw_control(adapter);
  3659. e1000e_reset(adapter);
  3660. }
  3661. e1000e_power_up_phy(adapter);
  3662. adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
  3663. if ((adapter->hw.mng_cookie.status &
  3664. E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
  3665. e1000_update_mng_vlan(adapter);
  3666. /* DMA latency requirement to workaround jumbo issue */
  3667. pm_qos_add_request(&adapter->netdev->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
  3668. PM_QOS_DEFAULT_VALUE);
  3669. /* before we allocate an interrupt, we must be ready to handle it.
  3670. * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
  3671. * as soon as we call pci_request_irq, so we have to setup our
  3672. * clean_rx handler before we do so.
  3673. */
  3674. e1000_configure(adapter);
  3675. err = e1000_request_irq(adapter);
  3676. if (err)
  3677. goto err_req_irq;
  3678. /* Work around PCIe errata with MSI interrupts causing some chipsets to
  3679. * ignore e1000e MSI messages, which means we need to test our MSI
  3680. * interrupt now
  3681. */
  3682. if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
  3683. err = e1000_test_msi(adapter);
  3684. if (err) {
  3685. e_err("Interrupt allocation failed\n");
  3686. goto err_req_irq;
  3687. }
  3688. }
  3689. /* From here on the code is the same as e1000e_up() */
  3690. clear_bit(__E1000_DOWN, &adapter->state);
  3691. napi_enable(&adapter->napi);
  3692. e1000_irq_enable(adapter);
  3693. adapter->tx_hang_recheck = false;
  3694. netif_start_queue(netdev);
  3695. adapter->idle_check = true;
  3696. pm_runtime_put(&pdev->dev);
  3697. /* fire a link status change interrupt to start the watchdog */
  3698. if (adapter->msix_entries)
  3699. ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
  3700. else
  3701. ew32(ICS, E1000_ICS_LSC);
  3702. return 0;
  3703. err_req_irq:
  3704. e1000e_release_hw_control(adapter);
  3705. e1000_power_down_phy(adapter);
  3706. e1000e_free_rx_resources(adapter->rx_ring);
  3707. err_setup_rx:
  3708. e1000e_free_tx_resources(adapter->tx_ring);
  3709. err_setup_tx:
  3710. e1000e_reset(adapter);
  3711. pm_runtime_put_sync(&pdev->dev);
  3712. return err;
  3713. }
  3714. /**
  3715. * e1000_close - Disables a network interface
  3716. * @netdev: network interface device structure
  3717. *
  3718. * Returns 0, this is not allowed to fail
  3719. *
  3720. * The close entry point is called when an interface is de-activated
  3721. * by the OS. The hardware is still under the drivers control, but
  3722. * needs to be disabled. A global MAC reset is issued to stop the
  3723. * hardware, and all transmit and receive resources are freed.
  3724. **/
  3725. static int e1000_close(struct net_device *netdev)
  3726. {
  3727. struct e1000_adapter *adapter = netdev_priv(netdev);
  3728. struct pci_dev *pdev = adapter->pdev;
  3729. int count = E1000_CHECK_RESET_COUNT;
  3730. while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
  3731. usleep_range(10000, 20000);
  3732. WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
  3733. pm_runtime_get_sync(&pdev->dev);
  3734. napi_disable(&adapter->napi);
  3735. if (!test_bit(__E1000_DOWN, &adapter->state)) {
  3736. e1000e_down(adapter);
  3737. e1000_free_irq(adapter);
  3738. }
  3739. e1000_power_down_phy(adapter);
  3740. e1000e_free_tx_resources(adapter->tx_ring);
  3741. e1000e_free_rx_resources(adapter->rx_ring);
  3742. /* kill manageability vlan ID if supported, but not if a vlan with
  3743. * the same ID is registered on the host OS (let 8021q kill it)
  3744. */
  3745. if (adapter->hw.mng_cookie.status &
  3746. E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
  3747. e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
  3748. /* If AMT is enabled, let the firmware know that the network
  3749. * interface is now closed
  3750. */
  3751. if ((adapter->flags & FLAG_HAS_AMT) &&
  3752. !test_bit(__E1000_TESTING, &adapter->state))
  3753. e1000e_release_hw_control(adapter);
  3754. pm_qos_remove_request(&adapter->netdev->pm_qos_req);
  3755. pm_runtime_put_sync(&pdev->dev);
  3756. return 0;
  3757. }
  3758. /**
  3759. * e1000_set_mac - Change the Ethernet Address of the NIC
  3760. * @netdev: network interface device structure
  3761. * @p: pointer to an address structure
  3762. *
  3763. * Returns 0 on success, negative on failure
  3764. **/
  3765. static int e1000_set_mac(struct net_device *netdev, void *p)
  3766. {
  3767. struct e1000_adapter *adapter = netdev_priv(netdev);
  3768. struct e1000_hw *hw = &adapter->hw;
  3769. struct sockaddr *addr = p;
  3770. if (!is_valid_ether_addr(addr->sa_data))
  3771. return -EADDRNOTAVAIL;
  3772. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  3773. memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
  3774. hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
  3775. if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
  3776. /* activate the work around */
  3777. e1000e_set_laa_state_82571(&adapter->hw, 1);
  3778. /* Hold a copy of the LAA in RAR[14] This is done so that
  3779. * between the time RAR[0] gets clobbered and the time it
  3780. * gets fixed (in e1000_watchdog), the actual LAA is in one
  3781. * of the RARs and no incoming packets directed to this port
  3782. * are dropped. Eventually the LAA will be in RAR[0] and
  3783. * RAR[14]
  3784. */
  3785. hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
  3786. adapter->hw.mac.rar_entry_count - 1);
  3787. }
  3788. return 0;
  3789. }
  3790. /**
  3791. * e1000e_update_phy_task - work thread to update phy
  3792. * @work: pointer to our work struct
  3793. *
  3794. * this worker thread exists because we must acquire a
  3795. * semaphore to read the phy, which we could msleep while
  3796. * waiting for it, and we can't msleep in a timer.
  3797. **/
  3798. static void e1000e_update_phy_task(struct work_struct *work)
  3799. {
  3800. struct e1000_adapter *adapter = container_of(work,
  3801. struct e1000_adapter, update_phy_task);
  3802. if (test_bit(__E1000_DOWN, &adapter->state))
  3803. return;
  3804. e1000_get_phy_info(&adapter->hw);
  3805. }
  3806. /**
  3807. * e1000_update_phy_info - timre call-back to update PHY info
  3808. * @data: pointer to adapter cast into an unsigned long
  3809. *
  3810. * Need to wait a few seconds after link up to get diagnostic information from
  3811. * the phy
  3812. **/
  3813. static void e1000_update_phy_info(unsigned long data)
  3814. {
  3815. struct e1000_adapter *adapter = (struct e1000_adapter *) data;
  3816. if (test_bit(__E1000_DOWN, &adapter->state))
  3817. return;
  3818. schedule_work(&adapter->update_phy_task);
  3819. }
  3820. /**
  3821. * e1000e_update_phy_stats - Update the PHY statistics counters
  3822. * @adapter: board private structure
  3823. *
  3824. * Read/clear the upper 16-bit PHY registers and read/accumulate lower
  3825. **/
  3826. static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
  3827. {
  3828. struct e1000_hw *hw = &adapter->hw;
  3829. s32 ret_val;
  3830. u16 phy_data;
  3831. ret_val = hw->phy.ops.acquire(hw);
  3832. if (ret_val)
  3833. return;
  3834. /* A page set is expensive so check if already on desired page.
  3835. * If not, set to the page with the PHY status registers.
  3836. */
  3837. hw->phy.addr = 1;
  3838. ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
  3839. &phy_data);
  3840. if (ret_val)
  3841. goto release;
  3842. if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
  3843. ret_val = hw->phy.ops.set_page(hw,
  3844. HV_STATS_PAGE << IGP_PAGE_SHIFT);
  3845. if (ret_val)
  3846. goto release;
  3847. }
  3848. /* Single Collision Count */
  3849. hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
  3850. ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
  3851. if (!ret_val)
  3852. adapter->stats.scc += phy_data;
  3853. /* Excessive Collision Count */
  3854. hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
  3855. ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
  3856. if (!ret_val)
  3857. adapter->stats.ecol += phy_data;
  3858. /* Multiple Collision Count */
  3859. hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
  3860. ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
  3861. if (!ret_val)
  3862. adapter->stats.mcc += phy_data;
  3863. /* Late Collision Count */
  3864. hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
  3865. ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
  3866. if (!ret_val)
  3867. adapter->stats.latecol += phy_data;
  3868. /* Collision Count - also used for adaptive IFS */
  3869. hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
  3870. ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
  3871. if (!ret_val)
  3872. hw->mac.collision_delta = phy_data;
  3873. /* Defer Count */
  3874. hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
  3875. ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
  3876. if (!ret_val)
  3877. adapter->stats.dc += phy_data;
  3878. /* Transmit with no CRS */
  3879. hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
  3880. ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
  3881. if (!ret_val)
  3882. adapter->stats.tncrs += phy_data;
  3883. release:
  3884. hw->phy.ops.release(hw);
  3885. }
  3886. /**
  3887. * e1000e_update_stats - Update the board statistics counters
  3888. * @adapter: board private structure
  3889. **/
  3890. static void e1000e_update_stats(struct e1000_adapter *adapter)
  3891. {
  3892. struct net_device *netdev = adapter->netdev;
  3893. struct e1000_hw *hw = &adapter->hw;
  3894. struct pci_dev *pdev = adapter->pdev;
  3895. /* Prevent stats update while adapter is being reset, or if the pci
  3896. * connection is down.
  3897. */
  3898. if (adapter->link_speed == 0)
  3899. return;
  3900. if (pci_channel_offline(pdev))
  3901. return;
  3902. adapter->stats.crcerrs += er32(CRCERRS);
  3903. adapter->stats.gprc += er32(GPRC);
  3904. adapter->stats.gorc += er32(GORCL);
  3905. er32(GORCH); /* Clear gorc */
  3906. adapter->stats.bprc += er32(BPRC);
  3907. adapter->stats.mprc += er32(MPRC);
  3908. adapter->stats.roc += er32(ROC);
  3909. adapter->stats.mpc += er32(MPC);
  3910. /* Half-duplex statistics */
  3911. if (adapter->link_duplex == HALF_DUPLEX) {
  3912. if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
  3913. e1000e_update_phy_stats(adapter);
  3914. } else {
  3915. adapter->stats.scc += er32(SCC);
  3916. adapter->stats.ecol += er32(ECOL);
  3917. adapter->stats.mcc += er32(MCC);
  3918. adapter->stats.latecol += er32(LATECOL);
  3919. adapter->stats.dc += er32(DC);
  3920. hw->mac.collision_delta = er32(COLC);
  3921. if ((hw->mac.type != e1000_82574) &&
  3922. (hw->mac.type != e1000_82583))
  3923. adapter->stats.tncrs += er32(TNCRS);
  3924. }
  3925. adapter->stats.colc += hw->mac.collision_delta;
  3926. }
  3927. adapter->stats.xonrxc += er32(XONRXC);
  3928. adapter->stats.xontxc += er32(XONTXC);
  3929. adapter->stats.xoffrxc += er32(XOFFRXC);
  3930. adapter->stats.xofftxc += er32(XOFFTXC);
  3931. adapter->stats.gptc += er32(GPTC);
  3932. adapter->stats.gotc += er32(GOTCL);
  3933. er32(GOTCH); /* Clear gotc */
  3934. adapter->stats.rnbc += er32(RNBC);
  3935. adapter->stats.ruc += er32(RUC);
  3936. adapter->stats.mptc += er32(MPTC);
  3937. adapter->stats.bptc += er32(BPTC);
  3938. /* used for adaptive IFS */
  3939. hw->mac.tx_packet_delta = er32(TPT);
  3940. adapter->stats.tpt += hw->mac.tx_packet_delta;
  3941. adapter->stats.algnerrc += er32(ALGNERRC);
  3942. adapter->stats.rxerrc += er32(RXERRC);
  3943. adapter->stats.cexterr += er32(CEXTERR);
  3944. adapter->stats.tsctc += er32(TSCTC);
  3945. adapter->stats.tsctfc += er32(TSCTFC);
  3946. /* Fill out the OS statistics structure */
  3947. netdev->stats.multicast = adapter->stats.mprc;
  3948. netdev->stats.collisions = adapter->stats.colc;
  3949. /* Rx Errors */
  3950. /* RLEC on some newer hardware can be incorrect so build
  3951. * our own version based on RUC and ROC
  3952. */
  3953. netdev->stats.rx_errors = adapter->stats.rxerrc +
  3954. adapter->stats.crcerrs + adapter->stats.algnerrc +
  3955. adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
  3956. netdev->stats.rx_length_errors = adapter->stats.ruc +
  3957. adapter->stats.roc;
  3958. netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
  3959. netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
  3960. netdev->stats.rx_missed_errors = adapter->stats.mpc;
  3961. /* Tx Errors */
  3962. netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
  3963. netdev->stats.tx_aborted_errors = adapter->stats.ecol;
  3964. netdev->stats.tx_window_errors = adapter->stats.latecol;
  3965. netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
  3966. /* Tx Dropped needs to be maintained elsewhere */
  3967. /* Management Stats */
  3968. adapter->stats.mgptc += er32(MGTPTC);
  3969. adapter->stats.mgprc += er32(MGTPRC);
  3970. adapter->stats.mgpdc += er32(MGTPDC);
  3971. /* Correctable ECC Errors */
  3972. if (hw->mac.type == e1000_pch_lpt) {
  3973. u32 pbeccsts = er32(PBECCSTS);
  3974. adapter->corr_errors +=
  3975. pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
  3976. adapter->uncorr_errors +=
  3977. (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
  3978. E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
  3979. }
  3980. }
  3981. /**
  3982. * e1000_phy_read_status - Update the PHY register status snapshot
  3983. * @adapter: board private structure
  3984. **/
  3985. static void e1000_phy_read_status(struct e1000_adapter *adapter)
  3986. {
  3987. struct e1000_hw *hw = &adapter->hw;
  3988. struct e1000_phy_regs *phy = &adapter->phy_regs;
  3989. if ((er32(STATUS) & E1000_STATUS_LU) &&
  3990. (adapter->hw.phy.media_type == e1000_media_type_copper)) {
  3991. int ret_val;
  3992. ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
  3993. ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
  3994. ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
  3995. ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
  3996. ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
  3997. ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
  3998. ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
  3999. ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
  4000. if (ret_val)
  4001. e_warn("Error reading PHY register\n");
  4002. } else {
  4003. /* Do not read PHY registers if link is not up
  4004. * Set values to typical power-on defaults
  4005. */
  4006. phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
  4007. phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
  4008. BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
  4009. BMSR_ERCAP);
  4010. phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
  4011. ADVERTISE_ALL | ADVERTISE_CSMA);
  4012. phy->lpa = 0;
  4013. phy->expansion = EXPANSION_ENABLENPAGE;
  4014. phy->ctrl1000 = ADVERTISE_1000FULL;
  4015. phy->stat1000 = 0;
  4016. phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
  4017. }
  4018. }
  4019. static void e1000_print_link_info(struct e1000_adapter *adapter)
  4020. {
  4021. struct e1000_hw *hw = &adapter->hw;
  4022. u32 ctrl = er32(CTRL);
  4023. /* Link status message must follow this format for user tools */
  4024. pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
  4025. adapter->netdev->name, adapter->link_speed,
  4026. adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
  4027. (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
  4028. (ctrl & E1000_CTRL_RFCE) ? "Rx" :
  4029. (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
  4030. }
  4031. static bool e1000e_has_link(struct e1000_adapter *adapter)
  4032. {
  4033. struct e1000_hw *hw = &adapter->hw;
  4034. bool link_active = false;
  4035. s32 ret_val = 0;
  4036. /* get_link_status is set on LSC (link status) interrupt or
  4037. * Rx sequence error interrupt. get_link_status will stay
  4038. * false until the check_for_link establishes link
  4039. * for copper adapters ONLY
  4040. */
  4041. switch (hw->phy.media_type) {
  4042. case e1000_media_type_copper:
  4043. if (hw->mac.get_link_status) {
  4044. ret_val = hw->mac.ops.check_for_link(hw);
  4045. link_active = !hw->mac.get_link_status;
  4046. } else {
  4047. link_active = true;
  4048. }
  4049. break;
  4050. case e1000_media_type_fiber:
  4051. ret_val = hw->mac.ops.check_for_link(hw);
  4052. link_active = !!(er32(STATUS) & E1000_STATUS_LU);
  4053. break;
  4054. case e1000_media_type_internal_serdes:
  4055. ret_val = hw->mac.ops.check_for_link(hw);
  4056. link_active = adapter->hw.mac.serdes_has_link;
  4057. break;
  4058. default:
  4059. case e1000_media_type_unknown:
  4060. break;
  4061. }
  4062. if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
  4063. (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
  4064. /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
  4065. e_info("Gigabit has been disabled, downgrading speed\n");
  4066. }
  4067. return link_active;
  4068. }
  4069. static void e1000e_enable_receives(struct e1000_adapter *adapter)
  4070. {
  4071. /* make sure the receive unit is started */
  4072. if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
  4073. (adapter->flags & FLAG_RESTART_NOW)) {
  4074. struct e1000_hw *hw = &adapter->hw;
  4075. u32 rctl = er32(RCTL);
  4076. ew32(RCTL, rctl | E1000_RCTL_EN);
  4077. adapter->flags &= ~FLAG_RESTART_NOW;
  4078. }
  4079. }
  4080. static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
  4081. {
  4082. struct e1000_hw *hw = &adapter->hw;
  4083. /* With 82574 controllers, PHY needs to be checked periodically
  4084. * for hung state and reset, if two calls return true
  4085. */
  4086. if (e1000_check_phy_82574(hw))
  4087. adapter->phy_hang_count++;
  4088. else
  4089. adapter->phy_hang_count = 0;
  4090. if (adapter->phy_hang_count > 1) {
  4091. adapter->phy_hang_count = 0;
  4092. schedule_work(&adapter->reset_task);
  4093. }
  4094. }
  4095. /**
  4096. * e1000_watchdog - Timer Call-back
  4097. * @data: pointer to adapter cast into an unsigned long
  4098. **/
  4099. static void e1000_watchdog(unsigned long data)
  4100. {
  4101. struct e1000_adapter *adapter = (struct e1000_adapter *) data;
  4102. /* Do the rest outside of interrupt context */
  4103. schedule_work(&adapter->watchdog_task);
  4104. /* TODO: make this use queue_delayed_work() */
  4105. }
  4106. static void e1000_watchdog_task(struct work_struct *work)
  4107. {
  4108. struct e1000_adapter *adapter = container_of(work,
  4109. struct e1000_adapter, watchdog_task);
  4110. struct net_device *netdev = adapter->netdev;
  4111. struct e1000_mac_info *mac = &adapter->hw.mac;
  4112. struct e1000_phy_info *phy = &adapter->hw.phy;
  4113. struct e1000_ring *tx_ring = adapter->tx_ring;
  4114. struct e1000_hw *hw = &adapter->hw;
  4115. u32 link, tctl;
  4116. if (test_bit(__E1000_DOWN, &adapter->state))
  4117. return;
  4118. link = e1000e_has_link(adapter);
  4119. if ((netif_carrier_ok(netdev)) && link) {
  4120. /* Cancel scheduled suspend requests. */
  4121. pm_runtime_resume(netdev->dev.parent);
  4122. e1000e_enable_receives(adapter);
  4123. goto link_up;
  4124. }
  4125. if ((e1000e_enable_tx_pkt_filtering(hw)) &&
  4126. (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
  4127. e1000_update_mng_vlan(adapter);
  4128. if (link) {
  4129. if (!netif_carrier_ok(netdev)) {
  4130. bool txb2b = true;
  4131. /* Cancel scheduled suspend requests. */
  4132. pm_runtime_resume(netdev->dev.parent);
  4133. /* update snapshot of PHY registers on LSC */
  4134. e1000_phy_read_status(adapter);
  4135. mac->ops.get_link_up_info(&adapter->hw,
  4136. &adapter->link_speed,
  4137. &adapter->link_duplex);
  4138. e1000_print_link_info(adapter);
  4139. /* check if SmartSpeed worked */
  4140. e1000e_check_downshift(hw);
  4141. if (phy->speed_downgraded)
  4142. netdev_warn(netdev,
  4143. "Link Speed was downgraded by SmartSpeed\n");
  4144. /* On supported PHYs, check for duplex mismatch only
  4145. * if link has autonegotiated at 10/100 half
  4146. */
  4147. if ((hw->phy.type == e1000_phy_igp_3 ||
  4148. hw->phy.type == e1000_phy_bm) &&
  4149. (hw->mac.autoneg == true) &&
  4150. (adapter->link_speed == SPEED_10 ||
  4151. adapter->link_speed == SPEED_100) &&
  4152. (adapter->link_duplex == HALF_DUPLEX)) {
  4153. u16 autoneg_exp;
  4154. e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
  4155. if (!(autoneg_exp & EXPANSION_NWAY))
  4156. e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
  4157. }
  4158. /* adjust timeout factor according to speed/duplex */
  4159. adapter->tx_timeout_factor = 1;
  4160. switch (adapter->link_speed) {
  4161. case SPEED_10:
  4162. txb2b = false;
  4163. adapter->tx_timeout_factor = 16;
  4164. break;
  4165. case SPEED_100:
  4166. txb2b = false;
  4167. adapter->tx_timeout_factor = 10;
  4168. break;
  4169. }
  4170. /* workaround: re-program speed mode bit after
  4171. * link-up event
  4172. */
  4173. if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
  4174. !txb2b) {
  4175. u32 tarc0;
  4176. tarc0 = er32(TARC(0));
  4177. tarc0 &= ~SPEED_MODE_BIT;
  4178. ew32(TARC(0), tarc0);
  4179. }
  4180. /* disable TSO for pcie and 10/100 speeds, to avoid
  4181. * some hardware issues
  4182. */
  4183. if (!(adapter->flags & FLAG_TSO_FORCE)) {
  4184. switch (adapter->link_speed) {
  4185. case SPEED_10:
  4186. case SPEED_100:
  4187. e_info("10/100 speed: disabling TSO\n");
  4188. netdev->features &= ~NETIF_F_TSO;
  4189. netdev->features &= ~NETIF_F_TSO6;
  4190. break;
  4191. case SPEED_1000:
  4192. netdev->features |= NETIF_F_TSO;
  4193. netdev->features |= NETIF_F_TSO6;
  4194. break;
  4195. default:
  4196. /* oops */
  4197. break;
  4198. }
  4199. }
  4200. /* enable transmits in the hardware, need to do this
  4201. * after setting TARC(0)
  4202. */
  4203. tctl = er32(TCTL);
  4204. tctl |= E1000_TCTL_EN;
  4205. ew32(TCTL, tctl);
  4206. /* Perform any post-link-up configuration before
  4207. * reporting link up.
  4208. */
  4209. if (phy->ops.cfg_on_link_up)
  4210. phy->ops.cfg_on_link_up(hw);
  4211. netif_carrier_on(netdev);
  4212. if (!test_bit(__E1000_DOWN, &adapter->state))
  4213. mod_timer(&adapter->phy_info_timer,
  4214. round_jiffies(jiffies + 2 * HZ));
  4215. }
  4216. } else {
  4217. if (netif_carrier_ok(netdev)) {
  4218. adapter->link_speed = 0;
  4219. adapter->link_duplex = 0;
  4220. /* Link status message must follow this format */
  4221. pr_info("%s NIC Link is Down\n", adapter->netdev->name);
  4222. netif_carrier_off(netdev);
  4223. if (!test_bit(__E1000_DOWN, &adapter->state))
  4224. mod_timer(&adapter->phy_info_timer,
  4225. round_jiffies(jiffies + 2 * HZ));
  4226. /* The link is lost so the controller stops DMA.
  4227. * If there is queued Tx work that cannot be done
  4228. * or if on an 8000ES2LAN which requires a Rx packet
  4229. * buffer work-around on link down event, reset the
  4230. * controller to flush the Tx/Rx packet buffers.
  4231. * (Do the reset outside of interrupt context).
  4232. */
  4233. if ((adapter->flags & FLAG_RX_NEEDS_RESTART) ||
  4234. (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
  4235. adapter->flags |= FLAG_RESTART_NOW;
  4236. else
  4237. pm_schedule_suspend(netdev->dev.parent,
  4238. LINK_TIMEOUT);
  4239. }
  4240. }
  4241. link_up:
  4242. spin_lock(&adapter->stats64_lock);
  4243. e1000e_update_stats(adapter);
  4244. mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
  4245. adapter->tpt_old = adapter->stats.tpt;
  4246. mac->collision_delta = adapter->stats.colc - adapter->colc_old;
  4247. adapter->colc_old = adapter->stats.colc;
  4248. adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
  4249. adapter->gorc_old = adapter->stats.gorc;
  4250. adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
  4251. adapter->gotc_old = adapter->stats.gotc;
  4252. spin_unlock(&adapter->stats64_lock);
  4253. if (adapter->flags & FLAG_RESTART_NOW) {
  4254. schedule_work(&adapter->reset_task);
  4255. /* return immediately since reset is imminent */
  4256. return;
  4257. }
  4258. e1000e_update_adaptive(&adapter->hw);
  4259. /* Simple mode for Interrupt Throttle Rate (ITR) */
  4260. if (adapter->itr_setting == 4) {
  4261. /* Symmetric Tx/Rx gets a reduced ITR=2000;
  4262. * Total asymmetrical Tx or Rx gets ITR=8000;
  4263. * everyone else is between 2000-8000.
  4264. */
  4265. u32 goc = (adapter->gotc + adapter->gorc) / 10000;
  4266. u32 dif = (adapter->gotc > adapter->gorc ?
  4267. adapter->gotc - adapter->gorc :
  4268. adapter->gorc - adapter->gotc) / 10000;
  4269. u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
  4270. e1000e_write_itr(adapter, itr);
  4271. }
  4272. /* Cause software interrupt to ensure Rx ring is cleaned */
  4273. if (adapter->msix_entries)
  4274. ew32(ICS, adapter->rx_ring->ims_val);
  4275. else
  4276. ew32(ICS, E1000_ICS_RXDMT0);
  4277. /* flush pending descriptors to memory before detecting Tx hang */
  4278. e1000e_flush_descriptors(adapter);
  4279. /* Force detection of hung controller every watchdog period */
  4280. adapter->detect_tx_hung = true;
  4281. /* With 82571 controllers, LAA may be overwritten due to controller
  4282. * reset from the other port. Set the appropriate LAA in RAR[0]
  4283. */
  4284. if (e1000e_get_laa_state_82571(hw))
  4285. hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
  4286. if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
  4287. e1000e_check_82574_phy_workaround(adapter);
  4288. /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
  4289. if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
  4290. if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
  4291. (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
  4292. er32(RXSTMPH);
  4293. adapter->rx_hwtstamp_cleared++;
  4294. } else {
  4295. adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
  4296. }
  4297. }
  4298. /* Reset the timer */
  4299. if (!test_bit(__E1000_DOWN, &adapter->state))
  4300. mod_timer(&adapter->watchdog_timer,
  4301. round_jiffies(jiffies + 2 * HZ));
  4302. }
  4303. #define E1000_TX_FLAGS_CSUM 0x00000001
  4304. #define E1000_TX_FLAGS_VLAN 0x00000002
  4305. #define E1000_TX_FLAGS_TSO 0x00000004
  4306. #define E1000_TX_FLAGS_IPV4 0x00000008
  4307. #define E1000_TX_FLAGS_NO_FCS 0x00000010
  4308. #define E1000_TX_FLAGS_HWTSTAMP 0x00000020
  4309. #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
  4310. #define E1000_TX_FLAGS_VLAN_SHIFT 16
  4311. static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
  4312. {
  4313. struct e1000_context_desc *context_desc;
  4314. struct e1000_buffer *buffer_info;
  4315. unsigned int i;
  4316. u32 cmd_length = 0;
  4317. u16 ipcse = 0, mss;
  4318. u8 ipcss, ipcso, tucss, tucso, hdr_len;
  4319. if (!skb_is_gso(skb))
  4320. return 0;
  4321. if (skb_header_cloned(skb)) {
  4322. int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
  4323. if (err)
  4324. return err;
  4325. }
  4326. hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  4327. mss = skb_shinfo(skb)->gso_size;
  4328. if (skb->protocol == htons(ETH_P_IP)) {
  4329. struct iphdr *iph = ip_hdr(skb);
  4330. iph->tot_len = 0;
  4331. iph->check = 0;
  4332. tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
  4333. 0, IPPROTO_TCP, 0);
  4334. cmd_length = E1000_TXD_CMD_IP;
  4335. ipcse = skb_transport_offset(skb) - 1;
  4336. } else if (skb_is_gso_v6(skb)) {
  4337. ipv6_hdr(skb)->payload_len = 0;
  4338. tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
  4339. &ipv6_hdr(skb)->daddr,
  4340. 0, IPPROTO_TCP, 0);
  4341. ipcse = 0;
  4342. }
  4343. ipcss = skb_network_offset(skb);
  4344. ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
  4345. tucss = skb_transport_offset(skb);
  4346. tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
  4347. cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
  4348. E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
  4349. i = tx_ring->next_to_use;
  4350. context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
  4351. buffer_info = &tx_ring->buffer_info[i];
  4352. context_desc->lower_setup.ip_fields.ipcss = ipcss;
  4353. context_desc->lower_setup.ip_fields.ipcso = ipcso;
  4354. context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
  4355. context_desc->upper_setup.tcp_fields.tucss = tucss;
  4356. context_desc->upper_setup.tcp_fields.tucso = tucso;
  4357. context_desc->upper_setup.tcp_fields.tucse = 0;
  4358. context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
  4359. context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
  4360. context_desc->cmd_and_length = cpu_to_le32(cmd_length);
  4361. buffer_info->time_stamp = jiffies;
  4362. buffer_info->next_to_watch = i;
  4363. i++;
  4364. if (i == tx_ring->count)
  4365. i = 0;
  4366. tx_ring->next_to_use = i;
  4367. return 1;
  4368. }
  4369. static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
  4370. {
  4371. struct e1000_adapter *adapter = tx_ring->adapter;
  4372. struct e1000_context_desc *context_desc;
  4373. struct e1000_buffer *buffer_info;
  4374. unsigned int i;
  4375. u8 css;
  4376. u32 cmd_len = E1000_TXD_CMD_DEXT;
  4377. __be16 protocol;
  4378. if (skb->ip_summed != CHECKSUM_PARTIAL)
  4379. return 0;
  4380. if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
  4381. protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
  4382. else
  4383. protocol = skb->protocol;
  4384. switch (protocol) {
  4385. case cpu_to_be16(ETH_P_IP):
  4386. if (ip_hdr(skb)->protocol == IPPROTO_TCP)
  4387. cmd_len |= E1000_TXD_CMD_TCP;
  4388. break;
  4389. case cpu_to_be16(ETH_P_IPV6):
  4390. /* XXX not handling all IPV6 headers */
  4391. if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
  4392. cmd_len |= E1000_TXD_CMD_TCP;
  4393. break;
  4394. default:
  4395. if (unlikely(net_ratelimit()))
  4396. e_warn("checksum_partial proto=%x!\n",
  4397. be16_to_cpu(protocol));
  4398. break;
  4399. }
  4400. css = skb_checksum_start_offset(skb);
  4401. i = tx_ring->next_to_use;
  4402. buffer_info = &tx_ring->buffer_info[i];
  4403. context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
  4404. context_desc->lower_setup.ip_config = 0;
  4405. context_desc->upper_setup.tcp_fields.tucss = css;
  4406. context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
  4407. context_desc->upper_setup.tcp_fields.tucse = 0;
  4408. context_desc->tcp_seg_setup.data = 0;
  4409. context_desc->cmd_and_length = cpu_to_le32(cmd_len);
  4410. buffer_info->time_stamp = jiffies;
  4411. buffer_info->next_to_watch = i;
  4412. i++;
  4413. if (i == tx_ring->count)
  4414. i = 0;
  4415. tx_ring->next_to_use = i;
  4416. return 1;
  4417. }
  4418. static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
  4419. unsigned int first, unsigned int max_per_txd,
  4420. unsigned int nr_frags)
  4421. {
  4422. struct e1000_adapter *adapter = tx_ring->adapter;
  4423. struct pci_dev *pdev = adapter->pdev;
  4424. struct e1000_buffer *buffer_info;
  4425. unsigned int len = skb_headlen(skb);
  4426. unsigned int offset = 0, size, count = 0, i;
  4427. unsigned int f, bytecount, segs;
  4428. i = tx_ring->next_to_use;
  4429. while (len) {
  4430. buffer_info = &tx_ring->buffer_info[i];
  4431. size = min(len, max_per_txd);
  4432. buffer_info->length = size;
  4433. buffer_info->time_stamp = jiffies;
  4434. buffer_info->next_to_watch = i;
  4435. buffer_info->dma = dma_map_single(&pdev->dev,
  4436. skb->data + offset,
  4437. size, DMA_TO_DEVICE);
  4438. buffer_info->mapped_as_page = false;
  4439. if (dma_mapping_error(&pdev->dev, buffer_info->dma))
  4440. goto dma_error;
  4441. len -= size;
  4442. offset += size;
  4443. count++;
  4444. if (len) {
  4445. i++;
  4446. if (i == tx_ring->count)
  4447. i = 0;
  4448. }
  4449. }
  4450. for (f = 0; f < nr_frags; f++) {
  4451. const struct skb_frag_struct *frag;
  4452. frag = &skb_shinfo(skb)->frags[f];
  4453. len = skb_frag_size(frag);
  4454. offset = 0;
  4455. while (len) {
  4456. i++;
  4457. if (i == tx_ring->count)
  4458. i = 0;
  4459. buffer_info = &tx_ring->buffer_info[i];
  4460. size = min(len, max_per_txd);
  4461. buffer_info->length = size;
  4462. buffer_info->time_stamp = jiffies;
  4463. buffer_info->next_to_watch = i;
  4464. buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
  4465. offset, size, DMA_TO_DEVICE);
  4466. buffer_info->mapped_as_page = true;
  4467. if (dma_mapping_error(&pdev->dev, buffer_info->dma))
  4468. goto dma_error;
  4469. len -= size;
  4470. offset += size;
  4471. count++;
  4472. }
  4473. }
  4474. segs = skb_shinfo(skb)->gso_segs ? : 1;
  4475. /* multiply data chunks by size of headers */
  4476. bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
  4477. tx_ring->buffer_info[i].skb = skb;
  4478. tx_ring->buffer_info[i].segs = segs;
  4479. tx_ring->buffer_info[i].bytecount = bytecount;
  4480. tx_ring->buffer_info[first].next_to_watch = i;
  4481. return count;
  4482. dma_error:
  4483. dev_err(&pdev->dev, "Tx DMA map failed\n");
  4484. buffer_info->dma = 0;
  4485. if (count)
  4486. count--;
  4487. while (count--) {
  4488. if (i == 0)
  4489. i += tx_ring->count;
  4490. i--;
  4491. buffer_info = &tx_ring->buffer_info[i];
  4492. e1000_put_txbuf(tx_ring, buffer_info);
  4493. }
  4494. return 0;
  4495. }
  4496. static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
  4497. {
  4498. struct e1000_adapter *adapter = tx_ring->adapter;
  4499. struct e1000_tx_desc *tx_desc = NULL;
  4500. struct e1000_buffer *buffer_info;
  4501. u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
  4502. unsigned int i;
  4503. if (tx_flags & E1000_TX_FLAGS_TSO) {
  4504. txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
  4505. E1000_TXD_CMD_TSE;
  4506. txd_upper |= E1000_TXD_POPTS_TXSM << 8;
  4507. if (tx_flags & E1000_TX_FLAGS_IPV4)
  4508. txd_upper |= E1000_TXD_POPTS_IXSM << 8;
  4509. }
  4510. if (tx_flags & E1000_TX_FLAGS_CSUM) {
  4511. txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
  4512. txd_upper |= E1000_TXD_POPTS_TXSM << 8;
  4513. }
  4514. if (tx_flags & E1000_TX_FLAGS_VLAN) {
  4515. txd_lower |= E1000_TXD_CMD_VLE;
  4516. txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
  4517. }
  4518. if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
  4519. txd_lower &= ~(E1000_TXD_CMD_IFCS);
  4520. if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
  4521. txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
  4522. txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
  4523. }
  4524. i = tx_ring->next_to_use;
  4525. do {
  4526. buffer_info = &tx_ring->buffer_info[i];
  4527. tx_desc = E1000_TX_DESC(*tx_ring, i);
  4528. tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
  4529. tx_desc->lower.data = cpu_to_le32(txd_lower |
  4530. buffer_info->length);
  4531. tx_desc->upper.data = cpu_to_le32(txd_upper);
  4532. i++;
  4533. if (i == tx_ring->count)
  4534. i = 0;
  4535. } while (--count > 0);
  4536. tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
  4537. /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
  4538. if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
  4539. tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
  4540. /* Force memory writes to complete before letting h/w
  4541. * know there are new descriptors to fetch. (Only
  4542. * applicable for weak-ordered memory model archs,
  4543. * such as IA-64).
  4544. */
  4545. wmb();
  4546. tx_ring->next_to_use = i;
  4547. if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
  4548. e1000e_update_tdt_wa(tx_ring, i);
  4549. else
  4550. writel(i, tx_ring->tail);
  4551. /* we need this if more than one processor can write to our tail
  4552. * at a time, it synchronizes IO on IA64/Altix systems
  4553. */
  4554. mmiowb();
  4555. }
  4556. #define MINIMUM_DHCP_PACKET_SIZE 282
  4557. static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
  4558. struct sk_buff *skb)
  4559. {
  4560. struct e1000_hw *hw = &adapter->hw;
  4561. u16 length, offset;
  4562. if (vlan_tx_tag_present(skb) &&
  4563. !((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
  4564. (adapter->hw.mng_cookie.status &
  4565. E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
  4566. return 0;
  4567. if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
  4568. return 0;
  4569. if (((struct ethhdr *) skb->data)->h_proto != htons(ETH_P_IP))
  4570. return 0;
  4571. {
  4572. const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14);
  4573. struct udphdr *udp;
  4574. if (ip->protocol != IPPROTO_UDP)
  4575. return 0;
  4576. udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
  4577. if (ntohs(udp->dest) != 67)
  4578. return 0;
  4579. offset = (u8 *)udp + 8 - skb->data;
  4580. length = skb->len - offset;
  4581. return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
  4582. }
  4583. return 0;
  4584. }
  4585. static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
  4586. {
  4587. struct e1000_adapter *adapter = tx_ring->adapter;
  4588. netif_stop_queue(adapter->netdev);
  4589. /* Herbert's original patch had:
  4590. * smp_mb__after_netif_stop_queue();
  4591. * but since that doesn't exist yet, just open code it.
  4592. */
  4593. smp_mb();
  4594. /* We need to check again in a case another CPU has just
  4595. * made room available.
  4596. */
  4597. if (e1000_desc_unused(tx_ring) < size)
  4598. return -EBUSY;
  4599. /* A reprieve! */
  4600. netif_start_queue(adapter->netdev);
  4601. ++adapter->restart_queue;
  4602. return 0;
  4603. }
  4604. static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
  4605. {
  4606. BUG_ON(size > tx_ring->count);
  4607. if (e1000_desc_unused(tx_ring) >= size)
  4608. return 0;
  4609. return __e1000_maybe_stop_tx(tx_ring, size);
  4610. }
  4611. static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
  4612. struct net_device *netdev)
  4613. {
  4614. struct e1000_adapter *adapter = netdev_priv(netdev);
  4615. struct e1000_ring *tx_ring = adapter->tx_ring;
  4616. unsigned int first;
  4617. unsigned int tx_flags = 0;
  4618. unsigned int len = skb_headlen(skb);
  4619. unsigned int nr_frags;
  4620. unsigned int mss;
  4621. int count = 0;
  4622. int tso;
  4623. unsigned int f;
  4624. if (test_bit(__E1000_DOWN, &adapter->state)) {
  4625. dev_kfree_skb_any(skb);
  4626. return NETDEV_TX_OK;
  4627. }
  4628. if (skb->len <= 0) {
  4629. dev_kfree_skb_any(skb);
  4630. return NETDEV_TX_OK;
  4631. }
  4632. /* The minimum packet size with TCTL.PSP set is 17 bytes so
  4633. * pad skb in order to meet this minimum size requirement
  4634. */
  4635. if (unlikely(skb->len < 17)) {
  4636. if (skb_pad(skb, 17 - skb->len))
  4637. return NETDEV_TX_OK;
  4638. skb->len = 17;
  4639. skb_set_tail_pointer(skb, 17);
  4640. }
  4641. mss = skb_shinfo(skb)->gso_size;
  4642. if (mss) {
  4643. u8 hdr_len;
  4644. /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
  4645. * points to just header, pull a few bytes of payload from
  4646. * frags into skb->data
  4647. */
  4648. hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  4649. /* we do this workaround for ES2LAN, but it is un-necessary,
  4650. * avoiding it could save a lot of cycles
  4651. */
  4652. if (skb->data_len && (hdr_len == len)) {
  4653. unsigned int pull_size;
  4654. pull_size = min_t(unsigned int, 4, skb->data_len);
  4655. if (!__pskb_pull_tail(skb, pull_size)) {
  4656. e_err("__pskb_pull_tail failed.\n");
  4657. dev_kfree_skb_any(skb);
  4658. return NETDEV_TX_OK;
  4659. }
  4660. len = skb_headlen(skb);
  4661. }
  4662. }
  4663. /* reserve a descriptor for the offload context */
  4664. if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
  4665. count++;
  4666. count++;
  4667. count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
  4668. nr_frags = skb_shinfo(skb)->nr_frags;
  4669. for (f = 0; f < nr_frags; f++)
  4670. count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
  4671. adapter->tx_fifo_limit);
  4672. if (adapter->hw.mac.tx_pkt_filtering)
  4673. e1000_transfer_dhcp_info(adapter, skb);
  4674. /* need: count + 2 desc gap to keep tail from touching
  4675. * head, otherwise try next time
  4676. */
  4677. if (e1000_maybe_stop_tx(tx_ring, count + 2))
  4678. return NETDEV_TX_BUSY;
  4679. if (vlan_tx_tag_present(skb)) {
  4680. tx_flags |= E1000_TX_FLAGS_VLAN;
  4681. tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
  4682. }
  4683. first = tx_ring->next_to_use;
  4684. tso = e1000_tso(tx_ring, skb);
  4685. if (tso < 0) {
  4686. dev_kfree_skb_any(skb);
  4687. return NETDEV_TX_OK;
  4688. }
  4689. if (tso)
  4690. tx_flags |= E1000_TX_FLAGS_TSO;
  4691. else if (e1000_tx_csum(tx_ring, skb))
  4692. tx_flags |= E1000_TX_FLAGS_CSUM;
  4693. /* Old method was to assume IPv4 packet by default if TSO was enabled.
  4694. * 82571 hardware supports TSO capabilities for IPv6 as well...
  4695. * no longer assume, we must.
  4696. */
  4697. if (skb->protocol == htons(ETH_P_IP))
  4698. tx_flags |= E1000_TX_FLAGS_IPV4;
  4699. if (unlikely(skb->no_fcs))
  4700. tx_flags |= E1000_TX_FLAGS_NO_FCS;
  4701. /* if count is 0 then mapping error has occurred */
  4702. count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
  4703. nr_frags);
  4704. if (count) {
  4705. if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
  4706. !adapter->tx_hwtstamp_skb)) {
  4707. skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
  4708. tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
  4709. adapter->tx_hwtstamp_skb = skb_get(skb);
  4710. schedule_work(&adapter->tx_hwtstamp_work);
  4711. } else {
  4712. skb_tx_timestamp(skb);
  4713. }
  4714. netdev_sent_queue(netdev, skb->len);
  4715. e1000_tx_queue(tx_ring, tx_flags, count);
  4716. /* Make sure there is space in the ring for the next send. */
  4717. e1000_maybe_stop_tx(tx_ring,
  4718. (MAX_SKB_FRAGS *
  4719. DIV_ROUND_UP(PAGE_SIZE,
  4720. adapter->tx_fifo_limit) + 2));
  4721. } else {
  4722. dev_kfree_skb_any(skb);
  4723. tx_ring->buffer_info[first].time_stamp = 0;
  4724. tx_ring->next_to_use = first;
  4725. }
  4726. return NETDEV_TX_OK;
  4727. }
  4728. /**
  4729. * e1000_tx_timeout - Respond to a Tx Hang
  4730. * @netdev: network interface device structure
  4731. **/
  4732. static void e1000_tx_timeout(struct net_device *netdev)
  4733. {
  4734. struct e1000_adapter *adapter = netdev_priv(netdev);
  4735. /* Do the reset outside of interrupt context */
  4736. adapter->tx_timeout_count++;
  4737. schedule_work(&adapter->reset_task);
  4738. }
  4739. static void e1000_reset_task(struct work_struct *work)
  4740. {
  4741. struct e1000_adapter *adapter;
  4742. adapter = container_of(work, struct e1000_adapter, reset_task);
  4743. /* don't run the task if already down */
  4744. if (test_bit(__E1000_DOWN, &adapter->state))
  4745. return;
  4746. if (!(adapter->flags & FLAG_RESTART_NOW)) {
  4747. e1000e_dump(adapter);
  4748. e_err("Reset adapter unexpectedly\n");
  4749. }
  4750. e1000e_reinit_locked(adapter);
  4751. }
  4752. /**
  4753. * e1000_get_stats64 - Get System Network Statistics
  4754. * @netdev: network interface device structure
  4755. * @stats: rtnl_link_stats64 pointer
  4756. *
  4757. * Returns the address of the device statistics structure.
  4758. **/
  4759. struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
  4760. struct rtnl_link_stats64 *stats)
  4761. {
  4762. struct e1000_adapter *adapter = netdev_priv(netdev);
  4763. memset(stats, 0, sizeof(struct rtnl_link_stats64));
  4764. spin_lock(&adapter->stats64_lock);
  4765. e1000e_update_stats(adapter);
  4766. /* Fill out the OS statistics structure */
  4767. stats->rx_bytes = adapter->stats.gorc;
  4768. stats->rx_packets = adapter->stats.gprc;
  4769. stats->tx_bytes = adapter->stats.gotc;
  4770. stats->tx_packets = adapter->stats.gptc;
  4771. stats->multicast = adapter->stats.mprc;
  4772. stats->collisions = adapter->stats.colc;
  4773. /* Rx Errors */
  4774. /* RLEC on some newer hardware can be incorrect so build
  4775. * our own version based on RUC and ROC
  4776. */
  4777. stats->rx_errors = adapter->stats.rxerrc +
  4778. adapter->stats.crcerrs + adapter->stats.algnerrc +
  4779. adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
  4780. stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
  4781. stats->rx_crc_errors = adapter->stats.crcerrs;
  4782. stats->rx_frame_errors = adapter->stats.algnerrc;
  4783. stats->rx_missed_errors = adapter->stats.mpc;
  4784. /* Tx Errors */
  4785. stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
  4786. stats->tx_aborted_errors = adapter->stats.ecol;
  4787. stats->tx_window_errors = adapter->stats.latecol;
  4788. stats->tx_carrier_errors = adapter->stats.tncrs;
  4789. /* Tx Dropped needs to be maintained elsewhere */
  4790. spin_unlock(&adapter->stats64_lock);
  4791. return stats;
  4792. }
  4793. /**
  4794. * e1000_change_mtu - Change the Maximum Transfer Unit
  4795. * @netdev: network interface device structure
  4796. * @new_mtu: new value for maximum frame size
  4797. *
  4798. * Returns 0 on success, negative on failure
  4799. **/
  4800. static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
  4801. {
  4802. struct e1000_adapter *adapter = netdev_priv(netdev);
  4803. int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
  4804. /* Jumbo frame support */
  4805. if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) &&
  4806. !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
  4807. e_err("Jumbo Frames not supported.\n");
  4808. return -EINVAL;
  4809. }
  4810. /* Supported frame sizes */
  4811. if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
  4812. (max_frame > adapter->max_hw_frame_size)) {
  4813. e_err("Unsupported MTU setting\n");
  4814. return -EINVAL;
  4815. }
  4816. /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
  4817. if ((adapter->hw.mac.type >= e1000_pch2lan) &&
  4818. !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
  4819. (new_mtu > ETH_DATA_LEN)) {
  4820. e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
  4821. return -EINVAL;
  4822. }
  4823. while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
  4824. usleep_range(1000, 2000);
  4825. /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
  4826. adapter->max_frame_size = max_frame;
  4827. e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
  4828. netdev->mtu = new_mtu;
  4829. if (netif_running(netdev))
  4830. e1000e_down(adapter);
  4831. /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
  4832. * means we reserve 2 more, this pushes us to allocate from the next
  4833. * larger slab size.
  4834. * i.e. RXBUFFER_2048 --> size-4096 slab
  4835. * However with the new *_jumbo_rx* routines, jumbo receives will use
  4836. * fragmented skbs
  4837. */
  4838. if (max_frame <= 2048)
  4839. adapter->rx_buffer_len = 2048;
  4840. else
  4841. adapter->rx_buffer_len = 4096;
  4842. /* adjust allocation if LPE protects us, and we aren't using SBP */
  4843. if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
  4844. (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
  4845. adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
  4846. + ETH_FCS_LEN;
  4847. if (netif_running(netdev))
  4848. e1000e_up(adapter);
  4849. else
  4850. e1000e_reset(adapter);
  4851. clear_bit(__E1000_RESETTING, &adapter->state);
  4852. return 0;
  4853. }
  4854. static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
  4855. int cmd)
  4856. {
  4857. struct e1000_adapter *adapter = netdev_priv(netdev);
  4858. struct mii_ioctl_data *data = if_mii(ifr);
  4859. if (adapter->hw.phy.media_type != e1000_media_type_copper)
  4860. return -EOPNOTSUPP;
  4861. switch (cmd) {
  4862. case SIOCGMIIPHY:
  4863. data->phy_id = adapter->hw.phy.addr;
  4864. break;
  4865. case SIOCGMIIREG:
  4866. e1000_phy_read_status(adapter);
  4867. switch (data->reg_num & 0x1F) {
  4868. case MII_BMCR:
  4869. data->val_out = adapter->phy_regs.bmcr;
  4870. break;
  4871. case MII_BMSR:
  4872. data->val_out = adapter->phy_regs.bmsr;
  4873. break;
  4874. case MII_PHYSID1:
  4875. data->val_out = (adapter->hw.phy.id >> 16);
  4876. break;
  4877. case MII_PHYSID2:
  4878. data->val_out = (adapter->hw.phy.id & 0xFFFF);
  4879. break;
  4880. case MII_ADVERTISE:
  4881. data->val_out = adapter->phy_regs.advertise;
  4882. break;
  4883. case MII_LPA:
  4884. data->val_out = adapter->phy_regs.lpa;
  4885. break;
  4886. case MII_EXPANSION:
  4887. data->val_out = adapter->phy_regs.expansion;
  4888. break;
  4889. case MII_CTRL1000:
  4890. data->val_out = adapter->phy_regs.ctrl1000;
  4891. break;
  4892. case MII_STAT1000:
  4893. data->val_out = adapter->phy_regs.stat1000;
  4894. break;
  4895. case MII_ESTATUS:
  4896. data->val_out = adapter->phy_regs.estatus;
  4897. break;
  4898. default:
  4899. return -EIO;
  4900. }
  4901. break;
  4902. case SIOCSMIIREG:
  4903. default:
  4904. return -EOPNOTSUPP;
  4905. }
  4906. return 0;
  4907. }
  4908. /**
  4909. * e1000e_hwtstamp_ioctl - control hardware time stamping
  4910. * @netdev: network interface device structure
  4911. * @ifreq: interface request
  4912. *
  4913. * Outgoing time stamping can be enabled and disabled. Play nice and
  4914. * disable it when requested, although it shouldn't cause any overhead
  4915. * when no packet needs it. At most one packet in the queue may be
  4916. * marked for time stamping, otherwise it would be impossible to tell
  4917. * for sure to which packet the hardware time stamp belongs.
  4918. *
  4919. * Incoming time stamping has to be configured via the hardware filters.
  4920. * Not all combinations are supported, in particular event type has to be
  4921. * specified. Matching the kind of event packet is not supported, with the
  4922. * exception of "all V2 events regardless of level 2 or 4".
  4923. **/
  4924. static int e1000e_hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr)
  4925. {
  4926. struct e1000_adapter *adapter = netdev_priv(netdev);
  4927. struct hwtstamp_config config;
  4928. int ret_val;
  4929. if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
  4930. return -EFAULT;
  4931. adapter->hwtstamp_config = config;
  4932. ret_val = e1000e_config_hwtstamp(adapter);
  4933. if (ret_val)
  4934. return ret_val;
  4935. config = adapter->hwtstamp_config;
  4936. switch (config.rx_filter) {
  4937. case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
  4938. case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
  4939. case HWTSTAMP_FILTER_PTP_V2_SYNC:
  4940. case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
  4941. case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
  4942. case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
  4943. /* With V2 type filters which specify a Sync or Delay Request,
  4944. * Path Delay Request/Response messages are also time stamped
  4945. * by hardware so notify the caller the requested packets plus
  4946. * some others are time stamped.
  4947. */
  4948. config.rx_filter = HWTSTAMP_FILTER_SOME;
  4949. break;
  4950. default:
  4951. break;
  4952. }
  4953. return copy_to_user(ifr->ifr_data, &config,
  4954. sizeof(config)) ? -EFAULT : 0;
  4955. }
  4956. static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
  4957. {
  4958. switch (cmd) {
  4959. case SIOCGMIIPHY:
  4960. case SIOCGMIIREG:
  4961. case SIOCSMIIREG:
  4962. return e1000_mii_ioctl(netdev, ifr, cmd);
  4963. case SIOCSHWTSTAMP:
  4964. return e1000e_hwtstamp_ioctl(netdev, ifr);
  4965. default:
  4966. return -EOPNOTSUPP;
  4967. }
  4968. }
  4969. static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
  4970. {
  4971. struct e1000_hw *hw = &adapter->hw;
  4972. u32 i, mac_reg;
  4973. u16 phy_reg, wuc_enable;
  4974. int retval;
  4975. /* copy MAC RARs to PHY RARs */
  4976. e1000_copy_rx_addrs_to_phy_ich8lan(hw);
  4977. retval = hw->phy.ops.acquire(hw);
  4978. if (retval) {
  4979. e_err("Could not acquire PHY\n");
  4980. return retval;
  4981. }
  4982. /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
  4983. retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
  4984. if (retval)
  4985. goto release;
  4986. /* copy MAC MTA to PHY MTA - only needed for pchlan */
  4987. for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
  4988. mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
  4989. hw->phy.ops.write_reg_page(hw, BM_MTA(i),
  4990. (u16)(mac_reg & 0xFFFF));
  4991. hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
  4992. (u16)((mac_reg >> 16) & 0xFFFF));
  4993. }
  4994. /* configure PHY Rx Control register */
  4995. hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
  4996. mac_reg = er32(RCTL);
  4997. if (mac_reg & E1000_RCTL_UPE)
  4998. phy_reg |= BM_RCTL_UPE;
  4999. if (mac_reg & E1000_RCTL_MPE)
  5000. phy_reg |= BM_RCTL_MPE;
  5001. phy_reg &= ~(BM_RCTL_MO_MASK);
  5002. if (mac_reg & E1000_RCTL_MO_3)
  5003. phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
  5004. << BM_RCTL_MO_SHIFT);
  5005. if (mac_reg & E1000_RCTL_BAM)
  5006. phy_reg |= BM_RCTL_BAM;
  5007. if (mac_reg & E1000_RCTL_PMCF)
  5008. phy_reg |= BM_RCTL_PMCF;
  5009. mac_reg = er32(CTRL);
  5010. if (mac_reg & E1000_CTRL_RFCE)
  5011. phy_reg |= BM_RCTL_RFCE;
  5012. hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
  5013. /* enable PHY wakeup in MAC register */
  5014. ew32(WUFC, wufc);
  5015. ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
  5016. /* configure and enable PHY wakeup in PHY registers */
  5017. hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
  5018. hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
  5019. /* activate PHY wakeup */
  5020. wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
  5021. retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
  5022. if (retval)
  5023. e_err("Could not set PHY Host Wakeup bit\n");
  5024. release:
  5025. hw->phy.ops.release(hw);
  5026. return retval;
  5027. }
  5028. static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
  5029. bool runtime)
  5030. {
  5031. struct net_device *netdev = pci_get_drvdata(pdev);
  5032. struct e1000_adapter *adapter = netdev_priv(netdev);
  5033. struct e1000_hw *hw = &adapter->hw;
  5034. u32 ctrl, ctrl_ext, rctl, status;
  5035. /* Runtime suspend should only enable wakeup for link changes */
  5036. u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
  5037. int retval = 0;
  5038. netif_device_detach(netdev);
  5039. if (netif_running(netdev)) {
  5040. int count = E1000_CHECK_RESET_COUNT;
  5041. while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
  5042. usleep_range(10000, 20000);
  5043. WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
  5044. e1000e_down(adapter);
  5045. e1000_free_irq(adapter);
  5046. }
  5047. e1000e_reset_interrupt_capability(adapter);
  5048. retval = pci_save_state(pdev);
  5049. if (retval)
  5050. return retval;
  5051. status = er32(STATUS);
  5052. if (status & E1000_STATUS_LU)
  5053. wufc &= ~E1000_WUFC_LNKC;
  5054. if (wufc) {
  5055. e1000_setup_rctl(adapter);
  5056. e1000e_set_rx_mode(netdev);
  5057. /* turn on all-multi mode if wake on multicast is enabled */
  5058. if (wufc & E1000_WUFC_MC) {
  5059. rctl = er32(RCTL);
  5060. rctl |= E1000_RCTL_MPE;
  5061. ew32(RCTL, rctl);
  5062. }
  5063. ctrl = er32(CTRL);
  5064. /* advertise wake from D3Cold */
  5065. #define E1000_CTRL_ADVD3WUC 0x00100000
  5066. /* phy power management enable */
  5067. #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
  5068. ctrl |= E1000_CTRL_ADVD3WUC;
  5069. if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
  5070. ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
  5071. ew32(CTRL, ctrl);
  5072. if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
  5073. adapter->hw.phy.media_type ==
  5074. e1000_media_type_internal_serdes) {
  5075. /* keep the laser running in D3 */
  5076. ctrl_ext = er32(CTRL_EXT);
  5077. ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
  5078. ew32(CTRL_EXT, ctrl_ext);
  5079. }
  5080. if (adapter->flags & FLAG_IS_ICH)
  5081. e1000_suspend_workarounds_ich8lan(&adapter->hw);
  5082. /* Allow time for pending master requests to run */
  5083. e1000e_disable_pcie_master(&adapter->hw);
  5084. if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
  5085. /* enable wakeup by the PHY */
  5086. retval = e1000_init_phy_wakeup(adapter, wufc);
  5087. if (retval)
  5088. return retval;
  5089. } else {
  5090. /* enable wakeup by the MAC */
  5091. ew32(WUFC, wufc);
  5092. ew32(WUC, E1000_WUC_PME_EN);
  5093. }
  5094. } else {
  5095. ew32(WUC, 0);
  5096. ew32(WUFC, 0);
  5097. }
  5098. *enable_wake = !!wufc;
  5099. /* make sure adapter isn't asleep if manageability is enabled */
  5100. if ((adapter->flags & FLAG_MNG_PT_ENABLED) ||
  5101. (hw->mac.ops.check_mng_mode(hw)))
  5102. *enable_wake = true;
  5103. if (adapter->hw.phy.type == e1000_phy_igp_3)
  5104. e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
  5105. /* Release control of h/w to f/w. If f/w is AMT enabled, this
  5106. * would have already happened in close and is redundant.
  5107. */
  5108. e1000e_release_hw_control(adapter);
  5109. pci_disable_device(pdev);
  5110. return 0;
  5111. }
  5112. static void e1000_power_off(struct pci_dev *pdev, bool sleep, bool wake)
  5113. {
  5114. if (sleep && wake) {
  5115. pci_prepare_to_sleep(pdev);
  5116. return;
  5117. }
  5118. pci_wake_from_d3(pdev, wake);
  5119. pci_set_power_state(pdev, PCI_D3hot);
  5120. }
  5121. static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep, bool wake)
  5122. {
  5123. struct net_device *netdev = pci_get_drvdata(pdev);
  5124. struct e1000_adapter *adapter = netdev_priv(netdev);
  5125. /* The pci-e switch on some quad port adapters will report a
  5126. * correctable error when the MAC transitions from D0 to D3. To
  5127. * prevent this we need to mask off the correctable errors on the
  5128. * downstream port of the pci-e switch.
  5129. */
  5130. if (adapter->flags & FLAG_IS_QUAD_PORT) {
  5131. struct pci_dev *us_dev = pdev->bus->self;
  5132. u16 devctl;
  5133. pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
  5134. pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
  5135. (devctl & ~PCI_EXP_DEVCTL_CERE));
  5136. e1000_power_off(pdev, sleep, wake);
  5137. pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
  5138. } else {
  5139. e1000_power_off(pdev, sleep, wake);
  5140. }
  5141. }
  5142. #ifdef CONFIG_PCIEASPM
  5143. static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
  5144. {
  5145. pci_disable_link_state_locked(pdev, state);
  5146. }
  5147. #else
  5148. static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
  5149. {
  5150. u16 aspm_ctl = 0;
  5151. if (state & PCIE_LINK_STATE_L0S)
  5152. aspm_ctl |= PCI_EXP_LNKCTL_ASPM_L0S;
  5153. if (state & PCIE_LINK_STATE_L1)
  5154. aspm_ctl |= PCI_EXP_LNKCTL_ASPM_L1;
  5155. /* Both device and parent should have the same ASPM setting.
  5156. * Disable ASPM in downstream component first and then upstream.
  5157. */
  5158. pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_ctl);
  5159. if (pdev->bus->self)
  5160. pcie_capability_clear_word(pdev->bus->self, PCI_EXP_LNKCTL,
  5161. aspm_ctl);
  5162. }
  5163. #endif
  5164. static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
  5165. {
  5166. dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
  5167. (state & PCIE_LINK_STATE_L0S) ? "L0s" : "",
  5168. (state & PCIE_LINK_STATE_L1) ? "L1" : "");
  5169. __e1000e_disable_aspm(pdev, state);
  5170. }
  5171. #ifdef CONFIG_PM
  5172. static bool e1000e_pm_ready(struct e1000_adapter *adapter)
  5173. {
  5174. return !!adapter->tx_ring->buffer_info;
  5175. }
  5176. static int __e1000_resume(struct pci_dev *pdev)
  5177. {
  5178. struct net_device *netdev = pci_get_drvdata(pdev);
  5179. struct e1000_adapter *adapter = netdev_priv(netdev);
  5180. struct e1000_hw *hw = &adapter->hw;
  5181. u16 aspm_disable_flag = 0;
  5182. u32 err;
  5183. if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
  5184. aspm_disable_flag = PCIE_LINK_STATE_L0S;
  5185. if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
  5186. aspm_disable_flag |= PCIE_LINK_STATE_L1;
  5187. if (aspm_disable_flag)
  5188. e1000e_disable_aspm(pdev, aspm_disable_flag);
  5189. pci_set_power_state(pdev, PCI_D0);
  5190. pci_restore_state(pdev);
  5191. pci_save_state(pdev);
  5192. e1000e_set_interrupt_capability(adapter);
  5193. if (netif_running(netdev)) {
  5194. err = e1000_request_irq(adapter);
  5195. if (err)
  5196. return err;
  5197. }
  5198. if (hw->mac.type >= e1000_pch2lan)
  5199. e1000_resume_workarounds_pchlan(&adapter->hw);
  5200. e1000e_power_up_phy(adapter);
  5201. /* report the system wakeup cause from S3/S4 */
  5202. if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
  5203. u16 phy_data;
  5204. e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
  5205. if (phy_data) {
  5206. e_info("PHY Wakeup cause - %s\n",
  5207. phy_data & E1000_WUS_EX ? "Unicast Packet" :
  5208. phy_data & E1000_WUS_MC ? "Multicast Packet" :
  5209. phy_data & E1000_WUS_BC ? "Broadcast Packet" :
  5210. phy_data & E1000_WUS_MAG ? "Magic Packet" :
  5211. phy_data & E1000_WUS_LNKC ?
  5212. "Link Status Change" : "other");
  5213. }
  5214. e1e_wphy(&adapter->hw, BM_WUS, ~0);
  5215. } else {
  5216. u32 wus = er32(WUS);
  5217. if (wus) {
  5218. e_info("MAC Wakeup cause - %s\n",
  5219. wus & E1000_WUS_EX ? "Unicast Packet" :
  5220. wus & E1000_WUS_MC ? "Multicast Packet" :
  5221. wus & E1000_WUS_BC ? "Broadcast Packet" :
  5222. wus & E1000_WUS_MAG ? "Magic Packet" :
  5223. wus & E1000_WUS_LNKC ? "Link Status Change" :
  5224. "other");
  5225. }
  5226. ew32(WUS, ~0);
  5227. }
  5228. e1000e_reset(adapter);
  5229. e1000_init_manageability_pt(adapter);
  5230. if (netif_running(netdev))
  5231. e1000e_up(adapter);
  5232. netif_device_attach(netdev);
  5233. /* If the controller has AMT, do not set DRV_LOAD until the interface
  5234. * is up. For all other cases, let the f/w know that the h/w is now
  5235. * under the control of the driver.
  5236. */
  5237. if (!(adapter->flags & FLAG_HAS_AMT))
  5238. e1000e_get_hw_control(adapter);
  5239. return 0;
  5240. }
  5241. #ifdef CONFIG_PM_SLEEP
  5242. static int e1000_suspend(struct device *dev)
  5243. {
  5244. struct pci_dev *pdev = to_pci_dev(dev);
  5245. int retval;
  5246. bool wake;
  5247. retval = __e1000_shutdown(pdev, &wake, false);
  5248. if (!retval)
  5249. e1000_complete_shutdown(pdev, true, wake);
  5250. return retval;
  5251. }
  5252. static int e1000_resume(struct device *dev)
  5253. {
  5254. struct pci_dev *pdev = to_pci_dev(dev);
  5255. struct net_device *netdev = pci_get_drvdata(pdev);
  5256. struct e1000_adapter *adapter = netdev_priv(netdev);
  5257. if (e1000e_pm_ready(adapter))
  5258. adapter->idle_check = true;
  5259. return __e1000_resume(pdev);
  5260. }
  5261. #endif /* CONFIG_PM_SLEEP */
  5262. #ifdef CONFIG_PM_RUNTIME
  5263. static int e1000_runtime_suspend(struct device *dev)
  5264. {
  5265. struct pci_dev *pdev = to_pci_dev(dev);
  5266. struct net_device *netdev = pci_get_drvdata(pdev);
  5267. struct e1000_adapter *adapter = netdev_priv(netdev);
  5268. if (e1000e_pm_ready(adapter)) {
  5269. bool wake;
  5270. __e1000_shutdown(pdev, &wake, true);
  5271. }
  5272. return 0;
  5273. }
  5274. static int e1000_idle(struct device *dev)
  5275. {
  5276. struct pci_dev *pdev = to_pci_dev(dev);
  5277. struct net_device *netdev = pci_get_drvdata(pdev);
  5278. struct e1000_adapter *adapter = netdev_priv(netdev);
  5279. if (!e1000e_pm_ready(adapter))
  5280. return 0;
  5281. if (adapter->idle_check) {
  5282. adapter->idle_check = false;
  5283. if (!e1000e_has_link(adapter))
  5284. pm_schedule_suspend(dev, MSEC_PER_SEC);
  5285. }
  5286. return -EBUSY;
  5287. }
  5288. static int e1000_runtime_resume(struct device *dev)
  5289. {
  5290. struct pci_dev *pdev = to_pci_dev(dev);
  5291. struct net_device *netdev = pci_get_drvdata(pdev);
  5292. struct e1000_adapter *adapter = netdev_priv(netdev);
  5293. if (!e1000e_pm_ready(adapter))
  5294. return 0;
  5295. adapter->idle_check = !dev->power.runtime_auto;
  5296. return __e1000_resume(pdev);
  5297. }
  5298. #endif /* CONFIG_PM_RUNTIME */
  5299. #endif /* CONFIG_PM */
  5300. static void e1000_shutdown(struct pci_dev *pdev)
  5301. {
  5302. bool wake = false;
  5303. __e1000_shutdown(pdev, &wake, false);
  5304. if (system_state == SYSTEM_POWER_OFF)
  5305. e1000_complete_shutdown(pdev, false, wake);
  5306. }
  5307. #ifdef CONFIG_NET_POLL_CONTROLLER
  5308. static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
  5309. {
  5310. struct net_device *netdev = data;
  5311. struct e1000_adapter *adapter = netdev_priv(netdev);
  5312. if (adapter->msix_entries) {
  5313. int vector, msix_irq;
  5314. vector = 0;
  5315. msix_irq = adapter->msix_entries[vector].vector;
  5316. disable_irq(msix_irq);
  5317. e1000_intr_msix_rx(msix_irq, netdev);
  5318. enable_irq(msix_irq);
  5319. vector++;
  5320. msix_irq = adapter->msix_entries[vector].vector;
  5321. disable_irq(msix_irq);
  5322. e1000_intr_msix_tx(msix_irq, netdev);
  5323. enable_irq(msix_irq);
  5324. vector++;
  5325. msix_irq = adapter->msix_entries[vector].vector;
  5326. disable_irq(msix_irq);
  5327. e1000_msix_other(msix_irq, netdev);
  5328. enable_irq(msix_irq);
  5329. }
  5330. return IRQ_HANDLED;
  5331. }
  5332. /**
  5333. * e1000_netpoll
  5334. * @netdev: network interface device structure
  5335. *
  5336. * Polling 'interrupt' - used by things like netconsole to send skbs
  5337. * without having to re-enable interrupts. It's not called while
  5338. * the interrupt routine is executing.
  5339. */
  5340. static void e1000_netpoll(struct net_device *netdev)
  5341. {
  5342. struct e1000_adapter *adapter = netdev_priv(netdev);
  5343. switch (adapter->int_mode) {
  5344. case E1000E_INT_MODE_MSIX:
  5345. e1000_intr_msix(adapter->pdev->irq, netdev);
  5346. break;
  5347. case E1000E_INT_MODE_MSI:
  5348. disable_irq(adapter->pdev->irq);
  5349. e1000_intr_msi(adapter->pdev->irq, netdev);
  5350. enable_irq(adapter->pdev->irq);
  5351. break;
  5352. default: /* E1000E_INT_MODE_LEGACY */
  5353. disable_irq(adapter->pdev->irq);
  5354. e1000_intr(adapter->pdev->irq, netdev);
  5355. enable_irq(adapter->pdev->irq);
  5356. break;
  5357. }
  5358. }
  5359. #endif
  5360. /**
  5361. * e1000_io_error_detected - called when PCI error is detected
  5362. * @pdev: Pointer to PCI device
  5363. * @state: The current pci connection state
  5364. *
  5365. * This function is called after a PCI bus error affecting
  5366. * this device has been detected.
  5367. */
  5368. static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
  5369. pci_channel_state_t state)
  5370. {
  5371. struct net_device *netdev = pci_get_drvdata(pdev);
  5372. struct e1000_adapter *adapter = netdev_priv(netdev);
  5373. netif_device_detach(netdev);
  5374. if (state == pci_channel_io_perm_failure)
  5375. return PCI_ERS_RESULT_DISCONNECT;
  5376. if (netif_running(netdev))
  5377. e1000e_down(adapter);
  5378. pci_disable_device(pdev);
  5379. /* Request a slot slot reset. */
  5380. return PCI_ERS_RESULT_NEED_RESET;
  5381. }
  5382. /**
  5383. * e1000_io_slot_reset - called after the pci bus has been reset.
  5384. * @pdev: Pointer to PCI device
  5385. *
  5386. * Restart the card from scratch, as if from a cold-boot. Implementation
  5387. * resembles the first-half of the e1000_resume routine.
  5388. */
  5389. static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
  5390. {
  5391. struct net_device *netdev = pci_get_drvdata(pdev);
  5392. struct e1000_adapter *adapter = netdev_priv(netdev);
  5393. struct e1000_hw *hw = &adapter->hw;
  5394. u16 aspm_disable_flag = 0;
  5395. int err;
  5396. pci_ers_result_t result;
  5397. if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
  5398. aspm_disable_flag = PCIE_LINK_STATE_L0S;
  5399. if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
  5400. aspm_disable_flag |= PCIE_LINK_STATE_L1;
  5401. if (aspm_disable_flag)
  5402. e1000e_disable_aspm(pdev, aspm_disable_flag);
  5403. err = pci_enable_device_mem(pdev);
  5404. if (err) {
  5405. dev_err(&pdev->dev,
  5406. "Cannot re-enable PCI device after reset.\n");
  5407. result = PCI_ERS_RESULT_DISCONNECT;
  5408. } else {
  5409. pci_set_master(pdev);
  5410. pdev->state_saved = true;
  5411. pci_restore_state(pdev);
  5412. pci_enable_wake(pdev, PCI_D3hot, 0);
  5413. pci_enable_wake(pdev, PCI_D3cold, 0);
  5414. e1000e_reset(adapter);
  5415. ew32(WUS, ~0);
  5416. result = PCI_ERS_RESULT_RECOVERED;
  5417. }
  5418. pci_cleanup_aer_uncorrect_error_status(pdev);
  5419. return result;
  5420. }
  5421. /**
  5422. * e1000_io_resume - called when traffic can start flowing again.
  5423. * @pdev: Pointer to PCI device
  5424. *
  5425. * This callback is called when the error recovery driver tells us that
  5426. * its OK to resume normal operation. Implementation resembles the
  5427. * second-half of the e1000_resume routine.
  5428. */
  5429. static void e1000_io_resume(struct pci_dev *pdev)
  5430. {
  5431. struct net_device *netdev = pci_get_drvdata(pdev);
  5432. struct e1000_adapter *adapter = netdev_priv(netdev);
  5433. e1000_init_manageability_pt(adapter);
  5434. if (netif_running(netdev)) {
  5435. if (e1000e_up(adapter)) {
  5436. dev_err(&pdev->dev,
  5437. "can't bring device back up after reset\n");
  5438. return;
  5439. }
  5440. }
  5441. netif_device_attach(netdev);
  5442. /* If the controller has AMT, do not set DRV_LOAD until the interface
  5443. * is up. For all other cases, let the f/w know that the h/w is now
  5444. * under the control of the driver.
  5445. */
  5446. if (!(adapter->flags & FLAG_HAS_AMT))
  5447. e1000e_get_hw_control(adapter);
  5448. }
  5449. static void e1000_print_device_info(struct e1000_adapter *adapter)
  5450. {
  5451. struct e1000_hw *hw = &adapter->hw;
  5452. struct net_device *netdev = adapter->netdev;
  5453. u32 ret_val;
  5454. u8 pba_str[E1000_PBANUM_LENGTH];
  5455. /* print bus type/speed/width info */
  5456. e_info("(PCI Express:2.5GT/s:%s) %pM\n",
  5457. /* bus width */
  5458. ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
  5459. "Width x1"),
  5460. /* MAC address */
  5461. netdev->dev_addr);
  5462. e_info("Intel(R) PRO/%s Network Connection\n",
  5463. (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
  5464. ret_val = e1000_read_pba_string_generic(hw, pba_str,
  5465. E1000_PBANUM_LENGTH);
  5466. if (ret_val)
  5467. strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
  5468. e_info("MAC: %d, PHY: %d, PBA No: %s\n",
  5469. hw->mac.type, hw->phy.type, pba_str);
  5470. }
  5471. static void e1000_eeprom_checks(struct e1000_adapter *adapter)
  5472. {
  5473. struct e1000_hw *hw = &adapter->hw;
  5474. int ret_val;
  5475. u16 buf = 0;
  5476. if (hw->mac.type != e1000_82573)
  5477. return;
  5478. ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
  5479. le16_to_cpus(&buf);
  5480. if (!ret_val && (!(buf & (1 << 0)))) {
  5481. /* Deep Smart Power Down (DSPD) */
  5482. dev_warn(&adapter->pdev->dev,
  5483. "Warning: detected DSPD enabled in EEPROM\n");
  5484. }
  5485. }
  5486. static int e1000_set_features(struct net_device *netdev,
  5487. netdev_features_t features)
  5488. {
  5489. struct e1000_adapter *adapter = netdev_priv(netdev);
  5490. netdev_features_t changed = features ^ netdev->features;
  5491. if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
  5492. adapter->flags |= FLAG_TSO_FORCE;
  5493. if (!(changed & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX |
  5494. NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
  5495. NETIF_F_RXALL)))
  5496. return 0;
  5497. if (changed & NETIF_F_RXFCS) {
  5498. if (features & NETIF_F_RXFCS) {
  5499. adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
  5500. } else {
  5501. /* We need to take it back to defaults, which might mean
  5502. * stripping is still disabled at the adapter level.
  5503. */
  5504. if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
  5505. adapter->flags2 |= FLAG2_CRC_STRIPPING;
  5506. else
  5507. adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
  5508. }
  5509. }
  5510. netdev->features = features;
  5511. if (netif_running(netdev))
  5512. e1000e_reinit_locked(adapter);
  5513. else
  5514. e1000e_reset(adapter);
  5515. return 0;
  5516. }
  5517. static const struct net_device_ops e1000e_netdev_ops = {
  5518. .ndo_open = e1000_open,
  5519. .ndo_stop = e1000_close,
  5520. .ndo_start_xmit = e1000_xmit_frame,
  5521. .ndo_get_stats64 = e1000e_get_stats64,
  5522. .ndo_set_rx_mode = e1000e_set_rx_mode,
  5523. .ndo_set_mac_address = e1000_set_mac,
  5524. .ndo_change_mtu = e1000_change_mtu,
  5525. .ndo_do_ioctl = e1000_ioctl,
  5526. .ndo_tx_timeout = e1000_tx_timeout,
  5527. .ndo_validate_addr = eth_validate_addr,
  5528. .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
  5529. .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
  5530. #ifdef CONFIG_NET_POLL_CONTROLLER
  5531. .ndo_poll_controller = e1000_netpoll,
  5532. #endif
  5533. .ndo_set_features = e1000_set_features,
  5534. };
  5535. /**
  5536. * e1000_probe - Device Initialization Routine
  5537. * @pdev: PCI device information struct
  5538. * @ent: entry in e1000_pci_tbl
  5539. *
  5540. * Returns 0 on success, negative on failure
  5541. *
  5542. * e1000_probe initializes an adapter identified by a pci_dev structure.
  5543. * The OS initialization, configuring of the adapter private structure,
  5544. * and a hardware reset occur.
  5545. **/
  5546. static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  5547. {
  5548. struct net_device *netdev;
  5549. struct e1000_adapter *adapter;
  5550. struct e1000_hw *hw;
  5551. const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
  5552. resource_size_t mmio_start, mmio_len;
  5553. resource_size_t flash_start, flash_len;
  5554. static int cards_found;
  5555. u16 aspm_disable_flag = 0;
  5556. int i, err, pci_using_dac;
  5557. u16 eeprom_data = 0;
  5558. u16 eeprom_apme_mask = E1000_EEPROM_APME;
  5559. if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
  5560. aspm_disable_flag = PCIE_LINK_STATE_L0S;
  5561. if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
  5562. aspm_disable_flag |= PCIE_LINK_STATE_L1;
  5563. if (aspm_disable_flag)
  5564. e1000e_disable_aspm(pdev, aspm_disable_flag);
  5565. err = pci_enable_device_mem(pdev);
  5566. if (err)
  5567. return err;
  5568. pci_using_dac = 0;
  5569. err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
  5570. if (!err) {
  5571. err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
  5572. if (!err)
  5573. pci_using_dac = 1;
  5574. } else {
  5575. err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
  5576. if (err) {
  5577. err = dma_set_coherent_mask(&pdev->dev,
  5578. DMA_BIT_MASK(32));
  5579. if (err) {
  5580. dev_err(&pdev->dev,
  5581. "No usable DMA configuration, aborting\n");
  5582. goto err_dma;
  5583. }
  5584. }
  5585. }
  5586. err = pci_request_selected_regions_exclusive(pdev,
  5587. pci_select_bars(pdev, IORESOURCE_MEM),
  5588. e1000e_driver_name);
  5589. if (err)
  5590. goto err_pci_reg;
  5591. /* AER (Advanced Error Reporting) hooks */
  5592. pci_enable_pcie_error_reporting(pdev);
  5593. pci_set_master(pdev);
  5594. /* PCI config space info */
  5595. err = pci_save_state(pdev);
  5596. if (err)
  5597. goto err_alloc_etherdev;
  5598. err = -ENOMEM;
  5599. netdev = alloc_etherdev(sizeof(struct e1000_adapter));
  5600. if (!netdev)
  5601. goto err_alloc_etherdev;
  5602. SET_NETDEV_DEV(netdev, &pdev->dev);
  5603. netdev->irq = pdev->irq;
  5604. pci_set_drvdata(pdev, netdev);
  5605. adapter = netdev_priv(netdev);
  5606. hw = &adapter->hw;
  5607. adapter->netdev = netdev;
  5608. adapter->pdev = pdev;
  5609. adapter->ei = ei;
  5610. adapter->pba = ei->pba;
  5611. adapter->flags = ei->flags;
  5612. adapter->flags2 = ei->flags2;
  5613. adapter->hw.adapter = adapter;
  5614. adapter->hw.mac.type = ei->mac;
  5615. adapter->max_hw_frame_size = ei->max_hw_frame_size;
  5616. adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
  5617. mmio_start = pci_resource_start(pdev, 0);
  5618. mmio_len = pci_resource_len(pdev, 0);
  5619. err = -EIO;
  5620. adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
  5621. if (!adapter->hw.hw_addr)
  5622. goto err_ioremap;
  5623. if ((adapter->flags & FLAG_HAS_FLASH) &&
  5624. (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
  5625. flash_start = pci_resource_start(pdev, 1);
  5626. flash_len = pci_resource_len(pdev, 1);
  5627. adapter->hw.flash_address = ioremap(flash_start, flash_len);
  5628. if (!adapter->hw.flash_address)
  5629. goto err_flashmap;
  5630. }
  5631. /* construct the net_device struct */
  5632. netdev->netdev_ops = &e1000e_netdev_ops;
  5633. e1000e_set_ethtool_ops(netdev);
  5634. netdev->watchdog_timeo = 5 * HZ;
  5635. netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
  5636. strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
  5637. netdev->mem_start = mmio_start;
  5638. netdev->mem_end = mmio_start + mmio_len;
  5639. adapter->bd_number = cards_found++;
  5640. e1000e_check_options(adapter);
  5641. /* setup adapter struct */
  5642. err = e1000_sw_init(adapter);
  5643. if (err)
  5644. goto err_sw_init;
  5645. memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
  5646. memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
  5647. memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
  5648. err = ei->get_variants(adapter);
  5649. if (err)
  5650. goto err_hw_init;
  5651. if ((adapter->flags & FLAG_IS_ICH) &&
  5652. (adapter->flags & FLAG_READ_ONLY_NVM))
  5653. e1000e_write_protect_nvm_ich8lan(&adapter->hw);
  5654. hw->mac.ops.get_bus_info(&adapter->hw);
  5655. adapter->hw.phy.autoneg_wait_to_complete = 0;
  5656. /* Copper options */
  5657. if (adapter->hw.phy.media_type == e1000_media_type_copper) {
  5658. adapter->hw.phy.mdix = AUTO_ALL_MODES;
  5659. adapter->hw.phy.disable_polarity_correction = 0;
  5660. adapter->hw.phy.ms_type = e1000_ms_hw_default;
  5661. }
  5662. if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
  5663. dev_info(&pdev->dev,
  5664. "PHY reset is blocked due to SOL/IDER session.\n");
  5665. /* Set initial default active device features */
  5666. netdev->features = (NETIF_F_SG |
  5667. NETIF_F_HW_VLAN_RX |
  5668. NETIF_F_HW_VLAN_TX |
  5669. NETIF_F_TSO |
  5670. NETIF_F_TSO6 |
  5671. NETIF_F_RXHASH |
  5672. NETIF_F_RXCSUM |
  5673. NETIF_F_HW_CSUM);
  5674. /* Set user-changeable features (subset of all device features) */
  5675. netdev->hw_features = netdev->features;
  5676. netdev->hw_features |= NETIF_F_RXFCS;
  5677. netdev->priv_flags |= IFF_SUPP_NOFCS;
  5678. netdev->hw_features |= NETIF_F_RXALL;
  5679. if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
  5680. netdev->features |= NETIF_F_HW_VLAN_FILTER;
  5681. netdev->vlan_features |= (NETIF_F_SG |
  5682. NETIF_F_TSO |
  5683. NETIF_F_TSO6 |
  5684. NETIF_F_HW_CSUM);
  5685. netdev->priv_flags |= IFF_UNICAST_FLT;
  5686. if (pci_using_dac) {
  5687. netdev->features |= NETIF_F_HIGHDMA;
  5688. netdev->vlan_features |= NETIF_F_HIGHDMA;
  5689. }
  5690. if (e1000e_enable_mng_pass_thru(&adapter->hw))
  5691. adapter->flags |= FLAG_MNG_PT_ENABLED;
  5692. /* before reading the NVM, reset the controller to
  5693. * put the device in a known good starting state
  5694. */
  5695. adapter->hw.mac.ops.reset_hw(&adapter->hw);
  5696. /* systems with ASPM and others may see the checksum fail on the first
  5697. * attempt. Let's give it a few tries
  5698. */
  5699. for (i = 0;; i++) {
  5700. if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
  5701. break;
  5702. if (i == 2) {
  5703. dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
  5704. err = -EIO;
  5705. goto err_eeprom;
  5706. }
  5707. }
  5708. e1000_eeprom_checks(adapter);
  5709. /* copy the MAC address */
  5710. if (e1000e_read_mac_addr(&adapter->hw))
  5711. dev_err(&pdev->dev,
  5712. "NVM Read Error while reading MAC address\n");
  5713. memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
  5714. if (!is_valid_ether_addr(netdev->dev_addr)) {
  5715. dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
  5716. netdev->dev_addr);
  5717. err = -EIO;
  5718. goto err_eeprom;
  5719. }
  5720. init_timer(&adapter->watchdog_timer);
  5721. adapter->watchdog_timer.function = e1000_watchdog;
  5722. adapter->watchdog_timer.data = (unsigned long) adapter;
  5723. init_timer(&adapter->phy_info_timer);
  5724. adapter->phy_info_timer.function = e1000_update_phy_info;
  5725. adapter->phy_info_timer.data = (unsigned long) adapter;
  5726. INIT_WORK(&adapter->reset_task, e1000_reset_task);
  5727. INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
  5728. INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
  5729. INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
  5730. INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
  5731. /* Initialize link parameters. User can change them with ethtool */
  5732. adapter->hw.mac.autoneg = 1;
  5733. adapter->fc_autoneg = true;
  5734. adapter->hw.fc.requested_mode = e1000_fc_default;
  5735. adapter->hw.fc.current_mode = e1000_fc_default;
  5736. adapter->hw.phy.autoneg_advertised = 0x2f;
  5737. /* ring size defaults */
  5738. adapter->rx_ring->count = E1000_DEFAULT_RXD;
  5739. adapter->tx_ring->count = E1000_DEFAULT_TXD;
  5740. /* Initial Wake on LAN setting - If APM wake is enabled in
  5741. * the EEPROM, enable the ACPI Magic Packet filter
  5742. */
  5743. if (adapter->flags & FLAG_APME_IN_WUC) {
  5744. /* APME bit in EEPROM is mapped to WUC.APME */
  5745. eeprom_data = er32(WUC);
  5746. eeprom_apme_mask = E1000_WUC_APME;
  5747. if ((hw->mac.type > e1000_ich10lan) &&
  5748. (eeprom_data & E1000_WUC_PHY_WAKE))
  5749. adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
  5750. } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
  5751. if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
  5752. (adapter->hw.bus.func == 1))
  5753. e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B,
  5754. 1, &eeprom_data);
  5755. else
  5756. e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A,
  5757. 1, &eeprom_data);
  5758. }
  5759. /* fetch WoL from EEPROM */
  5760. if (eeprom_data & eeprom_apme_mask)
  5761. adapter->eeprom_wol |= E1000_WUFC_MAG;
  5762. /* now that we have the eeprom settings, apply the special cases
  5763. * where the eeprom may be wrong or the board simply won't support
  5764. * wake on lan on a particular port
  5765. */
  5766. if (!(adapter->flags & FLAG_HAS_WOL))
  5767. adapter->eeprom_wol = 0;
  5768. /* initialize the wol settings based on the eeprom settings */
  5769. adapter->wol = adapter->eeprom_wol;
  5770. device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
  5771. /* save off EEPROM version number */
  5772. e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
  5773. /* reset the hardware with the new settings */
  5774. e1000e_reset(adapter);
  5775. /* If the controller has AMT, do not set DRV_LOAD until the interface
  5776. * is up. For all other cases, let the f/w know that the h/w is now
  5777. * under the control of the driver.
  5778. */
  5779. if (!(adapter->flags & FLAG_HAS_AMT))
  5780. e1000e_get_hw_control(adapter);
  5781. strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
  5782. err = register_netdev(netdev);
  5783. if (err)
  5784. goto err_register;
  5785. /* carrier off reporting is important to ethtool even BEFORE open */
  5786. netif_carrier_off(netdev);
  5787. /* init PTP hardware clock */
  5788. e1000e_ptp_init(adapter);
  5789. e1000_print_device_info(adapter);
  5790. if (pci_dev_run_wake(pdev))
  5791. pm_runtime_put_noidle(&pdev->dev);
  5792. return 0;
  5793. err_register:
  5794. if (!(adapter->flags & FLAG_HAS_AMT))
  5795. e1000e_release_hw_control(adapter);
  5796. err_eeprom:
  5797. if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
  5798. e1000_phy_hw_reset(&adapter->hw);
  5799. err_hw_init:
  5800. kfree(adapter->tx_ring);
  5801. kfree(adapter->rx_ring);
  5802. err_sw_init:
  5803. if (adapter->hw.flash_address)
  5804. iounmap(adapter->hw.flash_address);
  5805. e1000e_reset_interrupt_capability(adapter);
  5806. err_flashmap:
  5807. iounmap(adapter->hw.hw_addr);
  5808. err_ioremap:
  5809. free_netdev(netdev);
  5810. err_alloc_etherdev:
  5811. pci_release_selected_regions(pdev,
  5812. pci_select_bars(pdev, IORESOURCE_MEM));
  5813. err_pci_reg:
  5814. err_dma:
  5815. pci_disable_device(pdev);
  5816. return err;
  5817. }
  5818. /**
  5819. * e1000_remove - Device Removal Routine
  5820. * @pdev: PCI device information struct
  5821. *
  5822. * e1000_remove is called by the PCI subsystem to alert the driver
  5823. * that it should release a PCI device. The could be caused by a
  5824. * Hot-Plug event, or because the driver is going to be removed from
  5825. * memory.
  5826. **/
  5827. static void e1000_remove(struct pci_dev *pdev)
  5828. {
  5829. struct net_device *netdev = pci_get_drvdata(pdev);
  5830. struct e1000_adapter *adapter = netdev_priv(netdev);
  5831. bool down = test_bit(__E1000_DOWN, &adapter->state);
  5832. e1000e_ptp_remove(adapter);
  5833. /* The timers may be rescheduled, so explicitly disable them
  5834. * from being rescheduled.
  5835. */
  5836. if (!down)
  5837. set_bit(__E1000_DOWN, &adapter->state);
  5838. del_timer_sync(&adapter->watchdog_timer);
  5839. del_timer_sync(&adapter->phy_info_timer);
  5840. cancel_work_sync(&adapter->reset_task);
  5841. cancel_work_sync(&adapter->watchdog_task);
  5842. cancel_work_sync(&adapter->downshift_task);
  5843. cancel_work_sync(&adapter->update_phy_task);
  5844. cancel_work_sync(&adapter->print_hang_task);
  5845. if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
  5846. cancel_work_sync(&adapter->tx_hwtstamp_work);
  5847. if (adapter->tx_hwtstamp_skb) {
  5848. dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
  5849. adapter->tx_hwtstamp_skb = NULL;
  5850. }
  5851. }
  5852. if (!(netdev->flags & IFF_UP))
  5853. e1000_power_down_phy(adapter);
  5854. /* Don't lie to e1000_close() down the road. */
  5855. if (!down)
  5856. clear_bit(__E1000_DOWN, &adapter->state);
  5857. unregister_netdev(netdev);
  5858. if (pci_dev_run_wake(pdev))
  5859. pm_runtime_get_noresume(&pdev->dev);
  5860. /* Release control of h/w to f/w. If f/w is AMT enabled, this
  5861. * would have already happened in close and is redundant.
  5862. */
  5863. e1000e_release_hw_control(adapter);
  5864. e1000e_reset_interrupt_capability(adapter);
  5865. kfree(adapter->tx_ring);
  5866. kfree(adapter->rx_ring);
  5867. iounmap(adapter->hw.hw_addr);
  5868. if (adapter->hw.flash_address)
  5869. iounmap(adapter->hw.flash_address);
  5870. pci_release_selected_regions(pdev,
  5871. pci_select_bars(pdev, IORESOURCE_MEM));
  5872. free_netdev(netdev);
  5873. /* AER disable */
  5874. pci_disable_pcie_error_reporting(pdev);
  5875. pci_disable_device(pdev);
  5876. }
  5877. /* PCI Error Recovery (ERS) */
  5878. static const struct pci_error_handlers e1000_err_handler = {
  5879. .error_detected = e1000_io_error_detected,
  5880. .slot_reset = e1000_io_slot_reset,
  5881. .resume = e1000_io_resume,
  5882. };
  5883. static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
  5884. { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
  5885. { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
  5886. { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
  5887. { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), board_82571 },
  5888. { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
  5889. { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
  5890. { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
  5891. { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
  5892. { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
  5893. { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
  5894. { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
  5895. { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
  5896. { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
  5897. { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
  5898. { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
  5899. { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
  5900. { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
  5901. { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
  5902. { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
  5903. { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
  5904. board_80003es2lan },
  5905. { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
  5906. board_80003es2lan },
  5907. { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
  5908. board_80003es2lan },
  5909. { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
  5910. board_80003es2lan },
  5911. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
  5912. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
  5913. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
  5914. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
  5915. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
  5916. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
  5917. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
  5918. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
  5919. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
  5920. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
  5921. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
  5922. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
  5923. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
  5924. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
  5925. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
  5926. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
  5927. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
  5928. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
  5929. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
  5930. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
  5931. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
  5932. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
  5933. { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
  5934. { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
  5935. { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
  5936. { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
  5937. { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
  5938. { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
  5939. { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
  5940. { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
  5941. { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
  5942. { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
  5943. { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
  5944. { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
  5945. };
  5946. MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
  5947. #ifdef CONFIG_PM
  5948. static const struct dev_pm_ops e1000_pm_ops = {
  5949. SET_SYSTEM_SLEEP_PM_OPS(e1000_suspend, e1000_resume)
  5950. SET_RUNTIME_PM_OPS(e1000_runtime_suspend,
  5951. e1000_runtime_resume, e1000_idle)
  5952. };
  5953. #endif
  5954. /* PCI Device API Driver */
  5955. static struct pci_driver e1000_driver = {
  5956. .name = e1000e_driver_name,
  5957. .id_table = e1000_pci_tbl,
  5958. .probe = e1000_probe,
  5959. .remove = e1000_remove,
  5960. #ifdef CONFIG_PM
  5961. .driver = {
  5962. .pm = &e1000_pm_ops,
  5963. },
  5964. #endif
  5965. .shutdown = e1000_shutdown,
  5966. .err_handler = &e1000_err_handler
  5967. };
  5968. /**
  5969. * e1000_init_module - Driver Registration Routine
  5970. *
  5971. * e1000_init_module is the first routine called when the driver is
  5972. * loaded. All it does is register with the PCI subsystem.
  5973. **/
  5974. static int __init e1000_init_module(void)
  5975. {
  5976. int ret;
  5977. pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
  5978. e1000e_driver_version);
  5979. pr_info("Copyright(c) 1999 - 2013 Intel Corporation.\n");
  5980. ret = pci_register_driver(&e1000_driver);
  5981. return ret;
  5982. }
  5983. module_init(e1000_init_module);
  5984. /**
  5985. * e1000_exit_module - Driver Exit Cleanup Routine
  5986. *
  5987. * e1000_exit_module is called just before the driver is removed
  5988. * from memory.
  5989. **/
  5990. static void __exit e1000_exit_module(void)
  5991. {
  5992. pci_unregister_driver(&e1000_driver);
  5993. }
  5994. module_exit(e1000_exit_module);
  5995. MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
  5996. MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
  5997. MODULE_LICENSE("GPL");
  5998. MODULE_VERSION(DRV_VERSION);
  5999. /* netdev.c */