mach-smdk6410.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682
  1. /* linux/arch/arm/mach-s3c64xx/mach-smdk6410.c
  2. *
  3. * Copyright 2008 Openmoko, Inc.
  4. * Copyright 2008 Simtec Electronics
  5. * Ben Dooks <ben@simtec.co.uk>
  6. * http://armlinux.simtec.co.uk/
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/list.h>
  17. #include <linux/timer.h>
  18. #include <linux/init.h>
  19. #include <linux/serial_core.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/io.h>
  22. #include <linux/i2c.h>
  23. #include <linux/leds.h>
  24. #include <linux/fb.h>
  25. #include <linux/gpio.h>
  26. #include <linux/delay.h>
  27. #include <linux/smsc911x.h>
  28. #include <linux/regulator/fixed.h>
  29. #ifdef CONFIG_SMDK6410_WM1190_EV1
  30. #include <linux/mfd/wm8350/core.h>
  31. #include <linux/mfd/wm8350/pmic.h>
  32. #endif
  33. #ifdef CONFIG_SMDK6410_WM1192_EV1
  34. #include <linux/mfd/wm831x/core.h>
  35. #include <linux/mfd/wm831x/pdata.h>
  36. #endif
  37. #include <video/platform_lcd.h>
  38. #include <asm/mach/arch.h>
  39. #include <asm/mach/map.h>
  40. #include <asm/mach/irq.h>
  41. #include <mach/hardware.h>
  42. #include <mach/regs-fb.h>
  43. #include <mach/map.h>
  44. #include <asm/irq.h>
  45. #include <asm/mach-types.h>
  46. #include <plat/regs-serial.h>
  47. #include <mach/regs-modem.h>
  48. #include <mach/regs-gpio.h>
  49. #include <mach/regs-sys.h>
  50. #include <mach/regs-srom.h>
  51. #include <plat/iic.h>
  52. #include <plat/fb.h>
  53. #include <plat/gpio-cfg.h>
  54. #include <mach/s3c6410.h>
  55. #include <plat/clock.h>
  56. #include <plat/devs.h>
  57. #include <plat/cpu.h>
  58. #include <plat/adc.h>
  59. #include <plat/ts.h>
  60. #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
  61. #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  62. #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  63. static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
  64. [0] = {
  65. .hwport = 0,
  66. .flags = 0,
  67. .ucon = UCON,
  68. .ulcon = ULCON,
  69. .ufcon = UFCON,
  70. },
  71. [1] = {
  72. .hwport = 1,
  73. .flags = 0,
  74. .ucon = UCON,
  75. .ulcon = ULCON,
  76. .ufcon = UFCON,
  77. },
  78. [2] = {
  79. .hwport = 2,
  80. .flags = 0,
  81. .ucon = UCON,
  82. .ulcon = ULCON,
  83. .ufcon = UFCON,
  84. },
  85. [3] = {
  86. .hwport = 3,
  87. .flags = 0,
  88. .ucon = UCON,
  89. .ulcon = ULCON,
  90. .ufcon = UFCON,
  91. },
  92. };
  93. /* framebuffer and LCD setup. */
  94. /* GPF15 = LCD backlight control
  95. * GPF13 => Panel power
  96. * GPN5 = LCD nRESET signal
  97. * PWM_TOUT1 => backlight brightness
  98. */
  99. static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
  100. unsigned int power)
  101. {
  102. if (power) {
  103. gpio_direction_output(S3C64XX_GPF(13), 1);
  104. gpio_direction_output(S3C64XX_GPF(15), 1);
  105. /* fire nRESET on power up */
  106. gpio_direction_output(S3C64XX_GPN(5), 0);
  107. msleep(10);
  108. gpio_direction_output(S3C64XX_GPN(5), 1);
  109. msleep(1);
  110. } else {
  111. gpio_direction_output(S3C64XX_GPF(15), 0);
  112. gpio_direction_output(S3C64XX_GPF(13), 0);
  113. }
  114. }
  115. static struct plat_lcd_data smdk6410_lcd_power_data = {
  116. .set_power = smdk6410_lcd_power_set,
  117. };
  118. static struct platform_device smdk6410_lcd_powerdev = {
  119. .name = "platform-lcd",
  120. .dev.parent = &s3c_device_fb.dev,
  121. .dev.platform_data = &smdk6410_lcd_power_data,
  122. };
  123. static struct s3c_fb_pd_win smdk6410_fb_win0 = {
  124. /* this is to ensure we use win0 */
  125. .win_mode = {
  126. .pixclock = 41094,
  127. .left_margin = 8,
  128. .right_margin = 13,
  129. .upper_margin = 7,
  130. .lower_margin = 5,
  131. .hsync_len = 3,
  132. .vsync_len = 1,
  133. .xres = 800,
  134. .yres = 480,
  135. },
  136. .max_bpp = 32,
  137. .default_bpp = 16,
  138. };
  139. /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
  140. static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
  141. .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
  142. .win[0] = &smdk6410_fb_win0,
  143. .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
  144. .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
  145. };
  146. /*
  147. * Configuring Ethernet on SMDK6410
  148. *
  149. * Both CS8900A and LAN9115 chips share one chip select mediated by CFG6.
  150. * The constant address below corresponds to nCS1
  151. *
  152. * 1) Set CFGB2 p3 ON others off, no other CFGB selects "ethernet"
  153. * 2) CFG6 needs to be switched to "LAN9115" side
  154. */
  155. static struct resource smdk6410_smsc911x_resources[] = {
  156. [0] = {
  157. .start = S3C64XX_PA_XM0CSN1,
  158. .end = S3C64XX_PA_XM0CSN1 + SZ_64K - 1,
  159. .flags = IORESOURCE_MEM,
  160. },
  161. [1] = {
  162. .start = S3C_EINT(10),
  163. .end = S3C_EINT(10),
  164. .flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW,
  165. },
  166. };
  167. static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
  168. .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
  169. .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
  170. .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
  171. .phy_interface = PHY_INTERFACE_MODE_MII,
  172. };
  173. static struct platform_device smdk6410_smsc911x = {
  174. .name = "smsc911x",
  175. .id = -1,
  176. .num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources),
  177. .resource = &smdk6410_smsc911x_resources[0],
  178. .dev = {
  179. .platform_data = &smdk6410_smsc911x_pdata,
  180. },
  181. };
  182. #ifdef CONFIG_REGULATOR
  183. static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
  184. {
  185. /* WM8580 */
  186. .supply = "PVDD",
  187. .dev_name = "0-001b",
  188. },
  189. {
  190. /* WM8580 */
  191. .supply = "AVDD",
  192. .dev_name = "0-001b",
  193. },
  194. };
  195. static struct regulator_init_data smdk6410_b_pwr_5v_data = {
  196. .constraints = {
  197. .always_on = 1,
  198. },
  199. .num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers),
  200. .consumer_supplies = smdk6410_b_pwr_5v_consumers,
  201. };
  202. static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
  203. .supply_name = "B_PWR_5V",
  204. .microvolts = 5000000,
  205. .init_data = &smdk6410_b_pwr_5v_data,
  206. .gpio = -EINVAL,
  207. };
  208. static struct platform_device smdk6410_b_pwr_5v = {
  209. .name = "reg-fixed-voltage",
  210. .id = -1,
  211. .dev = {
  212. .platform_data = &smdk6410_b_pwr_5v_pdata,
  213. },
  214. };
  215. #endif
  216. static struct map_desc smdk6410_iodesc[] = {};
  217. static struct platform_device *smdk6410_devices[] __initdata = {
  218. #ifdef CONFIG_SMDK6410_SD_CH0
  219. &s3c_device_hsmmc0,
  220. #endif
  221. #ifdef CONFIG_SMDK6410_SD_CH1
  222. &s3c_device_hsmmc1,
  223. #endif
  224. &s3c_device_i2c0,
  225. &s3c_device_i2c1,
  226. &s3c_device_fb,
  227. &s3c_device_ohci,
  228. &s3c_device_usb_hsotg,
  229. &s3c_device_pcm,
  230. &s3c64xx_device_iisv4,
  231. #ifdef CONFIG_REGULATOR
  232. &smdk6410_b_pwr_5v,
  233. #endif
  234. &smdk6410_lcd_powerdev,
  235. &smdk6410_smsc911x,
  236. &s3c_device_adc,
  237. &s3c_device_ts,
  238. &s3c_device_wdt,
  239. };
  240. #ifdef CONFIG_REGULATOR
  241. /* ARM core */
  242. static struct regulator_consumer_supply smdk6410_vddarm_consumers[] = {
  243. {
  244. .supply = "vddarm",
  245. }
  246. };
  247. /* VDDARM, BUCK1 on J5 */
  248. static struct regulator_init_data smdk6410_vddarm = {
  249. .constraints = {
  250. .name = "PVDD_ARM",
  251. .min_uV = 1000000,
  252. .max_uV = 1300000,
  253. .always_on = 1,
  254. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
  255. },
  256. .num_consumer_supplies = ARRAY_SIZE(smdk6410_vddarm_consumers),
  257. .consumer_supplies = smdk6410_vddarm_consumers,
  258. };
  259. /* VDD_INT, BUCK2 on J5 */
  260. static struct regulator_init_data smdk6410_vddint = {
  261. .constraints = {
  262. .name = "PVDD_INT",
  263. .min_uV = 1000000,
  264. .max_uV = 1200000,
  265. .always_on = 1,
  266. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
  267. },
  268. };
  269. /* VDD_HI, LDO3 on J5 */
  270. static struct regulator_init_data smdk6410_vddhi = {
  271. .constraints = {
  272. .name = "PVDD_HI",
  273. .always_on = 1,
  274. },
  275. };
  276. /* VDD_PLL, LDO2 on J5 */
  277. static struct regulator_init_data smdk6410_vddpll = {
  278. .constraints = {
  279. .name = "PVDD_PLL",
  280. .always_on = 1,
  281. },
  282. };
  283. /* VDD_UH_MMC, LDO5 on J5 */
  284. static struct regulator_init_data smdk6410_vdduh_mmc = {
  285. .constraints = {
  286. .name = "PVDD_UH/PVDD_MMC",
  287. .always_on = 1,
  288. },
  289. };
  290. /* VCCM3BT, LDO8 on J5 */
  291. static struct regulator_init_data smdk6410_vccmc3bt = {
  292. .constraints = {
  293. .name = "PVCCM3BT",
  294. .always_on = 1,
  295. },
  296. };
  297. /* VCCM2MTV, LDO11 on J5 */
  298. static struct regulator_init_data smdk6410_vccm2mtv = {
  299. .constraints = {
  300. .name = "PVCCM2MTV",
  301. .always_on = 1,
  302. },
  303. };
  304. /* VDD_LCD, LDO12 on J5 */
  305. static struct regulator_init_data smdk6410_vddlcd = {
  306. .constraints = {
  307. .name = "PVDD_LCD",
  308. .always_on = 1,
  309. },
  310. };
  311. /* VDD_OTGI, LDO9 on J5 */
  312. static struct regulator_init_data smdk6410_vddotgi = {
  313. .constraints = {
  314. .name = "PVDD_OTGI",
  315. .always_on = 1,
  316. },
  317. };
  318. /* VDD_OTG, LDO14 on J5 */
  319. static struct regulator_init_data smdk6410_vddotg = {
  320. .constraints = {
  321. .name = "PVDD_OTG",
  322. .always_on = 1,
  323. },
  324. };
  325. /* VDD_ALIVE, LDO15 on J5 */
  326. static struct regulator_init_data smdk6410_vddalive = {
  327. .constraints = {
  328. .name = "PVDD_ALIVE",
  329. .always_on = 1,
  330. },
  331. };
  332. /* VDD_AUDIO, VLDO_AUDIO on J5 */
  333. static struct regulator_init_data smdk6410_vddaudio = {
  334. .constraints = {
  335. .name = "PVDD_AUDIO",
  336. .always_on = 1,
  337. },
  338. };
  339. #endif
  340. #ifdef CONFIG_SMDK6410_WM1190_EV1
  341. /* S3C64xx internal logic & PLL */
  342. static struct regulator_init_data wm8350_dcdc1_data = {
  343. .constraints = {
  344. .name = "PVDD_INT/PVDD_PLL",
  345. .min_uV = 1200000,
  346. .max_uV = 1200000,
  347. .always_on = 1,
  348. .apply_uV = 1,
  349. },
  350. };
  351. /* Memory */
  352. static struct regulator_init_data wm8350_dcdc3_data = {
  353. .constraints = {
  354. .name = "PVDD_MEM",
  355. .min_uV = 1800000,
  356. .max_uV = 1800000,
  357. .always_on = 1,
  358. .state_mem = {
  359. .uV = 1800000,
  360. .mode = REGULATOR_MODE_NORMAL,
  361. .enabled = 1,
  362. },
  363. .initial_state = PM_SUSPEND_MEM,
  364. },
  365. };
  366. /* USB, EXT, PCM, ADC/DAC, USB, MMC */
  367. static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
  368. {
  369. /* WM8580 */
  370. .supply = "DVDD",
  371. .dev_name = "0-001b",
  372. },
  373. };
  374. static struct regulator_init_data wm8350_dcdc4_data = {
  375. .constraints = {
  376. .name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
  377. .min_uV = 3000000,
  378. .max_uV = 3000000,
  379. .always_on = 1,
  380. },
  381. .num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers),
  382. .consumer_supplies = wm8350_dcdc4_consumers,
  383. };
  384. /* OTGi/1190-EV1 HPVDD & AVDD */
  385. static struct regulator_init_data wm8350_ldo4_data = {
  386. .constraints = {
  387. .name = "PVDD_OTGI/HPVDD/AVDD",
  388. .min_uV = 1200000,
  389. .max_uV = 1200000,
  390. .apply_uV = 1,
  391. .always_on = 1,
  392. },
  393. };
  394. static struct {
  395. int regulator;
  396. struct regulator_init_data *initdata;
  397. } wm1190_regulators[] = {
  398. { WM8350_DCDC_1, &wm8350_dcdc1_data },
  399. { WM8350_DCDC_3, &wm8350_dcdc3_data },
  400. { WM8350_DCDC_4, &wm8350_dcdc4_data },
  401. { WM8350_DCDC_6, &smdk6410_vddarm },
  402. { WM8350_LDO_1, &smdk6410_vddalive },
  403. { WM8350_LDO_2, &smdk6410_vddotg },
  404. { WM8350_LDO_3, &smdk6410_vddlcd },
  405. { WM8350_LDO_4, &wm8350_ldo4_data },
  406. };
  407. static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
  408. {
  409. int i;
  410. /* Configure the IRQ line */
  411. s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
  412. /* Instantiate the regulators */
  413. for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
  414. wm8350_register_regulator(wm8350,
  415. wm1190_regulators[i].regulator,
  416. wm1190_regulators[i].initdata);
  417. return 0;
  418. }
  419. static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
  420. .init = smdk6410_wm8350_init,
  421. .irq_high = 1,
  422. .irq_base = IRQ_BOARD_START,
  423. };
  424. #endif
  425. #ifdef CONFIG_SMDK6410_WM1192_EV1
  426. static struct gpio_led wm1192_pmic_leds[] = {
  427. {
  428. .name = "PMIC:red:power",
  429. .gpio = GPIO_BOARD_START + 3,
  430. .default_state = LEDS_GPIO_DEFSTATE_ON,
  431. },
  432. };
  433. static struct gpio_led_platform_data wm1192_pmic_led = {
  434. .num_leds = ARRAY_SIZE(wm1192_pmic_leds),
  435. .leds = wm1192_pmic_leds,
  436. };
  437. static struct platform_device wm1192_pmic_led_dev = {
  438. .name = "leds-gpio",
  439. .id = -1,
  440. .dev = {
  441. .platform_data = &wm1192_pmic_led,
  442. },
  443. };
  444. static int wm1192_pre_init(struct wm831x *wm831x)
  445. {
  446. int ret;
  447. /* Configure the IRQ line */
  448. s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
  449. ret = platform_device_register(&wm1192_pmic_led_dev);
  450. if (ret != 0)
  451. dev_err(wm831x->dev, "Failed to add PMIC LED: %d\n", ret);
  452. return 0;
  453. }
  454. static struct wm831x_backlight_pdata wm1192_backlight_pdata = {
  455. .isink = 1,
  456. .max_uA = 27554,
  457. };
  458. static struct regulator_init_data wm1192_dcdc3 = {
  459. .constraints = {
  460. .name = "PVDD_MEM/PVDD_GPS",
  461. .always_on = 1,
  462. },
  463. };
  464. static struct regulator_consumer_supply wm1192_ldo1_consumers[] = {
  465. { .supply = "DVDD", .dev_name = "0-001b", }, /* WM8580 */
  466. };
  467. static struct regulator_init_data wm1192_ldo1 = {
  468. .constraints = {
  469. .name = "PVDD_LCD/PVDD_EXT",
  470. .always_on = 1,
  471. },
  472. .consumer_supplies = wm1192_ldo1_consumers,
  473. .num_consumer_supplies = ARRAY_SIZE(wm1192_ldo1_consumers),
  474. };
  475. static struct wm831x_status_pdata wm1192_led7_pdata = {
  476. .name = "LED7:green:",
  477. };
  478. static struct wm831x_status_pdata wm1192_led8_pdata = {
  479. .name = "LED8:green:",
  480. };
  481. static struct wm831x_pdata smdk6410_wm1192_pdata = {
  482. .pre_init = wm1192_pre_init,
  483. .irq_base = IRQ_BOARD_START,
  484. .backlight = &wm1192_backlight_pdata,
  485. .dcdc = {
  486. &smdk6410_vddarm, /* DCDC1 */
  487. &smdk6410_vddint, /* DCDC2 */
  488. &wm1192_dcdc3,
  489. },
  490. .gpio_base = GPIO_BOARD_START,
  491. .ldo = {
  492. &wm1192_ldo1, /* LDO1 */
  493. &smdk6410_vdduh_mmc, /* LDO2 */
  494. NULL, /* LDO3 NC */
  495. &smdk6410_vddotgi, /* LDO4 */
  496. &smdk6410_vddotg, /* LDO5 */
  497. &smdk6410_vddhi, /* LDO6 */
  498. &smdk6410_vddaudio, /* LDO7 */
  499. &smdk6410_vccm2mtv, /* LDO8 */
  500. &smdk6410_vddpll, /* LDO9 */
  501. &smdk6410_vccmc3bt, /* LDO10 */
  502. &smdk6410_vddalive, /* LDO11 */
  503. },
  504. .status = {
  505. &wm1192_led7_pdata,
  506. &wm1192_led8_pdata,
  507. },
  508. };
  509. #endif
  510. static struct i2c_board_info i2c_devs0[] __initdata = {
  511. { I2C_BOARD_INFO("24c08", 0x50), },
  512. { I2C_BOARD_INFO("wm8580", 0x1b), },
  513. #ifdef CONFIG_SMDK6410_WM1192_EV1
  514. { I2C_BOARD_INFO("wm8312", 0x34),
  515. .platform_data = &smdk6410_wm1192_pdata,
  516. .irq = S3C_EINT(12),
  517. },
  518. #endif
  519. #ifdef CONFIG_SMDK6410_WM1190_EV1
  520. { I2C_BOARD_INFO("wm8350", 0x1a),
  521. .platform_data = &smdk6410_wm8350_pdata,
  522. .irq = S3C_EINT(12),
  523. },
  524. #endif
  525. };
  526. static struct i2c_board_info i2c_devs1[] __initdata = {
  527. { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */
  528. };
  529. static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
  530. .delay = 10000,
  531. .presc = 49,
  532. .oversampling_shift = 2,
  533. };
  534. static void __init smdk6410_map_io(void)
  535. {
  536. u32 tmp;
  537. s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
  538. s3c24xx_init_clocks(12000000);
  539. s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
  540. /* set the LCD type */
  541. tmp = __raw_readl(S3C64XX_SPCON);
  542. tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
  543. tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
  544. __raw_writel(tmp, S3C64XX_SPCON);
  545. /* remove the lcd bypass */
  546. tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
  547. tmp &= ~MIFPCON_LCD_BYPASS;
  548. __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
  549. }
  550. static void __init smdk6410_machine_init(void)
  551. {
  552. u32 cs1;
  553. s3c_i2c0_set_platdata(NULL);
  554. s3c_i2c1_set_platdata(NULL);
  555. s3c_fb_set_platdata(&smdk6410_lcd_pdata);
  556. s3c24xx_ts_set_platdata(&s3c_ts_platform);
  557. /* configure nCS1 width to 16 bits */
  558. cs1 = __raw_readl(S3C64XX_SROM_BW) &
  559. ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
  560. cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
  561. (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
  562. (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
  563. S3C64XX_SROM_BW__NCS1__SHIFT;
  564. __raw_writel(cs1, S3C64XX_SROM_BW);
  565. /* set timing for nCS1 suitable for ethernet chip */
  566. __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
  567. (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
  568. (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
  569. (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
  570. (0xe << S3C64XX_SROM_BCX__TACC__SHIFT) |
  571. (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
  572. (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
  573. gpio_request(S3C64XX_GPN(5), "LCD power");
  574. gpio_request(S3C64XX_GPF(13), "LCD power");
  575. gpio_request(S3C64XX_GPF(15), "LCD power");
  576. i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
  577. i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
  578. platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
  579. }
  580. MACHINE_START(SMDK6410, "SMDK6410")
  581. /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
  582. .phys_io = S3C_PA_UART & 0xfff00000,
  583. .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
  584. .boot_params = S3C64XX_PA_SDRAM + 0x100,
  585. .init_irq = s3c6410_init_irq,
  586. .map_io = smdk6410_map_io,
  587. .init_machine = smdk6410_machine_init,
  588. .timer = &s3c24xx_timer,
  589. MACHINE_END