resource_tracker.c 110 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
  4. * All rights reserved.
  5. * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
  6. *
  7. * This software is available to you under a choice of one of two
  8. * licenses. You may choose to be licensed under the terms of the GNU
  9. * General Public License (GPL) Version 2, available from the file
  10. * COPYING in the main directory of this source tree, or the
  11. * OpenIB.org BSD license below:
  12. *
  13. * Redistribution and use in source and binary forms, with or
  14. * without modification, are permitted provided that the following
  15. * conditions are met:
  16. *
  17. * - Redistributions of source code must retain the above
  18. * copyright notice, this list of conditions and the following
  19. * disclaimer.
  20. *
  21. * - Redistributions in binary form must reproduce the above
  22. * copyright notice, this list of conditions and the following
  23. * disclaimer in the documentation and/or other materials
  24. * provided with the distribution.
  25. *
  26. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33. * SOFTWARE.
  34. */
  35. #include <linux/sched.h>
  36. #include <linux/pci.h>
  37. #include <linux/errno.h>
  38. #include <linux/kernel.h>
  39. #include <linux/io.h>
  40. #include <linux/slab.h>
  41. #include <linux/mlx4/cmd.h>
  42. #include <linux/mlx4/qp.h>
  43. #include <linux/if_ether.h>
  44. #include <linux/etherdevice.h>
  45. #include "mlx4.h"
  46. #include "fw.h"
  47. #define MLX4_MAC_VALID (1ull << 63)
  48. struct mac_res {
  49. struct list_head list;
  50. u64 mac;
  51. u8 port;
  52. };
  53. struct vlan_res {
  54. struct list_head list;
  55. u16 vlan;
  56. int ref_count;
  57. int vlan_index;
  58. u8 port;
  59. };
  60. struct res_common {
  61. struct list_head list;
  62. struct rb_node node;
  63. u64 res_id;
  64. int owner;
  65. int state;
  66. int from_state;
  67. int to_state;
  68. int removing;
  69. };
  70. enum {
  71. RES_ANY_BUSY = 1
  72. };
  73. struct res_gid {
  74. struct list_head list;
  75. u8 gid[16];
  76. enum mlx4_protocol prot;
  77. enum mlx4_steer_type steer;
  78. u64 reg_id;
  79. };
  80. enum res_qp_states {
  81. RES_QP_BUSY = RES_ANY_BUSY,
  82. /* QP number was allocated */
  83. RES_QP_RESERVED,
  84. /* ICM memory for QP context was mapped */
  85. RES_QP_MAPPED,
  86. /* QP is in hw ownership */
  87. RES_QP_HW
  88. };
  89. struct res_qp {
  90. struct res_common com;
  91. struct res_mtt *mtt;
  92. struct res_cq *rcq;
  93. struct res_cq *scq;
  94. struct res_srq *srq;
  95. struct list_head mcg_list;
  96. spinlock_t mcg_spl;
  97. int local_qpn;
  98. atomic_t ref_count;
  99. u32 qpc_flags;
  100. /* saved qp params before VST enforcement in order to restore on VGT */
  101. u8 sched_queue;
  102. __be32 param3;
  103. u8 vlan_control;
  104. u8 fvl_rx;
  105. u8 pri_path_fl;
  106. u8 vlan_index;
  107. u8 feup;
  108. };
  109. enum res_mtt_states {
  110. RES_MTT_BUSY = RES_ANY_BUSY,
  111. RES_MTT_ALLOCATED,
  112. };
  113. static inline const char *mtt_states_str(enum res_mtt_states state)
  114. {
  115. switch (state) {
  116. case RES_MTT_BUSY: return "RES_MTT_BUSY";
  117. case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
  118. default: return "Unknown";
  119. }
  120. }
  121. struct res_mtt {
  122. struct res_common com;
  123. int order;
  124. atomic_t ref_count;
  125. };
  126. enum res_mpt_states {
  127. RES_MPT_BUSY = RES_ANY_BUSY,
  128. RES_MPT_RESERVED,
  129. RES_MPT_MAPPED,
  130. RES_MPT_HW,
  131. };
  132. struct res_mpt {
  133. struct res_common com;
  134. struct res_mtt *mtt;
  135. int key;
  136. };
  137. enum res_eq_states {
  138. RES_EQ_BUSY = RES_ANY_BUSY,
  139. RES_EQ_RESERVED,
  140. RES_EQ_HW,
  141. };
  142. struct res_eq {
  143. struct res_common com;
  144. struct res_mtt *mtt;
  145. };
  146. enum res_cq_states {
  147. RES_CQ_BUSY = RES_ANY_BUSY,
  148. RES_CQ_ALLOCATED,
  149. RES_CQ_HW,
  150. };
  151. struct res_cq {
  152. struct res_common com;
  153. struct res_mtt *mtt;
  154. atomic_t ref_count;
  155. };
  156. enum res_srq_states {
  157. RES_SRQ_BUSY = RES_ANY_BUSY,
  158. RES_SRQ_ALLOCATED,
  159. RES_SRQ_HW,
  160. };
  161. struct res_srq {
  162. struct res_common com;
  163. struct res_mtt *mtt;
  164. struct res_cq *cq;
  165. atomic_t ref_count;
  166. };
  167. enum res_counter_states {
  168. RES_COUNTER_BUSY = RES_ANY_BUSY,
  169. RES_COUNTER_ALLOCATED,
  170. };
  171. struct res_counter {
  172. struct res_common com;
  173. int port;
  174. };
  175. enum res_xrcdn_states {
  176. RES_XRCD_BUSY = RES_ANY_BUSY,
  177. RES_XRCD_ALLOCATED,
  178. };
  179. struct res_xrcdn {
  180. struct res_common com;
  181. int port;
  182. };
  183. enum res_fs_rule_states {
  184. RES_FS_RULE_BUSY = RES_ANY_BUSY,
  185. RES_FS_RULE_ALLOCATED,
  186. };
  187. struct res_fs_rule {
  188. struct res_common com;
  189. int qpn;
  190. };
  191. static void *res_tracker_lookup(struct rb_root *root, u64 res_id)
  192. {
  193. struct rb_node *node = root->rb_node;
  194. while (node) {
  195. struct res_common *res = container_of(node, struct res_common,
  196. node);
  197. if (res_id < res->res_id)
  198. node = node->rb_left;
  199. else if (res_id > res->res_id)
  200. node = node->rb_right;
  201. else
  202. return res;
  203. }
  204. return NULL;
  205. }
  206. static int res_tracker_insert(struct rb_root *root, struct res_common *res)
  207. {
  208. struct rb_node **new = &(root->rb_node), *parent = NULL;
  209. /* Figure out where to put new node */
  210. while (*new) {
  211. struct res_common *this = container_of(*new, struct res_common,
  212. node);
  213. parent = *new;
  214. if (res->res_id < this->res_id)
  215. new = &((*new)->rb_left);
  216. else if (res->res_id > this->res_id)
  217. new = &((*new)->rb_right);
  218. else
  219. return -EEXIST;
  220. }
  221. /* Add new node and rebalance tree. */
  222. rb_link_node(&res->node, parent, new);
  223. rb_insert_color(&res->node, root);
  224. return 0;
  225. }
  226. enum qp_transition {
  227. QP_TRANS_INIT2RTR,
  228. QP_TRANS_RTR2RTS,
  229. QP_TRANS_RTS2RTS,
  230. QP_TRANS_SQERR2RTS,
  231. QP_TRANS_SQD2SQD,
  232. QP_TRANS_SQD2RTS
  233. };
  234. /* For Debug uses */
  235. static const char *ResourceType(enum mlx4_resource rt)
  236. {
  237. switch (rt) {
  238. case RES_QP: return "RES_QP";
  239. case RES_CQ: return "RES_CQ";
  240. case RES_SRQ: return "RES_SRQ";
  241. case RES_MPT: return "RES_MPT";
  242. case RES_MTT: return "RES_MTT";
  243. case RES_MAC: return "RES_MAC";
  244. case RES_VLAN: return "RES_VLAN";
  245. case RES_EQ: return "RES_EQ";
  246. case RES_COUNTER: return "RES_COUNTER";
  247. case RES_FS_RULE: return "RES_FS_RULE";
  248. case RES_XRCD: return "RES_XRCD";
  249. default: return "Unknown resource type !!!";
  250. };
  251. }
  252. static void rem_slave_vlans(struct mlx4_dev *dev, int slave);
  253. static inline int mlx4_grant_resource(struct mlx4_dev *dev, int slave,
  254. enum mlx4_resource res_type, int count,
  255. int port)
  256. {
  257. struct mlx4_priv *priv = mlx4_priv(dev);
  258. struct resource_allocator *res_alloc =
  259. &priv->mfunc.master.res_tracker.res_alloc[res_type];
  260. int err = -EINVAL;
  261. int allocated, free, reserved, guaranteed, from_free;
  262. if (slave > dev->num_vfs)
  263. return -EINVAL;
  264. spin_lock(&res_alloc->alloc_lock);
  265. allocated = (port > 0) ?
  266. res_alloc->allocated[(port - 1) * (dev->num_vfs + 1) + slave] :
  267. res_alloc->allocated[slave];
  268. free = (port > 0) ? res_alloc->res_port_free[port - 1] :
  269. res_alloc->res_free;
  270. reserved = (port > 0) ? res_alloc->res_port_rsvd[port - 1] :
  271. res_alloc->res_reserved;
  272. guaranteed = res_alloc->guaranteed[slave];
  273. if (allocated + count > res_alloc->quota[slave])
  274. goto out;
  275. if (allocated + count <= guaranteed) {
  276. err = 0;
  277. } else {
  278. /* portion may need to be obtained from free area */
  279. if (guaranteed - allocated > 0)
  280. from_free = count - (guaranteed - allocated);
  281. else
  282. from_free = count;
  283. if (free - from_free > reserved)
  284. err = 0;
  285. }
  286. if (!err) {
  287. /* grant the request */
  288. if (port > 0) {
  289. res_alloc->allocated[(port - 1) * (dev->num_vfs + 1) + slave] += count;
  290. res_alloc->res_port_free[port - 1] -= count;
  291. } else {
  292. res_alloc->allocated[slave] += count;
  293. res_alloc->res_free -= count;
  294. }
  295. }
  296. out:
  297. spin_unlock(&res_alloc->alloc_lock);
  298. return err;
  299. }
  300. static inline void mlx4_release_resource(struct mlx4_dev *dev, int slave,
  301. enum mlx4_resource res_type, int count,
  302. int port)
  303. {
  304. struct mlx4_priv *priv = mlx4_priv(dev);
  305. struct resource_allocator *res_alloc =
  306. &priv->mfunc.master.res_tracker.res_alloc[res_type];
  307. if (slave > dev->num_vfs)
  308. return;
  309. spin_lock(&res_alloc->alloc_lock);
  310. if (port > 0) {
  311. res_alloc->allocated[(port - 1) * (dev->num_vfs + 1) + slave] -= count;
  312. res_alloc->res_port_free[port - 1] += count;
  313. } else {
  314. res_alloc->allocated[slave] -= count;
  315. res_alloc->res_free += count;
  316. }
  317. spin_unlock(&res_alloc->alloc_lock);
  318. return;
  319. }
  320. static inline void initialize_res_quotas(struct mlx4_dev *dev,
  321. struct resource_allocator *res_alloc,
  322. enum mlx4_resource res_type,
  323. int vf, int num_instances)
  324. {
  325. res_alloc->guaranteed[vf] = num_instances / (2 * (dev->num_vfs + 1));
  326. res_alloc->quota[vf] = (num_instances / 2) + res_alloc->guaranteed[vf];
  327. if (vf == mlx4_master_func_num(dev)) {
  328. res_alloc->res_free = num_instances;
  329. if (res_type == RES_MTT) {
  330. /* reserved mtts will be taken out of the PF allocation */
  331. res_alloc->res_free += dev->caps.reserved_mtts;
  332. res_alloc->guaranteed[vf] += dev->caps.reserved_mtts;
  333. res_alloc->quota[vf] += dev->caps.reserved_mtts;
  334. }
  335. }
  336. }
  337. void mlx4_init_quotas(struct mlx4_dev *dev)
  338. {
  339. struct mlx4_priv *priv = mlx4_priv(dev);
  340. int pf;
  341. /* quotas for VFs are initialized in mlx4_slave_cap */
  342. if (mlx4_is_slave(dev))
  343. return;
  344. if (!mlx4_is_mfunc(dev)) {
  345. dev->quotas.qp = dev->caps.num_qps - dev->caps.reserved_qps -
  346. mlx4_num_reserved_sqps(dev);
  347. dev->quotas.cq = dev->caps.num_cqs - dev->caps.reserved_cqs;
  348. dev->quotas.srq = dev->caps.num_srqs - dev->caps.reserved_srqs;
  349. dev->quotas.mtt = dev->caps.num_mtts - dev->caps.reserved_mtts;
  350. dev->quotas.mpt = dev->caps.num_mpts - dev->caps.reserved_mrws;
  351. return;
  352. }
  353. pf = mlx4_master_func_num(dev);
  354. dev->quotas.qp =
  355. priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[pf];
  356. dev->quotas.cq =
  357. priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[pf];
  358. dev->quotas.srq =
  359. priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[pf];
  360. dev->quotas.mtt =
  361. priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[pf];
  362. dev->quotas.mpt =
  363. priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[pf];
  364. }
  365. int mlx4_init_resource_tracker(struct mlx4_dev *dev)
  366. {
  367. struct mlx4_priv *priv = mlx4_priv(dev);
  368. int i, j;
  369. int t;
  370. priv->mfunc.master.res_tracker.slave_list =
  371. kzalloc(dev->num_slaves * sizeof(struct slave_list),
  372. GFP_KERNEL);
  373. if (!priv->mfunc.master.res_tracker.slave_list)
  374. return -ENOMEM;
  375. for (i = 0 ; i < dev->num_slaves; i++) {
  376. for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
  377. INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
  378. slave_list[i].res_list[t]);
  379. mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  380. }
  381. mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
  382. dev->num_slaves);
  383. for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
  384. priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT;
  385. for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
  386. struct resource_allocator *res_alloc =
  387. &priv->mfunc.master.res_tracker.res_alloc[i];
  388. res_alloc->quota = kmalloc((dev->num_vfs + 1) * sizeof(int), GFP_KERNEL);
  389. res_alloc->guaranteed = kmalloc((dev->num_vfs + 1) * sizeof(int), GFP_KERNEL);
  390. if (i == RES_MAC || i == RES_VLAN)
  391. res_alloc->allocated = kzalloc(MLX4_MAX_PORTS *
  392. (dev->num_vfs + 1) * sizeof(int),
  393. GFP_KERNEL);
  394. else
  395. res_alloc->allocated = kzalloc((dev->num_vfs + 1) * sizeof(int), GFP_KERNEL);
  396. if (!res_alloc->quota || !res_alloc->guaranteed ||
  397. !res_alloc->allocated)
  398. goto no_mem_err;
  399. spin_lock_init(&res_alloc->alloc_lock);
  400. for (t = 0; t < dev->num_vfs + 1; t++) {
  401. switch (i) {
  402. case RES_QP:
  403. initialize_res_quotas(dev, res_alloc, RES_QP,
  404. t, dev->caps.num_qps -
  405. dev->caps.reserved_qps -
  406. mlx4_num_reserved_sqps(dev));
  407. break;
  408. case RES_CQ:
  409. initialize_res_quotas(dev, res_alloc, RES_CQ,
  410. t, dev->caps.num_cqs -
  411. dev->caps.reserved_cqs);
  412. break;
  413. case RES_SRQ:
  414. initialize_res_quotas(dev, res_alloc, RES_SRQ,
  415. t, dev->caps.num_srqs -
  416. dev->caps.reserved_srqs);
  417. break;
  418. case RES_MPT:
  419. initialize_res_quotas(dev, res_alloc, RES_MPT,
  420. t, dev->caps.num_mpts -
  421. dev->caps.reserved_mrws);
  422. break;
  423. case RES_MTT:
  424. initialize_res_quotas(dev, res_alloc, RES_MTT,
  425. t, dev->caps.num_mtts -
  426. dev->caps.reserved_mtts);
  427. break;
  428. case RES_MAC:
  429. if (t == mlx4_master_func_num(dev)) {
  430. res_alloc->quota[t] = MLX4_MAX_MAC_NUM;
  431. res_alloc->guaranteed[t] = 2;
  432. for (j = 0; j < MLX4_MAX_PORTS; j++)
  433. res_alloc->res_port_free[j] = MLX4_MAX_MAC_NUM;
  434. } else {
  435. res_alloc->quota[t] = MLX4_MAX_MAC_NUM;
  436. res_alloc->guaranteed[t] = 2;
  437. }
  438. break;
  439. case RES_VLAN:
  440. if (t == mlx4_master_func_num(dev)) {
  441. res_alloc->quota[t] = MLX4_MAX_VLAN_NUM;
  442. res_alloc->guaranteed[t] = MLX4_MAX_VLAN_NUM / 2;
  443. for (j = 0; j < MLX4_MAX_PORTS; j++)
  444. res_alloc->res_port_free[j] =
  445. res_alloc->quota[t];
  446. } else {
  447. res_alloc->quota[t] = MLX4_MAX_VLAN_NUM / 2;
  448. res_alloc->guaranteed[t] = 0;
  449. }
  450. break;
  451. case RES_COUNTER:
  452. res_alloc->quota[t] = dev->caps.max_counters;
  453. res_alloc->guaranteed[t] = 0;
  454. if (t == mlx4_master_func_num(dev))
  455. res_alloc->res_free = res_alloc->quota[t];
  456. break;
  457. default:
  458. break;
  459. }
  460. if (i == RES_MAC || i == RES_VLAN) {
  461. for (j = 0; j < MLX4_MAX_PORTS; j++)
  462. res_alloc->res_port_rsvd[j] +=
  463. res_alloc->guaranteed[t];
  464. } else {
  465. res_alloc->res_reserved += res_alloc->guaranteed[t];
  466. }
  467. }
  468. }
  469. spin_lock_init(&priv->mfunc.master.res_tracker.lock);
  470. return 0;
  471. no_mem_err:
  472. for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
  473. kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
  474. priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
  475. kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
  476. priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
  477. kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
  478. priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
  479. }
  480. return -ENOMEM;
  481. }
  482. void mlx4_free_resource_tracker(struct mlx4_dev *dev,
  483. enum mlx4_res_tracker_free_type type)
  484. {
  485. struct mlx4_priv *priv = mlx4_priv(dev);
  486. int i;
  487. if (priv->mfunc.master.res_tracker.slave_list) {
  488. if (type != RES_TR_FREE_STRUCTS_ONLY) {
  489. for (i = 0; i < dev->num_slaves; i++) {
  490. if (type == RES_TR_FREE_ALL ||
  491. dev->caps.function != i)
  492. mlx4_delete_all_resources_for_slave(dev, i);
  493. }
  494. /* free master's vlans */
  495. i = dev->caps.function;
  496. mutex_lock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  497. rem_slave_vlans(dev, i);
  498. mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  499. }
  500. if (type != RES_TR_FREE_SLAVES_ONLY) {
  501. for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
  502. kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
  503. priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
  504. kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
  505. priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
  506. kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
  507. priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
  508. }
  509. kfree(priv->mfunc.master.res_tracker.slave_list);
  510. priv->mfunc.master.res_tracker.slave_list = NULL;
  511. }
  512. }
  513. }
  514. static void update_pkey_index(struct mlx4_dev *dev, int slave,
  515. struct mlx4_cmd_mailbox *inbox)
  516. {
  517. u8 sched = *(u8 *)(inbox->buf + 64);
  518. u8 orig_index = *(u8 *)(inbox->buf + 35);
  519. u8 new_index;
  520. struct mlx4_priv *priv = mlx4_priv(dev);
  521. int port;
  522. port = (sched >> 6 & 1) + 1;
  523. new_index = priv->virt2phys_pkey[slave][port - 1][orig_index];
  524. *(u8 *)(inbox->buf + 35) = new_index;
  525. }
  526. static void update_gid(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *inbox,
  527. u8 slave)
  528. {
  529. struct mlx4_qp_context *qp_ctx = inbox->buf + 8;
  530. enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *) inbox->buf);
  531. u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  532. if (MLX4_QP_ST_UD == ts)
  533. qp_ctx->pri_path.mgid_index = 0x80 | slave;
  534. if (MLX4_QP_ST_RC == ts || MLX4_QP_ST_UC == ts) {
  535. if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH)
  536. qp_ctx->pri_path.mgid_index = slave & 0x7F;
  537. if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH)
  538. qp_ctx->alt_path.mgid_index = slave & 0x7F;
  539. }
  540. }
  541. static int update_vport_qp_param(struct mlx4_dev *dev,
  542. struct mlx4_cmd_mailbox *inbox,
  543. u8 slave, u32 qpn)
  544. {
  545. struct mlx4_qp_context *qpc = inbox->buf + 8;
  546. struct mlx4_vport_oper_state *vp_oper;
  547. struct mlx4_priv *priv;
  548. u32 qp_type;
  549. int port;
  550. port = (qpc->pri_path.sched_queue & 0x40) ? 2 : 1;
  551. priv = mlx4_priv(dev);
  552. vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
  553. if (MLX4_VGT != vp_oper->state.default_vlan) {
  554. qp_type = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
  555. if (MLX4_QP_ST_RC == qp_type ||
  556. (MLX4_QP_ST_UD == qp_type &&
  557. !mlx4_is_qp_reserved(dev, qpn)))
  558. return -EINVAL;
  559. /* the reserved QPs (special, proxy, tunnel)
  560. * do not operate over vlans
  561. */
  562. if (mlx4_is_qp_reserved(dev, qpn))
  563. return 0;
  564. /* force strip vlan by clear vsd */
  565. qpc->param3 &= ~cpu_to_be32(MLX4_STRIP_VLAN);
  566. if (vp_oper->state.link_state == IFLA_VF_LINK_STATE_DISABLE &&
  567. dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP) {
  568. qpc->pri_path.vlan_control =
  569. MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  570. MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
  571. MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
  572. MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
  573. MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
  574. MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
  575. } else if (0 != vp_oper->state.default_vlan) {
  576. qpc->pri_path.vlan_control =
  577. MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  578. MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
  579. MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
  580. } else { /* priority tagged */
  581. qpc->pri_path.vlan_control =
  582. MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  583. MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
  584. }
  585. qpc->pri_path.fvl_rx |= MLX4_FVL_RX_FORCE_ETH_VLAN;
  586. qpc->pri_path.vlan_index = vp_oper->vlan_idx;
  587. qpc->pri_path.fl |= MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
  588. qpc->pri_path.feup |= MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
  589. qpc->pri_path.sched_queue &= 0xC7;
  590. qpc->pri_path.sched_queue |= (vp_oper->state.default_qos) << 3;
  591. }
  592. if (vp_oper->state.spoofchk) {
  593. qpc->pri_path.feup |= MLX4_FSM_FORCE_ETH_SRC_MAC;
  594. qpc->pri_path.grh_mylmc = (0x80 & qpc->pri_path.grh_mylmc) + vp_oper->mac_idx;
  595. }
  596. return 0;
  597. }
  598. static int mpt_mask(struct mlx4_dev *dev)
  599. {
  600. return dev->caps.num_mpts - 1;
  601. }
  602. static void *find_res(struct mlx4_dev *dev, u64 res_id,
  603. enum mlx4_resource type)
  604. {
  605. struct mlx4_priv *priv = mlx4_priv(dev);
  606. return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
  607. res_id);
  608. }
  609. static int get_res(struct mlx4_dev *dev, int slave, u64 res_id,
  610. enum mlx4_resource type,
  611. void *res)
  612. {
  613. struct res_common *r;
  614. int err = 0;
  615. spin_lock_irq(mlx4_tlock(dev));
  616. r = find_res(dev, res_id, type);
  617. if (!r) {
  618. err = -ENONET;
  619. goto exit;
  620. }
  621. if (r->state == RES_ANY_BUSY) {
  622. err = -EBUSY;
  623. goto exit;
  624. }
  625. if (r->owner != slave) {
  626. err = -EPERM;
  627. goto exit;
  628. }
  629. r->from_state = r->state;
  630. r->state = RES_ANY_BUSY;
  631. if (res)
  632. *((struct res_common **)res) = r;
  633. exit:
  634. spin_unlock_irq(mlx4_tlock(dev));
  635. return err;
  636. }
  637. int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
  638. enum mlx4_resource type,
  639. u64 res_id, int *slave)
  640. {
  641. struct res_common *r;
  642. int err = -ENOENT;
  643. int id = res_id;
  644. if (type == RES_QP)
  645. id &= 0x7fffff;
  646. spin_lock(mlx4_tlock(dev));
  647. r = find_res(dev, id, type);
  648. if (r) {
  649. *slave = r->owner;
  650. err = 0;
  651. }
  652. spin_unlock(mlx4_tlock(dev));
  653. return err;
  654. }
  655. static void put_res(struct mlx4_dev *dev, int slave, u64 res_id,
  656. enum mlx4_resource type)
  657. {
  658. struct res_common *r;
  659. spin_lock_irq(mlx4_tlock(dev));
  660. r = find_res(dev, res_id, type);
  661. if (r)
  662. r->state = r->from_state;
  663. spin_unlock_irq(mlx4_tlock(dev));
  664. }
  665. static struct res_common *alloc_qp_tr(int id)
  666. {
  667. struct res_qp *ret;
  668. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  669. if (!ret)
  670. return NULL;
  671. ret->com.res_id = id;
  672. ret->com.state = RES_QP_RESERVED;
  673. ret->local_qpn = id;
  674. INIT_LIST_HEAD(&ret->mcg_list);
  675. spin_lock_init(&ret->mcg_spl);
  676. atomic_set(&ret->ref_count, 0);
  677. return &ret->com;
  678. }
  679. static struct res_common *alloc_mtt_tr(int id, int order)
  680. {
  681. struct res_mtt *ret;
  682. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  683. if (!ret)
  684. return NULL;
  685. ret->com.res_id = id;
  686. ret->order = order;
  687. ret->com.state = RES_MTT_ALLOCATED;
  688. atomic_set(&ret->ref_count, 0);
  689. return &ret->com;
  690. }
  691. static struct res_common *alloc_mpt_tr(int id, int key)
  692. {
  693. struct res_mpt *ret;
  694. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  695. if (!ret)
  696. return NULL;
  697. ret->com.res_id = id;
  698. ret->com.state = RES_MPT_RESERVED;
  699. ret->key = key;
  700. return &ret->com;
  701. }
  702. static struct res_common *alloc_eq_tr(int id)
  703. {
  704. struct res_eq *ret;
  705. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  706. if (!ret)
  707. return NULL;
  708. ret->com.res_id = id;
  709. ret->com.state = RES_EQ_RESERVED;
  710. return &ret->com;
  711. }
  712. static struct res_common *alloc_cq_tr(int id)
  713. {
  714. struct res_cq *ret;
  715. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  716. if (!ret)
  717. return NULL;
  718. ret->com.res_id = id;
  719. ret->com.state = RES_CQ_ALLOCATED;
  720. atomic_set(&ret->ref_count, 0);
  721. return &ret->com;
  722. }
  723. static struct res_common *alloc_srq_tr(int id)
  724. {
  725. struct res_srq *ret;
  726. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  727. if (!ret)
  728. return NULL;
  729. ret->com.res_id = id;
  730. ret->com.state = RES_SRQ_ALLOCATED;
  731. atomic_set(&ret->ref_count, 0);
  732. return &ret->com;
  733. }
  734. static struct res_common *alloc_counter_tr(int id)
  735. {
  736. struct res_counter *ret;
  737. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  738. if (!ret)
  739. return NULL;
  740. ret->com.res_id = id;
  741. ret->com.state = RES_COUNTER_ALLOCATED;
  742. return &ret->com;
  743. }
  744. static struct res_common *alloc_xrcdn_tr(int id)
  745. {
  746. struct res_xrcdn *ret;
  747. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  748. if (!ret)
  749. return NULL;
  750. ret->com.res_id = id;
  751. ret->com.state = RES_XRCD_ALLOCATED;
  752. return &ret->com;
  753. }
  754. static struct res_common *alloc_fs_rule_tr(u64 id, int qpn)
  755. {
  756. struct res_fs_rule *ret;
  757. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  758. if (!ret)
  759. return NULL;
  760. ret->com.res_id = id;
  761. ret->com.state = RES_FS_RULE_ALLOCATED;
  762. ret->qpn = qpn;
  763. return &ret->com;
  764. }
  765. static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave,
  766. int extra)
  767. {
  768. struct res_common *ret;
  769. switch (type) {
  770. case RES_QP:
  771. ret = alloc_qp_tr(id);
  772. break;
  773. case RES_MPT:
  774. ret = alloc_mpt_tr(id, extra);
  775. break;
  776. case RES_MTT:
  777. ret = alloc_mtt_tr(id, extra);
  778. break;
  779. case RES_EQ:
  780. ret = alloc_eq_tr(id);
  781. break;
  782. case RES_CQ:
  783. ret = alloc_cq_tr(id);
  784. break;
  785. case RES_SRQ:
  786. ret = alloc_srq_tr(id);
  787. break;
  788. case RES_MAC:
  789. printk(KERN_ERR "implementation missing\n");
  790. return NULL;
  791. case RES_COUNTER:
  792. ret = alloc_counter_tr(id);
  793. break;
  794. case RES_XRCD:
  795. ret = alloc_xrcdn_tr(id);
  796. break;
  797. case RES_FS_RULE:
  798. ret = alloc_fs_rule_tr(id, extra);
  799. break;
  800. default:
  801. return NULL;
  802. }
  803. if (ret)
  804. ret->owner = slave;
  805. return ret;
  806. }
  807. static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
  808. enum mlx4_resource type, int extra)
  809. {
  810. int i;
  811. int err;
  812. struct mlx4_priv *priv = mlx4_priv(dev);
  813. struct res_common **res_arr;
  814. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  815. struct rb_root *root = &tracker->res_tree[type];
  816. res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
  817. if (!res_arr)
  818. return -ENOMEM;
  819. for (i = 0; i < count; ++i) {
  820. res_arr[i] = alloc_tr(base + i, type, slave, extra);
  821. if (!res_arr[i]) {
  822. for (--i; i >= 0; --i)
  823. kfree(res_arr[i]);
  824. kfree(res_arr);
  825. return -ENOMEM;
  826. }
  827. }
  828. spin_lock_irq(mlx4_tlock(dev));
  829. for (i = 0; i < count; ++i) {
  830. if (find_res(dev, base + i, type)) {
  831. err = -EEXIST;
  832. goto undo;
  833. }
  834. err = res_tracker_insert(root, res_arr[i]);
  835. if (err)
  836. goto undo;
  837. list_add_tail(&res_arr[i]->list,
  838. &tracker->slave_list[slave].res_list[type]);
  839. }
  840. spin_unlock_irq(mlx4_tlock(dev));
  841. kfree(res_arr);
  842. return 0;
  843. undo:
  844. for (--i; i >= base; --i)
  845. rb_erase(&res_arr[i]->node, root);
  846. spin_unlock_irq(mlx4_tlock(dev));
  847. for (i = 0; i < count; ++i)
  848. kfree(res_arr[i]);
  849. kfree(res_arr);
  850. return err;
  851. }
  852. static int remove_qp_ok(struct res_qp *res)
  853. {
  854. if (res->com.state == RES_QP_BUSY || atomic_read(&res->ref_count) ||
  855. !list_empty(&res->mcg_list)) {
  856. pr_err("resource tracker: fail to remove qp, state %d, ref_count %d\n",
  857. res->com.state, atomic_read(&res->ref_count));
  858. return -EBUSY;
  859. } else if (res->com.state != RES_QP_RESERVED) {
  860. return -EPERM;
  861. }
  862. return 0;
  863. }
  864. static int remove_mtt_ok(struct res_mtt *res, int order)
  865. {
  866. if (res->com.state == RES_MTT_BUSY ||
  867. atomic_read(&res->ref_count)) {
  868. printk(KERN_DEBUG "%s-%d: state %s, ref_count %d\n",
  869. __func__, __LINE__,
  870. mtt_states_str(res->com.state),
  871. atomic_read(&res->ref_count));
  872. return -EBUSY;
  873. } else if (res->com.state != RES_MTT_ALLOCATED)
  874. return -EPERM;
  875. else if (res->order != order)
  876. return -EINVAL;
  877. return 0;
  878. }
  879. static int remove_mpt_ok(struct res_mpt *res)
  880. {
  881. if (res->com.state == RES_MPT_BUSY)
  882. return -EBUSY;
  883. else if (res->com.state != RES_MPT_RESERVED)
  884. return -EPERM;
  885. return 0;
  886. }
  887. static int remove_eq_ok(struct res_eq *res)
  888. {
  889. if (res->com.state == RES_MPT_BUSY)
  890. return -EBUSY;
  891. else if (res->com.state != RES_MPT_RESERVED)
  892. return -EPERM;
  893. return 0;
  894. }
  895. static int remove_counter_ok(struct res_counter *res)
  896. {
  897. if (res->com.state == RES_COUNTER_BUSY)
  898. return -EBUSY;
  899. else if (res->com.state != RES_COUNTER_ALLOCATED)
  900. return -EPERM;
  901. return 0;
  902. }
  903. static int remove_xrcdn_ok(struct res_xrcdn *res)
  904. {
  905. if (res->com.state == RES_XRCD_BUSY)
  906. return -EBUSY;
  907. else if (res->com.state != RES_XRCD_ALLOCATED)
  908. return -EPERM;
  909. return 0;
  910. }
  911. static int remove_fs_rule_ok(struct res_fs_rule *res)
  912. {
  913. if (res->com.state == RES_FS_RULE_BUSY)
  914. return -EBUSY;
  915. else if (res->com.state != RES_FS_RULE_ALLOCATED)
  916. return -EPERM;
  917. return 0;
  918. }
  919. static int remove_cq_ok(struct res_cq *res)
  920. {
  921. if (res->com.state == RES_CQ_BUSY)
  922. return -EBUSY;
  923. else if (res->com.state != RES_CQ_ALLOCATED)
  924. return -EPERM;
  925. return 0;
  926. }
  927. static int remove_srq_ok(struct res_srq *res)
  928. {
  929. if (res->com.state == RES_SRQ_BUSY)
  930. return -EBUSY;
  931. else if (res->com.state != RES_SRQ_ALLOCATED)
  932. return -EPERM;
  933. return 0;
  934. }
  935. static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
  936. {
  937. switch (type) {
  938. case RES_QP:
  939. return remove_qp_ok((struct res_qp *)res);
  940. case RES_CQ:
  941. return remove_cq_ok((struct res_cq *)res);
  942. case RES_SRQ:
  943. return remove_srq_ok((struct res_srq *)res);
  944. case RES_MPT:
  945. return remove_mpt_ok((struct res_mpt *)res);
  946. case RES_MTT:
  947. return remove_mtt_ok((struct res_mtt *)res, extra);
  948. case RES_MAC:
  949. return -ENOSYS;
  950. case RES_EQ:
  951. return remove_eq_ok((struct res_eq *)res);
  952. case RES_COUNTER:
  953. return remove_counter_ok((struct res_counter *)res);
  954. case RES_XRCD:
  955. return remove_xrcdn_ok((struct res_xrcdn *)res);
  956. case RES_FS_RULE:
  957. return remove_fs_rule_ok((struct res_fs_rule *)res);
  958. default:
  959. return -EINVAL;
  960. }
  961. }
  962. static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
  963. enum mlx4_resource type, int extra)
  964. {
  965. u64 i;
  966. int err;
  967. struct mlx4_priv *priv = mlx4_priv(dev);
  968. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  969. struct res_common *r;
  970. spin_lock_irq(mlx4_tlock(dev));
  971. for (i = base; i < base + count; ++i) {
  972. r = res_tracker_lookup(&tracker->res_tree[type], i);
  973. if (!r) {
  974. err = -ENOENT;
  975. goto out;
  976. }
  977. if (r->owner != slave) {
  978. err = -EPERM;
  979. goto out;
  980. }
  981. err = remove_ok(r, type, extra);
  982. if (err)
  983. goto out;
  984. }
  985. for (i = base; i < base + count; ++i) {
  986. r = res_tracker_lookup(&tracker->res_tree[type], i);
  987. rb_erase(&r->node, &tracker->res_tree[type]);
  988. list_del(&r->list);
  989. kfree(r);
  990. }
  991. err = 0;
  992. out:
  993. spin_unlock_irq(mlx4_tlock(dev));
  994. return err;
  995. }
  996. static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
  997. enum res_qp_states state, struct res_qp **qp,
  998. int alloc)
  999. {
  1000. struct mlx4_priv *priv = mlx4_priv(dev);
  1001. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1002. struct res_qp *r;
  1003. int err = 0;
  1004. spin_lock_irq(mlx4_tlock(dev));
  1005. r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn);
  1006. if (!r)
  1007. err = -ENOENT;
  1008. else if (r->com.owner != slave)
  1009. err = -EPERM;
  1010. else {
  1011. switch (state) {
  1012. case RES_QP_BUSY:
  1013. mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n",
  1014. __func__, r->com.res_id);
  1015. err = -EBUSY;
  1016. break;
  1017. case RES_QP_RESERVED:
  1018. if (r->com.state == RES_QP_MAPPED && !alloc)
  1019. break;
  1020. mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", r->com.res_id);
  1021. err = -EINVAL;
  1022. break;
  1023. case RES_QP_MAPPED:
  1024. if ((r->com.state == RES_QP_RESERVED && alloc) ||
  1025. r->com.state == RES_QP_HW)
  1026. break;
  1027. else {
  1028. mlx4_dbg(dev, "failed RES_QP, 0x%llx\n",
  1029. r->com.res_id);
  1030. err = -EINVAL;
  1031. }
  1032. break;
  1033. case RES_QP_HW:
  1034. if (r->com.state != RES_QP_MAPPED)
  1035. err = -EINVAL;
  1036. break;
  1037. default:
  1038. err = -EINVAL;
  1039. }
  1040. if (!err) {
  1041. r->com.from_state = r->com.state;
  1042. r->com.to_state = state;
  1043. r->com.state = RES_QP_BUSY;
  1044. if (qp)
  1045. *qp = r;
  1046. }
  1047. }
  1048. spin_unlock_irq(mlx4_tlock(dev));
  1049. return err;
  1050. }
  1051. static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  1052. enum res_mpt_states state, struct res_mpt **mpt)
  1053. {
  1054. struct mlx4_priv *priv = mlx4_priv(dev);
  1055. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1056. struct res_mpt *r;
  1057. int err = 0;
  1058. spin_lock_irq(mlx4_tlock(dev));
  1059. r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index);
  1060. if (!r)
  1061. err = -ENOENT;
  1062. else if (r->com.owner != slave)
  1063. err = -EPERM;
  1064. else {
  1065. switch (state) {
  1066. case RES_MPT_BUSY:
  1067. err = -EINVAL;
  1068. break;
  1069. case RES_MPT_RESERVED:
  1070. if (r->com.state != RES_MPT_MAPPED)
  1071. err = -EINVAL;
  1072. break;
  1073. case RES_MPT_MAPPED:
  1074. if (r->com.state != RES_MPT_RESERVED &&
  1075. r->com.state != RES_MPT_HW)
  1076. err = -EINVAL;
  1077. break;
  1078. case RES_MPT_HW:
  1079. if (r->com.state != RES_MPT_MAPPED)
  1080. err = -EINVAL;
  1081. break;
  1082. default:
  1083. err = -EINVAL;
  1084. }
  1085. if (!err) {
  1086. r->com.from_state = r->com.state;
  1087. r->com.to_state = state;
  1088. r->com.state = RES_MPT_BUSY;
  1089. if (mpt)
  1090. *mpt = r;
  1091. }
  1092. }
  1093. spin_unlock_irq(mlx4_tlock(dev));
  1094. return err;
  1095. }
  1096. static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  1097. enum res_eq_states state, struct res_eq **eq)
  1098. {
  1099. struct mlx4_priv *priv = mlx4_priv(dev);
  1100. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1101. struct res_eq *r;
  1102. int err = 0;
  1103. spin_lock_irq(mlx4_tlock(dev));
  1104. r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index);
  1105. if (!r)
  1106. err = -ENOENT;
  1107. else if (r->com.owner != slave)
  1108. err = -EPERM;
  1109. else {
  1110. switch (state) {
  1111. case RES_EQ_BUSY:
  1112. err = -EINVAL;
  1113. break;
  1114. case RES_EQ_RESERVED:
  1115. if (r->com.state != RES_EQ_HW)
  1116. err = -EINVAL;
  1117. break;
  1118. case RES_EQ_HW:
  1119. if (r->com.state != RES_EQ_RESERVED)
  1120. err = -EINVAL;
  1121. break;
  1122. default:
  1123. err = -EINVAL;
  1124. }
  1125. if (!err) {
  1126. r->com.from_state = r->com.state;
  1127. r->com.to_state = state;
  1128. r->com.state = RES_EQ_BUSY;
  1129. if (eq)
  1130. *eq = r;
  1131. }
  1132. }
  1133. spin_unlock_irq(mlx4_tlock(dev));
  1134. return err;
  1135. }
  1136. static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
  1137. enum res_cq_states state, struct res_cq **cq)
  1138. {
  1139. struct mlx4_priv *priv = mlx4_priv(dev);
  1140. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1141. struct res_cq *r;
  1142. int err;
  1143. spin_lock_irq(mlx4_tlock(dev));
  1144. r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn);
  1145. if (!r)
  1146. err = -ENOENT;
  1147. else if (r->com.owner != slave)
  1148. err = -EPERM;
  1149. else {
  1150. switch (state) {
  1151. case RES_CQ_BUSY:
  1152. err = -EBUSY;
  1153. break;
  1154. case RES_CQ_ALLOCATED:
  1155. if (r->com.state != RES_CQ_HW)
  1156. err = -EINVAL;
  1157. else if (atomic_read(&r->ref_count))
  1158. err = -EBUSY;
  1159. else
  1160. err = 0;
  1161. break;
  1162. case RES_CQ_HW:
  1163. if (r->com.state != RES_CQ_ALLOCATED)
  1164. err = -EINVAL;
  1165. else
  1166. err = 0;
  1167. break;
  1168. default:
  1169. err = -EINVAL;
  1170. }
  1171. if (!err) {
  1172. r->com.from_state = r->com.state;
  1173. r->com.to_state = state;
  1174. r->com.state = RES_CQ_BUSY;
  1175. if (cq)
  1176. *cq = r;
  1177. }
  1178. }
  1179. spin_unlock_irq(mlx4_tlock(dev));
  1180. return err;
  1181. }
  1182. static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  1183. enum res_cq_states state, struct res_srq **srq)
  1184. {
  1185. struct mlx4_priv *priv = mlx4_priv(dev);
  1186. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1187. struct res_srq *r;
  1188. int err = 0;
  1189. spin_lock_irq(mlx4_tlock(dev));
  1190. r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index);
  1191. if (!r)
  1192. err = -ENOENT;
  1193. else if (r->com.owner != slave)
  1194. err = -EPERM;
  1195. else {
  1196. switch (state) {
  1197. case RES_SRQ_BUSY:
  1198. err = -EINVAL;
  1199. break;
  1200. case RES_SRQ_ALLOCATED:
  1201. if (r->com.state != RES_SRQ_HW)
  1202. err = -EINVAL;
  1203. else if (atomic_read(&r->ref_count))
  1204. err = -EBUSY;
  1205. break;
  1206. case RES_SRQ_HW:
  1207. if (r->com.state != RES_SRQ_ALLOCATED)
  1208. err = -EINVAL;
  1209. break;
  1210. default:
  1211. err = -EINVAL;
  1212. }
  1213. if (!err) {
  1214. r->com.from_state = r->com.state;
  1215. r->com.to_state = state;
  1216. r->com.state = RES_SRQ_BUSY;
  1217. if (srq)
  1218. *srq = r;
  1219. }
  1220. }
  1221. spin_unlock_irq(mlx4_tlock(dev));
  1222. return err;
  1223. }
  1224. static void res_abort_move(struct mlx4_dev *dev, int slave,
  1225. enum mlx4_resource type, int id)
  1226. {
  1227. struct mlx4_priv *priv = mlx4_priv(dev);
  1228. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1229. struct res_common *r;
  1230. spin_lock_irq(mlx4_tlock(dev));
  1231. r = res_tracker_lookup(&tracker->res_tree[type], id);
  1232. if (r && (r->owner == slave))
  1233. r->state = r->from_state;
  1234. spin_unlock_irq(mlx4_tlock(dev));
  1235. }
  1236. static void res_end_move(struct mlx4_dev *dev, int slave,
  1237. enum mlx4_resource type, int id)
  1238. {
  1239. struct mlx4_priv *priv = mlx4_priv(dev);
  1240. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1241. struct res_common *r;
  1242. spin_lock_irq(mlx4_tlock(dev));
  1243. r = res_tracker_lookup(&tracker->res_tree[type], id);
  1244. if (r && (r->owner == slave))
  1245. r->state = r->to_state;
  1246. spin_unlock_irq(mlx4_tlock(dev));
  1247. }
  1248. static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
  1249. {
  1250. return mlx4_is_qp_reserved(dev, qpn) &&
  1251. (mlx4_is_master(dev) || mlx4_is_guest_proxy(dev, slave, qpn));
  1252. }
  1253. static int fw_reserved(struct mlx4_dev *dev, int qpn)
  1254. {
  1255. return qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
  1256. }
  1257. static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1258. u64 in_param, u64 *out_param)
  1259. {
  1260. int err;
  1261. int count;
  1262. int align;
  1263. int base;
  1264. int qpn;
  1265. switch (op) {
  1266. case RES_OP_RESERVE:
  1267. count = get_param_l(&in_param);
  1268. align = get_param_h(&in_param);
  1269. err = mlx4_grant_resource(dev, slave, RES_QP, count, 0);
  1270. if (err)
  1271. return err;
  1272. err = __mlx4_qp_reserve_range(dev, count, align, &base);
  1273. if (err) {
  1274. mlx4_release_resource(dev, slave, RES_QP, count, 0);
  1275. return err;
  1276. }
  1277. err = add_res_range(dev, slave, base, count, RES_QP, 0);
  1278. if (err) {
  1279. mlx4_release_resource(dev, slave, RES_QP, count, 0);
  1280. __mlx4_qp_release_range(dev, base, count);
  1281. return err;
  1282. }
  1283. set_param_l(out_param, base);
  1284. break;
  1285. case RES_OP_MAP_ICM:
  1286. qpn = get_param_l(&in_param) & 0x7fffff;
  1287. if (valid_reserved(dev, slave, qpn)) {
  1288. err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
  1289. if (err)
  1290. return err;
  1291. }
  1292. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
  1293. NULL, 1);
  1294. if (err)
  1295. return err;
  1296. if (!fw_reserved(dev, qpn)) {
  1297. err = __mlx4_qp_alloc_icm(dev, qpn);
  1298. if (err) {
  1299. res_abort_move(dev, slave, RES_QP, qpn);
  1300. return err;
  1301. }
  1302. }
  1303. res_end_move(dev, slave, RES_QP, qpn);
  1304. break;
  1305. default:
  1306. err = -EINVAL;
  1307. break;
  1308. }
  1309. return err;
  1310. }
  1311. static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1312. u64 in_param, u64 *out_param)
  1313. {
  1314. int err = -EINVAL;
  1315. int base;
  1316. int order;
  1317. if (op != RES_OP_RESERVE_AND_MAP)
  1318. return err;
  1319. order = get_param_l(&in_param);
  1320. err = mlx4_grant_resource(dev, slave, RES_MTT, 1 << order, 0);
  1321. if (err)
  1322. return err;
  1323. base = __mlx4_alloc_mtt_range(dev, order);
  1324. if (base == -1) {
  1325. mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
  1326. return -ENOMEM;
  1327. }
  1328. err = add_res_range(dev, slave, base, 1, RES_MTT, order);
  1329. if (err) {
  1330. mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
  1331. __mlx4_free_mtt_range(dev, base, order);
  1332. } else {
  1333. set_param_l(out_param, base);
  1334. }
  1335. return err;
  1336. }
  1337. static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1338. u64 in_param, u64 *out_param)
  1339. {
  1340. int err = -EINVAL;
  1341. int index;
  1342. int id;
  1343. struct res_mpt *mpt;
  1344. switch (op) {
  1345. case RES_OP_RESERVE:
  1346. err = mlx4_grant_resource(dev, slave, RES_MPT, 1, 0);
  1347. if (err)
  1348. break;
  1349. index = __mlx4_mpt_reserve(dev);
  1350. if (index == -1) {
  1351. mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
  1352. break;
  1353. }
  1354. id = index & mpt_mask(dev);
  1355. err = add_res_range(dev, slave, id, 1, RES_MPT, index);
  1356. if (err) {
  1357. mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
  1358. __mlx4_mpt_release(dev, index);
  1359. break;
  1360. }
  1361. set_param_l(out_param, index);
  1362. break;
  1363. case RES_OP_MAP_ICM:
  1364. index = get_param_l(&in_param);
  1365. id = index & mpt_mask(dev);
  1366. err = mr_res_start_move_to(dev, slave, id,
  1367. RES_MPT_MAPPED, &mpt);
  1368. if (err)
  1369. return err;
  1370. err = __mlx4_mpt_alloc_icm(dev, mpt->key);
  1371. if (err) {
  1372. res_abort_move(dev, slave, RES_MPT, id);
  1373. return err;
  1374. }
  1375. res_end_move(dev, slave, RES_MPT, id);
  1376. break;
  1377. }
  1378. return err;
  1379. }
  1380. static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1381. u64 in_param, u64 *out_param)
  1382. {
  1383. int cqn;
  1384. int err;
  1385. switch (op) {
  1386. case RES_OP_RESERVE_AND_MAP:
  1387. err = mlx4_grant_resource(dev, slave, RES_CQ, 1, 0);
  1388. if (err)
  1389. break;
  1390. err = __mlx4_cq_alloc_icm(dev, &cqn);
  1391. if (err) {
  1392. mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
  1393. break;
  1394. }
  1395. err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1396. if (err) {
  1397. mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
  1398. __mlx4_cq_free_icm(dev, cqn);
  1399. break;
  1400. }
  1401. set_param_l(out_param, cqn);
  1402. break;
  1403. default:
  1404. err = -EINVAL;
  1405. }
  1406. return err;
  1407. }
  1408. static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1409. u64 in_param, u64 *out_param)
  1410. {
  1411. int srqn;
  1412. int err;
  1413. switch (op) {
  1414. case RES_OP_RESERVE_AND_MAP:
  1415. err = mlx4_grant_resource(dev, slave, RES_SRQ, 1, 0);
  1416. if (err)
  1417. break;
  1418. err = __mlx4_srq_alloc_icm(dev, &srqn);
  1419. if (err) {
  1420. mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
  1421. break;
  1422. }
  1423. err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1424. if (err) {
  1425. mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
  1426. __mlx4_srq_free_icm(dev, srqn);
  1427. break;
  1428. }
  1429. set_param_l(out_param, srqn);
  1430. break;
  1431. default:
  1432. err = -EINVAL;
  1433. }
  1434. return err;
  1435. }
  1436. static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port)
  1437. {
  1438. struct mlx4_priv *priv = mlx4_priv(dev);
  1439. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1440. struct mac_res *res;
  1441. if (mlx4_grant_resource(dev, slave, RES_MAC, 1, port))
  1442. return -EINVAL;
  1443. res = kzalloc(sizeof *res, GFP_KERNEL);
  1444. if (!res) {
  1445. mlx4_release_resource(dev, slave, RES_MAC, 1, port);
  1446. return -ENOMEM;
  1447. }
  1448. res->mac = mac;
  1449. res->port = (u8) port;
  1450. list_add_tail(&res->list,
  1451. &tracker->slave_list[slave].res_list[RES_MAC]);
  1452. return 0;
  1453. }
  1454. static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
  1455. int port)
  1456. {
  1457. struct mlx4_priv *priv = mlx4_priv(dev);
  1458. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1459. struct list_head *mac_list =
  1460. &tracker->slave_list[slave].res_list[RES_MAC];
  1461. struct mac_res *res, *tmp;
  1462. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1463. if (res->mac == mac && res->port == (u8) port) {
  1464. list_del(&res->list);
  1465. mlx4_release_resource(dev, slave, RES_MAC, 1, port);
  1466. kfree(res);
  1467. break;
  1468. }
  1469. }
  1470. }
  1471. static void rem_slave_macs(struct mlx4_dev *dev, int slave)
  1472. {
  1473. struct mlx4_priv *priv = mlx4_priv(dev);
  1474. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1475. struct list_head *mac_list =
  1476. &tracker->slave_list[slave].res_list[RES_MAC];
  1477. struct mac_res *res, *tmp;
  1478. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1479. list_del(&res->list);
  1480. __mlx4_unregister_mac(dev, res->port, res->mac);
  1481. mlx4_release_resource(dev, slave, RES_MAC, 1, res->port);
  1482. kfree(res);
  1483. }
  1484. }
  1485. static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1486. u64 in_param, u64 *out_param, int in_port)
  1487. {
  1488. int err = -EINVAL;
  1489. int port;
  1490. u64 mac;
  1491. if (op != RES_OP_RESERVE_AND_MAP)
  1492. return err;
  1493. port = !in_port ? get_param_l(out_param) : in_port;
  1494. mac = in_param;
  1495. err = __mlx4_register_mac(dev, port, mac);
  1496. if (err >= 0) {
  1497. set_param_l(out_param, err);
  1498. err = 0;
  1499. }
  1500. if (!err) {
  1501. err = mac_add_to_slave(dev, slave, mac, port);
  1502. if (err)
  1503. __mlx4_unregister_mac(dev, port, mac);
  1504. }
  1505. return err;
  1506. }
  1507. static int vlan_add_to_slave(struct mlx4_dev *dev, int slave, u16 vlan,
  1508. int port, int vlan_index)
  1509. {
  1510. struct mlx4_priv *priv = mlx4_priv(dev);
  1511. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1512. struct list_head *vlan_list =
  1513. &tracker->slave_list[slave].res_list[RES_VLAN];
  1514. struct vlan_res *res, *tmp;
  1515. list_for_each_entry_safe(res, tmp, vlan_list, list) {
  1516. if (res->vlan == vlan && res->port == (u8) port) {
  1517. /* vlan found. update ref count */
  1518. ++res->ref_count;
  1519. return 0;
  1520. }
  1521. }
  1522. if (mlx4_grant_resource(dev, slave, RES_VLAN, 1, port))
  1523. return -EINVAL;
  1524. res = kzalloc(sizeof(*res), GFP_KERNEL);
  1525. if (!res) {
  1526. mlx4_release_resource(dev, slave, RES_VLAN, 1, port);
  1527. return -ENOMEM;
  1528. }
  1529. res->vlan = vlan;
  1530. res->port = (u8) port;
  1531. res->vlan_index = vlan_index;
  1532. res->ref_count = 1;
  1533. list_add_tail(&res->list,
  1534. &tracker->slave_list[slave].res_list[RES_VLAN]);
  1535. return 0;
  1536. }
  1537. static void vlan_del_from_slave(struct mlx4_dev *dev, int slave, u16 vlan,
  1538. int port)
  1539. {
  1540. struct mlx4_priv *priv = mlx4_priv(dev);
  1541. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1542. struct list_head *vlan_list =
  1543. &tracker->slave_list[slave].res_list[RES_VLAN];
  1544. struct vlan_res *res, *tmp;
  1545. list_for_each_entry_safe(res, tmp, vlan_list, list) {
  1546. if (res->vlan == vlan && res->port == (u8) port) {
  1547. if (!--res->ref_count) {
  1548. list_del(&res->list);
  1549. mlx4_release_resource(dev, slave, RES_VLAN,
  1550. 1, port);
  1551. kfree(res);
  1552. }
  1553. break;
  1554. }
  1555. }
  1556. }
  1557. static void rem_slave_vlans(struct mlx4_dev *dev, int slave)
  1558. {
  1559. struct mlx4_priv *priv = mlx4_priv(dev);
  1560. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1561. struct list_head *vlan_list =
  1562. &tracker->slave_list[slave].res_list[RES_VLAN];
  1563. struct vlan_res *res, *tmp;
  1564. int i;
  1565. list_for_each_entry_safe(res, tmp, vlan_list, list) {
  1566. list_del(&res->list);
  1567. /* dereference the vlan the num times the slave referenced it */
  1568. for (i = 0; i < res->ref_count; i++)
  1569. __mlx4_unregister_vlan(dev, res->port, res->vlan);
  1570. mlx4_release_resource(dev, slave, RES_VLAN, 1, res->port);
  1571. kfree(res);
  1572. }
  1573. }
  1574. static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1575. u64 in_param, u64 *out_param, int in_port)
  1576. {
  1577. struct mlx4_priv *priv = mlx4_priv(dev);
  1578. struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
  1579. int err;
  1580. u16 vlan;
  1581. int vlan_index;
  1582. int port;
  1583. port = !in_port ? get_param_l(out_param) : in_port;
  1584. if (!port || op != RES_OP_RESERVE_AND_MAP)
  1585. return -EINVAL;
  1586. /* upstream kernels had NOP for reg/unreg vlan. Continue this. */
  1587. if (!in_port && port > 0 && port <= dev->caps.num_ports) {
  1588. slave_state[slave].old_vlan_api = true;
  1589. return 0;
  1590. }
  1591. vlan = (u16) in_param;
  1592. err = __mlx4_register_vlan(dev, port, vlan, &vlan_index);
  1593. if (!err) {
  1594. set_param_l(out_param, (u32) vlan_index);
  1595. err = vlan_add_to_slave(dev, slave, vlan, port, vlan_index);
  1596. if (err)
  1597. __mlx4_unregister_vlan(dev, port, vlan);
  1598. }
  1599. return err;
  1600. }
  1601. static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1602. u64 in_param, u64 *out_param)
  1603. {
  1604. u32 index;
  1605. int err;
  1606. if (op != RES_OP_RESERVE)
  1607. return -EINVAL;
  1608. err = mlx4_grant_resource(dev, slave, RES_COUNTER, 1, 0);
  1609. if (err)
  1610. return err;
  1611. err = __mlx4_counter_alloc(dev, &index);
  1612. if (err) {
  1613. mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
  1614. return err;
  1615. }
  1616. err = add_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  1617. if (err) {
  1618. __mlx4_counter_free(dev, index);
  1619. mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
  1620. } else {
  1621. set_param_l(out_param, index);
  1622. }
  1623. return err;
  1624. }
  1625. static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1626. u64 in_param, u64 *out_param)
  1627. {
  1628. u32 xrcdn;
  1629. int err;
  1630. if (op != RES_OP_RESERVE)
  1631. return -EINVAL;
  1632. err = __mlx4_xrcd_alloc(dev, &xrcdn);
  1633. if (err)
  1634. return err;
  1635. err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1636. if (err)
  1637. __mlx4_xrcd_free(dev, xrcdn);
  1638. else
  1639. set_param_l(out_param, xrcdn);
  1640. return err;
  1641. }
  1642. int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
  1643. struct mlx4_vhcr *vhcr,
  1644. struct mlx4_cmd_mailbox *inbox,
  1645. struct mlx4_cmd_mailbox *outbox,
  1646. struct mlx4_cmd_info *cmd)
  1647. {
  1648. int err;
  1649. int alop = vhcr->op_modifier;
  1650. switch (vhcr->in_modifier & 0xFF) {
  1651. case RES_QP:
  1652. err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1653. vhcr->in_param, &vhcr->out_param);
  1654. break;
  1655. case RES_MTT:
  1656. err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1657. vhcr->in_param, &vhcr->out_param);
  1658. break;
  1659. case RES_MPT:
  1660. err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1661. vhcr->in_param, &vhcr->out_param);
  1662. break;
  1663. case RES_CQ:
  1664. err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1665. vhcr->in_param, &vhcr->out_param);
  1666. break;
  1667. case RES_SRQ:
  1668. err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1669. vhcr->in_param, &vhcr->out_param);
  1670. break;
  1671. case RES_MAC:
  1672. err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1673. vhcr->in_param, &vhcr->out_param,
  1674. (vhcr->in_modifier >> 8) & 0xFF);
  1675. break;
  1676. case RES_VLAN:
  1677. err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1678. vhcr->in_param, &vhcr->out_param,
  1679. (vhcr->in_modifier >> 8) & 0xFF);
  1680. break;
  1681. case RES_COUNTER:
  1682. err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1683. vhcr->in_param, &vhcr->out_param);
  1684. break;
  1685. case RES_XRCD:
  1686. err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1687. vhcr->in_param, &vhcr->out_param);
  1688. break;
  1689. default:
  1690. err = -EINVAL;
  1691. break;
  1692. }
  1693. return err;
  1694. }
  1695. static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1696. u64 in_param)
  1697. {
  1698. int err;
  1699. int count;
  1700. int base;
  1701. int qpn;
  1702. switch (op) {
  1703. case RES_OP_RESERVE:
  1704. base = get_param_l(&in_param) & 0x7fffff;
  1705. count = get_param_h(&in_param);
  1706. err = rem_res_range(dev, slave, base, count, RES_QP, 0);
  1707. if (err)
  1708. break;
  1709. mlx4_release_resource(dev, slave, RES_QP, count, 0);
  1710. __mlx4_qp_release_range(dev, base, count);
  1711. break;
  1712. case RES_OP_MAP_ICM:
  1713. qpn = get_param_l(&in_param) & 0x7fffff;
  1714. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
  1715. NULL, 0);
  1716. if (err)
  1717. return err;
  1718. if (!fw_reserved(dev, qpn))
  1719. __mlx4_qp_free_icm(dev, qpn);
  1720. res_end_move(dev, slave, RES_QP, qpn);
  1721. if (valid_reserved(dev, slave, qpn))
  1722. err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
  1723. break;
  1724. default:
  1725. err = -EINVAL;
  1726. break;
  1727. }
  1728. return err;
  1729. }
  1730. static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1731. u64 in_param, u64 *out_param)
  1732. {
  1733. int err = -EINVAL;
  1734. int base;
  1735. int order;
  1736. if (op != RES_OP_RESERVE_AND_MAP)
  1737. return err;
  1738. base = get_param_l(&in_param);
  1739. order = get_param_h(&in_param);
  1740. err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
  1741. if (!err) {
  1742. mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
  1743. __mlx4_free_mtt_range(dev, base, order);
  1744. }
  1745. return err;
  1746. }
  1747. static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1748. u64 in_param)
  1749. {
  1750. int err = -EINVAL;
  1751. int index;
  1752. int id;
  1753. struct res_mpt *mpt;
  1754. switch (op) {
  1755. case RES_OP_RESERVE:
  1756. index = get_param_l(&in_param);
  1757. id = index & mpt_mask(dev);
  1758. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1759. if (err)
  1760. break;
  1761. index = mpt->key;
  1762. put_res(dev, slave, id, RES_MPT);
  1763. err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
  1764. if (err)
  1765. break;
  1766. mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
  1767. __mlx4_mpt_release(dev, index);
  1768. break;
  1769. case RES_OP_MAP_ICM:
  1770. index = get_param_l(&in_param);
  1771. id = index & mpt_mask(dev);
  1772. err = mr_res_start_move_to(dev, slave, id,
  1773. RES_MPT_RESERVED, &mpt);
  1774. if (err)
  1775. return err;
  1776. __mlx4_mpt_free_icm(dev, mpt->key);
  1777. res_end_move(dev, slave, RES_MPT, id);
  1778. return err;
  1779. break;
  1780. default:
  1781. err = -EINVAL;
  1782. break;
  1783. }
  1784. return err;
  1785. }
  1786. static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1787. u64 in_param, u64 *out_param)
  1788. {
  1789. int cqn;
  1790. int err;
  1791. switch (op) {
  1792. case RES_OP_RESERVE_AND_MAP:
  1793. cqn = get_param_l(&in_param);
  1794. err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1795. if (err)
  1796. break;
  1797. mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
  1798. __mlx4_cq_free_icm(dev, cqn);
  1799. break;
  1800. default:
  1801. err = -EINVAL;
  1802. break;
  1803. }
  1804. return err;
  1805. }
  1806. static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1807. u64 in_param, u64 *out_param)
  1808. {
  1809. int srqn;
  1810. int err;
  1811. switch (op) {
  1812. case RES_OP_RESERVE_AND_MAP:
  1813. srqn = get_param_l(&in_param);
  1814. err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1815. if (err)
  1816. break;
  1817. mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
  1818. __mlx4_srq_free_icm(dev, srqn);
  1819. break;
  1820. default:
  1821. err = -EINVAL;
  1822. break;
  1823. }
  1824. return err;
  1825. }
  1826. static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1827. u64 in_param, u64 *out_param, int in_port)
  1828. {
  1829. int port;
  1830. int err = 0;
  1831. switch (op) {
  1832. case RES_OP_RESERVE_AND_MAP:
  1833. port = !in_port ? get_param_l(out_param) : in_port;
  1834. mac_del_from_slave(dev, slave, in_param, port);
  1835. __mlx4_unregister_mac(dev, port, in_param);
  1836. break;
  1837. default:
  1838. err = -EINVAL;
  1839. break;
  1840. }
  1841. return err;
  1842. }
  1843. static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1844. u64 in_param, u64 *out_param, int port)
  1845. {
  1846. struct mlx4_priv *priv = mlx4_priv(dev);
  1847. struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
  1848. int err = 0;
  1849. switch (op) {
  1850. case RES_OP_RESERVE_AND_MAP:
  1851. if (slave_state[slave].old_vlan_api)
  1852. return 0;
  1853. if (!port)
  1854. return -EINVAL;
  1855. vlan_del_from_slave(dev, slave, in_param, port);
  1856. __mlx4_unregister_vlan(dev, port, in_param);
  1857. break;
  1858. default:
  1859. err = -EINVAL;
  1860. break;
  1861. }
  1862. return err;
  1863. }
  1864. static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1865. u64 in_param, u64 *out_param)
  1866. {
  1867. int index;
  1868. int err;
  1869. if (op != RES_OP_RESERVE)
  1870. return -EINVAL;
  1871. index = get_param_l(&in_param);
  1872. err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  1873. if (err)
  1874. return err;
  1875. __mlx4_counter_free(dev, index);
  1876. mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
  1877. return err;
  1878. }
  1879. static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1880. u64 in_param, u64 *out_param)
  1881. {
  1882. int xrcdn;
  1883. int err;
  1884. if (op != RES_OP_RESERVE)
  1885. return -EINVAL;
  1886. xrcdn = get_param_l(&in_param);
  1887. err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1888. if (err)
  1889. return err;
  1890. __mlx4_xrcd_free(dev, xrcdn);
  1891. return err;
  1892. }
  1893. int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
  1894. struct mlx4_vhcr *vhcr,
  1895. struct mlx4_cmd_mailbox *inbox,
  1896. struct mlx4_cmd_mailbox *outbox,
  1897. struct mlx4_cmd_info *cmd)
  1898. {
  1899. int err = -EINVAL;
  1900. int alop = vhcr->op_modifier;
  1901. switch (vhcr->in_modifier & 0xFF) {
  1902. case RES_QP:
  1903. err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
  1904. vhcr->in_param);
  1905. break;
  1906. case RES_MTT:
  1907. err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
  1908. vhcr->in_param, &vhcr->out_param);
  1909. break;
  1910. case RES_MPT:
  1911. err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
  1912. vhcr->in_param);
  1913. break;
  1914. case RES_CQ:
  1915. err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
  1916. vhcr->in_param, &vhcr->out_param);
  1917. break;
  1918. case RES_SRQ:
  1919. err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
  1920. vhcr->in_param, &vhcr->out_param);
  1921. break;
  1922. case RES_MAC:
  1923. err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
  1924. vhcr->in_param, &vhcr->out_param,
  1925. (vhcr->in_modifier >> 8) & 0xFF);
  1926. break;
  1927. case RES_VLAN:
  1928. err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
  1929. vhcr->in_param, &vhcr->out_param,
  1930. (vhcr->in_modifier >> 8) & 0xFF);
  1931. break;
  1932. case RES_COUNTER:
  1933. err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
  1934. vhcr->in_param, &vhcr->out_param);
  1935. break;
  1936. case RES_XRCD:
  1937. err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
  1938. vhcr->in_param, &vhcr->out_param);
  1939. default:
  1940. break;
  1941. }
  1942. return err;
  1943. }
  1944. /* ugly but other choices are uglier */
  1945. static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
  1946. {
  1947. return (be32_to_cpu(mpt->flags) >> 9) & 1;
  1948. }
  1949. static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
  1950. {
  1951. return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
  1952. }
  1953. static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
  1954. {
  1955. return be32_to_cpu(mpt->mtt_sz);
  1956. }
  1957. static u32 mr_get_pd(struct mlx4_mpt_entry *mpt)
  1958. {
  1959. return be32_to_cpu(mpt->pd_flags) & 0x00ffffff;
  1960. }
  1961. static int mr_is_fmr(struct mlx4_mpt_entry *mpt)
  1962. {
  1963. return be32_to_cpu(mpt->pd_flags) & MLX4_MPT_PD_FLAG_FAST_REG;
  1964. }
  1965. static int mr_is_bind_enabled(struct mlx4_mpt_entry *mpt)
  1966. {
  1967. return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_BIND_ENABLE;
  1968. }
  1969. static int mr_is_region(struct mlx4_mpt_entry *mpt)
  1970. {
  1971. return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_REGION;
  1972. }
  1973. static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
  1974. {
  1975. return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
  1976. }
  1977. static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
  1978. {
  1979. return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
  1980. }
  1981. static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
  1982. {
  1983. int page_shift = (qpc->log_page_size & 0x3f) + 12;
  1984. int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
  1985. int log_sq_sride = qpc->sq_size_stride & 7;
  1986. int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
  1987. int log_rq_stride = qpc->rq_size_stride & 7;
  1988. int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
  1989. int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
  1990. u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
  1991. int xrc = (ts == MLX4_QP_ST_XRC) ? 1 : 0;
  1992. int sq_size;
  1993. int rq_size;
  1994. int total_pages;
  1995. int total_mem;
  1996. int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
  1997. sq_size = 1 << (log_sq_size + log_sq_sride + 4);
  1998. rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
  1999. total_mem = sq_size + rq_size;
  2000. total_pages =
  2001. roundup_pow_of_two((total_mem + (page_offset << 6)) >>
  2002. page_shift);
  2003. return total_pages;
  2004. }
  2005. static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
  2006. int size, struct res_mtt *mtt)
  2007. {
  2008. int res_start = mtt->com.res_id;
  2009. int res_size = (1 << mtt->order);
  2010. if (start < res_start || start + size > res_start + res_size)
  2011. return -EPERM;
  2012. return 0;
  2013. }
  2014. int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  2015. struct mlx4_vhcr *vhcr,
  2016. struct mlx4_cmd_mailbox *inbox,
  2017. struct mlx4_cmd_mailbox *outbox,
  2018. struct mlx4_cmd_info *cmd)
  2019. {
  2020. int err;
  2021. int index = vhcr->in_modifier;
  2022. struct res_mtt *mtt;
  2023. struct res_mpt *mpt;
  2024. int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
  2025. int phys;
  2026. int id;
  2027. u32 pd;
  2028. int pd_slave;
  2029. id = index & mpt_mask(dev);
  2030. err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
  2031. if (err)
  2032. return err;
  2033. /* Disable memory windows for VFs. */
  2034. if (!mr_is_region(inbox->buf)) {
  2035. err = -EPERM;
  2036. goto ex_abort;
  2037. }
  2038. /* Make sure that the PD bits related to the slave id are zeros. */
  2039. pd = mr_get_pd(inbox->buf);
  2040. pd_slave = (pd >> 17) & 0x7f;
  2041. if (pd_slave != 0 && pd_slave != slave) {
  2042. err = -EPERM;
  2043. goto ex_abort;
  2044. }
  2045. if (mr_is_fmr(inbox->buf)) {
  2046. /* FMR and Bind Enable are forbidden in slave devices. */
  2047. if (mr_is_bind_enabled(inbox->buf)) {
  2048. err = -EPERM;
  2049. goto ex_abort;
  2050. }
  2051. /* FMR and Memory Windows are also forbidden. */
  2052. if (!mr_is_region(inbox->buf)) {
  2053. err = -EPERM;
  2054. goto ex_abort;
  2055. }
  2056. }
  2057. phys = mr_phys_mpt(inbox->buf);
  2058. if (!phys) {
  2059. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2060. if (err)
  2061. goto ex_abort;
  2062. err = check_mtt_range(dev, slave, mtt_base,
  2063. mr_get_mtt_size(inbox->buf), mtt);
  2064. if (err)
  2065. goto ex_put;
  2066. mpt->mtt = mtt;
  2067. }
  2068. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2069. if (err)
  2070. goto ex_put;
  2071. if (!phys) {
  2072. atomic_inc(&mtt->ref_count);
  2073. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2074. }
  2075. res_end_move(dev, slave, RES_MPT, id);
  2076. return 0;
  2077. ex_put:
  2078. if (!phys)
  2079. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2080. ex_abort:
  2081. res_abort_move(dev, slave, RES_MPT, id);
  2082. return err;
  2083. }
  2084. int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  2085. struct mlx4_vhcr *vhcr,
  2086. struct mlx4_cmd_mailbox *inbox,
  2087. struct mlx4_cmd_mailbox *outbox,
  2088. struct mlx4_cmd_info *cmd)
  2089. {
  2090. int err;
  2091. int index = vhcr->in_modifier;
  2092. struct res_mpt *mpt;
  2093. int id;
  2094. id = index & mpt_mask(dev);
  2095. err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
  2096. if (err)
  2097. return err;
  2098. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2099. if (err)
  2100. goto ex_abort;
  2101. if (mpt->mtt)
  2102. atomic_dec(&mpt->mtt->ref_count);
  2103. res_end_move(dev, slave, RES_MPT, id);
  2104. return 0;
  2105. ex_abort:
  2106. res_abort_move(dev, slave, RES_MPT, id);
  2107. return err;
  2108. }
  2109. int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
  2110. struct mlx4_vhcr *vhcr,
  2111. struct mlx4_cmd_mailbox *inbox,
  2112. struct mlx4_cmd_mailbox *outbox,
  2113. struct mlx4_cmd_info *cmd)
  2114. {
  2115. int err;
  2116. int index = vhcr->in_modifier;
  2117. struct res_mpt *mpt;
  2118. int id;
  2119. id = index & mpt_mask(dev);
  2120. err = get_res(dev, slave, id, RES_MPT, &mpt);
  2121. if (err)
  2122. return err;
  2123. if (mpt->com.from_state != RES_MPT_HW) {
  2124. err = -EBUSY;
  2125. goto out;
  2126. }
  2127. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2128. out:
  2129. put_res(dev, slave, id, RES_MPT);
  2130. return err;
  2131. }
  2132. static int qp_get_rcqn(struct mlx4_qp_context *qpc)
  2133. {
  2134. return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
  2135. }
  2136. static int qp_get_scqn(struct mlx4_qp_context *qpc)
  2137. {
  2138. return be32_to_cpu(qpc->cqn_send) & 0xffffff;
  2139. }
  2140. static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
  2141. {
  2142. return be32_to_cpu(qpc->srqn) & 0x1ffffff;
  2143. }
  2144. static void adjust_proxy_tun_qkey(struct mlx4_dev *dev, struct mlx4_vhcr *vhcr,
  2145. struct mlx4_qp_context *context)
  2146. {
  2147. u32 qpn = vhcr->in_modifier & 0xffffff;
  2148. u32 qkey = 0;
  2149. if (mlx4_get_parav_qkey(dev, qpn, &qkey))
  2150. return;
  2151. /* adjust qkey in qp context */
  2152. context->qkey = cpu_to_be32(qkey);
  2153. }
  2154. int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  2155. struct mlx4_vhcr *vhcr,
  2156. struct mlx4_cmd_mailbox *inbox,
  2157. struct mlx4_cmd_mailbox *outbox,
  2158. struct mlx4_cmd_info *cmd)
  2159. {
  2160. int err;
  2161. int qpn = vhcr->in_modifier & 0x7fffff;
  2162. struct res_mtt *mtt;
  2163. struct res_qp *qp;
  2164. struct mlx4_qp_context *qpc = inbox->buf + 8;
  2165. int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
  2166. int mtt_size = qp_get_mtt_size(qpc);
  2167. struct res_cq *rcq;
  2168. struct res_cq *scq;
  2169. int rcqn = qp_get_rcqn(qpc);
  2170. int scqn = qp_get_scqn(qpc);
  2171. u32 srqn = qp_get_srqn(qpc) & 0xffffff;
  2172. int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
  2173. struct res_srq *srq;
  2174. int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
  2175. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
  2176. if (err)
  2177. return err;
  2178. qp->local_qpn = local_qpn;
  2179. qp->sched_queue = 0;
  2180. qp->param3 = 0;
  2181. qp->vlan_control = 0;
  2182. qp->fvl_rx = 0;
  2183. qp->pri_path_fl = 0;
  2184. qp->vlan_index = 0;
  2185. qp->feup = 0;
  2186. qp->qpc_flags = be32_to_cpu(qpc->flags);
  2187. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2188. if (err)
  2189. goto ex_abort;
  2190. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  2191. if (err)
  2192. goto ex_put_mtt;
  2193. err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
  2194. if (err)
  2195. goto ex_put_mtt;
  2196. if (scqn != rcqn) {
  2197. err = get_res(dev, slave, scqn, RES_CQ, &scq);
  2198. if (err)
  2199. goto ex_put_rcq;
  2200. } else
  2201. scq = rcq;
  2202. if (use_srq) {
  2203. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2204. if (err)
  2205. goto ex_put_scq;
  2206. }
  2207. adjust_proxy_tun_qkey(dev, vhcr, qpc);
  2208. update_pkey_index(dev, slave, inbox);
  2209. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2210. if (err)
  2211. goto ex_put_srq;
  2212. atomic_inc(&mtt->ref_count);
  2213. qp->mtt = mtt;
  2214. atomic_inc(&rcq->ref_count);
  2215. qp->rcq = rcq;
  2216. atomic_inc(&scq->ref_count);
  2217. qp->scq = scq;
  2218. if (scqn != rcqn)
  2219. put_res(dev, slave, scqn, RES_CQ);
  2220. if (use_srq) {
  2221. atomic_inc(&srq->ref_count);
  2222. put_res(dev, slave, srqn, RES_SRQ);
  2223. qp->srq = srq;
  2224. }
  2225. put_res(dev, slave, rcqn, RES_CQ);
  2226. put_res(dev, slave, mtt_base, RES_MTT);
  2227. res_end_move(dev, slave, RES_QP, qpn);
  2228. return 0;
  2229. ex_put_srq:
  2230. if (use_srq)
  2231. put_res(dev, slave, srqn, RES_SRQ);
  2232. ex_put_scq:
  2233. if (scqn != rcqn)
  2234. put_res(dev, slave, scqn, RES_CQ);
  2235. ex_put_rcq:
  2236. put_res(dev, slave, rcqn, RES_CQ);
  2237. ex_put_mtt:
  2238. put_res(dev, slave, mtt_base, RES_MTT);
  2239. ex_abort:
  2240. res_abort_move(dev, slave, RES_QP, qpn);
  2241. return err;
  2242. }
  2243. static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
  2244. {
  2245. return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
  2246. }
  2247. static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
  2248. {
  2249. int log_eq_size = eqc->log_eq_size & 0x1f;
  2250. int page_shift = (eqc->log_page_size & 0x3f) + 12;
  2251. if (log_eq_size + 5 < page_shift)
  2252. return 1;
  2253. return 1 << (log_eq_size + 5 - page_shift);
  2254. }
  2255. static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
  2256. {
  2257. return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
  2258. }
  2259. static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
  2260. {
  2261. int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
  2262. int page_shift = (cqc->log_page_size & 0x3f) + 12;
  2263. if (log_cq_size + 5 < page_shift)
  2264. return 1;
  2265. return 1 << (log_cq_size + 5 - page_shift);
  2266. }
  2267. int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  2268. struct mlx4_vhcr *vhcr,
  2269. struct mlx4_cmd_mailbox *inbox,
  2270. struct mlx4_cmd_mailbox *outbox,
  2271. struct mlx4_cmd_info *cmd)
  2272. {
  2273. int err;
  2274. int eqn = vhcr->in_modifier;
  2275. int res_id = (slave << 8) | eqn;
  2276. struct mlx4_eq_context *eqc = inbox->buf;
  2277. int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
  2278. int mtt_size = eq_get_mtt_size(eqc);
  2279. struct res_eq *eq;
  2280. struct res_mtt *mtt;
  2281. err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  2282. if (err)
  2283. return err;
  2284. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
  2285. if (err)
  2286. goto out_add;
  2287. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2288. if (err)
  2289. goto out_move;
  2290. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  2291. if (err)
  2292. goto out_put;
  2293. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2294. if (err)
  2295. goto out_put;
  2296. atomic_inc(&mtt->ref_count);
  2297. eq->mtt = mtt;
  2298. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2299. res_end_move(dev, slave, RES_EQ, res_id);
  2300. return 0;
  2301. out_put:
  2302. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2303. out_move:
  2304. res_abort_move(dev, slave, RES_EQ, res_id);
  2305. out_add:
  2306. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  2307. return err;
  2308. }
  2309. static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
  2310. int len, struct res_mtt **res)
  2311. {
  2312. struct mlx4_priv *priv = mlx4_priv(dev);
  2313. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2314. struct res_mtt *mtt;
  2315. int err = -EINVAL;
  2316. spin_lock_irq(mlx4_tlock(dev));
  2317. list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
  2318. com.list) {
  2319. if (!check_mtt_range(dev, slave, start, len, mtt)) {
  2320. *res = mtt;
  2321. mtt->com.from_state = mtt->com.state;
  2322. mtt->com.state = RES_MTT_BUSY;
  2323. err = 0;
  2324. break;
  2325. }
  2326. }
  2327. spin_unlock_irq(mlx4_tlock(dev));
  2328. return err;
  2329. }
  2330. static int verify_qp_parameters(struct mlx4_dev *dev,
  2331. struct mlx4_cmd_mailbox *inbox,
  2332. enum qp_transition transition, u8 slave)
  2333. {
  2334. u32 qp_type;
  2335. struct mlx4_qp_context *qp_ctx;
  2336. enum mlx4_qp_optpar optpar;
  2337. qp_ctx = inbox->buf + 8;
  2338. qp_type = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  2339. optpar = be32_to_cpu(*(__be32 *) inbox->buf);
  2340. switch (qp_type) {
  2341. case MLX4_QP_ST_RC:
  2342. case MLX4_QP_ST_UC:
  2343. switch (transition) {
  2344. case QP_TRANS_INIT2RTR:
  2345. case QP_TRANS_RTR2RTS:
  2346. case QP_TRANS_RTS2RTS:
  2347. case QP_TRANS_SQD2SQD:
  2348. case QP_TRANS_SQD2RTS:
  2349. if (slave != mlx4_master_func_num(dev))
  2350. /* slaves have only gid index 0 */
  2351. if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH)
  2352. if (qp_ctx->pri_path.mgid_index)
  2353. return -EINVAL;
  2354. if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH)
  2355. if (qp_ctx->alt_path.mgid_index)
  2356. return -EINVAL;
  2357. break;
  2358. default:
  2359. break;
  2360. }
  2361. break;
  2362. default:
  2363. break;
  2364. }
  2365. return 0;
  2366. }
  2367. int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
  2368. struct mlx4_vhcr *vhcr,
  2369. struct mlx4_cmd_mailbox *inbox,
  2370. struct mlx4_cmd_mailbox *outbox,
  2371. struct mlx4_cmd_info *cmd)
  2372. {
  2373. struct mlx4_mtt mtt;
  2374. __be64 *page_list = inbox->buf;
  2375. u64 *pg_list = (u64 *)page_list;
  2376. int i;
  2377. struct res_mtt *rmtt = NULL;
  2378. int start = be64_to_cpu(page_list[0]);
  2379. int npages = vhcr->in_modifier;
  2380. int err;
  2381. err = get_containing_mtt(dev, slave, start, npages, &rmtt);
  2382. if (err)
  2383. return err;
  2384. /* Call the SW implementation of write_mtt:
  2385. * - Prepare a dummy mtt struct
  2386. * - Translate inbox contents to simple addresses in host endianess */
  2387. mtt.offset = 0; /* TBD this is broken but I don't handle it since
  2388. we don't really use it */
  2389. mtt.order = 0;
  2390. mtt.page_shift = 0;
  2391. for (i = 0; i < npages; ++i)
  2392. pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
  2393. err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
  2394. ((u64 *)page_list + 2));
  2395. if (rmtt)
  2396. put_res(dev, slave, rmtt->com.res_id, RES_MTT);
  2397. return err;
  2398. }
  2399. int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  2400. struct mlx4_vhcr *vhcr,
  2401. struct mlx4_cmd_mailbox *inbox,
  2402. struct mlx4_cmd_mailbox *outbox,
  2403. struct mlx4_cmd_info *cmd)
  2404. {
  2405. int eqn = vhcr->in_modifier;
  2406. int res_id = eqn | (slave << 8);
  2407. struct res_eq *eq;
  2408. int err;
  2409. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
  2410. if (err)
  2411. return err;
  2412. err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
  2413. if (err)
  2414. goto ex_abort;
  2415. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2416. if (err)
  2417. goto ex_put;
  2418. atomic_dec(&eq->mtt->ref_count);
  2419. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  2420. res_end_move(dev, slave, RES_EQ, res_id);
  2421. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  2422. return 0;
  2423. ex_put:
  2424. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  2425. ex_abort:
  2426. res_abort_move(dev, slave, RES_EQ, res_id);
  2427. return err;
  2428. }
  2429. int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
  2430. {
  2431. struct mlx4_priv *priv = mlx4_priv(dev);
  2432. struct mlx4_slave_event_eq_info *event_eq;
  2433. struct mlx4_cmd_mailbox *mailbox;
  2434. u32 in_modifier = 0;
  2435. int err;
  2436. int res_id;
  2437. struct res_eq *req;
  2438. if (!priv->mfunc.master.slave_state)
  2439. return -EINVAL;
  2440. event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
  2441. /* Create the event only if the slave is registered */
  2442. if (event_eq->eqn < 0)
  2443. return 0;
  2444. mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  2445. res_id = (slave << 8) | event_eq->eqn;
  2446. err = get_res(dev, slave, res_id, RES_EQ, &req);
  2447. if (err)
  2448. goto unlock;
  2449. if (req->com.from_state != RES_EQ_HW) {
  2450. err = -EINVAL;
  2451. goto put;
  2452. }
  2453. mailbox = mlx4_alloc_cmd_mailbox(dev);
  2454. if (IS_ERR(mailbox)) {
  2455. err = PTR_ERR(mailbox);
  2456. goto put;
  2457. }
  2458. if (eqe->type == MLX4_EVENT_TYPE_CMD) {
  2459. ++event_eq->token;
  2460. eqe->event.cmd.token = cpu_to_be16(event_eq->token);
  2461. }
  2462. memcpy(mailbox->buf, (u8 *) eqe, 28);
  2463. in_modifier = (slave & 0xff) | ((event_eq->eqn & 0xff) << 16);
  2464. err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
  2465. MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
  2466. MLX4_CMD_NATIVE);
  2467. put_res(dev, slave, res_id, RES_EQ);
  2468. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  2469. mlx4_free_cmd_mailbox(dev, mailbox);
  2470. return err;
  2471. put:
  2472. put_res(dev, slave, res_id, RES_EQ);
  2473. unlock:
  2474. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  2475. return err;
  2476. }
  2477. int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
  2478. struct mlx4_vhcr *vhcr,
  2479. struct mlx4_cmd_mailbox *inbox,
  2480. struct mlx4_cmd_mailbox *outbox,
  2481. struct mlx4_cmd_info *cmd)
  2482. {
  2483. int eqn = vhcr->in_modifier;
  2484. int res_id = eqn | (slave << 8);
  2485. struct res_eq *eq;
  2486. int err;
  2487. err = get_res(dev, slave, res_id, RES_EQ, &eq);
  2488. if (err)
  2489. return err;
  2490. if (eq->com.from_state != RES_EQ_HW) {
  2491. err = -EINVAL;
  2492. goto ex_put;
  2493. }
  2494. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2495. ex_put:
  2496. put_res(dev, slave, res_id, RES_EQ);
  2497. return err;
  2498. }
  2499. int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2500. struct mlx4_vhcr *vhcr,
  2501. struct mlx4_cmd_mailbox *inbox,
  2502. struct mlx4_cmd_mailbox *outbox,
  2503. struct mlx4_cmd_info *cmd)
  2504. {
  2505. int err;
  2506. int cqn = vhcr->in_modifier;
  2507. struct mlx4_cq_context *cqc = inbox->buf;
  2508. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  2509. struct res_cq *cq;
  2510. struct res_mtt *mtt;
  2511. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
  2512. if (err)
  2513. return err;
  2514. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2515. if (err)
  2516. goto out_move;
  2517. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  2518. if (err)
  2519. goto out_put;
  2520. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2521. if (err)
  2522. goto out_put;
  2523. atomic_inc(&mtt->ref_count);
  2524. cq->mtt = mtt;
  2525. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2526. res_end_move(dev, slave, RES_CQ, cqn);
  2527. return 0;
  2528. out_put:
  2529. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2530. out_move:
  2531. res_abort_move(dev, slave, RES_CQ, cqn);
  2532. return err;
  2533. }
  2534. int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2535. struct mlx4_vhcr *vhcr,
  2536. struct mlx4_cmd_mailbox *inbox,
  2537. struct mlx4_cmd_mailbox *outbox,
  2538. struct mlx4_cmd_info *cmd)
  2539. {
  2540. int err;
  2541. int cqn = vhcr->in_modifier;
  2542. struct res_cq *cq;
  2543. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
  2544. if (err)
  2545. return err;
  2546. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2547. if (err)
  2548. goto out_move;
  2549. atomic_dec(&cq->mtt->ref_count);
  2550. res_end_move(dev, slave, RES_CQ, cqn);
  2551. return 0;
  2552. out_move:
  2553. res_abort_move(dev, slave, RES_CQ, cqn);
  2554. return err;
  2555. }
  2556. int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2557. struct mlx4_vhcr *vhcr,
  2558. struct mlx4_cmd_mailbox *inbox,
  2559. struct mlx4_cmd_mailbox *outbox,
  2560. struct mlx4_cmd_info *cmd)
  2561. {
  2562. int cqn = vhcr->in_modifier;
  2563. struct res_cq *cq;
  2564. int err;
  2565. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  2566. if (err)
  2567. return err;
  2568. if (cq->com.from_state != RES_CQ_HW)
  2569. goto ex_put;
  2570. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2571. ex_put:
  2572. put_res(dev, slave, cqn, RES_CQ);
  2573. return err;
  2574. }
  2575. static int handle_resize(struct mlx4_dev *dev, int slave,
  2576. struct mlx4_vhcr *vhcr,
  2577. struct mlx4_cmd_mailbox *inbox,
  2578. struct mlx4_cmd_mailbox *outbox,
  2579. struct mlx4_cmd_info *cmd,
  2580. struct res_cq *cq)
  2581. {
  2582. int err;
  2583. struct res_mtt *orig_mtt;
  2584. struct res_mtt *mtt;
  2585. struct mlx4_cq_context *cqc = inbox->buf;
  2586. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  2587. err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
  2588. if (err)
  2589. return err;
  2590. if (orig_mtt != cq->mtt) {
  2591. err = -EINVAL;
  2592. goto ex_put;
  2593. }
  2594. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2595. if (err)
  2596. goto ex_put;
  2597. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  2598. if (err)
  2599. goto ex_put1;
  2600. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2601. if (err)
  2602. goto ex_put1;
  2603. atomic_dec(&orig_mtt->ref_count);
  2604. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  2605. atomic_inc(&mtt->ref_count);
  2606. cq->mtt = mtt;
  2607. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2608. return 0;
  2609. ex_put1:
  2610. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2611. ex_put:
  2612. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  2613. return err;
  2614. }
  2615. int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2616. struct mlx4_vhcr *vhcr,
  2617. struct mlx4_cmd_mailbox *inbox,
  2618. struct mlx4_cmd_mailbox *outbox,
  2619. struct mlx4_cmd_info *cmd)
  2620. {
  2621. int cqn = vhcr->in_modifier;
  2622. struct res_cq *cq;
  2623. int err;
  2624. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  2625. if (err)
  2626. return err;
  2627. if (cq->com.from_state != RES_CQ_HW)
  2628. goto ex_put;
  2629. if (vhcr->op_modifier == 0) {
  2630. err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
  2631. goto ex_put;
  2632. }
  2633. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2634. ex_put:
  2635. put_res(dev, slave, cqn, RES_CQ);
  2636. return err;
  2637. }
  2638. static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
  2639. {
  2640. int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
  2641. int log_rq_stride = srqc->logstride & 7;
  2642. int page_shift = (srqc->log_page_size & 0x3f) + 12;
  2643. if (log_srq_size + log_rq_stride + 4 < page_shift)
  2644. return 1;
  2645. return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
  2646. }
  2647. int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2648. struct mlx4_vhcr *vhcr,
  2649. struct mlx4_cmd_mailbox *inbox,
  2650. struct mlx4_cmd_mailbox *outbox,
  2651. struct mlx4_cmd_info *cmd)
  2652. {
  2653. int err;
  2654. int srqn = vhcr->in_modifier;
  2655. struct res_mtt *mtt;
  2656. struct res_srq *srq;
  2657. struct mlx4_srq_context *srqc = inbox->buf;
  2658. int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
  2659. if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
  2660. return -EINVAL;
  2661. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
  2662. if (err)
  2663. return err;
  2664. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2665. if (err)
  2666. goto ex_abort;
  2667. err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
  2668. mtt);
  2669. if (err)
  2670. goto ex_put_mtt;
  2671. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2672. if (err)
  2673. goto ex_put_mtt;
  2674. atomic_inc(&mtt->ref_count);
  2675. srq->mtt = mtt;
  2676. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2677. res_end_move(dev, slave, RES_SRQ, srqn);
  2678. return 0;
  2679. ex_put_mtt:
  2680. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2681. ex_abort:
  2682. res_abort_move(dev, slave, RES_SRQ, srqn);
  2683. return err;
  2684. }
  2685. int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2686. struct mlx4_vhcr *vhcr,
  2687. struct mlx4_cmd_mailbox *inbox,
  2688. struct mlx4_cmd_mailbox *outbox,
  2689. struct mlx4_cmd_info *cmd)
  2690. {
  2691. int err;
  2692. int srqn = vhcr->in_modifier;
  2693. struct res_srq *srq;
  2694. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
  2695. if (err)
  2696. return err;
  2697. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2698. if (err)
  2699. goto ex_abort;
  2700. atomic_dec(&srq->mtt->ref_count);
  2701. if (srq->cq)
  2702. atomic_dec(&srq->cq->ref_count);
  2703. res_end_move(dev, slave, RES_SRQ, srqn);
  2704. return 0;
  2705. ex_abort:
  2706. res_abort_move(dev, slave, RES_SRQ, srqn);
  2707. return err;
  2708. }
  2709. int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2710. struct mlx4_vhcr *vhcr,
  2711. struct mlx4_cmd_mailbox *inbox,
  2712. struct mlx4_cmd_mailbox *outbox,
  2713. struct mlx4_cmd_info *cmd)
  2714. {
  2715. int err;
  2716. int srqn = vhcr->in_modifier;
  2717. struct res_srq *srq;
  2718. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2719. if (err)
  2720. return err;
  2721. if (srq->com.from_state != RES_SRQ_HW) {
  2722. err = -EBUSY;
  2723. goto out;
  2724. }
  2725. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2726. out:
  2727. put_res(dev, slave, srqn, RES_SRQ);
  2728. return err;
  2729. }
  2730. int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2731. struct mlx4_vhcr *vhcr,
  2732. struct mlx4_cmd_mailbox *inbox,
  2733. struct mlx4_cmd_mailbox *outbox,
  2734. struct mlx4_cmd_info *cmd)
  2735. {
  2736. int err;
  2737. int srqn = vhcr->in_modifier;
  2738. struct res_srq *srq;
  2739. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2740. if (err)
  2741. return err;
  2742. if (srq->com.from_state != RES_SRQ_HW) {
  2743. err = -EBUSY;
  2744. goto out;
  2745. }
  2746. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2747. out:
  2748. put_res(dev, slave, srqn, RES_SRQ);
  2749. return err;
  2750. }
  2751. int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
  2752. struct mlx4_vhcr *vhcr,
  2753. struct mlx4_cmd_mailbox *inbox,
  2754. struct mlx4_cmd_mailbox *outbox,
  2755. struct mlx4_cmd_info *cmd)
  2756. {
  2757. int err;
  2758. int qpn = vhcr->in_modifier & 0x7fffff;
  2759. struct res_qp *qp;
  2760. err = get_res(dev, slave, qpn, RES_QP, &qp);
  2761. if (err)
  2762. return err;
  2763. if (qp->com.from_state != RES_QP_HW) {
  2764. err = -EBUSY;
  2765. goto out;
  2766. }
  2767. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2768. out:
  2769. put_res(dev, slave, qpn, RES_QP);
  2770. return err;
  2771. }
  2772. int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  2773. struct mlx4_vhcr *vhcr,
  2774. struct mlx4_cmd_mailbox *inbox,
  2775. struct mlx4_cmd_mailbox *outbox,
  2776. struct mlx4_cmd_info *cmd)
  2777. {
  2778. struct mlx4_qp_context *context = inbox->buf + 8;
  2779. adjust_proxy_tun_qkey(dev, vhcr, context);
  2780. update_pkey_index(dev, slave, inbox);
  2781. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2782. }
  2783. int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
  2784. struct mlx4_vhcr *vhcr,
  2785. struct mlx4_cmd_mailbox *inbox,
  2786. struct mlx4_cmd_mailbox *outbox,
  2787. struct mlx4_cmd_info *cmd)
  2788. {
  2789. int err;
  2790. struct mlx4_qp_context *qpc = inbox->buf + 8;
  2791. int qpn = vhcr->in_modifier & 0x7fffff;
  2792. struct res_qp *qp;
  2793. u8 orig_sched_queue;
  2794. __be32 orig_param3 = qpc->param3;
  2795. u8 orig_vlan_control = qpc->pri_path.vlan_control;
  2796. u8 orig_fvl_rx = qpc->pri_path.fvl_rx;
  2797. u8 orig_pri_path_fl = qpc->pri_path.fl;
  2798. u8 orig_vlan_index = qpc->pri_path.vlan_index;
  2799. u8 orig_feup = qpc->pri_path.feup;
  2800. err = verify_qp_parameters(dev, inbox, QP_TRANS_INIT2RTR, slave);
  2801. if (err)
  2802. return err;
  2803. update_pkey_index(dev, slave, inbox);
  2804. update_gid(dev, inbox, (u8)slave);
  2805. adjust_proxy_tun_qkey(dev, vhcr, qpc);
  2806. orig_sched_queue = qpc->pri_path.sched_queue;
  2807. err = update_vport_qp_param(dev, inbox, slave, qpn);
  2808. if (err)
  2809. return err;
  2810. err = get_res(dev, slave, qpn, RES_QP, &qp);
  2811. if (err)
  2812. return err;
  2813. if (qp->com.from_state != RES_QP_HW) {
  2814. err = -EBUSY;
  2815. goto out;
  2816. }
  2817. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2818. out:
  2819. /* if no error, save sched queue value passed in by VF. This is
  2820. * essentially the QOS value provided by the VF. This will be useful
  2821. * if we allow dynamic changes from VST back to VGT
  2822. */
  2823. if (!err) {
  2824. qp->sched_queue = orig_sched_queue;
  2825. qp->param3 = orig_param3;
  2826. qp->vlan_control = orig_vlan_control;
  2827. qp->fvl_rx = orig_fvl_rx;
  2828. qp->pri_path_fl = orig_pri_path_fl;
  2829. qp->vlan_index = orig_vlan_index;
  2830. qp->feup = orig_feup;
  2831. }
  2832. put_res(dev, slave, qpn, RES_QP);
  2833. return err;
  2834. }
  2835. int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2836. struct mlx4_vhcr *vhcr,
  2837. struct mlx4_cmd_mailbox *inbox,
  2838. struct mlx4_cmd_mailbox *outbox,
  2839. struct mlx4_cmd_info *cmd)
  2840. {
  2841. int err;
  2842. struct mlx4_qp_context *context = inbox->buf + 8;
  2843. err = verify_qp_parameters(dev, inbox, QP_TRANS_RTR2RTS, slave);
  2844. if (err)
  2845. return err;
  2846. update_pkey_index(dev, slave, inbox);
  2847. update_gid(dev, inbox, (u8)slave);
  2848. adjust_proxy_tun_qkey(dev, vhcr, context);
  2849. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2850. }
  2851. int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2852. struct mlx4_vhcr *vhcr,
  2853. struct mlx4_cmd_mailbox *inbox,
  2854. struct mlx4_cmd_mailbox *outbox,
  2855. struct mlx4_cmd_info *cmd)
  2856. {
  2857. int err;
  2858. struct mlx4_qp_context *context = inbox->buf + 8;
  2859. err = verify_qp_parameters(dev, inbox, QP_TRANS_RTS2RTS, slave);
  2860. if (err)
  2861. return err;
  2862. update_pkey_index(dev, slave, inbox);
  2863. update_gid(dev, inbox, (u8)slave);
  2864. adjust_proxy_tun_qkey(dev, vhcr, context);
  2865. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2866. }
  2867. int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2868. struct mlx4_vhcr *vhcr,
  2869. struct mlx4_cmd_mailbox *inbox,
  2870. struct mlx4_cmd_mailbox *outbox,
  2871. struct mlx4_cmd_info *cmd)
  2872. {
  2873. struct mlx4_qp_context *context = inbox->buf + 8;
  2874. adjust_proxy_tun_qkey(dev, vhcr, context);
  2875. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2876. }
  2877. int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
  2878. struct mlx4_vhcr *vhcr,
  2879. struct mlx4_cmd_mailbox *inbox,
  2880. struct mlx4_cmd_mailbox *outbox,
  2881. struct mlx4_cmd_info *cmd)
  2882. {
  2883. int err;
  2884. struct mlx4_qp_context *context = inbox->buf + 8;
  2885. err = verify_qp_parameters(dev, inbox, QP_TRANS_SQD2SQD, slave);
  2886. if (err)
  2887. return err;
  2888. adjust_proxy_tun_qkey(dev, vhcr, context);
  2889. update_gid(dev, inbox, (u8)slave);
  2890. update_pkey_index(dev, slave, inbox);
  2891. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2892. }
  2893. int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2894. struct mlx4_vhcr *vhcr,
  2895. struct mlx4_cmd_mailbox *inbox,
  2896. struct mlx4_cmd_mailbox *outbox,
  2897. struct mlx4_cmd_info *cmd)
  2898. {
  2899. int err;
  2900. struct mlx4_qp_context *context = inbox->buf + 8;
  2901. err = verify_qp_parameters(dev, inbox, QP_TRANS_SQD2RTS, slave);
  2902. if (err)
  2903. return err;
  2904. adjust_proxy_tun_qkey(dev, vhcr, context);
  2905. update_gid(dev, inbox, (u8)slave);
  2906. update_pkey_index(dev, slave, inbox);
  2907. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2908. }
  2909. int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
  2910. struct mlx4_vhcr *vhcr,
  2911. struct mlx4_cmd_mailbox *inbox,
  2912. struct mlx4_cmd_mailbox *outbox,
  2913. struct mlx4_cmd_info *cmd)
  2914. {
  2915. int err;
  2916. int qpn = vhcr->in_modifier & 0x7fffff;
  2917. struct res_qp *qp;
  2918. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
  2919. if (err)
  2920. return err;
  2921. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2922. if (err)
  2923. goto ex_abort;
  2924. atomic_dec(&qp->mtt->ref_count);
  2925. atomic_dec(&qp->rcq->ref_count);
  2926. atomic_dec(&qp->scq->ref_count);
  2927. if (qp->srq)
  2928. atomic_dec(&qp->srq->ref_count);
  2929. res_end_move(dev, slave, RES_QP, qpn);
  2930. return 0;
  2931. ex_abort:
  2932. res_abort_move(dev, slave, RES_QP, qpn);
  2933. return err;
  2934. }
  2935. static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
  2936. struct res_qp *rqp, u8 *gid)
  2937. {
  2938. struct res_gid *res;
  2939. list_for_each_entry(res, &rqp->mcg_list, list) {
  2940. if (!memcmp(res->gid, gid, 16))
  2941. return res;
  2942. }
  2943. return NULL;
  2944. }
  2945. static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2946. u8 *gid, enum mlx4_protocol prot,
  2947. enum mlx4_steer_type steer, u64 reg_id)
  2948. {
  2949. struct res_gid *res;
  2950. int err;
  2951. res = kzalloc(sizeof *res, GFP_KERNEL);
  2952. if (!res)
  2953. return -ENOMEM;
  2954. spin_lock_irq(&rqp->mcg_spl);
  2955. if (find_gid(dev, slave, rqp, gid)) {
  2956. kfree(res);
  2957. err = -EEXIST;
  2958. } else {
  2959. memcpy(res->gid, gid, 16);
  2960. res->prot = prot;
  2961. res->steer = steer;
  2962. res->reg_id = reg_id;
  2963. list_add_tail(&res->list, &rqp->mcg_list);
  2964. err = 0;
  2965. }
  2966. spin_unlock_irq(&rqp->mcg_spl);
  2967. return err;
  2968. }
  2969. static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2970. u8 *gid, enum mlx4_protocol prot,
  2971. enum mlx4_steer_type steer, u64 *reg_id)
  2972. {
  2973. struct res_gid *res;
  2974. int err;
  2975. spin_lock_irq(&rqp->mcg_spl);
  2976. res = find_gid(dev, slave, rqp, gid);
  2977. if (!res || res->prot != prot || res->steer != steer)
  2978. err = -EINVAL;
  2979. else {
  2980. *reg_id = res->reg_id;
  2981. list_del(&res->list);
  2982. kfree(res);
  2983. err = 0;
  2984. }
  2985. spin_unlock_irq(&rqp->mcg_spl);
  2986. return err;
  2987. }
  2988. static int qp_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
  2989. int block_loopback, enum mlx4_protocol prot,
  2990. enum mlx4_steer_type type, u64 *reg_id)
  2991. {
  2992. switch (dev->caps.steering_mode) {
  2993. case MLX4_STEERING_MODE_DEVICE_MANAGED:
  2994. return mlx4_trans_to_dmfs_attach(dev, qp, gid, gid[5],
  2995. block_loopback, prot,
  2996. reg_id);
  2997. case MLX4_STEERING_MODE_B0:
  2998. return mlx4_qp_attach_common(dev, qp, gid,
  2999. block_loopback, prot, type);
  3000. default:
  3001. return -EINVAL;
  3002. }
  3003. }
  3004. static int qp_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
  3005. enum mlx4_protocol prot, enum mlx4_steer_type type,
  3006. u64 reg_id)
  3007. {
  3008. switch (dev->caps.steering_mode) {
  3009. case MLX4_STEERING_MODE_DEVICE_MANAGED:
  3010. return mlx4_flow_detach(dev, reg_id);
  3011. case MLX4_STEERING_MODE_B0:
  3012. return mlx4_qp_detach_common(dev, qp, gid, prot, type);
  3013. default:
  3014. return -EINVAL;
  3015. }
  3016. }
  3017. int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  3018. struct mlx4_vhcr *vhcr,
  3019. struct mlx4_cmd_mailbox *inbox,
  3020. struct mlx4_cmd_mailbox *outbox,
  3021. struct mlx4_cmd_info *cmd)
  3022. {
  3023. struct mlx4_qp qp; /* dummy for calling attach/detach */
  3024. u8 *gid = inbox->buf;
  3025. enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
  3026. int err;
  3027. int qpn;
  3028. struct res_qp *rqp;
  3029. u64 reg_id = 0;
  3030. int attach = vhcr->op_modifier;
  3031. int block_loopback = vhcr->in_modifier >> 31;
  3032. u8 steer_type_mask = 2;
  3033. enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
  3034. qpn = vhcr->in_modifier & 0xffffff;
  3035. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  3036. if (err)
  3037. return err;
  3038. qp.qpn = qpn;
  3039. if (attach) {
  3040. err = qp_attach(dev, &qp, gid, block_loopback, prot,
  3041. type, &reg_id);
  3042. if (err) {
  3043. pr_err("Fail to attach rule to qp 0x%x\n", qpn);
  3044. goto ex_put;
  3045. }
  3046. err = add_mcg_res(dev, slave, rqp, gid, prot, type, reg_id);
  3047. if (err)
  3048. goto ex_detach;
  3049. } else {
  3050. err = rem_mcg_res(dev, slave, rqp, gid, prot, type, &reg_id);
  3051. if (err)
  3052. goto ex_put;
  3053. err = qp_detach(dev, &qp, gid, prot, type, reg_id);
  3054. if (err)
  3055. pr_err("Fail to detach rule from qp 0x%x reg_id = 0x%llx\n",
  3056. qpn, reg_id);
  3057. }
  3058. put_res(dev, slave, qpn, RES_QP);
  3059. return err;
  3060. ex_detach:
  3061. qp_detach(dev, &qp, gid, prot, type, reg_id);
  3062. ex_put:
  3063. put_res(dev, slave, qpn, RES_QP);
  3064. return err;
  3065. }
  3066. /*
  3067. * MAC validation for Flow Steering rules.
  3068. * VF can attach rules only with a mac address which is assigned to it.
  3069. */
  3070. static int validate_eth_header_mac(int slave, struct _rule_hw *eth_header,
  3071. struct list_head *rlist)
  3072. {
  3073. struct mac_res *res, *tmp;
  3074. __be64 be_mac;
  3075. /* make sure it isn't multicast or broadcast mac*/
  3076. if (!is_multicast_ether_addr(eth_header->eth.dst_mac) &&
  3077. !is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
  3078. list_for_each_entry_safe(res, tmp, rlist, list) {
  3079. be_mac = cpu_to_be64(res->mac << 16);
  3080. if (!memcmp(&be_mac, eth_header->eth.dst_mac, ETH_ALEN))
  3081. return 0;
  3082. }
  3083. pr_err("MAC %pM doesn't belong to VF %d, Steering rule rejected\n",
  3084. eth_header->eth.dst_mac, slave);
  3085. return -EINVAL;
  3086. }
  3087. return 0;
  3088. }
  3089. /*
  3090. * In case of missing eth header, append eth header with a MAC address
  3091. * assigned to the VF.
  3092. */
  3093. static int add_eth_header(struct mlx4_dev *dev, int slave,
  3094. struct mlx4_cmd_mailbox *inbox,
  3095. struct list_head *rlist, int header_id)
  3096. {
  3097. struct mac_res *res, *tmp;
  3098. u8 port;
  3099. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  3100. struct mlx4_net_trans_rule_hw_eth *eth_header;
  3101. struct mlx4_net_trans_rule_hw_ipv4 *ip_header;
  3102. struct mlx4_net_trans_rule_hw_tcp_udp *l4_header;
  3103. __be64 be_mac = 0;
  3104. __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
  3105. ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
  3106. port = ctrl->port;
  3107. eth_header = (struct mlx4_net_trans_rule_hw_eth *)(ctrl + 1);
  3108. /* Clear a space in the inbox for eth header */
  3109. switch (header_id) {
  3110. case MLX4_NET_TRANS_RULE_ID_IPV4:
  3111. ip_header =
  3112. (struct mlx4_net_trans_rule_hw_ipv4 *)(eth_header + 1);
  3113. memmove(ip_header, eth_header,
  3114. sizeof(*ip_header) + sizeof(*l4_header));
  3115. break;
  3116. case MLX4_NET_TRANS_RULE_ID_TCP:
  3117. case MLX4_NET_TRANS_RULE_ID_UDP:
  3118. l4_header = (struct mlx4_net_trans_rule_hw_tcp_udp *)
  3119. (eth_header + 1);
  3120. memmove(l4_header, eth_header, sizeof(*l4_header));
  3121. break;
  3122. default:
  3123. return -EINVAL;
  3124. }
  3125. list_for_each_entry_safe(res, tmp, rlist, list) {
  3126. if (port == res->port) {
  3127. be_mac = cpu_to_be64(res->mac << 16);
  3128. break;
  3129. }
  3130. }
  3131. if (!be_mac) {
  3132. pr_err("Failed adding eth header to FS rule, Can't find matching MAC for port %d .\n",
  3133. port);
  3134. return -EINVAL;
  3135. }
  3136. memset(eth_header, 0, sizeof(*eth_header));
  3137. eth_header->size = sizeof(*eth_header) >> 2;
  3138. eth_header->id = cpu_to_be16(__sw_id_hw[MLX4_NET_TRANS_RULE_ID_ETH]);
  3139. memcpy(eth_header->dst_mac, &be_mac, ETH_ALEN);
  3140. memcpy(eth_header->dst_mac_msk, &mac_msk, ETH_ALEN);
  3141. return 0;
  3142. }
  3143. int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  3144. struct mlx4_vhcr *vhcr,
  3145. struct mlx4_cmd_mailbox *inbox,
  3146. struct mlx4_cmd_mailbox *outbox,
  3147. struct mlx4_cmd_info *cmd)
  3148. {
  3149. struct mlx4_priv *priv = mlx4_priv(dev);
  3150. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3151. struct list_head *rlist = &tracker->slave_list[slave].res_list[RES_MAC];
  3152. int err;
  3153. int qpn;
  3154. struct res_qp *rqp;
  3155. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  3156. struct _rule_hw *rule_header;
  3157. int header_id;
  3158. if (dev->caps.steering_mode !=
  3159. MLX4_STEERING_MODE_DEVICE_MANAGED)
  3160. return -EOPNOTSUPP;
  3161. ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
  3162. qpn = be32_to_cpu(ctrl->qpn) & 0xffffff;
  3163. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  3164. if (err) {
  3165. pr_err("Steering rule with qpn 0x%x rejected.\n", qpn);
  3166. return err;
  3167. }
  3168. rule_header = (struct _rule_hw *)(ctrl + 1);
  3169. header_id = map_hw_to_sw_id(be16_to_cpu(rule_header->id));
  3170. switch (header_id) {
  3171. case MLX4_NET_TRANS_RULE_ID_ETH:
  3172. if (validate_eth_header_mac(slave, rule_header, rlist)) {
  3173. err = -EINVAL;
  3174. goto err_put;
  3175. }
  3176. break;
  3177. case MLX4_NET_TRANS_RULE_ID_IB:
  3178. break;
  3179. case MLX4_NET_TRANS_RULE_ID_IPV4:
  3180. case MLX4_NET_TRANS_RULE_ID_TCP:
  3181. case MLX4_NET_TRANS_RULE_ID_UDP:
  3182. pr_warn("Can't attach FS rule without L2 headers, adding L2 header.\n");
  3183. if (add_eth_header(dev, slave, inbox, rlist, header_id)) {
  3184. err = -EINVAL;
  3185. goto err_put;
  3186. }
  3187. vhcr->in_modifier +=
  3188. sizeof(struct mlx4_net_trans_rule_hw_eth) >> 2;
  3189. break;
  3190. default:
  3191. pr_err("Corrupted mailbox.\n");
  3192. err = -EINVAL;
  3193. goto err_put;
  3194. }
  3195. err = mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
  3196. vhcr->in_modifier, 0,
  3197. MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
  3198. MLX4_CMD_NATIVE);
  3199. if (err)
  3200. goto err_put;
  3201. err = add_res_range(dev, slave, vhcr->out_param, 1, RES_FS_RULE, qpn);
  3202. if (err) {
  3203. mlx4_err(dev, "Fail to add flow steering resources.\n ");
  3204. /* detach rule*/
  3205. mlx4_cmd(dev, vhcr->out_param, 0, 0,
  3206. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  3207. MLX4_CMD_NATIVE);
  3208. goto err_put;
  3209. }
  3210. atomic_inc(&rqp->ref_count);
  3211. err_put:
  3212. put_res(dev, slave, qpn, RES_QP);
  3213. return err;
  3214. }
  3215. int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
  3216. struct mlx4_vhcr *vhcr,
  3217. struct mlx4_cmd_mailbox *inbox,
  3218. struct mlx4_cmd_mailbox *outbox,
  3219. struct mlx4_cmd_info *cmd)
  3220. {
  3221. int err;
  3222. struct res_qp *rqp;
  3223. struct res_fs_rule *rrule;
  3224. if (dev->caps.steering_mode !=
  3225. MLX4_STEERING_MODE_DEVICE_MANAGED)
  3226. return -EOPNOTSUPP;
  3227. err = get_res(dev, slave, vhcr->in_param, RES_FS_RULE, &rrule);
  3228. if (err)
  3229. return err;
  3230. /* Release the rule form busy state before removal */
  3231. put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
  3232. err = get_res(dev, slave, rrule->qpn, RES_QP, &rqp);
  3233. if (err)
  3234. return err;
  3235. err = rem_res_range(dev, slave, vhcr->in_param, 1, RES_FS_RULE, 0);
  3236. if (err) {
  3237. mlx4_err(dev, "Fail to remove flow steering resources.\n ");
  3238. goto out;
  3239. }
  3240. err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
  3241. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  3242. MLX4_CMD_NATIVE);
  3243. if (!err)
  3244. atomic_dec(&rqp->ref_count);
  3245. out:
  3246. put_res(dev, slave, rrule->qpn, RES_QP);
  3247. return err;
  3248. }
  3249. enum {
  3250. BUSY_MAX_RETRIES = 10
  3251. };
  3252. int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
  3253. struct mlx4_vhcr *vhcr,
  3254. struct mlx4_cmd_mailbox *inbox,
  3255. struct mlx4_cmd_mailbox *outbox,
  3256. struct mlx4_cmd_info *cmd)
  3257. {
  3258. int err;
  3259. int index = vhcr->in_modifier & 0xffff;
  3260. err = get_res(dev, slave, index, RES_COUNTER, NULL);
  3261. if (err)
  3262. return err;
  3263. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  3264. put_res(dev, slave, index, RES_COUNTER);
  3265. return err;
  3266. }
  3267. static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
  3268. {
  3269. struct res_gid *rgid;
  3270. struct res_gid *tmp;
  3271. struct mlx4_qp qp; /* dummy for calling attach/detach */
  3272. list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
  3273. switch (dev->caps.steering_mode) {
  3274. case MLX4_STEERING_MODE_DEVICE_MANAGED:
  3275. mlx4_flow_detach(dev, rgid->reg_id);
  3276. break;
  3277. case MLX4_STEERING_MODE_B0:
  3278. qp.qpn = rqp->local_qpn;
  3279. (void) mlx4_qp_detach_common(dev, &qp, rgid->gid,
  3280. rgid->prot, rgid->steer);
  3281. break;
  3282. }
  3283. list_del(&rgid->list);
  3284. kfree(rgid);
  3285. }
  3286. }
  3287. static int _move_all_busy(struct mlx4_dev *dev, int slave,
  3288. enum mlx4_resource type, int print)
  3289. {
  3290. struct mlx4_priv *priv = mlx4_priv(dev);
  3291. struct mlx4_resource_tracker *tracker =
  3292. &priv->mfunc.master.res_tracker;
  3293. struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
  3294. struct res_common *r;
  3295. struct res_common *tmp;
  3296. int busy;
  3297. busy = 0;
  3298. spin_lock_irq(mlx4_tlock(dev));
  3299. list_for_each_entry_safe(r, tmp, rlist, list) {
  3300. if (r->owner == slave) {
  3301. if (!r->removing) {
  3302. if (r->state == RES_ANY_BUSY) {
  3303. if (print)
  3304. mlx4_dbg(dev,
  3305. "%s id 0x%llx is busy\n",
  3306. ResourceType(type),
  3307. r->res_id);
  3308. ++busy;
  3309. } else {
  3310. r->from_state = r->state;
  3311. r->state = RES_ANY_BUSY;
  3312. r->removing = 1;
  3313. }
  3314. }
  3315. }
  3316. }
  3317. spin_unlock_irq(mlx4_tlock(dev));
  3318. return busy;
  3319. }
  3320. static int move_all_busy(struct mlx4_dev *dev, int slave,
  3321. enum mlx4_resource type)
  3322. {
  3323. unsigned long begin;
  3324. int busy;
  3325. begin = jiffies;
  3326. do {
  3327. busy = _move_all_busy(dev, slave, type, 0);
  3328. if (time_after(jiffies, begin + 5 * HZ))
  3329. break;
  3330. if (busy)
  3331. cond_resched();
  3332. } while (busy);
  3333. if (busy)
  3334. busy = _move_all_busy(dev, slave, type, 1);
  3335. return busy;
  3336. }
  3337. static void rem_slave_qps(struct mlx4_dev *dev, int slave)
  3338. {
  3339. struct mlx4_priv *priv = mlx4_priv(dev);
  3340. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3341. struct list_head *qp_list =
  3342. &tracker->slave_list[slave].res_list[RES_QP];
  3343. struct res_qp *qp;
  3344. struct res_qp *tmp;
  3345. int state;
  3346. u64 in_param;
  3347. int qpn;
  3348. int err;
  3349. err = move_all_busy(dev, slave, RES_QP);
  3350. if (err)
  3351. mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy"
  3352. "for slave %d\n", slave);
  3353. spin_lock_irq(mlx4_tlock(dev));
  3354. list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
  3355. spin_unlock_irq(mlx4_tlock(dev));
  3356. if (qp->com.owner == slave) {
  3357. qpn = qp->com.res_id;
  3358. detach_qp(dev, slave, qp);
  3359. state = qp->com.from_state;
  3360. while (state != 0) {
  3361. switch (state) {
  3362. case RES_QP_RESERVED:
  3363. spin_lock_irq(mlx4_tlock(dev));
  3364. rb_erase(&qp->com.node,
  3365. &tracker->res_tree[RES_QP]);
  3366. list_del(&qp->com.list);
  3367. spin_unlock_irq(mlx4_tlock(dev));
  3368. if (!valid_reserved(dev, slave, qpn)) {
  3369. __mlx4_qp_release_range(dev, qpn, 1);
  3370. mlx4_release_resource(dev, slave,
  3371. RES_QP, 1, 0);
  3372. }
  3373. kfree(qp);
  3374. state = 0;
  3375. break;
  3376. case RES_QP_MAPPED:
  3377. if (!valid_reserved(dev, slave, qpn))
  3378. __mlx4_qp_free_icm(dev, qpn);
  3379. state = RES_QP_RESERVED;
  3380. break;
  3381. case RES_QP_HW:
  3382. in_param = slave;
  3383. err = mlx4_cmd(dev, in_param,
  3384. qp->local_qpn, 2,
  3385. MLX4_CMD_2RST_QP,
  3386. MLX4_CMD_TIME_CLASS_A,
  3387. MLX4_CMD_NATIVE);
  3388. if (err)
  3389. mlx4_dbg(dev, "rem_slave_qps: failed"
  3390. " to move slave %d qpn %d to"
  3391. " reset\n", slave,
  3392. qp->local_qpn);
  3393. atomic_dec(&qp->rcq->ref_count);
  3394. atomic_dec(&qp->scq->ref_count);
  3395. atomic_dec(&qp->mtt->ref_count);
  3396. if (qp->srq)
  3397. atomic_dec(&qp->srq->ref_count);
  3398. state = RES_QP_MAPPED;
  3399. break;
  3400. default:
  3401. state = 0;
  3402. }
  3403. }
  3404. }
  3405. spin_lock_irq(mlx4_tlock(dev));
  3406. }
  3407. spin_unlock_irq(mlx4_tlock(dev));
  3408. }
  3409. static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
  3410. {
  3411. struct mlx4_priv *priv = mlx4_priv(dev);
  3412. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3413. struct list_head *srq_list =
  3414. &tracker->slave_list[slave].res_list[RES_SRQ];
  3415. struct res_srq *srq;
  3416. struct res_srq *tmp;
  3417. int state;
  3418. u64 in_param;
  3419. LIST_HEAD(tlist);
  3420. int srqn;
  3421. int err;
  3422. err = move_all_busy(dev, slave, RES_SRQ);
  3423. if (err)
  3424. mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs to "
  3425. "busy for slave %d\n", slave);
  3426. spin_lock_irq(mlx4_tlock(dev));
  3427. list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
  3428. spin_unlock_irq(mlx4_tlock(dev));
  3429. if (srq->com.owner == slave) {
  3430. srqn = srq->com.res_id;
  3431. state = srq->com.from_state;
  3432. while (state != 0) {
  3433. switch (state) {
  3434. case RES_SRQ_ALLOCATED:
  3435. __mlx4_srq_free_icm(dev, srqn);
  3436. spin_lock_irq(mlx4_tlock(dev));
  3437. rb_erase(&srq->com.node,
  3438. &tracker->res_tree[RES_SRQ]);
  3439. list_del(&srq->com.list);
  3440. spin_unlock_irq(mlx4_tlock(dev));
  3441. mlx4_release_resource(dev, slave,
  3442. RES_SRQ, 1, 0);
  3443. kfree(srq);
  3444. state = 0;
  3445. break;
  3446. case RES_SRQ_HW:
  3447. in_param = slave;
  3448. err = mlx4_cmd(dev, in_param, srqn, 1,
  3449. MLX4_CMD_HW2SW_SRQ,
  3450. MLX4_CMD_TIME_CLASS_A,
  3451. MLX4_CMD_NATIVE);
  3452. if (err)
  3453. mlx4_dbg(dev, "rem_slave_srqs: failed"
  3454. " to move slave %d srq %d to"
  3455. " SW ownership\n",
  3456. slave, srqn);
  3457. atomic_dec(&srq->mtt->ref_count);
  3458. if (srq->cq)
  3459. atomic_dec(&srq->cq->ref_count);
  3460. state = RES_SRQ_ALLOCATED;
  3461. break;
  3462. default:
  3463. state = 0;
  3464. }
  3465. }
  3466. }
  3467. spin_lock_irq(mlx4_tlock(dev));
  3468. }
  3469. spin_unlock_irq(mlx4_tlock(dev));
  3470. }
  3471. static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
  3472. {
  3473. struct mlx4_priv *priv = mlx4_priv(dev);
  3474. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3475. struct list_head *cq_list =
  3476. &tracker->slave_list[slave].res_list[RES_CQ];
  3477. struct res_cq *cq;
  3478. struct res_cq *tmp;
  3479. int state;
  3480. u64 in_param;
  3481. LIST_HEAD(tlist);
  3482. int cqn;
  3483. int err;
  3484. err = move_all_busy(dev, slave, RES_CQ);
  3485. if (err)
  3486. mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs to "
  3487. "busy for slave %d\n", slave);
  3488. spin_lock_irq(mlx4_tlock(dev));
  3489. list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
  3490. spin_unlock_irq(mlx4_tlock(dev));
  3491. if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
  3492. cqn = cq->com.res_id;
  3493. state = cq->com.from_state;
  3494. while (state != 0) {
  3495. switch (state) {
  3496. case RES_CQ_ALLOCATED:
  3497. __mlx4_cq_free_icm(dev, cqn);
  3498. spin_lock_irq(mlx4_tlock(dev));
  3499. rb_erase(&cq->com.node,
  3500. &tracker->res_tree[RES_CQ]);
  3501. list_del(&cq->com.list);
  3502. spin_unlock_irq(mlx4_tlock(dev));
  3503. mlx4_release_resource(dev, slave,
  3504. RES_CQ, 1, 0);
  3505. kfree(cq);
  3506. state = 0;
  3507. break;
  3508. case RES_CQ_HW:
  3509. in_param = slave;
  3510. err = mlx4_cmd(dev, in_param, cqn, 1,
  3511. MLX4_CMD_HW2SW_CQ,
  3512. MLX4_CMD_TIME_CLASS_A,
  3513. MLX4_CMD_NATIVE);
  3514. if (err)
  3515. mlx4_dbg(dev, "rem_slave_cqs: failed"
  3516. " to move slave %d cq %d to"
  3517. " SW ownership\n",
  3518. slave, cqn);
  3519. atomic_dec(&cq->mtt->ref_count);
  3520. state = RES_CQ_ALLOCATED;
  3521. break;
  3522. default:
  3523. state = 0;
  3524. }
  3525. }
  3526. }
  3527. spin_lock_irq(mlx4_tlock(dev));
  3528. }
  3529. spin_unlock_irq(mlx4_tlock(dev));
  3530. }
  3531. static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
  3532. {
  3533. struct mlx4_priv *priv = mlx4_priv(dev);
  3534. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3535. struct list_head *mpt_list =
  3536. &tracker->slave_list[slave].res_list[RES_MPT];
  3537. struct res_mpt *mpt;
  3538. struct res_mpt *tmp;
  3539. int state;
  3540. u64 in_param;
  3541. LIST_HEAD(tlist);
  3542. int mptn;
  3543. int err;
  3544. err = move_all_busy(dev, slave, RES_MPT);
  3545. if (err)
  3546. mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts to "
  3547. "busy for slave %d\n", slave);
  3548. spin_lock_irq(mlx4_tlock(dev));
  3549. list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
  3550. spin_unlock_irq(mlx4_tlock(dev));
  3551. if (mpt->com.owner == slave) {
  3552. mptn = mpt->com.res_id;
  3553. state = mpt->com.from_state;
  3554. while (state != 0) {
  3555. switch (state) {
  3556. case RES_MPT_RESERVED:
  3557. __mlx4_mpt_release(dev, mpt->key);
  3558. spin_lock_irq(mlx4_tlock(dev));
  3559. rb_erase(&mpt->com.node,
  3560. &tracker->res_tree[RES_MPT]);
  3561. list_del(&mpt->com.list);
  3562. spin_unlock_irq(mlx4_tlock(dev));
  3563. mlx4_release_resource(dev, slave,
  3564. RES_MPT, 1, 0);
  3565. kfree(mpt);
  3566. state = 0;
  3567. break;
  3568. case RES_MPT_MAPPED:
  3569. __mlx4_mpt_free_icm(dev, mpt->key);
  3570. state = RES_MPT_RESERVED;
  3571. break;
  3572. case RES_MPT_HW:
  3573. in_param = slave;
  3574. err = mlx4_cmd(dev, in_param, mptn, 0,
  3575. MLX4_CMD_HW2SW_MPT,
  3576. MLX4_CMD_TIME_CLASS_A,
  3577. MLX4_CMD_NATIVE);
  3578. if (err)
  3579. mlx4_dbg(dev, "rem_slave_mrs: failed"
  3580. " to move slave %d mpt %d to"
  3581. " SW ownership\n",
  3582. slave, mptn);
  3583. if (mpt->mtt)
  3584. atomic_dec(&mpt->mtt->ref_count);
  3585. state = RES_MPT_MAPPED;
  3586. break;
  3587. default:
  3588. state = 0;
  3589. }
  3590. }
  3591. }
  3592. spin_lock_irq(mlx4_tlock(dev));
  3593. }
  3594. spin_unlock_irq(mlx4_tlock(dev));
  3595. }
  3596. static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
  3597. {
  3598. struct mlx4_priv *priv = mlx4_priv(dev);
  3599. struct mlx4_resource_tracker *tracker =
  3600. &priv->mfunc.master.res_tracker;
  3601. struct list_head *mtt_list =
  3602. &tracker->slave_list[slave].res_list[RES_MTT];
  3603. struct res_mtt *mtt;
  3604. struct res_mtt *tmp;
  3605. int state;
  3606. LIST_HEAD(tlist);
  3607. int base;
  3608. int err;
  3609. err = move_all_busy(dev, slave, RES_MTT);
  3610. if (err)
  3611. mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts to "
  3612. "busy for slave %d\n", slave);
  3613. spin_lock_irq(mlx4_tlock(dev));
  3614. list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
  3615. spin_unlock_irq(mlx4_tlock(dev));
  3616. if (mtt->com.owner == slave) {
  3617. base = mtt->com.res_id;
  3618. state = mtt->com.from_state;
  3619. while (state != 0) {
  3620. switch (state) {
  3621. case RES_MTT_ALLOCATED:
  3622. __mlx4_free_mtt_range(dev, base,
  3623. mtt->order);
  3624. spin_lock_irq(mlx4_tlock(dev));
  3625. rb_erase(&mtt->com.node,
  3626. &tracker->res_tree[RES_MTT]);
  3627. list_del(&mtt->com.list);
  3628. spin_unlock_irq(mlx4_tlock(dev));
  3629. mlx4_release_resource(dev, slave, RES_MTT,
  3630. 1 << mtt->order, 0);
  3631. kfree(mtt);
  3632. state = 0;
  3633. break;
  3634. default:
  3635. state = 0;
  3636. }
  3637. }
  3638. }
  3639. spin_lock_irq(mlx4_tlock(dev));
  3640. }
  3641. spin_unlock_irq(mlx4_tlock(dev));
  3642. }
  3643. static void rem_slave_fs_rule(struct mlx4_dev *dev, int slave)
  3644. {
  3645. struct mlx4_priv *priv = mlx4_priv(dev);
  3646. struct mlx4_resource_tracker *tracker =
  3647. &priv->mfunc.master.res_tracker;
  3648. struct list_head *fs_rule_list =
  3649. &tracker->slave_list[slave].res_list[RES_FS_RULE];
  3650. struct res_fs_rule *fs_rule;
  3651. struct res_fs_rule *tmp;
  3652. int state;
  3653. u64 base;
  3654. int err;
  3655. err = move_all_busy(dev, slave, RES_FS_RULE);
  3656. if (err)
  3657. mlx4_warn(dev, "rem_slave_fs_rule: Could not move all mtts to busy for slave %d\n",
  3658. slave);
  3659. spin_lock_irq(mlx4_tlock(dev));
  3660. list_for_each_entry_safe(fs_rule, tmp, fs_rule_list, com.list) {
  3661. spin_unlock_irq(mlx4_tlock(dev));
  3662. if (fs_rule->com.owner == slave) {
  3663. base = fs_rule->com.res_id;
  3664. state = fs_rule->com.from_state;
  3665. while (state != 0) {
  3666. switch (state) {
  3667. case RES_FS_RULE_ALLOCATED:
  3668. /* detach rule */
  3669. err = mlx4_cmd(dev, base, 0, 0,
  3670. MLX4_QP_FLOW_STEERING_DETACH,
  3671. MLX4_CMD_TIME_CLASS_A,
  3672. MLX4_CMD_NATIVE);
  3673. spin_lock_irq(mlx4_tlock(dev));
  3674. rb_erase(&fs_rule->com.node,
  3675. &tracker->res_tree[RES_FS_RULE]);
  3676. list_del(&fs_rule->com.list);
  3677. spin_unlock_irq(mlx4_tlock(dev));
  3678. kfree(fs_rule);
  3679. state = 0;
  3680. break;
  3681. default:
  3682. state = 0;
  3683. }
  3684. }
  3685. }
  3686. spin_lock_irq(mlx4_tlock(dev));
  3687. }
  3688. spin_unlock_irq(mlx4_tlock(dev));
  3689. }
  3690. static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
  3691. {
  3692. struct mlx4_priv *priv = mlx4_priv(dev);
  3693. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3694. struct list_head *eq_list =
  3695. &tracker->slave_list[slave].res_list[RES_EQ];
  3696. struct res_eq *eq;
  3697. struct res_eq *tmp;
  3698. int err;
  3699. int state;
  3700. LIST_HEAD(tlist);
  3701. int eqn;
  3702. struct mlx4_cmd_mailbox *mailbox;
  3703. err = move_all_busy(dev, slave, RES_EQ);
  3704. if (err)
  3705. mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs to "
  3706. "busy for slave %d\n", slave);
  3707. spin_lock_irq(mlx4_tlock(dev));
  3708. list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
  3709. spin_unlock_irq(mlx4_tlock(dev));
  3710. if (eq->com.owner == slave) {
  3711. eqn = eq->com.res_id;
  3712. state = eq->com.from_state;
  3713. while (state != 0) {
  3714. switch (state) {
  3715. case RES_EQ_RESERVED:
  3716. spin_lock_irq(mlx4_tlock(dev));
  3717. rb_erase(&eq->com.node,
  3718. &tracker->res_tree[RES_EQ]);
  3719. list_del(&eq->com.list);
  3720. spin_unlock_irq(mlx4_tlock(dev));
  3721. kfree(eq);
  3722. state = 0;
  3723. break;
  3724. case RES_EQ_HW:
  3725. mailbox = mlx4_alloc_cmd_mailbox(dev);
  3726. if (IS_ERR(mailbox)) {
  3727. cond_resched();
  3728. continue;
  3729. }
  3730. err = mlx4_cmd_box(dev, slave, 0,
  3731. eqn & 0xff, 0,
  3732. MLX4_CMD_HW2SW_EQ,
  3733. MLX4_CMD_TIME_CLASS_A,
  3734. MLX4_CMD_NATIVE);
  3735. if (err)
  3736. mlx4_dbg(dev, "rem_slave_eqs: failed"
  3737. " to move slave %d eqs %d to"
  3738. " SW ownership\n", slave, eqn);
  3739. mlx4_free_cmd_mailbox(dev, mailbox);
  3740. atomic_dec(&eq->mtt->ref_count);
  3741. state = RES_EQ_RESERVED;
  3742. break;
  3743. default:
  3744. state = 0;
  3745. }
  3746. }
  3747. }
  3748. spin_lock_irq(mlx4_tlock(dev));
  3749. }
  3750. spin_unlock_irq(mlx4_tlock(dev));
  3751. }
  3752. static void rem_slave_counters(struct mlx4_dev *dev, int slave)
  3753. {
  3754. struct mlx4_priv *priv = mlx4_priv(dev);
  3755. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3756. struct list_head *counter_list =
  3757. &tracker->slave_list[slave].res_list[RES_COUNTER];
  3758. struct res_counter *counter;
  3759. struct res_counter *tmp;
  3760. int err;
  3761. int index;
  3762. err = move_all_busy(dev, slave, RES_COUNTER);
  3763. if (err)
  3764. mlx4_warn(dev, "rem_slave_counters: Could not move all counters to "
  3765. "busy for slave %d\n", slave);
  3766. spin_lock_irq(mlx4_tlock(dev));
  3767. list_for_each_entry_safe(counter, tmp, counter_list, com.list) {
  3768. if (counter->com.owner == slave) {
  3769. index = counter->com.res_id;
  3770. rb_erase(&counter->com.node,
  3771. &tracker->res_tree[RES_COUNTER]);
  3772. list_del(&counter->com.list);
  3773. kfree(counter);
  3774. __mlx4_counter_free(dev, index);
  3775. mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
  3776. }
  3777. }
  3778. spin_unlock_irq(mlx4_tlock(dev));
  3779. }
  3780. static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
  3781. {
  3782. struct mlx4_priv *priv = mlx4_priv(dev);
  3783. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3784. struct list_head *xrcdn_list =
  3785. &tracker->slave_list[slave].res_list[RES_XRCD];
  3786. struct res_xrcdn *xrcd;
  3787. struct res_xrcdn *tmp;
  3788. int err;
  3789. int xrcdn;
  3790. err = move_all_busy(dev, slave, RES_XRCD);
  3791. if (err)
  3792. mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns to "
  3793. "busy for slave %d\n", slave);
  3794. spin_lock_irq(mlx4_tlock(dev));
  3795. list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
  3796. if (xrcd->com.owner == slave) {
  3797. xrcdn = xrcd->com.res_id;
  3798. rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]);
  3799. list_del(&xrcd->com.list);
  3800. kfree(xrcd);
  3801. __mlx4_xrcd_free(dev, xrcdn);
  3802. }
  3803. }
  3804. spin_unlock_irq(mlx4_tlock(dev));
  3805. }
  3806. void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
  3807. {
  3808. struct mlx4_priv *priv = mlx4_priv(dev);
  3809. mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  3810. rem_slave_vlans(dev, slave);
  3811. rem_slave_macs(dev, slave);
  3812. rem_slave_fs_rule(dev, slave);
  3813. rem_slave_qps(dev, slave);
  3814. rem_slave_srqs(dev, slave);
  3815. rem_slave_cqs(dev, slave);
  3816. rem_slave_mrs(dev, slave);
  3817. rem_slave_eqs(dev, slave);
  3818. rem_slave_mtts(dev, slave);
  3819. rem_slave_counters(dev, slave);
  3820. rem_slave_xrcdns(dev, slave);
  3821. mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  3822. }
  3823. void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work)
  3824. {
  3825. struct mlx4_vf_immed_vlan_work *work =
  3826. container_of(_work, struct mlx4_vf_immed_vlan_work, work);
  3827. struct mlx4_cmd_mailbox *mailbox;
  3828. struct mlx4_update_qp_context *upd_context;
  3829. struct mlx4_dev *dev = &work->priv->dev;
  3830. struct mlx4_resource_tracker *tracker =
  3831. &work->priv->mfunc.master.res_tracker;
  3832. struct list_head *qp_list =
  3833. &tracker->slave_list[work->slave].res_list[RES_QP];
  3834. struct res_qp *qp;
  3835. struct res_qp *tmp;
  3836. u64 qp_path_mask_vlan_ctrl =
  3837. ((1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED) |
  3838. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P) |
  3839. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED) |
  3840. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED) |
  3841. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P) |
  3842. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED));
  3843. u64 qp_path_mask = ((1ULL << MLX4_UPD_QP_PATH_MASK_VLAN_INDEX) |
  3844. (1ULL << MLX4_UPD_QP_PATH_MASK_FVL) |
  3845. (1ULL << MLX4_UPD_QP_PATH_MASK_CV) |
  3846. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN) |
  3847. (1ULL << MLX4_UPD_QP_PATH_MASK_FEUP) |
  3848. (1ULL << MLX4_UPD_QP_PATH_MASK_FVL_RX) |
  3849. (1ULL << MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE));
  3850. int err;
  3851. int port, errors = 0;
  3852. u8 vlan_control;
  3853. if (mlx4_is_slave(dev)) {
  3854. mlx4_warn(dev, "Trying to update-qp in slave %d\n",
  3855. work->slave);
  3856. goto out;
  3857. }
  3858. mailbox = mlx4_alloc_cmd_mailbox(dev);
  3859. if (IS_ERR(mailbox))
  3860. goto out;
  3861. if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE) /* block all */
  3862. vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  3863. MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
  3864. MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
  3865. MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
  3866. MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
  3867. MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
  3868. else if (!work->vlan_id)
  3869. vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  3870. MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
  3871. else
  3872. vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  3873. MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
  3874. MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
  3875. upd_context = mailbox->buf;
  3876. upd_context->qp_mask = cpu_to_be64(MLX4_UPD_QP_MASK_VSD);
  3877. spin_lock_irq(mlx4_tlock(dev));
  3878. list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
  3879. spin_unlock_irq(mlx4_tlock(dev));
  3880. if (qp->com.owner == work->slave) {
  3881. if (qp->com.from_state != RES_QP_HW ||
  3882. !qp->sched_queue || /* no INIT2RTR trans yet */
  3883. mlx4_is_qp_reserved(dev, qp->local_qpn) ||
  3884. qp->qpc_flags & (1 << MLX4_RSS_QPC_FLAG_OFFSET)) {
  3885. spin_lock_irq(mlx4_tlock(dev));
  3886. continue;
  3887. }
  3888. port = (qp->sched_queue >> 6 & 1) + 1;
  3889. if (port != work->port) {
  3890. spin_lock_irq(mlx4_tlock(dev));
  3891. continue;
  3892. }
  3893. if (MLX4_QP_ST_RC == ((qp->qpc_flags >> 16) & 0xff))
  3894. upd_context->primary_addr_path_mask = cpu_to_be64(qp_path_mask);
  3895. else
  3896. upd_context->primary_addr_path_mask =
  3897. cpu_to_be64(qp_path_mask | qp_path_mask_vlan_ctrl);
  3898. if (work->vlan_id == MLX4_VGT) {
  3899. upd_context->qp_context.param3 = qp->param3;
  3900. upd_context->qp_context.pri_path.vlan_control = qp->vlan_control;
  3901. upd_context->qp_context.pri_path.fvl_rx = qp->fvl_rx;
  3902. upd_context->qp_context.pri_path.vlan_index = qp->vlan_index;
  3903. upd_context->qp_context.pri_path.fl = qp->pri_path_fl;
  3904. upd_context->qp_context.pri_path.feup = qp->feup;
  3905. upd_context->qp_context.pri_path.sched_queue =
  3906. qp->sched_queue;
  3907. } else {
  3908. upd_context->qp_context.param3 = qp->param3 & ~cpu_to_be32(MLX4_STRIP_VLAN);
  3909. upd_context->qp_context.pri_path.vlan_control = vlan_control;
  3910. upd_context->qp_context.pri_path.vlan_index = work->vlan_ix;
  3911. upd_context->qp_context.pri_path.fvl_rx =
  3912. qp->fvl_rx | MLX4_FVL_RX_FORCE_ETH_VLAN;
  3913. upd_context->qp_context.pri_path.fl =
  3914. qp->pri_path_fl | MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
  3915. upd_context->qp_context.pri_path.feup =
  3916. qp->feup | MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
  3917. upd_context->qp_context.pri_path.sched_queue =
  3918. qp->sched_queue & 0xC7;
  3919. upd_context->qp_context.pri_path.sched_queue |=
  3920. ((work->qos & 0x7) << 3);
  3921. }
  3922. err = mlx4_cmd(dev, mailbox->dma,
  3923. qp->local_qpn & 0xffffff,
  3924. 0, MLX4_CMD_UPDATE_QP,
  3925. MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
  3926. if (err) {
  3927. mlx4_info(dev, "UPDATE_QP failed for slave %d, "
  3928. "port %d, qpn %d (%d)\n",
  3929. work->slave, port, qp->local_qpn,
  3930. err);
  3931. errors++;
  3932. }
  3933. }
  3934. spin_lock_irq(mlx4_tlock(dev));
  3935. }
  3936. spin_unlock_irq(mlx4_tlock(dev));
  3937. mlx4_free_cmd_mailbox(dev, mailbox);
  3938. if (errors)
  3939. mlx4_err(dev, "%d UPDATE_QP failures for slave %d, port %d\n",
  3940. errors, work->slave, work->port);
  3941. /* unregister previous vlan_id if needed and we had no errors
  3942. * while updating the QPs
  3943. */
  3944. if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN && !errors &&
  3945. NO_INDX != work->orig_vlan_ix)
  3946. __mlx4_unregister_vlan(&work->priv->dev, work->port,
  3947. work->orig_vlan_id);
  3948. out:
  3949. kfree(work);
  3950. return;
  3951. }