fsl_mxc_udc.c 2.8 KB

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  1. /*
  2. * Copyright (C) 2009
  3. * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
  4. *
  5. * Description:
  6. * Helper routines for i.MX3x SoCs from Freescale, needed by the fsl_usb2_udc.c
  7. * driver to function correctly on these systems.
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. */
  14. #include <linux/clk.h>
  15. #include <linux/delay.h>
  16. #include <linux/err.h>
  17. #include <linux/fsl_devices.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/io.h>
  20. static struct clk *mxc_ahb_clk;
  21. static struct clk *mxc_per_clk;
  22. static struct clk *mxc_ipg_clk;
  23. /* workaround ENGcm09152 for i.MX35 */
  24. #define USBPHYCTRL_OTGBASE_OFFSET 0x608
  25. #define USBPHYCTRL_EVDO (1 << 23)
  26. int fsl_udc_clk_init(struct platform_device *pdev)
  27. {
  28. struct fsl_usb2_platform_data *pdata;
  29. unsigned long freq;
  30. int ret;
  31. pdata = pdev->dev.platform_data;
  32. mxc_ipg_clk = devm_clk_get(&pdev->dev, "ipg");
  33. if (IS_ERR(mxc_ipg_clk)) {
  34. dev_err(&pdev->dev, "clk_get(\"ipg\") failed\n");
  35. return PTR_ERR(mxc_ipg_clk);
  36. }
  37. mxc_ahb_clk = devm_clk_get(&pdev->dev, "ahb");
  38. if (IS_ERR(mxc_ahb_clk)) {
  39. dev_err(&pdev->dev, "clk_get(\"ahb\") failed\n");
  40. return PTR_ERR(mxc_ahb_clk);
  41. }
  42. mxc_per_clk = devm_clk_get(&pdev->dev, "per");
  43. if (IS_ERR(mxc_per_clk)) {
  44. dev_err(&pdev->dev, "clk_get(\"per\") failed\n");
  45. return PTR_ERR(mxc_per_clk);
  46. }
  47. clk_prepare_enable(mxc_ipg_clk);
  48. clk_prepare_enable(mxc_ahb_clk);
  49. clk_prepare_enable(mxc_per_clk);
  50. /* make sure USB_CLK is running at 60 MHz +/- 1000 Hz */
  51. if (!strcmp(pdev->id_entry->name, "imx-udc-mx27")) {
  52. freq = clk_get_rate(mxc_per_clk);
  53. if (pdata->phy_mode != FSL_USB2_PHY_ULPI &&
  54. (freq < 59999000 || freq > 60001000)) {
  55. dev_err(&pdev->dev, "USB_CLK=%lu, should be 60MHz\n", freq);
  56. ret = -EINVAL;
  57. goto eclkrate;
  58. }
  59. }
  60. return 0;
  61. eclkrate:
  62. clk_disable_unprepare(mxc_ipg_clk);
  63. clk_disable_unprepare(mxc_ahb_clk);
  64. clk_disable_unprepare(mxc_per_clk);
  65. mxc_per_clk = NULL;
  66. return ret;
  67. }
  68. void fsl_udc_clk_finalize(struct platform_device *pdev)
  69. {
  70. struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
  71. unsigned int v;
  72. /* workaround ENGcm09152 for i.MX35 */
  73. if (pdata->workaround & FLS_USB2_WORKAROUND_ENGCM09152) {
  74. v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
  75. USBPHYCTRL_OTGBASE_OFFSET));
  76. writel(v | USBPHYCTRL_EVDO,
  77. MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
  78. USBPHYCTRL_OTGBASE_OFFSET));
  79. }
  80. /* ULPI transceivers don't need usbpll */
  81. if (pdata->phy_mode == FSL_USB2_PHY_ULPI) {
  82. clk_disable_unprepare(mxc_per_clk);
  83. mxc_per_clk = NULL;
  84. }
  85. }
  86. void fsl_udc_clk_release(void)
  87. {
  88. if (mxc_per_clk)
  89. clk_disable_unprepare(mxc_per_clk);
  90. clk_disable_unprepare(mxc_ahb_clk);
  91. clk_disable_unprepare(mxc_ipg_clk);
  92. }