mpc832x_mds.dts 7.6 KB

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  1. /*
  2. * MPC8323E EMDS Device Tree Source
  3. *
  4. * Copyright 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. / {
  12. model = "MPC8323EMDS";
  13. compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. cpus {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. PowerPC,8323@0 {
  20. device_type = "cpu";
  21. reg = <0>;
  22. d-cache-line-size = <20>; // 32 bytes
  23. i-cache-line-size = <20>; // 32 bytes
  24. d-cache-size = <4000>; // L1, 16K
  25. i-cache-size = <4000>; // L1, 16K
  26. timebase-frequency = <0>;
  27. bus-frequency = <0>;
  28. clock-frequency = <0>;
  29. };
  30. };
  31. memory {
  32. device_type = "memory";
  33. reg = <00000000 08000000>;
  34. };
  35. bcsr@f8000000 {
  36. device_type = "board-control";
  37. reg = <f8000000 8000>;
  38. };
  39. soc8323@e0000000 {
  40. #address-cells = <1>;
  41. #size-cells = <1>;
  42. device_type = "soc";
  43. ranges = <0 e0000000 00100000>;
  44. reg = <e0000000 00000200>;
  45. bus-frequency = <7DE2900>;
  46. wdt@200 {
  47. device_type = "watchdog";
  48. compatible = "mpc83xx_wdt";
  49. reg = <200 100>;
  50. };
  51. i2c@3000 {
  52. device_type = "i2c";
  53. compatible = "fsl-i2c";
  54. reg = <3000 100>;
  55. interrupts = <e 8>;
  56. interrupt-parent = < &ipic >;
  57. dfsrr;
  58. };
  59. serial@4500 {
  60. device_type = "serial";
  61. compatible = "ns16550";
  62. reg = <4500 100>;
  63. clock-frequency = <0>;
  64. interrupts = <9 8>;
  65. interrupt-parent = < &ipic >;
  66. };
  67. serial@4600 {
  68. device_type = "serial";
  69. compatible = "ns16550";
  70. reg = <4600 100>;
  71. clock-frequency = <0>;
  72. interrupts = <a 8>;
  73. interrupt-parent = < &ipic >;
  74. };
  75. crypto@30000 {
  76. device_type = "crypto";
  77. model = "SEC2";
  78. compatible = "talitos";
  79. reg = <30000 7000>;
  80. interrupts = <b 8>;
  81. interrupt-parent = < &ipic >;
  82. /* Rev. 2.2 */
  83. num-channels = <1>;
  84. channel-fifo-len = <18>;
  85. exec-units-mask = <0000004c>;
  86. descriptor-types-mask = <0122003f>;
  87. };
  88. pci@8500 {
  89. interrupt-map-mask = <f800 0 0 7>;
  90. interrupt-map = <
  91. /* IDSEL 0x11 AD17 */
  92. 8800 0 0 1 &ipic 14 8
  93. 8800 0 0 2 &ipic 15 8
  94. 8800 0 0 3 &ipic 16 8
  95. 8800 0 0 4 &ipic 17 8
  96. /* IDSEL 0x12 AD18 */
  97. 9000 0 0 1 &ipic 16 8
  98. 9000 0 0 2 &ipic 17 8
  99. 9000 0 0 3 &ipic 14 8
  100. 9000 0 0 4 &ipic 15 8
  101. /* IDSEL 0x13 AD19 */
  102. 9800 0 0 1 &ipic 17 8
  103. 9800 0 0 2 &ipic 14 8
  104. 9800 0 0 3 &ipic 15 8
  105. 9800 0 0 4 &ipic 16 8
  106. /* IDSEL 0x15 AD21*/
  107. a800 0 0 1 &ipic 14 8
  108. a800 0 0 2 &ipic 15 8
  109. a800 0 0 3 &ipic 16 8
  110. a800 0 0 4 &ipic 17 8
  111. /* IDSEL 0x16 AD22*/
  112. b000 0 0 1 &ipic 17 8
  113. b000 0 0 2 &ipic 14 8
  114. b000 0 0 3 &ipic 15 8
  115. b000 0 0 4 &ipic 16 8
  116. /* IDSEL 0x17 AD23*/
  117. b800 0 0 1 &ipic 16 8
  118. b800 0 0 2 &ipic 17 8
  119. b800 0 0 3 &ipic 14 8
  120. b800 0 0 4 &ipic 15 8
  121. /* IDSEL 0x18 AD24*/
  122. c000 0 0 1 &ipic 15 8
  123. c000 0 0 2 &ipic 16 8
  124. c000 0 0 3 &ipic 17 8
  125. c000 0 0 4 &ipic 14 8>;
  126. interrupt-parent = < &ipic >;
  127. interrupts = <42 8>;
  128. bus-range = <0 0>;
  129. ranges = <02000000 0 90000000 90000000 0 10000000
  130. 42000000 0 80000000 80000000 0 10000000
  131. 01000000 0 00000000 d0000000 0 00100000>;
  132. clock-frequency = <0>;
  133. #interrupt-cells = <1>;
  134. #size-cells = <2>;
  135. #address-cells = <3>;
  136. reg = <8500 100>;
  137. compatible = "fsl,mpc8349-pci";
  138. device_type = "pci";
  139. };
  140. ipic: pic@700 {
  141. interrupt-controller;
  142. #address-cells = <0>;
  143. #interrupt-cells = <2>;
  144. reg = <700 100>;
  145. device_type = "ipic";
  146. };
  147. par_io@1400 {
  148. reg = <1400 100>;
  149. device_type = "par_io";
  150. num-ports = <7>;
  151. pio3: ucc_pin@03 {
  152. pio-map = <
  153. /* port pin dir open_drain assignment has_irq */
  154. 3 4 3 0 2 0 /* MDIO */
  155. 3 5 1 0 2 0 /* MDC */
  156. 0 d 2 0 1 0 /* RX_CLK (CLK9) */
  157. 3 18 2 0 1 0 /* TX_CLK (CLK10) */
  158. 1 1 1 0 1 0 /* TxD1 */
  159. 1 0 1 0 1 0 /* TxD0 */
  160. 1 1 1 0 1 0 /* TxD1 */
  161. 1 2 1 0 1 0 /* TxD2 */
  162. 1 3 1 0 1 0 /* TxD3 */
  163. 1 4 2 0 1 0 /* RxD0 */
  164. 1 5 2 0 1 0 /* RxD1 */
  165. 1 6 2 0 1 0 /* RxD2 */
  166. 1 7 2 0 1 0 /* RxD3 */
  167. 1 8 2 0 1 0 /* RX_ER */
  168. 1 9 1 0 1 0 /* TX_ER */
  169. 1 a 2 0 1 0 /* RX_DV */
  170. 1 b 2 0 1 0 /* COL */
  171. 1 c 1 0 1 0 /* TX_EN */
  172. 1 d 2 0 1 0>;/* CRS */
  173. };
  174. pio4: ucc_pin@04 {
  175. pio-map = <
  176. /* port pin dir open_drain assignment has_irq */
  177. 3 1f 2 0 1 0 /* RX_CLK (CLK7) */
  178. 3 6 2 0 1 0 /* TX_CLK (CLK8) */
  179. 1 12 1 0 1 0 /* TxD0 */
  180. 1 13 1 0 1 0 /* TxD1 */
  181. 1 14 1 0 1 0 /* TxD2 */
  182. 1 15 1 0 1 0 /* TxD3 */
  183. 1 16 2 0 1 0 /* RxD0 */
  184. 1 17 2 0 1 0 /* RxD1 */
  185. 1 18 2 0 1 0 /* RxD2 */
  186. 1 19 2 0 1 0 /* RxD3 */
  187. 1 1a 2 0 1 0 /* RX_ER */
  188. 1 1b 1 0 1 0 /* TX_ER */
  189. 1 1c 2 0 1 0 /* RX_DV */
  190. 1 1d 2 0 1 0 /* COL */
  191. 1 1e 1 0 1 0 /* TX_EN */
  192. 1 1f 2 0 1 0>;/* CRS */
  193. };
  194. };
  195. };
  196. qe@e0100000 {
  197. #address-cells = <1>;
  198. #size-cells = <1>;
  199. device_type = "qe";
  200. model = "QE";
  201. ranges = <0 e0100000 00100000>;
  202. reg = <e0100000 480>;
  203. brg-frequency = <0>;
  204. bus-frequency = <BCD3D80>;
  205. muram@10000 {
  206. device_type = "muram";
  207. ranges = <0 00010000 00004000>;
  208. data-only@0 {
  209. reg = <0 4000>;
  210. };
  211. };
  212. spi@4c0 {
  213. device_type = "spi";
  214. compatible = "fsl_spi";
  215. reg = <4c0 40>;
  216. interrupts = <2>;
  217. interrupt-parent = < &qeic >;
  218. mode = "cpu";
  219. };
  220. spi@500 {
  221. device_type = "spi";
  222. compatible = "fsl_spi";
  223. reg = <500 40>;
  224. interrupts = <1>;
  225. interrupt-parent = < &qeic >;
  226. mode = "cpu";
  227. };
  228. usb@6c0 {
  229. device_type = "usb";
  230. compatible = "qe_udc";
  231. reg = <6c0 40 8B00 100>;
  232. interrupts = <b>;
  233. interrupt-parent = < &qeic >;
  234. mode = "slave";
  235. };
  236. ucc@2200 {
  237. device_type = "network";
  238. compatible = "ucc_geth";
  239. model = "UCC";
  240. device-id = <3>;
  241. reg = <2200 200>;
  242. interrupts = <22>;
  243. interrupt-parent = < &qeic >;
  244. /*
  245. * mac-address is deprecated and will be removed
  246. * in 2.6.25. Only recent versions of
  247. * U-Boot support local-mac-address, however.
  248. */
  249. mac-address = [ 00 00 00 00 00 00 ];
  250. local-mac-address = [ 00 00 00 00 00 00 ];
  251. rx-clock = <19>;
  252. tx-clock = <1a>;
  253. phy-handle = < &phy3 >;
  254. pio-handle = < &pio3 >;
  255. };
  256. ucc@3200 {
  257. device_type = "network";
  258. compatible = "ucc_geth";
  259. model = "UCC";
  260. device-id = <4>;
  261. reg = <3000 200>;
  262. interrupts = <23>;
  263. interrupt-parent = < &qeic >;
  264. /*
  265. * mac-address is deprecated and will be removed
  266. * in 2.6.25. Only recent versions of
  267. * U-Boot support local-mac-address, however.
  268. */
  269. mac-address = [ 00 00 00 00 00 00 ];
  270. local-mac-address = [ 00 00 00 00 00 00 ];
  271. rx-clock = <17>;
  272. tx-clock = <18>;
  273. phy-handle = < &phy4 >;
  274. pio-handle = < &pio4 >;
  275. };
  276. mdio@2320 {
  277. #address-cells = <1>;
  278. #size-cells = <0>;
  279. reg = <2320 18>;
  280. device_type = "mdio";
  281. compatible = "ucc_geth_phy";
  282. phy3: ethernet-phy@03 {
  283. interrupt-parent = < &ipic >;
  284. interrupts = <11 8>;
  285. reg = <3>;
  286. device_type = "ethernet-phy";
  287. };
  288. phy4: ethernet-phy@04 {
  289. interrupt-parent = < &ipic >;
  290. interrupts = <12 8>;
  291. reg = <4>;
  292. device_type = "ethernet-phy";
  293. };
  294. };
  295. qeic: qeic@80 {
  296. interrupt-controller;
  297. device_type = "qeic";
  298. #address-cells = <0>;
  299. #interrupt-cells = <1>;
  300. reg = <80 80>;
  301. big-endian;
  302. interrupts = <20 8 21 8>; //high:32 low:33
  303. interrupt-parent = < &ipic >;
  304. };
  305. };
  306. };