vmwgfx_kms.c 49 KB

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  1. /**************************************************************************
  2. *
  3. * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
  4. * All Rights Reserved.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the
  8. * "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish,
  10. * distribute, sub license, and/or sell copies of the Software, and to
  11. * permit persons to whom the Software is furnished to do so, subject to
  12. * the following conditions:
  13. *
  14. * The above copyright notice and this permission notice (including the
  15. * next paragraph) shall be included in all copies or substantial portions
  16. * of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. *
  26. **************************************************************************/
  27. #include "vmwgfx_kms.h"
  28. /* Might need a hrtimer here? */
  29. #define VMWGFX_PRESENT_RATE ((HZ / 60 > 0) ? HZ / 60 : 1)
  30. void vmw_display_unit_cleanup(struct vmw_display_unit *du)
  31. {
  32. if (du->cursor_surface)
  33. vmw_surface_unreference(&du->cursor_surface);
  34. if (du->cursor_dmabuf)
  35. vmw_dmabuf_unreference(&du->cursor_dmabuf);
  36. drm_crtc_cleanup(&du->crtc);
  37. drm_encoder_cleanup(&du->encoder);
  38. drm_connector_cleanup(&du->connector);
  39. }
  40. /*
  41. * Display Unit Cursor functions
  42. */
  43. int vmw_cursor_update_image(struct vmw_private *dev_priv,
  44. u32 *image, u32 width, u32 height,
  45. u32 hotspotX, u32 hotspotY)
  46. {
  47. struct {
  48. u32 cmd;
  49. SVGAFifoCmdDefineAlphaCursor cursor;
  50. } *cmd;
  51. u32 image_size = width * height * 4;
  52. u32 cmd_size = sizeof(*cmd) + image_size;
  53. if (!image)
  54. return -EINVAL;
  55. cmd = vmw_fifo_reserve(dev_priv, cmd_size);
  56. if (unlikely(cmd == NULL)) {
  57. DRM_ERROR("Fifo reserve failed.\n");
  58. return -ENOMEM;
  59. }
  60. memset(cmd, 0, sizeof(*cmd));
  61. memcpy(&cmd[1], image, image_size);
  62. cmd->cmd = cpu_to_le32(SVGA_CMD_DEFINE_ALPHA_CURSOR);
  63. cmd->cursor.id = cpu_to_le32(0);
  64. cmd->cursor.width = cpu_to_le32(width);
  65. cmd->cursor.height = cpu_to_le32(height);
  66. cmd->cursor.hotspotX = cpu_to_le32(hotspotX);
  67. cmd->cursor.hotspotY = cpu_to_le32(hotspotY);
  68. vmw_fifo_commit(dev_priv, cmd_size);
  69. return 0;
  70. }
  71. void vmw_cursor_update_position(struct vmw_private *dev_priv,
  72. bool show, int x, int y)
  73. {
  74. __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  75. uint32_t count;
  76. iowrite32(show ? 1 : 0, fifo_mem + SVGA_FIFO_CURSOR_ON);
  77. iowrite32(x, fifo_mem + SVGA_FIFO_CURSOR_X);
  78. iowrite32(y, fifo_mem + SVGA_FIFO_CURSOR_Y);
  79. count = ioread32(fifo_mem + SVGA_FIFO_CURSOR_COUNT);
  80. iowrite32(++count, fifo_mem + SVGA_FIFO_CURSOR_COUNT);
  81. }
  82. int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
  83. uint32_t handle, uint32_t width, uint32_t height)
  84. {
  85. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  86. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  87. struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
  88. struct vmw_surface *surface = NULL;
  89. struct vmw_dma_buffer *dmabuf = NULL;
  90. int ret;
  91. if (handle) {
  92. ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
  93. handle, &surface);
  94. if (!ret) {
  95. if (!surface->snooper.image) {
  96. DRM_ERROR("surface not suitable for cursor\n");
  97. vmw_surface_unreference(&surface);
  98. return -EINVAL;
  99. }
  100. } else {
  101. ret = vmw_user_dmabuf_lookup(tfile,
  102. handle, &dmabuf);
  103. if (ret) {
  104. DRM_ERROR("failed to find surface or dmabuf: %i\n", ret);
  105. return -EINVAL;
  106. }
  107. }
  108. }
  109. /* takedown old cursor */
  110. if (du->cursor_surface) {
  111. du->cursor_surface->snooper.crtc = NULL;
  112. vmw_surface_unreference(&du->cursor_surface);
  113. }
  114. if (du->cursor_dmabuf)
  115. vmw_dmabuf_unreference(&du->cursor_dmabuf);
  116. /* setup new image */
  117. if (surface) {
  118. /* vmw_user_surface_lookup takes one reference */
  119. du->cursor_surface = surface;
  120. du->cursor_surface->snooper.crtc = crtc;
  121. du->cursor_age = du->cursor_surface->snooper.age;
  122. vmw_cursor_update_image(dev_priv, surface->snooper.image,
  123. 64, 64, du->hotspot_x, du->hotspot_y);
  124. } else if (dmabuf) {
  125. struct ttm_bo_kmap_obj map;
  126. unsigned long kmap_offset;
  127. unsigned long kmap_num;
  128. void *virtual;
  129. bool dummy;
  130. /* vmw_user_surface_lookup takes one reference */
  131. du->cursor_dmabuf = dmabuf;
  132. kmap_offset = 0;
  133. kmap_num = (64*64*4) >> PAGE_SHIFT;
  134. ret = ttm_bo_reserve(&dmabuf->base, true, false, false, 0);
  135. if (unlikely(ret != 0)) {
  136. DRM_ERROR("reserve failed\n");
  137. return -EINVAL;
  138. }
  139. ret = ttm_bo_kmap(&dmabuf->base, kmap_offset, kmap_num, &map);
  140. if (unlikely(ret != 0))
  141. goto err_unreserve;
  142. virtual = ttm_kmap_obj_virtual(&map, &dummy);
  143. vmw_cursor_update_image(dev_priv, virtual, 64, 64,
  144. du->hotspot_x, du->hotspot_y);
  145. ttm_bo_kunmap(&map);
  146. err_unreserve:
  147. ttm_bo_unreserve(&dmabuf->base);
  148. } else {
  149. vmw_cursor_update_position(dev_priv, false, 0, 0);
  150. return 0;
  151. }
  152. vmw_cursor_update_position(dev_priv, true,
  153. du->cursor_x + du->hotspot_x,
  154. du->cursor_y + du->hotspot_y);
  155. return 0;
  156. }
  157. int vmw_du_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  158. {
  159. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  160. struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
  161. bool shown = du->cursor_surface || du->cursor_dmabuf ? true : false;
  162. du->cursor_x = x + crtc->x;
  163. du->cursor_y = y + crtc->y;
  164. vmw_cursor_update_position(dev_priv, shown,
  165. du->cursor_x + du->hotspot_x,
  166. du->cursor_y + du->hotspot_y);
  167. return 0;
  168. }
  169. void vmw_kms_cursor_snoop(struct vmw_surface *srf,
  170. struct ttm_object_file *tfile,
  171. struct ttm_buffer_object *bo,
  172. SVGA3dCmdHeader *header)
  173. {
  174. struct ttm_bo_kmap_obj map;
  175. unsigned long kmap_offset;
  176. unsigned long kmap_num;
  177. SVGA3dCopyBox *box;
  178. unsigned box_count;
  179. void *virtual;
  180. bool dummy;
  181. struct vmw_dma_cmd {
  182. SVGA3dCmdHeader header;
  183. SVGA3dCmdSurfaceDMA dma;
  184. } *cmd;
  185. int i, ret;
  186. cmd = container_of(header, struct vmw_dma_cmd, header);
  187. /* No snooper installed */
  188. if (!srf->snooper.image)
  189. return;
  190. if (cmd->dma.host.face != 0 || cmd->dma.host.mipmap != 0) {
  191. DRM_ERROR("face and mipmap for cursors should never != 0\n");
  192. return;
  193. }
  194. if (cmd->header.size < 64) {
  195. DRM_ERROR("at least one full copy box must be given\n");
  196. return;
  197. }
  198. box = (SVGA3dCopyBox *)&cmd[1];
  199. box_count = (cmd->header.size - sizeof(SVGA3dCmdSurfaceDMA)) /
  200. sizeof(SVGA3dCopyBox);
  201. if (cmd->dma.guest.ptr.offset % PAGE_SIZE ||
  202. box->x != 0 || box->y != 0 || box->z != 0 ||
  203. box->srcx != 0 || box->srcy != 0 || box->srcz != 0 ||
  204. box->d != 1 || box_count != 1) {
  205. /* TODO handle none page aligned offsets */
  206. /* TODO handle more dst & src != 0 */
  207. /* TODO handle more then one copy */
  208. DRM_ERROR("Cant snoop dma request for cursor!\n");
  209. DRM_ERROR("(%u, %u, %u) (%u, %u, %u) (%ux%ux%u) %u %u\n",
  210. box->srcx, box->srcy, box->srcz,
  211. box->x, box->y, box->z,
  212. box->w, box->h, box->d, box_count,
  213. cmd->dma.guest.ptr.offset);
  214. return;
  215. }
  216. kmap_offset = cmd->dma.guest.ptr.offset >> PAGE_SHIFT;
  217. kmap_num = (64*64*4) >> PAGE_SHIFT;
  218. ret = ttm_bo_reserve(bo, true, false, false, 0);
  219. if (unlikely(ret != 0)) {
  220. DRM_ERROR("reserve failed\n");
  221. return;
  222. }
  223. ret = ttm_bo_kmap(bo, kmap_offset, kmap_num, &map);
  224. if (unlikely(ret != 0))
  225. goto err_unreserve;
  226. virtual = ttm_kmap_obj_virtual(&map, &dummy);
  227. if (box->w == 64 && cmd->dma.guest.pitch == 64*4) {
  228. memcpy(srf->snooper.image, virtual, 64*64*4);
  229. } else {
  230. /* Image is unsigned pointer. */
  231. for (i = 0; i < box->h; i++)
  232. memcpy(srf->snooper.image + i * 64,
  233. virtual + i * cmd->dma.guest.pitch,
  234. box->w * 4);
  235. }
  236. srf->snooper.age++;
  237. /* we can't call this function from this function since execbuf has
  238. * reserved fifo space.
  239. *
  240. * if (srf->snooper.crtc)
  241. * vmw_ldu_crtc_cursor_update_image(dev_priv,
  242. * srf->snooper.image, 64, 64,
  243. * du->hotspot_x, du->hotspot_y);
  244. */
  245. ttm_bo_kunmap(&map);
  246. err_unreserve:
  247. ttm_bo_unreserve(bo);
  248. }
  249. void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv)
  250. {
  251. struct drm_device *dev = dev_priv->dev;
  252. struct vmw_display_unit *du;
  253. struct drm_crtc *crtc;
  254. mutex_lock(&dev->mode_config.mutex);
  255. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  256. du = vmw_crtc_to_du(crtc);
  257. if (!du->cursor_surface ||
  258. du->cursor_age == du->cursor_surface->snooper.age)
  259. continue;
  260. du->cursor_age = du->cursor_surface->snooper.age;
  261. vmw_cursor_update_image(dev_priv,
  262. du->cursor_surface->snooper.image,
  263. 64, 64, du->hotspot_x, du->hotspot_y);
  264. }
  265. mutex_unlock(&dev->mode_config.mutex);
  266. }
  267. /*
  268. * Generic framebuffer code
  269. */
  270. int vmw_framebuffer_create_handle(struct drm_framebuffer *fb,
  271. struct drm_file *file_priv,
  272. unsigned int *handle)
  273. {
  274. if (handle)
  275. handle = 0;
  276. return 0;
  277. }
  278. /*
  279. * Surface framebuffer code
  280. */
  281. #define vmw_framebuffer_to_vfbs(x) \
  282. container_of(x, struct vmw_framebuffer_surface, base.base)
  283. struct vmw_framebuffer_surface {
  284. struct vmw_framebuffer base;
  285. struct vmw_surface *surface;
  286. struct vmw_dma_buffer *buffer;
  287. struct list_head head;
  288. struct drm_master *master;
  289. };
  290. void vmw_framebuffer_surface_destroy(struct drm_framebuffer *framebuffer)
  291. {
  292. struct vmw_framebuffer_surface *vfbs =
  293. vmw_framebuffer_to_vfbs(framebuffer);
  294. struct vmw_master *vmaster = vmw_master(vfbs->master);
  295. mutex_lock(&vmaster->fb_surf_mutex);
  296. list_del(&vfbs->head);
  297. mutex_unlock(&vmaster->fb_surf_mutex);
  298. drm_master_put(&vfbs->master);
  299. drm_framebuffer_cleanup(framebuffer);
  300. vmw_surface_unreference(&vfbs->surface);
  301. ttm_base_object_unref(&vfbs->base.user_obj);
  302. kfree(vfbs);
  303. }
  304. static int do_surface_dirty_sou(struct vmw_private *dev_priv,
  305. struct drm_file *file_priv,
  306. struct vmw_framebuffer *framebuffer,
  307. unsigned flags, unsigned color,
  308. struct drm_clip_rect *clips,
  309. unsigned num_clips, int inc)
  310. {
  311. struct drm_clip_rect *clips_ptr;
  312. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  313. struct drm_crtc *crtc;
  314. size_t fifo_size;
  315. int i, num_units;
  316. int ret = 0; /* silence warning */
  317. int left, right, top, bottom;
  318. struct {
  319. SVGA3dCmdHeader header;
  320. SVGA3dCmdBlitSurfaceToScreen body;
  321. } *cmd;
  322. SVGASignedRect *blits;
  323. num_units = 0;
  324. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list,
  325. head) {
  326. if (crtc->fb != &framebuffer->base)
  327. continue;
  328. units[num_units++] = vmw_crtc_to_du(crtc);
  329. }
  330. BUG_ON(!clips || !num_clips);
  331. fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
  332. cmd = kzalloc(fifo_size, GFP_KERNEL);
  333. if (unlikely(cmd == NULL)) {
  334. DRM_ERROR("Temporary fifo memory alloc failed.\n");
  335. return -ENOMEM;
  336. }
  337. left = clips->x1;
  338. right = clips->x2;
  339. top = clips->y1;
  340. bottom = clips->y2;
  341. /* skip the first clip rect */
  342. for (i = 1, clips_ptr = clips + inc;
  343. i < num_clips; i++, clips_ptr += inc) {
  344. left = min_t(int, left, (int)clips_ptr->x1);
  345. right = max_t(int, right, (int)clips_ptr->x2);
  346. top = min_t(int, top, (int)clips_ptr->y1);
  347. bottom = max_t(int, bottom, (int)clips_ptr->y2);
  348. }
  349. /* only need to do this once */
  350. memset(cmd, 0, fifo_size);
  351. cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
  352. cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
  353. cmd->body.srcRect.left = left;
  354. cmd->body.srcRect.right = right;
  355. cmd->body.srcRect.top = top;
  356. cmd->body.srcRect.bottom = bottom;
  357. clips_ptr = clips;
  358. blits = (SVGASignedRect *)&cmd[1];
  359. for (i = 0; i < num_clips; i++, clips_ptr += inc) {
  360. blits[i].left = clips_ptr->x1 - left;
  361. blits[i].right = clips_ptr->x2 - left;
  362. blits[i].top = clips_ptr->y1 - top;
  363. blits[i].bottom = clips_ptr->y2 - top;
  364. }
  365. /* do per unit writing, reuse fifo for each */
  366. for (i = 0; i < num_units; i++) {
  367. struct vmw_display_unit *unit = units[i];
  368. int clip_x1 = left - unit->crtc.x;
  369. int clip_y1 = top - unit->crtc.y;
  370. int clip_x2 = right - unit->crtc.x;
  371. int clip_y2 = bottom - unit->crtc.y;
  372. /* skip any crtcs that misses the clip region */
  373. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  374. clip_y1 >= unit->crtc.mode.vdisplay ||
  375. clip_x2 <= 0 || clip_y2 <= 0)
  376. continue;
  377. /* need to reset sid as it is changed by execbuf */
  378. cmd->body.srcImage.sid = cpu_to_le32(framebuffer->user_handle);
  379. cmd->body.destScreenId = unit->unit;
  380. /*
  381. * The blit command is a lot more resilient then the
  382. * readback command when it comes to clip rects. So its
  383. * okay to go out of bounds.
  384. */
  385. cmd->body.destRect.left = clip_x1;
  386. cmd->body.destRect.right = clip_x2;
  387. cmd->body.destRect.top = clip_y1;
  388. cmd->body.destRect.bottom = clip_y2;
  389. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  390. fifo_size, 0, NULL);
  391. if (unlikely(ret != 0))
  392. break;
  393. }
  394. kfree(cmd);
  395. return ret;
  396. }
  397. int vmw_framebuffer_surface_dirty(struct drm_framebuffer *framebuffer,
  398. struct drm_file *file_priv,
  399. unsigned flags, unsigned color,
  400. struct drm_clip_rect *clips,
  401. unsigned num_clips)
  402. {
  403. struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
  404. struct vmw_master *vmaster = vmw_master(file_priv->master);
  405. struct vmw_framebuffer_surface *vfbs =
  406. vmw_framebuffer_to_vfbs(framebuffer);
  407. struct drm_clip_rect norect;
  408. int ret, inc = 1;
  409. if (unlikely(vfbs->master != file_priv->master))
  410. return -EINVAL;
  411. /* Require ScreenObject support for 3D */
  412. if (!dev_priv->sou_priv)
  413. return -EINVAL;
  414. ret = ttm_read_lock(&vmaster->lock, true);
  415. if (unlikely(ret != 0))
  416. return ret;
  417. if (!num_clips) {
  418. num_clips = 1;
  419. clips = &norect;
  420. norect.x1 = norect.y1 = 0;
  421. norect.x2 = framebuffer->width;
  422. norect.y2 = framebuffer->height;
  423. } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
  424. num_clips /= 2;
  425. inc = 2; /* skip source rects */
  426. }
  427. ret = do_surface_dirty_sou(dev_priv, file_priv, &vfbs->base,
  428. flags, color,
  429. clips, num_clips, inc);
  430. ttm_read_unlock(&vmaster->lock);
  431. return 0;
  432. }
  433. static struct drm_framebuffer_funcs vmw_framebuffer_surface_funcs = {
  434. .destroy = vmw_framebuffer_surface_destroy,
  435. .dirty = vmw_framebuffer_surface_dirty,
  436. .create_handle = vmw_framebuffer_create_handle,
  437. };
  438. static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv,
  439. struct drm_file *file_priv,
  440. struct vmw_surface *surface,
  441. struct vmw_framebuffer **out,
  442. const struct drm_mode_fb_cmd
  443. *mode_cmd)
  444. {
  445. struct drm_device *dev = dev_priv->dev;
  446. struct vmw_framebuffer_surface *vfbs;
  447. enum SVGA3dSurfaceFormat format;
  448. struct vmw_master *vmaster = vmw_master(file_priv->master);
  449. int ret;
  450. /* 3D is only supported on HWv8 hosts which supports screen objects */
  451. if (!dev_priv->sou_priv)
  452. return -ENOSYS;
  453. /*
  454. * Sanity checks.
  455. */
  456. if (unlikely(surface->mip_levels[0] != 1 ||
  457. surface->num_sizes != 1 ||
  458. surface->sizes[0].width < mode_cmd->width ||
  459. surface->sizes[0].height < mode_cmd->height ||
  460. surface->sizes[0].depth != 1)) {
  461. DRM_ERROR("Incompatible surface dimensions "
  462. "for requested mode.\n");
  463. return -EINVAL;
  464. }
  465. switch (mode_cmd->depth) {
  466. case 32:
  467. format = SVGA3D_A8R8G8B8;
  468. break;
  469. case 24:
  470. format = SVGA3D_X8R8G8B8;
  471. break;
  472. case 16:
  473. format = SVGA3D_R5G6B5;
  474. break;
  475. case 15:
  476. format = SVGA3D_A1R5G5B5;
  477. break;
  478. case 8:
  479. format = SVGA3D_LUMINANCE8;
  480. break;
  481. default:
  482. DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
  483. return -EINVAL;
  484. }
  485. if (unlikely(format != surface->format)) {
  486. DRM_ERROR("Invalid surface format for requested mode.\n");
  487. return -EINVAL;
  488. }
  489. vfbs = kzalloc(sizeof(*vfbs), GFP_KERNEL);
  490. if (!vfbs) {
  491. ret = -ENOMEM;
  492. goto out_err1;
  493. }
  494. ret = drm_framebuffer_init(dev, &vfbs->base.base,
  495. &vmw_framebuffer_surface_funcs);
  496. if (ret)
  497. goto out_err2;
  498. if (!vmw_surface_reference(surface)) {
  499. DRM_ERROR("failed to reference surface %p\n", surface);
  500. goto out_err3;
  501. }
  502. /* XXX get the first 3 from the surface info */
  503. vfbs->base.base.bits_per_pixel = mode_cmd->bpp;
  504. vfbs->base.base.pitch = mode_cmd->pitch;
  505. vfbs->base.base.depth = mode_cmd->depth;
  506. vfbs->base.base.width = mode_cmd->width;
  507. vfbs->base.base.height = mode_cmd->height;
  508. vfbs->surface = surface;
  509. vfbs->base.user_handle = mode_cmd->handle;
  510. vfbs->master = drm_master_get(file_priv->master);
  511. mutex_lock(&vmaster->fb_surf_mutex);
  512. list_add_tail(&vfbs->head, &vmaster->fb_surf);
  513. mutex_unlock(&vmaster->fb_surf_mutex);
  514. *out = &vfbs->base;
  515. return 0;
  516. out_err3:
  517. drm_framebuffer_cleanup(&vfbs->base.base);
  518. out_err2:
  519. kfree(vfbs);
  520. out_err1:
  521. return ret;
  522. }
  523. /*
  524. * Dmabuf framebuffer code
  525. */
  526. #define vmw_framebuffer_to_vfbd(x) \
  527. container_of(x, struct vmw_framebuffer_dmabuf, base.base)
  528. struct vmw_framebuffer_dmabuf {
  529. struct vmw_framebuffer base;
  530. struct vmw_dma_buffer *buffer;
  531. };
  532. void vmw_framebuffer_dmabuf_destroy(struct drm_framebuffer *framebuffer)
  533. {
  534. struct vmw_framebuffer_dmabuf *vfbd =
  535. vmw_framebuffer_to_vfbd(framebuffer);
  536. drm_framebuffer_cleanup(framebuffer);
  537. vmw_dmabuf_unreference(&vfbd->buffer);
  538. ttm_base_object_unref(&vfbd->base.user_obj);
  539. kfree(vfbd);
  540. }
  541. static int do_dmabuf_dirty_ldu(struct vmw_private *dev_priv,
  542. struct vmw_framebuffer *framebuffer,
  543. unsigned flags, unsigned color,
  544. struct drm_clip_rect *clips,
  545. unsigned num_clips, int increment)
  546. {
  547. size_t fifo_size;
  548. int i;
  549. struct {
  550. uint32_t header;
  551. SVGAFifoCmdUpdate body;
  552. } *cmd;
  553. fifo_size = sizeof(*cmd) * num_clips;
  554. cmd = vmw_fifo_reserve(dev_priv, fifo_size);
  555. if (unlikely(cmd == NULL)) {
  556. DRM_ERROR("Fifo reserve failed.\n");
  557. return -ENOMEM;
  558. }
  559. memset(cmd, 0, fifo_size);
  560. for (i = 0; i < num_clips; i++, clips += increment) {
  561. cmd[i].header = cpu_to_le32(SVGA_CMD_UPDATE);
  562. cmd[i].body.x = cpu_to_le32(clips->x1);
  563. cmd[i].body.y = cpu_to_le32(clips->y1);
  564. cmd[i].body.width = cpu_to_le32(clips->x2 - clips->x1);
  565. cmd[i].body.height = cpu_to_le32(clips->y2 - clips->y1);
  566. }
  567. vmw_fifo_commit(dev_priv, fifo_size);
  568. return 0;
  569. }
  570. static int do_dmabuf_define_gmrfb(struct drm_file *file_priv,
  571. struct vmw_private *dev_priv,
  572. struct vmw_framebuffer *framebuffer)
  573. {
  574. int depth = framebuffer->base.depth;
  575. size_t fifo_size;
  576. int ret;
  577. struct {
  578. uint32_t header;
  579. SVGAFifoCmdDefineGMRFB body;
  580. } *cmd;
  581. /* Emulate RGBA support, contrary to svga_reg.h this is not
  582. * supported by hosts. This is only a problem if we are reading
  583. * this value later and expecting what we uploaded back.
  584. */
  585. if (depth == 32)
  586. depth = 24;
  587. fifo_size = sizeof(*cmd);
  588. cmd = kmalloc(fifo_size, GFP_KERNEL);
  589. if (unlikely(cmd == NULL)) {
  590. DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
  591. return -ENOMEM;
  592. }
  593. memset(cmd, 0, fifo_size);
  594. cmd->header = SVGA_CMD_DEFINE_GMRFB;
  595. cmd->body.format.bitsPerPixel = framebuffer->base.bits_per_pixel;
  596. cmd->body.format.colorDepth = depth;
  597. cmd->body.format.reserved = 0;
  598. cmd->body.bytesPerLine = framebuffer->base.pitch;
  599. cmd->body.ptr.gmrId = framebuffer->user_handle;
  600. cmd->body.ptr.offset = 0;
  601. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  602. fifo_size, 0, NULL);
  603. kfree(cmd);
  604. return ret;
  605. }
  606. static int do_dmabuf_dirty_sou(struct drm_file *file_priv,
  607. struct vmw_private *dev_priv,
  608. struct vmw_framebuffer *framebuffer,
  609. unsigned flags, unsigned color,
  610. struct drm_clip_rect *clips,
  611. unsigned num_clips, int increment)
  612. {
  613. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  614. struct drm_clip_rect *clips_ptr;
  615. int i, k, num_units, ret;
  616. struct drm_crtc *crtc;
  617. size_t fifo_size;
  618. struct {
  619. uint32_t header;
  620. SVGAFifoCmdBlitGMRFBToScreen body;
  621. } *blits;
  622. ret = do_dmabuf_define_gmrfb(file_priv, dev_priv, framebuffer);
  623. if (unlikely(ret != 0))
  624. return ret; /* define_gmrfb prints warnings */
  625. fifo_size = sizeof(*blits) * num_clips;
  626. blits = kmalloc(fifo_size, GFP_KERNEL);
  627. if (unlikely(blits == NULL)) {
  628. DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
  629. return -ENOMEM;
  630. }
  631. num_units = 0;
  632. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  633. if (crtc->fb != &framebuffer->base)
  634. continue;
  635. units[num_units++] = vmw_crtc_to_du(crtc);
  636. }
  637. for (k = 0; k < num_units; k++) {
  638. struct vmw_display_unit *unit = units[k];
  639. int hit_num = 0;
  640. clips_ptr = clips;
  641. for (i = 0; i < num_clips; i++, clips_ptr += increment) {
  642. int clip_x1 = clips_ptr->x1 - unit->crtc.x;
  643. int clip_y1 = clips_ptr->y1 - unit->crtc.y;
  644. int clip_x2 = clips_ptr->x2 - unit->crtc.x;
  645. int clip_y2 = clips_ptr->y2 - unit->crtc.y;
  646. /* skip any crtcs that misses the clip region */
  647. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  648. clip_y1 >= unit->crtc.mode.vdisplay ||
  649. clip_x2 <= 0 || clip_y2 <= 0)
  650. continue;
  651. blits[hit_num].header = SVGA_CMD_BLIT_GMRFB_TO_SCREEN;
  652. blits[hit_num].body.destScreenId = unit->unit;
  653. blits[hit_num].body.srcOrigin.x = clips_ptr->x1;
  654. blits[hit_num].body.srcOrigin.y = clips_ptr->y1;
  655. blits[hit_num].body.destRect.left = clip_x1;
  656. blits[hit_num].body.destRect.top = clip_y1;
  657. blits[hit_num].body.destRect.right = clip_x2;
  658. blits[hit_num].body.destRect.bottom = clip_y2;
  659. hit_num++;
  660. }
  661. /* no clips hit the crtc */
  662. if (hit_num == 0)
  663. continue;
  664. fifo_size = sizeof(*blits) * hit_num;
  665. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, blits,
  666. fifo_size, 0, NULL);
  667. if (unlikely(ret != 0))
  668. break;
  669. }
  670. kfree(blits);
  671. return ret;
  672. }
  673. int vmw_framebuffer_dmabuf_dirty(struct drm_framebuffer *framebuffer,
  674. struct drm_file *file_priv,
  675. unsigned flags, unsigned color,
  676. struct drm_clip_rect *clips,
  677. unsigned num_clips)
  678. {
  679. struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
  680. struct vmw_master *vmaster = vmw_master(file_priv->master);
  681. struct vmw_framebuffer_dmabuf *vfbd =
  682. vmw_framebuffer_to_vfbd(framebuffer);
  683. struct drm_clip_rect norect;
  684. int ret, increment = 1;
  685. ret = ttm_read_lock(&vmaster->lock, true);
  686. if (unlikely(ret != 0))
  687. return ret;
  688. if (!num_clips) {
  689. num_clips = 1;
  690. clips = &norect;
  691. norect.x1 = norect.y1 = 0;
  692. norect.x2 = framebuffer->width;
  693. norect.y2 = framebuffer->height;
  694. } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
  695. num_clips /= 2;
  696. increment = 2;
  697. }
  698. if (dev_priv->ldu_priv) {
  699. ret = do_dmabuf_dirty_ldu(dev_priv, &vfbd->base,
  700. flags, color,
  701. clips, num_clips, increment);
  702. } else {
  703. ret = do_dmabuf_dirty_sou(file_priv, dev_priv, &vfbd->base,
  704. flags, color,
  705. clips, num_clips, increment);
  706. }
  707. ttm_read_unlock(&vmaster->lock);
  708. return ret;
  709. }
  710. static struct drm_framebuffer_funcs vmw_framebuffer_dmabuf_funcs = {
  711. .destroy = vmw_framebuffer_dmabuf_destroy,
  712. .dirty = vmw_framebuffer_dmabuf_dirty,
  713. .create_handle = vmw_framebuffer_create_handle,
  714. };
  715. /**
  716. * Pin the dmabuffer to the start of vram.
  717. */
  718. static int vmw_framebuffer_dmabuf_pin(struct vmw_framebuffer *vfb)
  719. {
  720. struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
  721. struct vmw_framebuffer_dmabuf *vfbd =
  722. vmw_framebuffer_to_vfbd(&vfb->base);
  723. int ret;
  724. /* This code should not be used with screen objects */
  725. BUG_ON(dev_priv->sou_priv);
  726. vmw_overlay_pause_all(dev_priv);
  727. ret = vmw_dmabuf_to_start_of_vram(dev_priv, vfbd->buffer, true, false);
  728. vmw_overlay_resume_all(dev_priv);
  729. WARN_ON(ret != 0);
  730. return 0;
  731. }
  732. static int vmw_framebuffer_dmabuf_unpin(struct vmw_framebuffer *vfb)
  733. {
  734. struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
  735. struct vmw_framebuffer_dmabuf *vfbd =
  736. vmw_framebuffer_to_vfbd(&vfb->base);
  737. if (!vfbd->buffer) {
  738. WARN_ON(!vfbd->buffer);
  739. return 0;
  740. }
  741. return vmw_dmabuf_unpin(dev_priv, vfbd->buffer, false);
  742. }
  743. static int vmw_kms_new_framebuffer_dmabuf(struct vmw_private *dev_priv,
  744. struct vmw_dma_buffer *dmabuf,
  745. struct vmw_framebuffer **out,
  746. const struct drm_mode_fb_cmd
  747. *mode_cmd)
  748. {
  749. struct drm_device *dev = dev_priv->dev;
  750. struct vmw_framebuffer_dmabuf *vfbd;
  751. unsigned int requested_size;
  752. int ret;
  753. requested_size = mode_cmd->height * mode_cmd->pitch;
  754. if (unlikely(requested_size > dmabuf->base.num_pages * PAGE_SIZE)) {
  755. DRM_ERROR("Screen buffer object size is too small "
  756. "for requested mode.\n");
  757. return -EINVAL;
  758. }
  759. /* Limited framebuffer color depth support for screen objects */
  760. if (dev_priv->sou_priv) {
  761. switch (mode_cmd->depth) {
  762. case 32:
  763. case 24:
  764. /* Only support 32 bpp for 32 and 24 depth fbs */
  765. if (mode_cmd->bpp == 32)
  766. break;
  767. DRM_ERROR("Invalid color depth/bbp: %d %d\n",
  768. mode_cmd->depth, mode_cmd->bpp);
  769. return -EINVAL;
  770. case 16:
  771. case 15:
  772. /* Only support 16 bpp for 16 and 15 depth fbs */
  773. if (mode_cmd->bpp == 16)
  774. break;
  775. DRM_ERROR("Invalid color depth/bbp: %d %d\n",
  776. mode_cmd->depth, mode_cmd->bpp);
  777. return -EINVAL;
  778. default:
  779. DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
  780. return -EINVAL;
  781. }
  782. }
  783. vfbd = kzalloc(sizeof(*vfbd), GFP_KERNEL);
  784. if (!vfbd) {
  785. ret = -ENOMEM;
  786. goto out_err1;
  787. }
  788. ret = drm_framebuffer_init(dev, &vfbd->base.base,
  789. &vmw_framebuffer_dmabuf_funcs);
  790. if (ret)
  791. goto out_err2;
  792. if (!vmw_dmabuf_reference(dmabuf)) {
  793. DRM_ERROR("failed to reference dmabuf %p\n", dmabuf);
  794. goto out_err3;
  795. }
  796. vfbd->base.base.bits_per_pixel = mode_cmd->bpp;
  797. vfbd->base.base.pitch = mode_cmd->pitch;
  798. vfbd->base.base.depth = mode_cmd->depth;
  799. vfbd->base.base.width = mode_cmd->width;
  800. vfbd->base.base.height = mode_cmd->height;
  801. if (!dev_priv->sou_priv) {
  802. vfbd->base.pin = vmw_framebuffer_dmabuf_pin;
  803. vfbd->base.unpin = vmw_framebuffer_dmabuf_unpin;
  804. }
  805. vfbd->base.dmabuf = true;
  806. vfbd->buffer = dmabuf;
  807. vfbd->base.user_handle = mode_cmd->handle;
  808. *out = &vfbd->base;
  809. return 0;
  810. out_err3:
  811. drm_framebuffer_cleanup(&vfbd->base.base);
  812. out_err2:
  813. kfree(vfbd);
  814. out_err1:
  815. return ret;
  816. }
  817. /*
  818. * Generic Kernel modesetting functions
  819. */
  820. static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev,
  821. struct drm_file *file_priv,
  822. struct drm_mode_fb_cmd *mode_cmd)
  823. {
  824. struct vmw_private *dev_priv = vmw_priv(dev);
  825. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  826. struct vmw_framebuffer *vfb = NULL;
  827. struct vmw_surface *surface = NULL;
  828. struct vmw_dma_buffer *bo = NULL;
  829. struct ttm_base_object *user_obj;
  830. u64 required_size;
  831. int ret;
  832. /**
  833. * This code should be conditioned on Screen Objects not being used.
  834. * If screen objects are used, we can allocate a GMR to hold the
  835. * requested framebuffer.
  836. */
  837. required_size = mode_cmd->pitch * mode_cmd->height;
  838. if (unlikely(required_size > (u64) dev_priv->vram_size)) {
  839. DRM_ERROR("VRAM size is too small for requested mode.\n");
  840. return ERR_PTR(-ENOMEM);
  841. }
  842. /*
  843. * Take a reference on the user object of the resource
  844. * backing the kms fb. This ensures that user-space handle
  845. * lookups on that resource will always work as long as
  846. * it's registered with a kms framebuffer. This is important,
  847. * since vmw_execbuf_process identifies resources in the
  848. * command stream using user-space handles.
  849. */
  850. user_obj = ttm_base_object_lookup(tfile, mode_cmd->handle);
  851. if (unlikely(user_obj == NULL)) {
  852. DRM_ERROR("Could not locate requested kms frame buffer.\n");
  853. return ERR_PTR(-ENOENT);
  854. }
  855. /**
  856. * End conditioned code.
  857. */
  858. ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
  859. mode_cmd->handle, &surface);
  860. if (ret)
  861. goto try_dmabuf;
  862. if (!surface->scanout)
  863. goto err_not_scanout;
  864. ret = vmw_kms_new_framebuffer_surface(dev_priv, file_priv, surface,
  865. &vfb, mode_cmd);
  866. /* vmw_user_surface_lookup takes one ref so does new_fb */
  867. vmw_surface_unreference(&surface);
  868. if (ret) {
  869. DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
  870. ttm_base_object_unref(&user_obj);
  871. return ERR_PTR(ret);
  872. } else
  873. vfb->user_obj = user_obj;
  874. return &vfb->base;
  875. try_dmabuf:
  876. DRM_INFO("%s: trying buffer\n", __func__);
  877. ret = vmw_user_dmabuf_lookup(tfile, mode_cmd->handle, &bo);
  878. if (ret) {
  879. DRM_ERROR("failed to find buffer: %i\n", ret);
  880. return ERR_PTR(-ENOENT);
  881. }
  882. ret = vmw_kms_new_framebuffer_dmabuf(dev_priv, bo, &vfb,
  883. mode_cmd);
  884. /* vmw_user_dmabuf_lookup takes one ref so does new_fb */
  885. vmw_dmabuf_unreference(&bo);
  886. if (ret) {
  887. DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
  888. ttm_base_object_unref(&user_obj);
  889. return ERR_PTR(ret);
  890. } else
  891. vfb->user_obj = user_obj;
  892. return &vfb->base;
  893. err_not_scanout:
  894. DRM_ERROR("surface not marked as scanout\n");
  895. /* vmw_user_surface_lookup takes one ref */
  896. vmw_surface_unreference(&surface);
  897. ttm_base_object_unref(&user_obj);
  898. return ERR_PTR(-EINVAL);
  899. }
  900. static struct drm_mode_config_funcs vmw_kms_funcs = {
  901. .fb_create = vmw_kms_fb_create,
  902. };
  903. int vmw_kms_present(struct vmw_private *dev_priv,
  904. struct drm_file *file_priv,
  905. struct vmw_framebuffer *vfb,
  906. struct vmw_surface *surface,
  907. uint32_t sid,
  908. int32_t destX, int32_t destY,
  909. struct drm_vmw_rect *clips,
  910. uint32_t num_clips)
  911. {
  912. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  913. struct drm_crtc *crtc;
  914. size_t fifo_size;
  915. int i, k, num_units;
  916. int ret = 0; /* silence warning */
  917. struct {
  918. SVGA3dCmdHeader header;
  919. SVGA3dCmdBlitSurfaceToScreen body;
  920. } *cmd;
  921. SVGASignedRect *blits;
  922. num_units = 0;
  923. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  924. if (crtc->fb != &vfb->base)
  925. continue;
  926. units[num_units++] = vmw_crtc_to_du(crtc);
  927. }
  928. BUG_ON(surface == NULL);
  929. BUG_ON(!clips || !num_clips);
  930. fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
  931. cmd = kmalloc(fifo_size, GFP_KERNEL);
  932. if (unlikely(cmd == NULL)) {
  933. DRM_ERROR("Failed to allocate temporary fifo memory.\n");
  934. return -ENOMEM;
  935. }
  936. /* only need to do this once */
  937. memset(cmd, 0, fifo_size);
  938. cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
  939. cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
  940. cmd->body.srcRect.left = 0;
  941. cmd->body.srcRect.right = surface->sizes[0].width;
  942. cmd->body.srcRect.top = 0;
  943. cmd->body.srcRect.bottom = surface->sizes[0].height;
  944. blits = (SVGASignedRect *)&cmd[1];
  945. for (i = 0; i < num_clips; i++) {
  946. blits[i].left = clips[i].x;
  947. blits[i].right = clips[i].x + clips[i].w;
  948. blits[i].top = clips[i].y;
  949. blits[i].bottom = clips[i].y + clips[i].h;
  950. }
  951. for (k = 0; k < num_units; k++) {
  952. struct vmw_display_unit *unit = units[k];
  953. int clip_x1 = destX - unit->crtc.x;
  954. int clip_y1 = destY - unit->crtc.y;
  955. int clip_x2 = clip_x1 + surface->sizes[0].width;
  956. int clip_y2 = clip_y1 + surface->sizes[0].height;
  957. /* skip any crtcs that misses the clip region */
  958. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  959. clip_y1 >= unit->crtc.mode.vdisplay ||
  960. clip_x2 <= 0 || clip_y2 <= 0)
  961. continue;
  962. /* need to reset sid as it is changed by execbuf */
  963. cmd->body.srcImage.sid = sid;
  964. cmd->body.destScreenId = unit->unit;
  965. /*
  966. * The blit command is a lot more resilient then the
  967. * readback command when it comes to clip rects. So its
  968. * okay to go out of bounds.
  969. */
  970. cmd->body.destRect.left = clip_x1;
  971. cmd->body.destRect.right = clip_x2;
  972. cmd->body.destRect.top = clip_y1;
  973. cmd->body.destRect.bottom = clip_y2;
  974. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  975. fifo_size, 0, NULL);
  976. if (unlikely(ret != 0))
  977. break;
  978. }
  979. kfree(cmd);
  980. return ret;
  981. }
  982. int vmw_kms_readback(struct vmw_private *dev_priv,
  983. struct drm_file *file_priv,
  984. struct vmw_framebuffer *vfb,
  985. struct drm_vmw_fence_rep __user *user_fence_rep,
  986. struct drm_vmw_rect *clips,
  987. uint32_t num_clips)
  988. {
  989. struct vmw_framebuffer_dmabuf *vfbd =
  990. vmw_framebuffer_to_vfbd(&vfb->base);
  991. struct vmw_dma_buffer *dmabuf = vfbd->buffer;
  992. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  993. struct drm_crtc *crtc;
  994. size_t fifo_size;
  995. int i, k, ret, num_units, blits_pos;
  996. struct {
  997. uint32_t header;
  998. SVGAFifoCmdDefineGMRFB body;
  999. } *cmd;
  1000. struct {
  1001. uint32_t header;
  1002. SVGAFifoCmdBlitScreenToGMRFB body;
  1003. } *blits;
  1004. num_units = 0;
  1005. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  1006. if (crtc->fb != &vfb->base)
  1007. continue;
  1008. units[num_units++] = vmw_crtc_to_du(crtc);
  1009. }
  1010. BUG_ON(dmabuf == NULL);
  1011. BUG_ON(!clips || !num_clips);
  1012. /* take a safe guess at fifo size */
  1013. fifo_size = sizeof(*cmd) + sizeof(*blits) * num_clips * num_units;
  1014. cmd = kmalloc(fifo_size, GFP_KERNEL);
  1015. if (unlikely(cmd == NULL)) {
  1016. DRM_ERROR("Failed to allocate temporary fifo memory.\n");
  1017. return -ENOMEM;
  1018. }
  1019. memset(cmd, 0, fifo_size);
  1020. cmd->header = SVGA_CMD_DEFINE_GMRFB;
  1021. cmd->body.format.bitsPerPixel = vfb->base.bits_per_pixel;
  1022. cmd->body.format.colorDepth = vfb->base.depth;
  1023. cmd->body.format.reserved = 0;
  1024. cmd->body.bytesPerLine = vfb->base.pitch;
  1025. cmd->body.ptr.gmrId = vfb->user_handle;
  1026. cmd->body.ptr.offset = 0;
  1027. blits = (void *)&cmd[1];
  1028. blits_pos = 0;
  1029. for (i = 0; i < num_units; i++) {
  1030. struct drm_vmw_rect *c = clips;
  1031. for (k = 0; k < num_clips; k++, c++) {
  1032. /* transform clip coords to crtc origin based coords */
  1033. int clip_x1 = c->x - units[i]->crtc.x;
  1034. int clip_x2 = c->x - units[i]->crtc.x + c->w;
  1035. int clip_y1 = c->y - units[i]->crtc.y;
  1036. int clip_y2 = c->y - units[i]->crtc.y + c->h;
  1037. int dest_x = c->x;
  1038. int dest_y = c->y;
  1039. /* compensate for clipping, we negate
  1040. * a negative number and add that.
  1041. */
  1042. if (clip_x1 < 0)
  1043. dest_x += -clip_x1;
  1044. if (clip_y1 < 0)
  1045. dest_y += -clip_y1;
  1046. /* clip */
  1047. clip_x1 = max(clip_x1, 0);
  1048. clip_y1 = max(clip_y1, 0);
  1049. clip_x2 = min(clip_x2, units[i]->crtc.mode.hdisplay);
  1050. clip_y2 = min(clip_y2, units[i]->crtc.mode.vdisplay);
  1051. /* and cull any rects that misses the crtc */
  1052. if (clip_x1 >= units[i]->crtc.mode.hdisplay ||
  1053. clip_y1 >= units[i]->crtc.mode.vdisplay ||
  1054. clip_x2 <= 0 || clip_y2 <= 0)
  1055. continue;
  1056. blits[blits_pos].header = SVGA_CMD_BLIT_SCREEN_TO_GMRFB;
  1057. blits[blits_pos].body.srcScreenId = units[i]->unit;
  1058. blits[blits_pos].body.destOrigin.x = dest_x;
  1059. blits[blits_pos].body.destOrigin.y = dest_y;
  1060. blits[blits_pos].body.srcRect.left = clip_x1;
  1061. blits[blits_pos].body.srcRect.top = clip_y1;
  1062. blits[blits_pos].body.srcRect.right = clip_x2;
  1063. blits[blits_pos].body.srcRect.bottom = clip_y2;
  1064. blits_pos++;
  1065. }
  1066. }
  1067. /* reset size here and use calculated exact size from loops */
  1068. fifo_size = sizeof(*cmd) + sizeof(*blits) * blits_pos;
  1069. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd, fifo_size,
  1070. 0, user_fence_rep);
  1071. kfree(cmd);
  1072. return ret;
  1073. }
  1074. int vmw_kms_init(struct vmw_private *dev_priv)
  1075. {
  1076. struct drm_device *dev = dev_priv->dev;
  1077. int ret;
  1078. drm_mode_config_init(dev);
  1079. dev->mode_config.funcs = &vmw_kms_funcs;
  1080. dev->mode_config.min_width = 1;
  1081. dev->mode_config.min_height = 1;
  1082. /* assumed largest fb size */
  1083. dev->mode_config.max_width = 8192;
  1084. dev->mode_config.max_height = 8192;
  1085. ret = vmw_kms_init_screen_object_display(dev_priv);
  1086. if (ret) /* Fallback */
  1087. (void)vmw_kms_init_legacy_display_system(dev_priv);
  1088. return 0;
  1089. }
  1090. int vmw_kms_close(struct vmw_private *dev_priv)
  1091. {
  1092. /*
  1093. * Docs says we should take the lock before calling this function
  1094. * but since it destroys encoders and our destructor calls
  1095. * drm_encoder_cleanup which takes the lock we deadlock.
  1096. */
  1097. drm_mode_config_cleanup(dev_priv->dev);
  1098. if (dev_priv->sou_priv)
  1099. vmw_kms_close_screen_object_display(dev_priv);
  1100. else
  1101. vmw_kms_close_legacy_display_system(dev_priv);
  1102. return 0;
  1103. }
  1104. int vmw_kms_cursor_bypass_ioctl(struct drm_device *dev, void *data,
  1105. struct drm_file *file_priv)
  1106. {
  1107. struct drm_vmw_cursor_bypass_arg *arg = data;
  1108. struct vmw_display_unit *du;
  1109. struct drm_mode_object *obj;
  1110. struct drm_crtc *crtc;
  1111. int ret = 0;
  1112. mutex_lock(&dev->mode_config.mutex);
  1113. if (arg->flags & DRM_VMW_CURSOR_BYPASS_ALL) {
  1114. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1115. du = vmw_crtc_to_du(crtc);
  1116. du->hotspot_x = arg->xhot;
  1117. du->hotspot_y = arg->yhot;
  1118. }
  1119. mutex_unlock(&dev->mode_config.mutex);
  1120. return 0;
  1121. }
  1122. obj = drm_mode_object_find(dev, arg->crtc_id, DRM_MODE_OBJECT_CRTC);
  1123. if (!obj) {
  1124. ret = -EINVAL;
  1125. goto out;
  1126. }
  1127. crtc = obj_to_crtc(obj);
  1128. du = vmw_crtc_to_du(crtc);
  1129. du->hotspot_x = arg->xhot;
  1130. du->hotspot_y = arg->yhot;
  1131. out:
  1132. mutex_unlock(&dev->mode_config.mutex);
  1133. return ret;
  1134. }
  1135. int vmw_kms_write_svga(struct vmw_private *vmw_priv,
  1136. unsigned width, unsigned height, unsigned pitch,
  1137. unsigned bpp, unsigned depth)
  1138. {
  1139. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1140. vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch);
  1141. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1142. iowrite32(pitch, vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
  1143. vmw_write(vmw_priv, SVGA_REG_WIDTH, width);
  1144. vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);
  1145. vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);
  1146. if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) {
  1147. DRM_ERROR("Invalid depth %u for %u bpp, host expects %u\n",
  1148. depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH));
  1149. return -EINVAL;
  1150. }
  1151. return 0;
  1152. }
  1153. int vmw_kms_save_vga(struct vmw_private *vmw_priv)
  1154. {
  1155. struct vmw_vga_topology_state *save;
  1156. uint32_t i;
  1157. vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH);
  1158. vmw_priv->vga_height = vmw_read(vmw_priv, SVGA_REG_HEIGHT);
  1159. vmw_priv->vga_bpp = vmw_read(vmw_priv, SVGA_REG_BITS_PER_PIXEL);
  1160. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1161. vmw_priv->vga_pitchlock =
  1162. vmw_read(vmw_priv, SVGA_REG_PITCHLOCK);
  1163. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1164. vmw_priv->vga_pitchlock = ioread32(vmw_priv->mmio_virt +
  1165. SVGA_FIFO_PITCHLOCK);
  1166. if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
  1167. return 0;
  1168. vmw_priv->num_displays = vmw_read(vmw_priv,
  1169. SVGA_REG_NUM_GUEST_DISPLAYS);
  1170. if (vmw_priv->num_displays == 0)
  1171. vmw_priv->num_displays = 1;
  1172. for (i = 0; i < vmw_priv->num_displays; ++i) {
  1173. save = &vmw_priv->vga_save[i];
  1174. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
  1175. save->primary = vmw_read(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY);
  1176. save->pos_x = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_X);
  1177. save->pos_y = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y);
  1178. save->width = vmw_read(vmw_priv, SVGA_REG_DISPLAY_WIDTH);
  1179. save->height = vmw_read(vmw_priv, SVGA_REG_DISPLAY_HEIGHT);
  1180. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
  1181. if (i == 0 && vmw_priv->num_displays == 1 &&
  1182. save->width == 0 && save->height == 0) {
  1183. /*
  1184. * It should be fairly safe to assume that these
  1185. * values are uninitialized.
  1186. */
  1187. save->width = vmw_priv->vga_width - save->pos_x;
  1188. save->height = vmw_priv->vga_height - save->pos_y;
  1189. }
  1190. }
  1191. return 0;
  1192. }
  1193. int vmw_kms_restore_vga(struct vmw_private *vmw_priv)
  1194. {
  1195. struct vmw_vga_topology_state *save;
  1196. uint32_t i;
  1197. vmw_write(vmw_priv, SVGA_REG_WIDTH, vmw_priv->vga_width);
  1198. vmw_write(vmw_priv, SVGA_REG_HEIGHT, vmw_priv->vga_height);
  1199. vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, vmw_priv->vga_bpp);
  1200. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1201. vmw_write(vmw_priv, SVGA_REG_PITCHLOCK,
  1202. vmw_priv->vga_pitchlock);
  1203. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1204. iowrite32(vmw_priv->vga_pitchlock,
  1205. vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
  1206. if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
  1207. return 0;
  1208. for (i = 0; i < vmw_priv->num_displays; ++i) {
  1209. save = &vmw_priv->vga_save[i];
  1210. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
  1211. vmw_write(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY, save->primary);
  1212. vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_X, save->pos_x);
  1213. vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y, save->pos_y);
  1214. vmw_write(vmw_priv, SVGA_REG_DISPLAY_WIDTH, save->width);
  1215. vmw_write(vmw_priv, SVGA_REG_DISPLAY_HEIGHT, save->height);
  1216. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
  1217. }
  1218. return 0;
  1219. }
  1220. bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv,
  1221. uint32_t pitch,
  1222. uint32_t height)
  1223. {
  1224. return ((u64) pitch * (u64) height) < (u64) dev_priv->vram_size;
  1225. }
  1226. /**
  1227. * Function called by DRM code called with vbl_lock held.
  1228. */
  1229. u32 vmw_get_vblank_counter(struct drm_device *dev, int crtc)
  1230. {
  1231. return 0;
  1232. }
  1233. /**
  1234. * Function called by DRM code called with vbl_lock held.
  1235. */
  1236. int vmw_enable_vblank(struct drm_device *dev, int crtc)
  1237. {
  1238. return -ENOSYS;
  1239. }
  1240. /**
  1241. * Function called by DRM code called with vbl_lock held.
  1242. */
  1243. void vmw_disable_vblank(struct drm_device *dev, int crtc)
  1244. {
  1245. }
  1246. /*
  1247. * Small shared kms functions.
  1248. */
  1249. int vmw_du_update_layout(struct vmw_private *dev_priv, unsigned num,
  1250. struct drm_vmw_rect *rects)
  1251. {
  1252. struct drm_device *dev = dev_priv->dev;
  1253. struct vmw_display_unit *du;
  1254. struct drm_connector *con;
  1255. mutex_lock(&dev->mode_config.mutex);
  1256. #if 0
  1257. {
  1258. unsigned int i;
  1259. DRM_INFO("%s: new layout ", __func__);
  1260. for (i = 0; i < num; i++)
  1261. DRM_INFO("(%i, %i %ux%u) ", rects[i].x, rects[i].y,
  1262. rects[i].w, rects[i].h);
  1263. DRM_INFO("\n");
  1264. }
  1265. #endif
  1266. list_for_each_entry(con, &dev->mode_config.connector_list, head) {
  1267. du = vmw_connector_to_du(con);
  1268. if (num > du->unit) {
  1269. du->pref_width = rects[du->unit].w;
  1270. du->pref_height = rects[du->unit].h;
  1271. du->pref_active = true;
  1272. du->gui_x = rects[du->unit].x;
  1273. du->gui_y = rects[du->unit].y;
  1274. } else {
  1275. du->pref_width = 800;
  1276. du->pref_height = 600;
  1277. du->pref_active = false;
  1278. }
  1279. con->status = vmw_du_connector_detect(con, true);
  1280. }
  1281. mutex_unlock(&dev->mode_config.mutex);
  1282. return 0;
  1283. }
  1284. void vmw_du_crtc_save(struct drm_crtc *crtc)
  1285. {
  1286. }
  1287. void vmw_du_crtc_restore(struct drm_crtc *crtc)
  1288. {
  1289. }
  1290. void vmw_du_crtc_gamma_set(struct drm_crtc *crtc,
  1291. u16 *r, u16 *g, u16 *b,
  1292. uint32_t start, uint32_t size)
  1293. {
  1294. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  1295. int i;
  1296. for (i = 0; i < size; i++) {
  1297. DRM_DEBUG("%d r/g/b = 0x%04x / 0x%04x / 0x%04x\n", i,
  1298. r[i], g[i], b[i]);
  1299. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 0, r[i] >> 8);
  1300. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 1, g[i] >> 8);
  1301. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 2, b[i] >> 8);
  1302. }
  1303. }
  1304. void vmw_du_connector_dpms(struct drm_connector *connector, int mode)
  1305. {
  1306. }
  1307. void vmw_du_connector_save(struct drm_connector *connector)
  1308. {
  1309. }
  1310. void vmw_du_connector_restore(struct drm_connector *connector)
  1311. {
  1312. }
  1313. enum drm_connector_status
  1314. vmw_du_connector_detect(struct drm_connector *connector, bool force)
  1315. {
  1316. uint32_t num_displays;
  1317. struct drm_device *dev = connector->dev;
  1318. struct vmw_private *dev_priv = vmw_priv(dev);
  1319. struct vmw_display_unit *du = vmw_connector_to_du(connector);
  1320. mutex_lock(&dev_priv->hw_mutex);
  1321. num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS);
  1322. mutex_unlock(&dev_priv->hw_mutex);
  1323. return ((vmw_connector_to_du(connector)->unit < num_displays &&
  1324. du->pref_active) ?
  1325. connector_status_connected : connector_status_disconnected);
  1326. }
  1327. static struct drm_display_mode vmw_kms_connector_builtin[] = {
  1328. /* 640x480@60Hz */
  1329. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
  1330. 752, 800, 0, 480, 489, 492, 525, 0,
  1331. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1332. /* 800x600@60Hz */
  1333. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
  1334. 968, 1056, 0, 600, 601, 605, 628, 0,
  1335. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1336. /* 1024x768@60Hz */
  1337. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
  1338. 1184, 1344, 0, 768, 771, 777, 806, 0,
  1339. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1340. /* 1152x864@75Hz */
  1341. { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
  1342. 1344, 1600, 0, 864, 865, 868, 900, 0,
  1343. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1344. /* 1280x768@60Hz */
  1345. { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
  1346. 1472, 1664, 0, 768, 771, 778, 798, 0,
  1347. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1348. /* 1280x800@60Hz */
  1349. { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
  1350. 1480, 1680, 0, 800, 803, 809, 831, 0,
  1351. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1352. /* 1280x960@60Hz */
  1353. { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
  1354. 1488, 1800, 0, 960, 961, 964, 1000, 0,
  1355. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1356. /* 1280x1024@60Hz */
  1357. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
  1358. 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
  1359. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1360. /* 1360x768@60Hz */
  1361. { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
  1362. 1536, 1792, 0, 768, 771, 777, 795, 0,
  1363. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1364. /* 1440x1050@60Hz */
  1365. { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
  1366. 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
  1367. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1368. /* 1440x900@60Hz */
  1369. { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
  1370. 1672, 1904, 0, 900, 903, 909, 934, 0,
  1371. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1372. /* 1600x1200@60Hz */
  1373. { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
  1374. 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
  1375. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1376. /* 1680x1050@60Hz */
  1377. { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
  1378. 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
  1379. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1380. /* 1792x1344@60Hz */
  1381. { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
  1382. 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
  1383. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1384. /* 1853x1392@60Hz */
  1385. { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
  1386. 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
  1387. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1388. /* 1920x1200@60Hz */
  1389. { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
  1390. 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
  1391. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1392. /* 1920x1440@60Hz */
  1393. { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
  1394. 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
  1395. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1396. /* 2560x1600@60Hz */
  1397. { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
  1398. 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
  1399. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1400. /* Terminate */
  1401. { DRM_MODE("", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) },
  1402. };
  1403. /**
  1404. * vmw_guess_mode_timing - Provide fake timings for a
  1405. * 60Hz vrefresh mode.
  1406. *
  1407. * @mode - Pointer to a struct drm_display_mode with hdisplay and vdisplay
  1408. * members filled in.
  1409. */
  1410. static void vmw_guess_mode_timing(struct drm_display_mode *mode)
  1411. {
  1412. mode->hsync_start = mode->hdisplay + 50;
  1413. mode->hsync_end = mode->hsync_start + 50;
  1414. mode->htotal = mode->hsync_end + 50;
  1415. mode->vsync_start = mode->vdisplay + 50;
  1416. mode->vsync_end = mode->vsync_start + 50;
  1417. mode->vtotal = mode->vsync_end + 50;
  1418. mode->clock = (u32)mode->htotal * (u32)mode->vtotal / 100 * 6;
  1419. mode->vrefresh = drm_mode_vrefresh(mode);
  1420. }
  1421. int vmw_du_connector_fill_modes(struct drm_connector *connector,
  1422. uint32_t max_width, uint32_t max_height)
  1423. {
  1424. struct vmw_display_unit *du = vmw_connector_to_du(connector);
  1425. struct drm_device *dev = connector->dev;
  1426. struct vmw_private *dev_priv = vmw_priv(dev);
  1427. struct drm_display_mode *mode = NULL;
  1428. struct drm_display_mode *bmode;
  1429. struct drm_display_mode prefmode = { DRM_MODE("preferred",
  1430. DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
  1431. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  1432. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)
  1433. };
  1434. int i;
  1435. /* Add preferred mode */
  1436. {
  1437. mode = drm_mode_duplicate(dev, &prefmode);
  1438. if (!mode)
  1439. return 0;
  1440. mode->hdisplay = du->pref_width;
  1441. mode->vdisplay = du->pref_height;
  1442. vmw_guess_mode_timing(mode);
  1443. if (vmw_kms_validate_mode_vram(dev_priv, mode->hdisplay * 2,
  1444. mode->vdisplay)) {
  1445. drm_mode_probed_add(connector, mode);
  1446. } else {
  1447. drm_mode_destroy(dev, mode);
  1448. mode = NULL;
  1449. }
  1450. if (du->pref_mode) {
  1451. list_del_init(&du->pref_mode->head);
  1452. drm_mode_destroy(dev, du->pref_mode);
  1453. }
  1454. /* mode might be null here, this is intended */
  1455. du->pref_mode = mode;
  1456. }
  1457. for (i = 0; vmw_kms_connector_builtin[i].type != 0; i++) {
  1458. bmode = &vmw_kms_connector_builtin[i];
  1459. if (bmode->hdisplay > max_width ||
  1460. bmode->vdisplay > max_height)
  1461. continue;
  1462. if (!vmw_kms_validate_mode_vram(dev_priv, bmode->hdisplay * 2,
  1463. bmode->vdisplay))
  1464. continue;
  1465. mode = drm_mode_duplicate(dev, bmode);
  1466. if (!mode)
  1467. return 0;
  1468. mode->vrefresh = drm_mode_vrefresh(mode);
  1469. drm_mode_probed_add(connector, mode);
  1470. }
  1471. /* Move the prefered mode first, help apps pick the right mode. */
  1472. if (du->pref_mode)
  1473. list_move(&du->pref_mode->head, &connector->probed_modes);
  1474. drm_mode_connector_list_update(connector);
  1475. return 1;
  1476. }
  1477. int vmw_du_connector_set_property(struct drm_connector *connector,
  1478. struct drm_property *property,
  1479. uint64_t val)
  1480. {
  1481. return 0;
  1482. }
  1483. int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data,
  1484. struct drm_file *file_priv)
  1485. {
  1486. struct vmw_private *dev_priv = vmw_priv(dev);
  1487. struct drm_vmw_update_layout_arg *arg =
  1488. (struct drm_vmw_update_layout_arg *)data;
  1489. struct vmw_master *vmaster = vmw_master(file_priv->master);
  1490. void __user *user_rects;
  1491. struct drm_vmw_rect *rects;
  1492. unsigned rects_size;
  1493. int ret;
  1494. int i;
  1495. struct drm_mode_config *mode_config = &dev->mode_config;
  1496. ret = ttm_read_lock(&vmaster->lock, true);
  1497. if (unlikely(ret != 0))
  1498. return ret;
  1499. if (!arg->num_outputs) {
  1500. struct drm_vmw_rect def_rect = {0, 0, 800, 600};
  1501. vmw_du_update_layout(dev_priv, 1, &def_rect);
  1502. goto out_unlock;
  1503. }
  1504. rects_size = arg->num_outputs * sizeof(struct drm_vmw_rect);
  1505. rects = kzalloc(rects_size, GFP_KERNEL);
  1506. if (unlikely(!rects)) {
  1507. ret = -ENOMEM;
  1508. goto out_unlock;
  1509. }
  1510. user_rects = (void __user *)(unsigned long)arg->rects;
  1511. ret = copy_from_user(rects, user_rects, rects_size);
  1512. if (unlikely(ret != 0)) {
  1513. DRM_ERROR("Failed to get rects.\n");
  1514. ret = -EFAULT;
  1515. goto out_free;
  1516. }
  1517. for (i = 0; i < arg->num_outputs; ++i) {
  1518. if (rects->x < 0 ||
  1519. rects->y < 0 ||
  1520. rects->x + rects->w > mode_config->max_width ||
  1521. rects->y + rects->h > mode_config->max_height) {
  1522. DRM_ERROR("Invalid GUI layout.\n");
  1523. ret = -EINVAL;
  1524. goto out_free;
  1525. }
  1526. }
  1527. vmw_du_update_layout(dev_priv, arg->num_outputs, rects);
  1528. out_free:
  1529. kfree(rects);
  1530. out_unlock:
  1531. ttm_read_unlock(&vmaster->lock);
  1532. return ret;
  1533. }