iwl-agn.c 94 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/mac80211.h>
  42. #include <asm/div64.h>
  43. #define DRV_NAME "iwlagn"
  44. #include "iwl-eeprom.h"
  45. #include "iwl-dev.h"
  46. #include "iwl-core.h"
  47. #include "iwl-io.h"
  48. #include "iwl-helpers.h"
  49. #include "iwl-sta.h"
  50. #include "iwl-calib.h"
  51. /******************************************************************************
  52. *
  53. * module boiler plate
  54. *
  55. ******************************************************************************/
  56. /*
  57. * module name, copyright, version, etc.
  58. */
  59. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  60. #ifdef CONFIG_IWLWIFI_DEBUG
  61. #define VD "d"
  62. #else
  63. #define VD
  64. #endif
  65. #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
  66. #define VS "s"
  67. #else
  68. #define VS
  69. #endif
  70. #define DRV_VERSION IWLWIFI_VERSION VD VS
  71. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  72. MODULE_VERSION(DRV_VERSION);
  73. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  74. MODULE_LICENSE("GPL");
  75. MODULE_ALIAS("iwl4965");
  76. /*************** STATION TABLE MANAGEMENT ****
  77. * mac80211 should be examined to determine if sta_info is duplicating
  78. * the functionality provided here
  79. */
  80. /**************************************************************/
  81. /**
  82. * iwl_commit_rxon - commit staging_rxon to hardware
  83. *
  84. * The RXON command in staging_rxon is committed to the hardware and
  85. * the active_rxon structure is updated with the new data. This
  86. * function correctly transitions out of the RXON_ASSOC_MSK state if
  87. * a HW tune is required based on the RXON structure changes.
  88. */
  89. int iwl_commit_rxon(struct iwl_priv *priv)
  90. {
  91. /* cast away the const for active_rxon in this function */
  92. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  93. int ret;
  94. bool new_assoc =
  95. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  96. if (!iwl_is_alive(priv))
  97. return -EBUSY;
  98. /* always get timestamp with Rx frame */
  99. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  100. ret = iwl_check_rxon_cmd(priv);
  101. if (ret) {
  102. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  103. return -EINVAL;
  104. }
  105. /* If we don't need to send a full RXON, we can use
  106. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  107. * and other flags for the current radio configuration. */
  108. if (!iwl_full_rxon_required(priv)) {
  109. ret = iwl_send_rxon_assoc(priv);
  110. if (ret) {
  111. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  112. return ret;
  113. }
  114. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  115. return 0;
  116. }
  117. /* station table will be cleared */
  118. priv->assoc_station_added = 0;
  119. /* If we are currently associated and the new config requires
  120. * an RXON_ASSOC and the new config wants the associated mask enabled,
  121. * we must clear the associated from the active configuration
  122. * before we apply the new config */
  123. if (iwl_is_associated(priv) && new_assoc) {
  124. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  125. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  126. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  127. sizeof(struct iwl_rxon_cmd),
  128. &priv->active_rxon);
  129. /* If the mask clearing failed then we set
  130. * active_rxon back to what it was previously */
  131. if (ret) {
  132. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  133. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  134. return ret;
  135. }
  136. }
  137. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  138. "* with%s RXON_FILTER_ASSOC_MSK\n"
  139. "* channel = %d\n"
  140. "* bssid = %pM\n",
  141. (new_assoc ? "" : "out"),
  142. le16_to_cpu(priv->staging_rxon.channel),
  143. priv->staging_rxon.bssid_addr);
  144. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  145. /* Apply the new configuration
  146. * RXON unassoc clears the station table in uCode, send it before
  147. * we add the bcast station. If assoc bit is set, we will send RXON
  148. * after having added the bcast and bssid station.
  149. */
  150. if (!new_assoc) {
  151. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  152. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  153. if (ret) {
  154. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  155. return ret;
  156. }
  157. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  158. }
  159. iwl_clear_stations_table(priv);
  160. priv->start_calib = 0;
  161. /* Add the broadcast address so we can send broadcast frames */
  162. if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
  163. IWL_INVALID_STATION) {
  164. IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
  165. return -EIO;
  166. }
  167. /* If we have set the ASSOC_MSK and we are in BSS mode then
  168. * add the IWL_AP_ID to the station rate table */
  169. if (new_assoc) {
  170. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  171. ret = iwl_rxon_add_station(priv,
  172. priv->active_rxon.bssid_addr, 1);
  173. if (ret == IWL_INVALID_STATION) {
  174. IWL_ERR(priv,
  175. "Error adding AP address for TX.\n");
  176. return -EIO;
  177. }
  178. priv->assoc_station_added = 1;
  179. if (priv->default_wep_key &&
  180. iwl_send_static_wepkey_cmd(priv, 0))
  181. IWL_ERR(priv,
  182. "Could not send WEP static key.\n");
  183. }
  184. /*
  185. * allow CTS-to-self if possible for new association.
  186. * this is relevant only for 5000 series and up,
  187. * but will not damage 4965
  188. */
  189. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  190. /* Apply the new configuration
  191. * RXON assoc doesn't clear the station table in uCode,
  192. */
  193. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  194. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  195. if (ret) {
  196. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  197. return ret;
  198. }
  199. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  200. }
  201. iwl_init_sensitivity(priv);
  202. /* If we issue a new RXON command which required a tune then we must
  203. * send a new TXPOWER command or we won't be able to Tx any frames */
  204. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  205. if (ret) {
  206. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  207. return ret;
  208. }
  209. return 0;
  210. }
  211. void iwl_update_chain_flags(struct iwl_priv *priv)
  212. {
  213. if (priv->cfg->ops->hcmd->set_rxon_chain)
  214. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  215. iwlcore_commit_rxon(priv);
  216. }
  217. static void iwl_clear_free_frames(struct iwl_priv *priv)
  218. {
  219. struct list_head *element;
  220. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  221. priv->frames_count);
  222. while (!list_empty(&priv->free_frames)) {
  223. element = priv->free_frames.next;
  224. list_del(element);
  225. kfree(list_entry(element, struct iwl_frame, list));
  226. priv->frames_count--;
  227. }
  228. if (priv->frames_count) {
  229. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  230. priv->frames_count);
  231. priv->frames_count = 0;
  232. }
  233. }
  234. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  235. {
  236. struct iwl_frame *frame;
  237. struct list_head *element;
  238. if (list_empty(&priv->free_frames)) {
  239. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  240. if (!frame) {
  241. IWL_ERR(priv, "Could not allocate frame!\n");
  242. return NULL;
  243. }
  244. priv->frames_count++;
  245. return frame;
  246. }
  247. element = priv->free_frames.next;
  248. list_del(element);
  249. return list_entry(element, struct iwl_frame, list);
  250. }
  251. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  252. {
  253. memset(frame, 0, sizeof(*frame));
  254. list_add(&frame->list, &priv->free_frames);
  255. }
  256. static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
  257. struct ieee80211_hdr *hdr,
  258. int left)
  259. {
  260. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  261. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  262. (priv->iw_mode != NL80211_IFTYPE_AP)))
  263. return 0;
  264. if (priv->ibss_beacon->len > left)
  265. return 0;
  266. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  267. return priv->ibss_beacon->len;
  268. }
  269. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  270. struct iwl_frame *frame, u8 rate)
  271. {
  272. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  273. unsigned int frame_size;
  274. tx_beacon_cmd = &frame->u.beacon;
  275. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  276. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  277. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  278. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  279. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  280. BUG_ON(frame_size > MAX_MPDU_SIZE);
  281. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  282. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  283. tx_beacon_cmd->tx.rate_n_flags =
  284. iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  285. else
  286. tx_beacon_cmd->tx.rate_n_flags =
  287. iwl_hw_set_rate_n_flags(rate, 0);
  288. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  289. TX_CMD_FLG_TSF_MSK |
  290. TX_CMD_FLG_STA_RATE_MSK;
  291. return sizeof(*tx_beacon_cmd) + frame_size;
  292. }
  293. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  294. {
  295. struct iwl_frame *frame;
  296. unsigned int frame_size;
  297. int rc;
  298. u8 rate;
  299. frame = iwl_get_free_frame(priv);
  300. if (!frame) {
  301. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  302. "command.\n");
  303. return -ENOMEM;
  304. }
  305. rate = iwl_rate_get_lowest_plcp(priv);
  306. frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
  307. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  308. &frame->u.cmd[0]);
  309. iwl_free_frame(priv, frame);
  310. return rc;
  311. }
  312. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  313. {
  314. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  315. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  316. if (sizeof(dma_addr_t) > sizeof(u32))
  317. addr |=
  318. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  319. return addr;
  320. }
  321. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  322. {
  323. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  324. return le16_to_cpu(tb->hi_n_len) >> 4;
  325. }
  326. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  327. dma_addr_t addr, u16 len)
  328. {
  329. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  330. u16 hi_n_len = len << 4;
  331. put_unaligned_le32(addr, &tb->lo);
  332. if (sizeof(dma_addr_t) > sizeof(u32))
  333. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  334. tb->hi_n_len = cpu_to_le16(hi_n_len);
  335. tfd->num_tbs = idx + 1;
  336. }
  337. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  338. {
  339. return tfd->num_tbs & 0x1f;
  340. }
  341. /**
  342. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  343. * @priv - driver private data
  344. * @txq - tx queue
  345. *
  346. * Does NOT advance any TFD circular buffer read/write indexes
  347. * Does NOT free the TFD itself (which is within circular buffer)
  348. */
  349. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  350. {
  351. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  352. struct iwl_tfd *tfd;
  353. struct pci_dev *dev = priv->pci_dev;
  354. int index = txq->q.read_ptr;
  355. int i;
  356. int num_tbs;
  357. tfd = &tfd_tmp[index];
  358. /* Sanity check on number of chunks */
  359. num_tbs = iwl_tfd_get_num_tbs(tfd);
  360. if (num_tbs >= IWL_NUM_OF_TBS) {
  361. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  362. /* @todo issue fatal error, it is quite serious situation */
  363. return;
  364. }
  365. /* Unmap tx_cmd */
  366. if (num_tbs)
  367. pci_unmap_single(dev,
  368. pci_unmap_addr(&txq->meta[index], mapping),
  369. pci_unmap_len(&txq->meta[index], len),
  370. PCI_DMA_BIDIRECTIONAL);
  371. /* Unmap chunks, if any. */
  372. for (i = 1; i < num_tbs; i++) {
  373. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  374. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  375. if (txq->txb) {
  376. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  377. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  378. }
  379. }
  380. }
  381. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  382. struct iwl_tx_queue *txq,
  383. dma_addr_t addr, u16 len,
  384. u8 reset, u8 pad)
  385. {
  386. struct iwl_queue *q;
  387. struct iwl_tfd *tfd, *tfd_tmp;
  388. u32 num_tbs;
  389. q = &txq->q;
  390. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  391. tfd = &tfd_tmp[q->write_ptr];
  392. if (reset)
  393. memset(tfd, 0, sizeof(*tfd));
  394. num_tbs = iwl_tfd_get_num_tbs(tfd);
  395. /* Each TFD can point to a maximum 20 Tx buffers */
  396. if (num_tbs >= IWL_NUM_OF_TBS) {
  397. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  398. IWL_NUM_OF_TBS);
  399. return -EINVAL;
  400. }
  401. BUG_ON(addr & ~DMA_BIT_MASK(36));
  402. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  403. IWL_ERR(priv, "Unaligned address = %llx\n",
  404. (unsigned long long)addr);
  405. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  406. return 0;
  407. }
  408. /*
  409. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  410. * given Tx queue, and enable the DMA channel used for that queue.
  411. *
  412. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  413. * channels supported in hardware.
  414. */
  415. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  416. struct iwl_tx_queue *txq)
  417. {
  418. int txq_id = txq->q.id;
  419. /* Circular buffer (TFD queue in DRAM) physical base address */
  420. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  421. txq->q.dma_addr >> 8);
  422. return 0;
  423. }
  424. /******************************************************************************
  425. *
  426. * Generic RX handler implementations
  427. *
  428. ******************************************************************************/
  429. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  430. struct iwl_rx_mem_buffer *rxb)
  431. {
  432. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  433. struct iwl_alive_resp *palive;
  434. struct delayed_work *pwork;
  435. palive = &pkt->u.alive_frame;
  436. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  437. "0x%01X 0x%01X\n",
  438. palive->is_valid, palive->ver_type,
  439. palive->ver_subtype);
  440. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  441. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  442. memcpy(&priv->card_alive_init,
  443. &pkt->u.alive_frame,
  444. sizeof(struct iwl_init_alive_resp));
  445. pwork = &priv->init_alive_start;
  446. } else {
  447. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  448. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  449. sizeof(struct iwl_alive_resp));
  450. pwork = &priv->alive_start;
  451. }
  452. /* We delay the ALIVE response by 5ms to
  453. * give the HW RF Kill time to activate... */
  454. if (palive->is_valid == UCODE_VALID_OK)
  455. queue_delayed_work(priv->workqueue, pwork,
  456. msecs_to_jiffies(5));
  457. else
  458. IWL_WARN(priv, "uCode did not respond OK.\n");
  459. }
  460. static void iwl_bg_beacon_update(struct work_struct *work)
  461. {
  462. struct iwl_priv *priv =
  463. container_of(work, struct iwl_priv, beacon_update);
  464. struct sk_buff *beacon;
  465. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  466. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  467. if (!beacon) {
  468. IWL_ERR(priv, "update beacon failed\n");
  469. return;
  470. }
  471. mutex_lock(&priv->mutex);
  472. /* new beacon skb is allocated every time; dispose previous.*/
  473. if (priv->ibss_beacon)
  474. dev_kfree_skb(priv->ibss_beacon);
  475. priv->ibss_beacon = beacon;
  476. mutex_unlock(&priv->mutex);
  477. iwl_send_beacon_cmd(priv);
  478. }
  479. /**
  480. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  481. *
  482. * This callback is provided in order to send a statistics request.
  483. *
  484. * This timer function is continually reset to execute within
  485. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  486. * was received. We need to ensure we receive the statistics in order
  487. * to update the temperature used for calibrating the TXPOWER.
  488. */
  489. static void iwl_bg_statistics_periodic(unsigned long data)
  490. {
  491. struct iwl_priv *priv = (struct iwl_priv *)data;
  492. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  493. return;
  494. /* dont send host command if rf-kill is on */
  495. if (!iwl_is_ready_rf(priv))
  496. return;
  497. iwl_send_statistics_request(priv, CMD_ASYNC);
  498. }
  499. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  500. struct iwl_rx_mem_buffer *rxb)
  501. {
  502. #ifdef CONFIG_IWLWIFI_DEBUG
  503. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  504. struct iwl4965_beacon_notif *beacon =
  505. (struct iwl4965_beacon_notif *)pkt->u.raw;
  506. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  507. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  508. "tsf %d %d rate %d\n",
  509. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  510. beacon->beacon_notify_hdr.failure_frame,
  511. le32_to_cpu(beacon->ibss_mgr_status),
  512. le32_to_cpu(beacon->high_tsf),
  513. le32_to_cpu(beacon->low_tsf), rate);
  514. #endif
  515. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  516. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  517. queue_work(priv->workqueue, &priv->beacon_update);
  518. }
  519. /* Handle notification from uCode that card's power state is changing
  520. * due to software, hardware, or critical temperature RFKILL */
  521. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  522. struct iwl_rx_mem_buffer *rxb)
  523. {
  524. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  525. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  526. unsigned long status = priv->status;
  527. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
  528. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  529. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  530. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  531. RF_CARD_DISABLED)) {
  532. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  533. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  534. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  535. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  536. if (!(flags & RXON_CARD_DISABLED)) {
  537. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  538. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  539. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  540. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  541. }
  542. if (flags & RF_CARD_DISABLED)
  543. iwl_tt_enter_ct_kill(priv);
  544. }
  545. if (!(flags & RF_CARD_DISABLED))
  546. iwl_tt_exit_ct_kill(priv);
  547. if (flags & HW_CARD_DISABLED)
  548. set_bit(STATUS_RF_KILL_HW, &priv->status);
  549. else
  550. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  551. if (!(flags & RXON_CARD_DISABLED))
  552. iwl_scan_cancel(priv);
  553. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  554. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  555. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  556. test_bit(STATUS_RF_KILL_HW, &priv->status));
  557. else
  558. wake_up_interruptible(&priv->wait_command_queue);
  559. }
  560. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  561. {
  562. if (src == IWL_PWR_SRC_VAUX) {
  563. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  564. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  565. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  566. ~APMG_PS_CTRL_MSK_PWR_SRC);
  567. } else {
  568. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  569. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  570. ~APMG_PS_CTRL_MSK_PWR_SRC);
  571. }
  572. return 0;
  573. }
  574. /**
  575. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  576. *
  577. * Setup the RX handlers for each of the reply types sent from the uCode
  578. * to the host.
  579. *
  580. * This function chains into the hardware specific files for them to setup
  581. * any hardware specific handlers as well.
  582. */
  583. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  584. {
  585. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  586. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  587. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  588. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  589. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  590. iwl_rx_pm_debug_statistics_notif;
  591. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  592. /*
  593. * The same handler is used for both the REPLY to a discrete
  594. * statistics request from the host as well as for the periodic
  595. * statistics notifications (after received beacons) from the uCode.
  596. */
  597. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
  598. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  599. iwl_setup_spectrum_handlers(priv);
  600. iwl_setup_rx_scan_handlers(priv);
  601. /* status change handler */
  602. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  603. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  604. iwl_rx_missed_beacon_notif;
  605. /* Rx handlers */
  606. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  607. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  608. /* block ack */
  609. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  610. /* Set up hardware specific Rx handlers */
  611. priv->cfg->ops->lib->rx_handler_setup(priv);
  612. }
  613. /**
  614. * iwl_rx_handle - Main entry function for receiving responses from uCode
  615. *
  616. * Uses the priv->rx_handlers callback function array to invoke
  617. * the appropriate handlers, including command responses,
  618. * frame-received notifications, and other notifications.
  619. */
  620. void iwl_rx_handle(struct iwl_priv *priv)
  621. {
  622. struct iwl_rx_mem_buffer *rxb;
  623. struct iwl_rx_packet *pkt;
  624. struct iwl_rx_queue *rxq = &priv->rxq;
  625. u32 r, i;
  626. int reclaim;
  627. unsigned long flags;
  628. u8 fill_rx = 0;
  629. u32 count = 8;
  630. int total_empty;
  631. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  632. * buffer that the driver may process (last buffer filled by ucode). */
  633. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  634. i = rxq->read;
  635. /* Rx interrupt, but nothing sent from uCode */
  636. if (i == r)
  637. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  638. /* calculate total frames need to be restock after handling RX */
  639. total_empty = r - priv->rxq.write_actual;
  640. if (total_empty < 0)
  641. total_empty += RX_QUEUE_SIZE;
  642. if (total_empty > (RX_QUEUE_SIZE / 2))
  643. fill_rx = 1;
  644. while (i != r) {
  645. rxb = rxq->queue[i];
  646. /* If an RXB doesn't have a Rx queue slot associated with it,
  647. * then a bug has been introduced in the queue refilling
  648. * routines -- catch it here */
  649. BUG_ON(rxb == NULL);
  650. rxq->queue[i] = NULL;
  651. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  652. PAGE_SIZE << priv->hw_params.rx_page_order,
  653. PCI_DMA_FROMDEVICE);
  654. pkt = rxb_addr(rxb);
  655. trace_iwlwifi_dev_rx(priv, pkt,
  656. le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
  657. /* Reclaim a command buffer only if this packet is a response
  658. * to a (driver-originated) command.
  659. * If the packet (e.g. Rx frame) originated from uCode,
  660. * there is no command buffer to reclaim.
  661. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  662. * but apparently a few don't get set; catch them here. */
  663. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  664. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  665. (pkt->hdr.cmd != REPLY_RX) &&
  666. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  667. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  668. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  669. (pkt->hdr.cmd != REPLY_TX);
  670. /* Based on type of command response or notification,
  671. * handle those that need handling via function in
  672. * rx_handlers table. See iwl_setup_rx_handlers() */
  673. if (priv->rx_handlers[pkt->hdr.cmd]) {
  674. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  675. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  676. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  677. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  678. } else {
  679. /* No handling needed */
  680. IWL_DEBUG_RX(priv,
  681. "r %d i %d No handler needed for %s, 0x%02x\n",
  682. r, i, get_cmd_string(pkt->hdr.cmd),
  683. pkt->hdr.cmd);
  684. }
  685. if (reclaim) {
  686. /* Invoke any callbacks, transfer the buffer to caller,
  687. * and fire off the (possibly) blocking iwl_send_cmd()
  688. * as we reclaim the driver command queue */
  689. if (rxb && rxb->page)
  690. iwl_tx_cmd_complete(priv, rxb);
  691. else
  692. IWL_WARN(priv, "Claim null rxb?\n");
  693. }
  694. /* For now we just don't re-use anything. We can tweak this
  695. * later to try and re-use notification packets and SKBs that
  696. * fail to Rx correctly */
  697. if (rxb->page != NULL) {
  698. priv->alloc_rxb_page--;
  699. __free_pages(rxb->page, priv->hw_params.rx_page_order);
  700. rxb->page = NULL;
  701. }
  702. spin_lock_irqsave(&rxq->lock, flags);
  703. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  704. spin_unlock_irqrestore(&rxq->lock, flags);
  705. i = (i + 1) & RX_QUEUE_MASK;
  706. /* If there are a lot of unused frames,
  707. * restock the Rx queue so ucode wont assert. */
  708. if (fill_rx) {
  709. count++;
  710. if (count >= 8) {
  711. priv->rxq.read = i;
  712. iwl_rx_replenish_now(priv);
  713. count = 0;
  714. }
  715. }
  716. }
  717. /* Backtrack one entry */
  718. priv->rxq.read = i;
  719. if (fill_rx)
  720. iwl_rx_replenish_now(priv);
  721. else
  722. iwl_rx_queue_restock(priv);
  723. }
  724. /* call this function to flush any scheduled tasklet */
  725. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  726. {
  727. /* wait to make sure we flush pending tasklet*/
  728. synchronize_irq(priv->pci_dev->irq);
  729. tasklet_kill(&priv->irq_tasklet);
  730. }
  731. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  732. {
  733. u32 inta, handled = 0;
  734. u32 inta_fh;
  735. unsigned long flags;
  736. #ifdef CONFIG_IWLWIFI_DEBUG
  737. u32 inta_mask;
  738. #endif
  739. spin_lock_irqsave(&priv->lock, flags);
  740. /* Ack/clear/reset pending uCode interrupts.
  741. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  742. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  743. inta = iwl_read32(priv, CSR_INT);
  744. iwl_write32(priv, CSR_INT, inta);
  745. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  746. * Any new interrupts that happen after this, either while we're
  747. * in this tasklet, or later, will show up in next ISR/tasklet. */
  748. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  749. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  750. #ifdef CONFIG_IWLWIFI_DEBUG
  751. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  752. /* just for debug */
  753. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  754. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  755. inta, inta_mask, inta_fh);
  756. }
  757. #endif
  758. spin_unlock_irqrestore(&priv->lock, flags);
  759. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  760. * atomic, make sure that inta covers all the interrupts that
  761. * we've discovered, even if FH interrupt came in just after
  762. * reading CSR_INT. */
  763. if (inta_fh & CSR49_FH_INT_RX_MASK)
  764. inta |= CSR_INT_BIT_FH_RX;
  765. if (inta_fh & CSR49_FH_INT_TX_MASK)
  766. inta |= CSR_INT_BIT_FH_TX;
  767. /* Now service all interrupt bits discovered above. */
  768. if (inta & CSR_INT_BIT_HW_ERR) {
  769. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  770. /* Tell the device to stop sending interrupts */
  771. iwl_disable_interrupts(priv);
  772. priv->isr_stats.hw++;
  773. iwl_irq_handle_error(priv);
  774. handled |= CSR_INT_BIT_HW_ERR;
  775. return;
  776. }
  777. #ifdef CONFIG_IWLWIFI_DEBUG
  778. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  779. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  780. if (inta & CSR_INT_BIT_SCD) {
  781. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  782. "the frame/frames.\n");
  783. priv->isr_stats.sch++;
  784. }
  785. /* Alive notification via Rx interrupt will do the real work */
  786. if (inta & CSR_INT_BIT_ALIVE) {
  787. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  788. priv->isr_stats.alive++;
  789. }
  790. }
  791. #endif
  792. /* Safely ignore these bits for debug checks below */
  793. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  794. /* HW RF KILL switch toggled */
  795. if (inta & CSR_INT_BIT_RF_KILL) {
  796. int hw_rf_kill = 0;
  797. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  798. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  799. hw_rf_kill = 1;
  800. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  801. hw_rf_kill ? "disable radio" : "enable radio");
  802. priv->isr_stats.rfkill++;
  803. /* driver only loads ucode once setting the interface up.
  804. * the driver allows loading the ucode even if the radio
  805. * is killed. Hence update the killswitch state here. The
  806. * rfkill handler will care about restarting if needed.
  807. */
  808. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  809. if (hw_rf_kill)
  810. set_bit(STATUS_RF_KILL_HW, &priv->status);
  811. else
  812. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  813. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  814. }
  815. handled |= CSR_INT_BIT_RF_KILL;
  816. }
  817. /* Chip got too hot and stopped itself */
  818. if (inta & CSR_INT_BIT_CT_KILL) {
  819. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  820. priv->isr_stats.ctkill++;
  821. handled |= CSR_INT_BIT_CT_KILL;
  822. }
  823. /* Error detected by uCode */
  824. if (inta & CSR_INT_BIT_SW_ERR) {
  825. IWL_ERR(priv, "Microcode SW error detected. "
  826. " Restarting 0x%X.\n", inta);
  827. priv->isr_stats.sw++;
  828. priv->isr_stats.sw_err = inta;
  829. iwl_irq_handle_error(priv);
  830. handled |= CSR_INT_BIT_SW_ERR;
  831. }
  832. /* uCode wakes up after power-down sleep */
  833. if (inta & CSR_INT_BIT_WAKEUP) {
  834. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  835. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  836. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  837. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  838. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  839. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  840. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  841. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  842. priv->isr_stats.wakeup++;
  843. handled |= CSR_INT_BIT_WAKEUP;
  844. }
  845. /* All uCode command responses, including Tx command responses,
  846. * Rx "responses" (frame-received notification), and other
  847. * notifications from uCode come through here*/
  848. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  849. iwl_rx_handle(priv);
  850. priv->isr_stats.rx++;
  851. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  852. }
  853. if (inta & CSR_INT_BIT_FH_TX) {
  854. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  855. priv->isr_stats.tx++;
  856. handled |= CSR_INT_BIT_FH_TX;
  857. /* FH finished to write, send event */
  858. priv->ucode_write_complete = 1;
  859. wake_up_interruptible(&priv->wait_command_queue);
  860. }
  861. if (inta & ~handled) {
  862. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  863. priv->isr_stats.unhandled++;
  864. }
  865. if (inta & ~(priv->inta_mask)) {
  866. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  867. inta & ~priv->inta_mask);
  868. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  869. }
  870. /* Re-enable all interrupts */
  871. /* only Re-enable if diabled by irq */
  872. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  873. iwl_enable_interrupts(priv);
  874. #ifdef CONFIG_IWLWIFI_DEBUG
  875. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  876. inta = iwl_read32(priv, CSR_INT);
  877. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  878. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  879. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  880. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  881. }
  882. #endif
  883. }
  884. /* tasklet for iwlagn interrupt */
  885. static void iwl_irq_tasklet(struct iwl_priv *priv)
  886. {
  887. u32 inta = 0;
  888. u32 handled = 0;
  889. unsigned long flags;
  890. #ifdef CONFIG_IWLWIFI_DEBUG
  891. u32 inta_mask;
  892. #endif
  893. spin_lock_irqsave(&priv->lock, flags);
  894. /* Ack/clear/reset pending uCode interrupts.
  895. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  896. */
  897. iwl_write32(priv, CSR_INT, priv->inta);
  898. inta = priv->inta;
  899. #ifdef CONFIG_IWLWIFI_DEBUG
  900. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  901. /* just for debug */
  902. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  903. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  904. inta, inta_mask);
  905. }
  906. #endif
  907. spin_unlock_irqrestore(&priv->lock, flags);
  908. /* saved interrupt in inta variable now we can reset priv->inta */
  909. priv->inta = 0;
  910. /* Now service all interrupt bits discovered above. */
  911. if (inta & CSR_INT_BIT_HW_ERR) {
  912. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  913. /* Tell the device to stop sending interrupts */
  914. iwl_disable_interrupts(priv);
  915. priv->isr_stats.hw++;
  916. iwl_irq_handle_error(priv);
  917. handled |= CSR_INT_BIT_HW_ERR;
  918. return;
  919. }
  920. #ifdef CONFIG_IWLWIFI_DEBUG
  921. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  922. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  923. if (inta & CSR_INT_BIT_SCD) {
  924. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  925. "the frame/frames.\n");
  926. priv->isr_stats.sch++;
  927. }
  928. /* Alive notification via Rx interrupt will do the real work */
  929. if (inta & CSR_INT_BIT_ALIVE) {
  930. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  931. priv->isr_stats.alive++;
  932. }
  933. }
  934. #endif
  935. /* Safely ignore these bits for debug checks below */
  936. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  937. /* HW RF KILL switch toggled */
  938. if (inta & CSR_INT_BIT_RF_KILL) {
  939. int hw_rf_kill = 0;
  940. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  941. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  942. hw_rf_kill = 1;
  943. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  944. hw_rf_kill ? "disable radio" : "enable radio");
  945. priv->isr_stats.rfkill++;
  946. /* driver only loads ucode once setting the interface up.
  947. * the driver allows loading the ucode even if the radio
  948. * is killed. Hence update the killswitch state here. The
  949. * rfkill handler will care about restarting if needed.
  950. */
  951. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  952. if (hw_rf_kill)
  953. set_bit(STATUS_RF_KILL_HW, &priv->status);
  954. else
  955. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  956. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  957. }
  958. handled |= CSR_INT_BIT_RF_KILL;
  959. }
  960. /* Chip got too hot and stopped itself */
  961. if (inta & CSR_INT_BIT_CT_KILL) {
  962. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  963. priv->isr_stats.ctkill++;
  964. handled |= CSR_INT_BIT_CT_KILL;
  965. }
  966. /* Error detected by uCode */
  967. if (inta & CSR_INT_BIT_SW_ERR) {
  968. IWL_ERR(priv, "Microcode SW error detected. "
  969. " Restarting 0x%X.\n", inta);
  970. priv->isr_stats.sw++;
  971. priv->isr_stats.sw_err = inta;
  972. iwl_irq_handle_error(priv);
  973. handled |= CSR_INT_BIT_SW_ERR;
  974. }
  975. /* uCode wakes up after power-down sleep */
  976. if (inta & CSR_INT_BIT_WAKEUP) {
  977. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  978. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  979. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  980. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  981. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  982. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  983. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  984. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  985. priv->isr_stats.wakeup++;
  986. handled |= CSR_INT_BIT_WAKEUP;
  987. }
  988. /* All uCode command responses, including Tx command responses,
  989. * Rx "responses" (frame-received notification), and other
  990. * notifications from uCode come through here*/
  991. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  992. CSR_INT_BIT_RX_PERIODIC)) {
  993. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  994. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  995. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  996. iwl_write32(priv, CSR_FH_INT_STATUS,
  997. CSR49_FH_INT_RX_MASK);
  998. }
  999. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1000. handled |= CSR_INT_BIT_RX_PERIODIC;
  1001. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1002. }
  1003. /* Sending RX interrupt require many steps to be done in the
  1004. * the device:
  1005. * 1- write interrupt to current index in ICT table.
  1006. * 2- dma RX frame.
  1007. * 3- update RX shared data to indicate last write index.
  1008. * 4- send interrupt.
  1009. * This could lead to RX race, driver could receive RX interrupt
  1010. * but the shared data changes does not reflect this.
  1011. * this could lead to RX race, RX periodic will solve this race
  1012. */
  1013. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1014. CSR_INT_PERIODIC_DIS);
  1015. iwl_rx_handle(priv);
  1016. /* Only set RX periodic if real RX is received. */
  1017. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1018. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1019. CSR_INT_PERIODIC_ENA);
  1020. priv->isr_stats.rx++;
  1021. }
  1022. if (inta & CSR_INT_BIT_FH_TX) {
  1023. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1024. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  1025. priv->isr_stats.tx++;
  1026. handled |= CSR_INT_BIT_FH_TX;
  1027. /* FH finished to write, send event */
  1028. priv->ucode_write_complete = 1;
  1029. wake_up_interruptible(&priv->wait_command_queue);
  1030. }
  1031. if (inta & ~handled) {
  1032. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1033. priv->isr_stats.unhandled++;
  1034. }
  1035. if (inta & ~(priv->inta_mask)) {
  1036. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1037. inta & ~priv->inta_mask);
  1038. }
  1039. /* Re-enable all interrupts */
  1040. /* only Re-enable if diabled by irq */
  1041. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1042. iwl_enable_interrupts(priv);
  1043. }
  1044. /******************************************************************************
  1045. *
  1046. * uCode download functions
  1047. *
  1048. ******************************************************************************/
  1049. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1050. {
  1051. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1052. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1053. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1054. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1055. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1056. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1057. }
  1058. static void iwl_nic_start(struct iwl_priv *priv)
  1059. {
  1060. /* Remove all resets to allow NIC to operate */
  1061. iwl_write32(priv, CSR_RESET, 0);
  1062. }
  1063. /**
  1064. * iwl_read_ucode - Read uCode images from disk file.
  1065. *
  1066. * Copy into buffers for card to fetch via bus-mastering
  1067. */
  1068. static int iwl_read_ucode(struct iwl_priv *priv)
  1069. {
  1070. struct iwl_ucode_header *ucode;
  1071. int ret = -EINVAL, index;
  1072. const struct firmware *ucode_raw;
  1073. const char *name_pre = priv->cfg->fw_name_pre;
  1074. const unsigned int api_max = priv->cfg->ucode_api_max;
  1075. const unsigned int api_min = priv->cfg->ucode_api_min;
  1076. char buf[25];
  1077. u8 *src;
  1078. size_t len;
  1079. u32 api_ver, build;
  1080. u32 inst_size, data_size, init_size, init_data_size, boot_size;
  1081. u16 eeprom_ver;
  1082. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1083. * request_firmware() is synchronous, file is in memory on return. */
  1084. for (index = api_max; index >= api_min; index--) {
  1085. sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
  1086. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1087. if (ret < 0) {
  1088. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1089. buf, ret);
  1090. if (ret == -ENOENT)
  1091. continue;
  1092. else
  1093. goto error;
  1094. } else {
  1095. if (index < api_max)
  1096. IWL_ERR(priv, "Loaded firmware %s, "
  1097. "which is deprecated. "
  1098. "Please use API v%u instead.\n",
  1099. buf, api_max);
  1100. IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
  1101. buf, ucode_raw->size);
  1102. break;
  1103. }
  1104. }
  1105. if (ret < 0)
  1106. goto error;
  1107. /* Make sure that we got at least the v1 header! */
  1108. if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
  1109. IWL_ERR(priv, "File size way too small!\n");
  1110. ret = -EINVAL;
  1111. goto err_release;
  1112. }
  1113. /* Data from ucode file: header followed by uCode images */
  1114. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1115. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1116. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1117. build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
  1118. inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
  1119. data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
  1120. init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
  1121. init_data_size =
  1122. priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
  1123. boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
  1124. src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
  1125. /* api_ver should match the api version forming part of the
  1126. * firmware filename ... but we don't check for that and only rely
  1127. * on the API version read from firmware header from here on forward */
  1128. if (api_ver < api_min || api_ver > api_max) {
  1129. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1130. "Driver supports v%u, firmware is v%u.\n",
  1131. api_max, api_ver);
  1132. priv->ucode_ver = 0;
  1133. ret = -EINVAL;
  1134. goto err_release;
  1135. }
  1136. if (api_ver != api_max)
  1137. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1138. "got v%u. New firmware can be obtained "
  1139. "from http://www.intellinuxwireless.org.\n",
  1140. api_max, api_ver);
  1141. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1142. IWL_UCODE_MAJOR(priv->ucode_ver),
  1143. IWL_UCODE_MINOR(priv->ucode_ver),
  1144. IWL_UCODE_API(priv->ucode_ver),
  1145. IWL_UCODE_SERIAL(priv->ucode_ver));
  1146. if (build)
  1147. IWL_DEBUG_INFO(priv, "Build %u\n", build);
  1148. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1149. IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
  1150. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  1151. ? "OTP" : "EEPROM", eeprom_ver);
  1152. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1153. priv->ucode_ver);
  1154. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1155. inst_size);
  1156. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1157. data_size);
  1158. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1159. init_size);
  1160. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1161. init_data_size);
  1162. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1163. boot_size);
  1164. /* Verify size of file vs. image size info in file's header */
  1165. if (ucode_raw->size !=
  1166. priv->cfg->ops->ucode->get_header_size(api_ver) +
  1167. inst_size + data_size + init_size +
  1168. init_data_size + boot_size) {
  1169. IWL_DEBUG_INFO(priv,
  1170. "uCode file size %d does not match expected size\n",
  1171. (int)ucode_raw->size);
  1172. ret = -EINVAL;
  1173. goto err_release;
  1174. }
  1175. /* Verify that uCode images will fit in card's SRAM */
  1176. if (inst_size > priv->hw_params.max_inst_size) {
  1177. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1178. inst_size);
  1179. ret = -EINVAL;
  1180. goto err_release;
  1181. }
  1182. if (data_size > priv->hw_params.max_data_size) {
  1183. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1184. data_size);
  1185. ret = -EINVAL;
  1186. goto err_release;
  1187. }
  1188. if (init_size > priv->hw_params.max_inst_size) {
  1189. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1190. init_size);
  1191. ret = -EINVAL;
  1192. goto err_release;
  1193. }
  1194. if (init_data_size > priv->hw_params.max_data_size) {
  1195. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1196. init_data_size);
  1197. ret = -EINVAL;
  1198. goto err_release;
  1199. }
  1200. if (boot_size > priv->hw_params.max_bsm_size) {
  1201. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1202. boot_size);
  1203. ret = -EINVAL;
  1204. goto err_release;
  1205. }
  1206. /* Allocate ucode buffers for card's bus-master loading ... */
  1207. /* Runtime instructions and 2 copies of data:
  1208. * 1) unmodified from disk
  1209. * 2) backup cache for save/restore during power-downs */
  1210. priv->ucode_code.len = inst_size;
  1211. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1212. priv->ucode_data.len = data_size;
  1213. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1214. priv->ucode_data_backup.len = data_size;
  1215. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1216. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1217. !priv->ucode_data_backup.v_addr)
  1218. goto err_pci_alloc;
  1219. /* Initialization instructions and data */
  1220. if (init_size && init_data_size) {
  1221. priv->ucode_init.len = init_size;
  1222. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1223. priv->ucode_init_data.len = init_data_size;
  1224. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1225. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1226. goto err_pci_alloc;
  1227. }
  1228. /* Bootstrap (instructions only, no data) */
  1229. if (boot_size) {
  1230. priv->ucode_boot.len = boot_size;
  1231. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1232. if (!priv->ucode_boot.v_addr)
  1233. goto err_pci_alloc;
  1234. }
  1235. /* Copy images into buffers for card's bus-master reads ... */
  1236. /* Runtime instructions (first block of data in file) */
  1237. len = inst_size;
  1238. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1239. memcpy(priv->ucode_code.v_addr, src, len);
  1240. src += len;
  1241. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1242. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1243. /* Runtime data (2nd block)
  1244. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1245. len = data_size;
  1246. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1247. memcpy(priv->ucode_data.v_addr, src, len);
  1248. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1249. src += len;
  1250. /* Initialization instructions (3rd block) */
  1251. if (init_size) {
  1252. len = init_size;
  1253. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1254. len);
  1255. memcpy(priv->ucode_init.v_addr, src, len);
  1256. src += len;
  1257. }
  1258. /* Initialization data (4th block) */
  1259. if (init_data_size) {
  1260. len = init_data_size;
  1261. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1262. len);
  1263. memcpy(priv->ucode_init_data.v_addr, src, len);
  1264. src += len;
  1265. }
  1266. /* Bootstrap instructions (5th block) */
  1267. len = boot_size;
  1268. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1269. memcpy(priv->ucode_boot.v_addr, src, len);
  1270. /* We have our copies now, allow OS release its copies */
  1271. release_firmware(ucode_raw);
  1272. return 0;
  1273. err_pci_alloc:
  1274. IWL_ERR(priv, "failed to allocate pci memory\n");
  1275. ret = -ENOMEM;
  1276. iwl_dealloc_ucode_pci(priv);
  1277. err_release:
  1278. release_firmware(ucode_raw);
  1279. error:
  1280. return ret;
  1281. }
  1282. #ifdef CONFIG_IWLWIFI_DEBUG
  1283. static const char *desc_lookup_text[] = {
  1284. "OK",
  1285. "FAIL",
  1286. "BAD_PARAM",
  1287. "BAD_CHECKSUM",
  1288. "NMI_INTERRUPT_WDG",
  1289. "SYSASSERT",
  1290. "FATAL_ERROR",
  1291. "BAD_COMMAND",
  1292. "HW_ERROR_TUNE_LOCK",
  1293. "HW_ERROR_TEMPERATURE",
  1294. "ILLEGAL_CHAN_FREQ",
  1295. "VCC_NOT_STABLE",
  1296. "FH_ERROR",
  1297. "NMI_INTERRUPT_HOST",
  1298. "NMI_INTERRUPT_ACTION_PT",
  1299. "NMI_INTERRUPT_UNKNOWN",
  1300. "UCODE_VERSION_MISMATCH",
  1301. "HW_ERROR_ABS_LOCK",
  1302. "HW_ERROR_CAL_LOCK_FAIL",
  1303. "NMI_INTERRUPT_INST_ACTION_PT",
  1304. "NMI_INTERRUPT_DATA_ACTION_PT",
  1305. "NMI_TRM_HW_ER",
  1306. "NMI_INTERRUPT_TRM",
  1307. "NMI_INTERRUPT_BREAK_POINT"
  1308. "DEBUG_0",
  1309. "DEBUG_1",
  1310. "DEBUG_2",
  1311. "DEBUG_3",
  1312. "UNKNOWN"
  1313. };
  1314. static const char *desc_lookup(int i)
  1315. {
  1316. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1317. if (i < 0 || i > max)
  1318. i = max;
  1319. return desc_lookup_text[i];
  1320. }
  1321. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1322. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1323. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1324. {
  1325. u32 data2, line;
  1326. u32 desc, time, count, base, data1;
  1327. u32 blink1, blink2, ilink1, ilink2;
  1328. if (priv->ucode_type == UCODE_INIT)
  1329. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1330. else
  1331. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1332. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1333. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  1334. return;
  1335. }
  1336. count = iwl_read_targ_mem(priv, base);
  1337. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1338. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1339. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1340. priv->status, count);
  1341. }
  1342. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1343. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1344. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1345. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1346. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1347. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1348. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1349. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1350. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1351. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
  1352. blink1, blink2, ilink1, ilink2);
  1353. IWL_ERR(priv, "Desc Time "
  1354. "data1 data2 line\n");
  1355. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1356. desc_lookup(desc), desc, time, data1, data2, line);
  1357. IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
  1358. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  1359. ilink1, ilink2);
  1360. }
  1361. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1362. /**
  1363. * iwl_print_event_log - Dump error event log to syslog
  1364. *
  1365. */
  1366. static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1367. u32 num_events, u32 mode)
  1368. {
  1369. u32 i;
  1370. u32 base; /* SRAM byte address of event log header */
  1371. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1372. u32 ptr; /* SRAM byte address of log data */
  1373. u32 ev, time, data; /* event log data */
  1374. if (num_events == 0)
  1375. return;
  1376. if (priv->ucode_type == UCODE_INIT)
  1377. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1378. else
  1379. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1380. if (mode == 0)
  1381. event_size = 2 * sizeof(u32);
  1382. else
  1383. event_size = 3 * sizeof(u32);
  1384. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1385. /* "time" is actually "data" for mode 0 (no timestamp).
  1386. * place event id # at far right for easier visual parsing. */
  1387. for (i = 0; i < num_events; i++) {
  1388. ev = iwl_read_targ_mem(priv, ptr);
  1389. ptr += sizeof(u32);
  1390. time = iwl_read_targ_mem(priv, ptr);
  1391. ptr += sizeof(u32);
  1392. if (mode == 0) {
  1393. /* data, ev */
  1394. trace_iwlwifi_dev_ucode_event(priv, 0, time, ev);
  1395. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
  1396. } else {
  1397. data = iwl_read_targ_mem(priv, ptr);
  1398. ptr += sizeof(u32);
  1399. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1400. time, data, ev);
  1401. trace_iwlwifi_dev_ucode_event(priv, time, data, ev);
  1402. }
  1403. }
  1404. }
  1405. void iwl_dump_nic_event_log(struct iwl_priv *priv)
  1406. {
  1407. u32 base; /* SRAM byte address of event log header */
  1408. u32 capacity; /* event log capacity in # entries */
  1409. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1410. u32 num_wraps; /* # times uCode wrapped to top of log */
  1411. u32 next_entry; /* index of next entry to be written by uCode */
  1412. u32 size; /* # entries that we'll print */
  1413. if (priv->ucode_type == UCODE_INIT)
  1414. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1415. else
  1416. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1417. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1418. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  1419. return;
  1420. }
  1421. /* event log header */
  1422. capacity = iwl_read_targ_mem(priv, base);
  1423. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1424. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1425. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1426. size = num_wraps ? capacity : next_entry;
  1427. /* bail out if nothing in log */
  1428. if (size == 0) {
  1429. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1430. return;
  1431. }
  1432. IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
  1433. size, num_wraps);
  1434. /* if uCode has wrapped back to top of log, start at the oldest entry,
  1435. * i.e the next one that uCode would fill. */
  1436. if (num_wraps)
  1437. iwl_print_event_log(priv, next_entry,
  1438. capacity - next_entry, mode);
  1439. /* (then/else) start at top of log */
  1440. iwl_print_event_log(priv, 0, next_entry, mode);
  1441. }
  1442. #endif
  1443. /**
  1444. * iwl_alive_start - called after REPLY_ALIVE notification received
  1445. * from protocol/runtime uCode (initialization uCode's
  1446. * Alive gets handled by iwl_init_alive_start()).
  1447. */
  1448. static void iwl_alive_start(struct iwl_priv *priv)
  1449. {
  1450. int ret = 0;
  1451. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1452. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1453. /* We had an error bringing up the hardware, so take it
  1454. * all the way back down so we can try again */
  1455. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1456. goto restart;
  1457. }
  1458. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1459. * This is a paranoid check, because we would not have gotten the
  1460. * "runtime" alive if code weren't properly loaded. */
  1461. if (iwl_verify_ucode(priv)) {
  1462. /* Runtime instruction load was bad;
  1463. * take it all the way back down so we can try again */
  1464. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1465. goto restart;
  1466. }
  1467. iwl_clear_stations_table(priv);
  1468. ret = priv->cfg->ops->lib->alive_notify(priv);
  1469. if (ret) {
  1470. IWL_WARN(priv,
  1471. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1472. goto restart;
  1473. }
  1474. /* After the ALIVE response, we can send host commands to the uCode */
  1475. set_bit(STATUS_ALIVE, &priv->status);
  1476. if (iwl_is_rfkill(priv))
  1477. return;
  1478. ieee80211_wake_queues(priv->hw);
  1479. priv->active_rate = priv->rates_mask;
  1480. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1481. /* Configure Tx antenna selection based on H/W config */
  1482. if (priv->cfg->ops->hcmd->set_tx_ant)
  1483. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  1484. if (iwl_is_associated(priv)) {
  1485. struct iwl_rxon_cmd *active_rxon =
  1486. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1487. /* apply any changes in staging */
  1488. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1489. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1490. } else {
  1491. /* Initialize our rx_config data */
  1492. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1493. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1494. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1495. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1496. }
  1497. /* Configure Bluetooth device coexistence support */
  1498. iwl_send_bt_config(priv);
  1499. iwl_reset_run_time_calib(priv);
  1500. /* Configure the adapter for unassociated operation */
  1501. iwlcore_commit_rxon(priv);
  1502. /* At this point, the NIC is initialized and operational */
  1503. iwl_rf_kill_ct_config(priv);
  1504. iwl_leds_init(priv);
  1505. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1506. set_bit(STATUS_READY, &priv->status);
  1507. wake_up_interruptible(&priv->wait_command_queue);
  1508. iwl_power_update_mode(priv, true);
  1509. /* reassociate for ADHOC mode */
  1510. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  1511. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  1512. priv->vif);
  1513. if (beacon)
  1514. iwl_mac_beacon_update(priv->hw, beacon);
  1515. }
  1516. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1517. iwl_set_mode(priv, priv->iw_mode);
  1518. return;
  1519. restart:
  1520. queue_work(priv->workqueue, &priv->restart);
  1521. }
  1522. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1523. static void __iwl_down(struct iwl_priv *priv)
  1524. {
  1525. unsigned long flags;
  1526. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1527. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1528. if (!exit_pending)
  1529. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1530. iwl_clear_stations_table(priv);
  1531. /* Unblock any waiting calls */
  1532. wake_up_interruptible_all(&priv->wait_command_queue);
  1533. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1534. * exiting the module */
  1535. if (!exit_pending)
  1536. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1537. /* stop and reset the on-board processor */
  1538. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1539. /* tell the device to stop sending interrupts */
  1540. spin_lock_irqsave(&priv->lock, flags);
  1541. iwl_disable_interrupts(priv);
  1542. spin_unlock_irqrestore(&priv->lock, flags);
  1543. iwl_synchronize_irq(priv);
  1544. if (priv->mac80211_registered)
  1545. ieee80211_stop_queues(priv->hw);
  1546. /* If we have not previously called iwl_init() then
  1547. * clear all bits but the RF Kill bit and return */
  1548. if (!iwl_is_init(priv)) {
  1549. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1550. STATUS_RF_KILL_HW |
  1551. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1552. STATUS_GEO_CONFIGURED |
  1553. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1554. STATUS_EXIT_PENDING;
  1555. goto exit;
  1556. }
  1557. /* ...otherwise clear out all the status bits but the RF Kill
  1558. * bit and continue taking the NIC down. */
  1559. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1560. STATUS_RF_KILL_HW |
  1561. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1562. STATUS_GEO_CONFIGURED |
  1563. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1564. STATUS_FW_ERROR |
  1565. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1566. STATUS_EXIT_PENDING;
  1567. /* device going down, Stop using ICT table */
  1568. iwl_disable_ict(priv);
  1569. spin_lock_irqsave(&priv->lock, flags);
  1570. iwl_clear_bit(priv, CSR_GP_CNTRL,
  1571. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1572. spin_unlock_irqrestore(&priv->lock, flags);
  1573. iwl_txq_ctx_stop(priv);
  1574. iwl_rxq_stop(priv);
  1575. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  1576. APMG_CLK_VAL_DMA_CLK_RQT);
  1577. udelay(5);
  1578. /* Stop the device, and put it in low power state */
  1579. priv->cfg->ops->lib->apm_ops.stop(priv);
  1580. exit:
  1581. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1582. if (priv->ibss_beacon)
  1583. dev_kfree_skb(priv->ibss_beacon);
  1584. priv->ibss_beacon = NULL;
  1585. /* clear out any free frames */
  1586. iwl_clear_free_frames(priv);
  1587. }
  1588. static void iwl_down(struct iwl_priv *priv)
  1589. {
  1590. mutex_lock(&priv->mutex);
  1591. __iwl_down(priv);
  1592. mutex_unlock(&priv->mutex);
  1593. iwl_cancel_deferred_work(priv);
  1594. }
  1595. #define HW_READY_TIMEOUT (50)
  1596. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1597. {
  1598. int ret = 0;
  1599. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1600. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1601. /* See if we got it */
  1602. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1603. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1604. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1605. HW_READY_TIMEOUT);
  1606. if (ret != -ETIMEDOUT)
  1607. priv->hw_ready = true;
  1608. else
  1609. priv->hw_ready = false;
  1610. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1611. (priv->hw_ready == 1) ? "ready" : "not ready");
  1612. return ret;
  1613. }
  1614. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1615. {
  1616. int ret = 0;
  1617. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
  1618. ret = iwl_set_hw_ready(priv);
  1619. if (priv->hw_ready)
  1620. return ret;
  1621. /* If HW is not ready, prepare the conditions to check again */
  1622. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1623. CSR_HW_IF_CONFIG_REG_PREPARE);
  1624. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1625. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1626. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1627. /* HW should be ready by now, check again. */
  1628. if (ret != -ETIMEDOUT)
  1629. iwl_set_hw_ready(priv);
  1630. return ret;
  1631. }
  1632. #define MAX_HW_RESTARTS 5
  1633. static int __iwl_up(struct iwl_priv *priv)
  1634. {
  1635. int i;
  1636. int ret;
  1637. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1638. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1639. return -EIO;
  1640. }
  1641. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1642. IWL_ERR(priv, "ucode not available for device bringup\n");
  1643. return -EIO;
  1644. }
  1645. iwl_prepare_card_hw(priv);
  1646. if (!priv->hw_ready) {
  1647. IWL_WARN(priv, "Exit HW not ready\n");
  1648. return -EIO;
  1649. }
  1650. /* If platform's RF_KILL switch is NOT set to KILL */
  1651. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1652. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1653. else
  1654. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1655. if (iwl_is_rfkill(priv)) {
  1656. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1657. iwl_enable_interrupts(priv);
  1658. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1659. return 0;
  1660. }
  1661. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1662. ret = iwl_hw_nic_init(priv);
  1663. if (ret) {
  1664. IWL_ERR(priv, "Unable to init nic\n");
  1665. return ret;
  1666. }
  1667. /* make sure rfkill handshake bits are cleared */
  1668. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1669. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1670. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1671. /* clear (again), then enable host interrupts */
  1672. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1673. iwl_enable_interrupts(priv);
  1674. /* really make sure rfkill handshake bits are cleared */
  1675. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1676. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1677. /* Copy original ucode data image from disk into backup cache.
  1678. * This will be used to initialize the on-board processor's
  1679. * data SRAM for a clean start when the runtime program first loads. */
  1680. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1681. priv->ucode_data.len);
  1682. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1683. iwl_clear_stations_table(priv);
  1684. /* load bootstrap state machine,
  1685. * load bootstrap program into processor's memory,
  1686. * prepare to load the "initialize" uCode */
  1687. ret = priv->cfg->ops->lib->load_ucode(priv);
  1688. if (ret) {
  1689. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1690. ret);
  1691. continue;
  1692. }
  1693. /* start card; "initialize" will load runtime ucode */
  1694. iwl_nic_start(priv);
  1695. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1696. return 0;
  1697. }
  1698. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1699. __iwl_down(priv);
  1700. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1701. /* tried to restart and config the device for as long as our
  1702. * patience could withstand */
  1703. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1704. return -EIO;
  1705. }
  1706. /*****************************************************************************
  1707. *
  1708. * Workqueue callbacks
  1709. *
  1710. *****************************************************************************/
  1711. static void iwl_bg_init_alive_start(struct work_struct *data)
  1712. {
  1713. struct iwl_priv *priv =
  1714. container_of(data, struct iwl_priv, init_alive_start.work);
  1715. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1716. return;
  1717. mutex_lock(&priv->mutex);
  1718. priv->cfg->ops->lib->init_alive_start(priv);
  1719. mutex_unlock(&priv->mutex);
  1720. }
  1721. static void iwl_bg_alive_start(struct work_struct *data)
  1722. {
  1723. struct iwl_priv *priv =
  1724. container_of(data, struct iwl_priv, alive_start.work);
  1725. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1726. return;
  1727. /* enable dram interrupt */
  1728. iwl_reset_ict(priv);
  1729. mutex_lock(&priv->mutex);
  1730. iwl_alive_start(priv);
  1731. mutex_unlock(&priv->mutex);
  1732. }
  1733. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  1734. {
  1735. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1736. run_time_calib_work);
  1737. mutex_lock(&priv->mutex);
  1738. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1739. test_bit(STATUS_SCANNING, &priv->status)) {
  1740. mutex_unlock(&priv->mutex);
  1741. return;
  1742. }
  1743. if (priv->start_calib) {
  1744. iwl_chain_noise_calibration(priv, &priv->statistics);
  1745. iwl_sensitivity_calibration(priv, &priv->statistics);
  1746. }
  1747. mutex_unlock(&priv->mutex);
  1748. return;
  1749. }
  1750. static void iwl_bg_up(struct work_struct *data)
  1751. {
  1752. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  1753. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1754. return;
  1755. mutex_lock(&priv->mutex);
  1756. __iwl_up(priv);
  1757. mutex_unlock(&priv->mutex);
  1758. }
  1759. static void iwl_bg_restart(struct work_struct *data)
  1760. {
  1761. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  1762. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1763. return;
  1764. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  1765. mutex_lock(&priv->mutex);
  1766. priv->vif = NULL;
  1767. priv->is_open = 0;
  1768. mutex_unlock(&priv->mutex);
  1769. iwl_down(priv);
  1770. ieee80211_restart_hw(priv->hw);
  1771. } else {
  1772. iwl_down(priv);
  1773. queue_work(priv->workqueue, &priv->up);
  1774. }
  1775. }
  1776. static void iwl_bg_rx_replenish(struct work_struct *data)
  1777. {
  1778. struct iwl_priv *priv =
  1779. container_of(data, struct iwl_priv, rx_replenish);
  1780. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1781. return;
  1782. mutex_lock(&priv->mutex);
  1783. iwl_rx_replenish(priv);
  1784. mutex_unlock(&priv->mutex);
  1785. }
  1786. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  1787. void iwl_post_associate(struct iwl_priv *priv)
  1788. {
  1789. struct ieee80211_conf *conf = NULL;
  1790. int ret = 0;
  1791. unsigned long flags;
  1792. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1793. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  1794. return;
  1795. }
  1796. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  1797. priv->assoc_id, priv->active_rxon.bssid_addr);
  1798. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1799. return;
  1800. if (!priv->vif || !priv->is_open)
  1801. return;
  1802. iwl_scan_cancel_timeout(priv, 200);
  1803. conf = ieee80211_get_hw_conf(priv->hw);
  1804. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1805. iwlcore_commit_rxon(priv);
  1806. iwl_setup_rxon_timing(priv);
  1807. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1808. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1809. if (ret)
  1810. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1811. "Attempting to continue.\n");
  1812. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1813. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  1814. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1815. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1816. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1817. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  1818. priv->assoc_id, priv->beacon_int);
  1819. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1820. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1821. else
  1822. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1823. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1824. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1825. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1826. else
  1827. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1828. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1829. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1830. }
  1831. iwlcore_commit_rxon(priv);
  1832. switch (priv->iw_mode) {
  1833. case NL80211_IFTYPE_STATION:
  1834. break;
  1835. case NL80211_IFTYPE_ADHOC:
  1836. /* assume default assoc id */
  1837. priv->assoc_id = 1;
  1838. iwl_rxon_add_station(priv, priv->bssid, 0);
  1839. iwl_send_beacon_cmd(priv);
  1840. break;
  1841. default:
  1842. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  1843. __func__, priv->iw_mode);
  1844. break;
  1845. }
  1846. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1847. priv->assoc_station_added = 1;
  1848. spin_lock_irqsave(&priv->lock, flags);
  1849. iwl_activate_qos(priv, 0);
  1850. spin_unlock_irqrestore(&priv->lock, flags);
  1851. /* the chain noise calibration will enabled PM upon completion
  1852. * If chain noise has already been run, then we need to enable
  1853. * power management here */
  1854. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  1855. iwl_power_update_mode(priv, false);
  1856. /* Enable Rx differential gain and sensitivity calibrations */
  1857. iwl_chain_noise_reset(priv);
  1858. priv->start_calib = 1;
  1859. }
  1860. /*****************************************************************************
  1861. *
  1862. * mac80211 entry point functions
  1863. *
  1864. *****************************************************************************/
  1865. #define UCODE_READY_TIMEOUT (4 * HZ)
  1866. /*
  1867. * Not a mac80211 entry point function, but it fits in with all the
  1868. * other mac80211 functions grouped here.
  1869. */
  1870. static int iwl_setup_mac(struct iwl_priv *priv)
  1871. {
  1872. int ret;
  1873. struct ieee80211_hw *hw = priv->hw;
  1874. hw->rate_control_algorithm = "iwl-agn-rs";
  1875. /* Tell mac80211 our characteristics */
  1876. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  1877. IEEE80211_HW_NOISE_DBM |
  1878. IEEE80211_HW_AMPDU_AGGREGATION |
  1879. IEEE80211_HW_SPECTRUM_MGMT;
  1880. if (!priv->cfg->broken_powersave)
  1881. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  1882. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  1883. hw->wiphy->interface_modes =
  1884. BIT(NL80211_IFTYPE_STATION) |
  1885. BIT(NL80211_IFTYPE_ADHOC);
  1886. hw->wiphy->custom_regulatory = true;
  1887. /* Firmware does not support this */
  1888. hw->wiphy->disable_beacon_hints = true;
  1889. /*
  1890. * For now, disable PS by default because it affects
  1891. * RX performance significantly.
  1892. */
  1893. hw->wiphy->ps_default = false;
  1894. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  1895. /* we create the 802.11 header and a zero-length SSID element */
  1896. hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
  1897. /* Default value; 4 EDCA QOS priorities */
  1898. hw->queues = 4;
  1899. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  1900. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  1901. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  1902. &priv->bands[IEEE80211_BAND_2GHZ];
  1903. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  1904. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  1905. &priv->bands[IEEE80211_BAND_5GHZ];
  1906. ret = ieee80211_register_hw(priv->hw);
  1907. if (ret) {
  1908. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  1909. return ret;
  1910. }
  1911. priv->mac80211_registered = 1;
  1912. return 0;
  1913. }
  1914. static int iwl_mac_start(struct ieee80211_hw *hw)
  1915. {
  1916. struct iwl_priv *priv = hw->priv;
  1917. int ret;
  1918. IWL_DEBUG_MAC80211(priv, "enter\n");
  1919. /* we should be verifying the device is ready to be opened */
  1920. mutex_lock(&priv->mutex);
  1921. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  1922. * ucode filename and max sizes are card-specific. */
  1923. if (!priv->ucode_code.len) {
  1924. ret = iwl_read_ucode(priv);
  1925. if (ret) {
  1926. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  1927. mutex_unlock(&priv->mutex);
  1928. return ret;
  1929. }
  1930. }
  1931. ret = __iwl_up(priv);
  1932. mutex_unlock(&priv->mutex);
  1933. if (ret)
  1934. return ret;
  1935. if (iwl_is_rfkill(priv))
  1936. goto out;
  1937. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  1938. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  1939. * mac80211 will not be run successfully. */
  1940. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  1941. test_bit(STATUS_READY, &priv->status),
  1942. UCODE_READY_TIMEOUT);
  1943. if (!ret) {
  1944. if (!test_bit(STATUS_READY, &priv->status)) {
  1945. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  1946. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  1947. return -ETIMEDOUT;
  1948. }
  1949. }
  1950. iwl_led_start(priv);
  1951. out:
  1952. priv->is_open = 1;
  1953. IWL_DEBUG_MAC80211(priv, "leave\n");
  1954. return 0;
  1955. }
  1956. static void iwl_mac_stop(struct ieee80211_hw *hw)
  1957. {
  1958. struct iwl_priv *priv = hw->priv;
  1959. IWL_DEBUG_MAC80211(priv, "enter\n");
  1960. if (!priv->is_open)
  1961. return;
  1962. priv->is_open = 0;
  1963. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  1964. /* stop mac, cancel any scan request and clear
  1965. * RXON_FILTER_ASSOC_MSK BIT
  1966. */
  1967. mutex_lock(&priv->mutex);
  1968. iwl_scan_cancel_timeout(priv, 100);
  1969. mutex_unlock(&priv->mutex);
  1970. }
  1971. iwl_down(priv);
  1972. flush_workqueue(priv->workqueue);
  1973. /* enable interrupts again in order to receive rfkill changes */
  1974. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1975. iwl_enable_interrupts(priv);
  1976. IWL_DEBUG_MAC80211(priv, "leave\n");
  1977. }
  1978. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  1979. {
  1980. struct iwl_priv *priv = hw->priv;
  1981. IWL_DEBUG_MACDUMP(priv, "enter\n");
  1982. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  1983. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  1984. if (iwl_tx_skb(priv, skb))
  1985. dev_kfree_skb_any(skb);
  1986. IWL_DEBUG_MACDUMP(priv, "leave\n");
  1987. return NETDEV_TX_OK;
  1988. }
  1989. void iwl_config_ap(struct iwl_priv *priv)
  1990. {
  1991. int ret = 0;
  1992. unsigned long flags;
  1993. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1994. return;
  1995. /* The following should be done only at AP bring up */
  1996. if (!iwl_is_associated(priv)) {
  1997. /* RXON - unassoc (to set timing command) */
  1998. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1999. iwlcore_commit_rxon(priv);
  2000. /* RXON Timing */
  2001. iwl_setup_rxon_timing(priv);
  2002. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2003. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2004. if (ret)
  2005. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2006. "Attempting to continue.\n");
  2007. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2008. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2009. /* FIXME: what should be the assoc_id for AP? */
  2010. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  2011. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2012. priv->staging_rxon.flags |=
  2013. RXON_FLG_SHORT_PREAMBLE_MSK;
  2014. else
  2015. priv->staging_rxon.flags &=
  2016. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2017. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2018. if (priv->assoc_capability &
  2019. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2020. priv->staging_rxon.flags |=
  2021. RXON_FLG_SHORT_SLOT_MSK;
  2022. else
  2023. priv->staging_rxon.flags &=
  2024. ~RXON_FLG_SHORT_SLOT_MSK;
  2025. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2026. priv->staging_rxon.flags &=
  2027. ~RXON_FLG_SHORT_SLOT_MSK;
  2028. }
  2029. /* restore RXON assoc */
  2030. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2031. iwlcore_commit_rxon(priv);
  2032. spin_lock_irqsave(&priv->lock, flags);
  2033. iwl_activate_qos(priv, 1);
  2034. spin_unlock_irqrestore(&priv->lock, flags);
  2035. iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
  2036. }
  2037. iwl_send_beacon_cmd(priv);
  2038. /* FIXME - we need to add code here to detect a totally new
  2039. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2040. * clear sta table, add BCAST sta... */
  2041. }
  2042. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  2043. struct ieee80211_key_conf *keyconf, const u8 *addr,
  2044. u32 iv32, u16 *phase1key)
  2045. {
  2046. struct iwl_priv *priv = hw->priv;
  2047. IWL_DEBUG_MAC80211(priv, "enter\n");
  2048. iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
  2049. IWL_DEBUG_MAC80211(priv, "leave\n");
  2050. }
  2051. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2052. struct ieee80211_vif *vif,
  2053. struct ieee80211_sta *sta,
  2054. struct ieee80211_key_conf *key)
  2055. {
  2056. struct iwl_priv *priv = hw->priv;
  2057. const u8 *addr;
  2058. int ret;
  2059. u8 sta_id;
  2060. bool is_default_wep_key = false;
  2061. IWL_DEBUG_MAC80211(priv, "enter\n");
  2062. if (priv->cfg->mod_params->sw_crypto) {
  2063. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2064. return -EOPNOTSUPP;
  2065. }
  2066. addr = sta ? sta->addr : iwl_bcast_addr;
  2067. sta_id = iwl_find_station(priv, addr);
  2068. if (sta_id == IWL_INVALID_STATION) {
  2069. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  2070. addr);
  2071. return -EINVAL;
  2072. }
  2073. mutex_lock(&priv->mutex);
  2074. iwl_scan_cancel_timeout(priv, 100);
  2075. mutex_unlock(&priv->mutex);
  2076. /* If we are getting WEP group key and we didn't receive any key mapping
  2077. * so far, we are in legacy wep mode (group key only), otherwise we are
  2078. * in 1X mode.
  2079. * In legacy wep mode, we use another host command to the uCode */
  2080. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  2081. priv->iw_mode != NL80211_IFTYPE_AP) {
  2082. if (cmd == SET_KEY)
  2083. is_default_wep_key = !priv->key_mapping_key;
  2084. else
  2085. is_default_wep_key =
  2086. (key->hw_key_idx == HW_KEY_DEFAULT);
  2087. }
  2088. switch (cmd) {
  2089. case SET_KEY:
  2090. if (is_default_wep_key)
  2091. ret = iwl_set_default_wep_key(priv, key);
  2092. else
  2093. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2094. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2095. break;
  2096. case DISABLE_KEY:
  2097. if (is_default_wep_key)
  2098. ret = iwl_remove_default_wep_key(priv, key);
  2099. else
  2100. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2101. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2102. break;
  2103. default:
  2104. ret = -EINVAL;
  2105. }
  2106. IWL_DEBUG_MAC80211(priv, "leave\n");
  2107. return ret;
  2108. }
  2109. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2110. enum ieee80211_ampdu_mlme_action action,
  2111. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2112. {
  2113. struct iwl_priv *priv = hw->priv;
  2114. int ret;
  2115. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2116. sta->addr, tid);
  2117. if (!(priv->cfg->sku & IWL_SKU_N))
  2118. return -EACCES;
  2119. switch (action) {
  2120. case IEEE80211_AMPDU_RX_START:
  2121. IWL_DEBUG_HT(priv, "start Rx\n");
  2122. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  2123. case IEEE80211_AMPDU_RX_STOP:
  2124. IWL_DEBUG_HT(priv, "stop Rx\n");
  2125. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  2126. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2127. return 0;
  2128. else
  2129. return ret;
  2130. case IEEE80211_AMPDU_TX_START:
  2131. IWL_DEBUG_HT(priv, "start Tx\n");
  2132. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  2133. case IEEE80211_AMPDU_TX_STOP:
  2134. IWL_DEBUG_HT(priv, "stop Tx\n");
  2135. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  2136. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2137. return 0;
  2138. else
  2139. return ret;
  2140. default:
  2141. IWL_DEBUG_HT(priv, "unknown\n");
  2142. return -EINVAL;
  2143. break;
  2144. }
  2145. return 0;
  2146. }
  2147. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  2148. struct ieee80211_low_level_stats *stats)
  2149. {
  2150. struct iwl_priv *priv = hw->priv;
  2151. priv = hw->priv;
  2152. IWL_DEBUG_MAC80211(priv, "enter\n");
  2153. IWL_DEBUG_MAC80211(priv, "leave\n");
  2154. return 0;
  2155. }
  2156. /*****************************************************************************
  2157. *
  2158. * sysfs attributes
  2159. *
  2160. *****************************************************************************/
  2161. #ifdef CONFIG_IWLWIFI_DEBUG
  2162. /*
  2163. * The following adds a new attribute to the sysfs representation
  2164. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2165. * used for controlling the debug level.
  2166. *
  2167. * See the level definitions in iwl for details.
  2168. *
  2169. * The debug_level being managed using sysfs below is a per device debug
  2170. * level that is used instead of the global debug level if it (the per
  2171. * device debug level) is set.
  2172. */
  2173. static ssize_t show_debug_level(struct device *d,
  2174. struct device_attribute *attr, char *buf)
  2175. {
  2176. struct iwl_priv *priv = dev_get_drvdata(d);
  2177. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2178. }
  2179. static ssize_t store_debug_level(struct device *d,
  2180. struct device_attribute *attr,
  2181. const char *buf, size_t count)
  2182. {
  2183. struct iwl_priv *priv = dev_get_drvdata(d);
  2184. unsigned long val;
  2185. int ret;
  2186. ret = strict_strtoul(buf, 0, &val);
  2187. if (ret)
  2188. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2189. else {
  2190. priv->debug_level = val;
  2191. if (iwl_alloc_traffic_mem(priv))
  2192. IWL_ERR(priv,
  2193. "Not enough memory to generate traffic log\n");
  2194. }
  2195. return strnlen(buf, count);
  2196. }
  2197. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2198. show_debug_level, store_debug_level);
  2199. #endif /* CONFIG_IWLWIFI_DEBUG */
  2200. static ssize_t show_temperature(struct device *d,
  2201. struct device_attribute *attr, char *buf)
  2202. {
  2203. struct iwl_priv *priv = dev_get_drvdata(d);
  2204. if (!iwl_is_alive(priv))
  2205. return -EAGAIN;
  2206. return sprintf(buf, "%d\n", priv->temperature);
  2207. }
  2208. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2209. static ssize_t show_tx_power(struct device *d,
  2210. struct device_attribute *attr, char *buf)
  2211. {
  2212. struct iwl_priv *priv = dev_get_drvdata(d);
  2213. if (!iwl_is_ready_rf(priv))
  2214. return sprintf(buf, "off\n");
  2215. else
  2216. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2217. }
  2218. static ssize_t store_tx_power(struct device *d,
  2219. struct device_attribute *attr,
  2220. const char *buf, size_t count)
  2221. {
  2222. struct iwl_priv *priv = dev_get_drvdata(d);
  2223. unsigned long val;
  2224. int ret;
  2225. ret = strict_strtoul(buf, 10, &val);
  2226. if (ret)
  2227. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2228. else {
  2229. ret = iwl_set_tx_power(priv, val, false);
  2230. if (ret)
  2231. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  2232. ret);
  2233. else
  2234. ret = count;
  2235. }
  2236. return ret;
  2237. }
  2238. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2239. static ssize_t show_flags(struct device *d,
  2240. struct device_attribute *attr, char *buf)
  2241. {
  2242. struct iwl_priv *priv = dev_get_drvdata(d);
  2243. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  2244. }
  2245. static ssize_t store_flags(struct device *d,
  2246. struct device_attribute *attr,
  2247. const char *buf, size_t count)
  2248. {
  2249. struct iwl_priv *priv = dev_get_drvdata(d);
  2250. unsigned long val;
  2251. u32 flags;
  2252. int ret = strict_strtoul(buf, 0, &val);
  2253. if (ret)
  2254. return ret;
  2255. flags = (u32)val;
  2256. mutex_lock(&priv->mutex);
  2257. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  2258. /* Cancel any currently running scans... */
  2259. if (iwl_scan_cancel_timeout(priv, 100))
  2260. IWL_WARN(priv, "Could not cancel scan.\n");
  2261. else {
  2262. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  2263. priv->staging_rxon.flags = cpu_to_le32(flags);
  2264. iwlcore_commit_rxon(priv);
  2265. }
  2266. }
  2267. mutex_unlock(&priv->mutex);
  2268. return count;
  2269. }
  2270. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2271. static ssize_t show_filter_flags(struct device *d,
  2272. struct device_attribute *attr, char *buf)
  2273. {
  2274. struct iwl_priv *priv = dev_get_drvdata(d);
  2275. return sprintf(buf, "0x%04X\n",
  2276. le32_to_cpu(priv->active_rxon.filter_flags));
  2277. }
  2278. static ssize_t store_filter_flags(struct device *d,
  2279. struct device_attribute *attr,
  2280. const char *buf, size_t count)
  2281. {
  2282. struct iwl_priv *priv = dev_get_drvdata(d);
  2283. unsigned long val;
  2284. u32 filter_flags;
  2285. int ret = strict_strtoul(buf, 0, &val);
  2286. if (ret)
  2287. return ret;
  2288. filter_flags = (u32)val;
  2289. mutex_lock(&priv->mutex);
  2290. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  2291. /* Cancel any currently running scans... */
  2292. if (iwl_scan_cancel_timeout(priv, 100))
  2293. IWL_WARN(priv, "Could not cancel scan.\n");
  2294. else {
  2295. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2296. "0x%04X\n", filter_flags);
  2297. priv->staging_rxon.filter_flags =
  2298. cpu_to_le32(filter_flags);
  2299. iwlcore_commit_rxon(priv);
  2300. }
  2301. }
  2302. mutex_unlock(&priv->mutex);
  2303. return count;
  2304. }
  2305. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2306. store_filter_flags);
  2307. static ssize_t show_statistics(struct device *d,
  2308. struct device_attribute *attr, char *buf)
  2309. {
  2310. struct iwl_priv *priv = dev_get_drvdata(d);
  2311. u32 size = sizeof(struct iwl_notif_statistics);
  2312. u32 len = 0, ofs = 0;
  2313. u8 *data = (u8 *)&priv->statistics;
  2314. int rc = 0;
  2315. if (!iwl_is_alive(priv))
  2316. return -EAGAIN;
  2317. mutex_lock(&priv->mutex);
  2318. rc = iwl_send_statistics_request(priv, 0);
  2319. mutex_unlock(&priv->mutex);
  2320. if (rc) {
  2321. len = sprintf(buf,
  2322. "Error sending statistics request: 0x%08X\n", rc);
  2323. return len;
  2324. }
  2325. while (size && (PAGE_SIZE - len)) {
  2326. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2327. PAGE_SIZE - len, 1);
  2328. len = strlen(buf);
  2329. if (PAGE_SIZE - len)
  2330. buf[len++] = '\n';
  2331. ofs += 16;
  2332. size -= min(size, 16U);
  2333. }
  2334. return len;
  2335. }
  2336. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2337. static ssize_t show_rts_ht_protection(struct device *d,
  2338. struct device_attribute *attr, char *buf)
  2339. {
  2340. struct iwl_priv *priv = dev_get_drvdata(d);
  2341. return sprintf(buf, "%s\n",
  2342. priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
  2343. }
  2344. static ssize_t store_rts_ht_protection(struct device *d,
  2345. struct device_attribute *attr,
  2346. const char *buf, size_t count)
  2347. {
  2348. struct iwl_priv *priv = dev_get_drvdata(d);
  2349. unsigned long val;
  2350. int ret;
  2351. ret = strict_strtoul(buf, 10, &val);
  2352. if (ret)
  2353. IWL_INFO(priv, "Input is not in decimal form.\n");
  2354. else {
  2355. if (!iwl_is_associated(priv))
  2356. priv->cfg->use_rts_for_ht = val ? true : false;
  2357. else
  2358. IWL_ERR(priv, "Sta associated with AP - "
  2359. "Change protection mechanism is not allowed\n");
  2360. ret = count;
  2361. }
  2362. return ret;
  2363. }
  2364. static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
  2365. show_rts_ht_protection, store_rts_ht_protection);
  2366. /*****************************************************************************
  2367. *
  2368. * driver setup and teardown
  2369. *
  2370. *****************************************************************************/
  2371. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2372. {
  2373. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2374. init_waitqueue_head(&priv->wait_command_queue);
  2375. INIT_WORK(&priv->up, iwl_bg_up);
  2376. INIT_WORK(&priv->restart, iwl_bg_restart);
  2377. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2378. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2379. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2380. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2381. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2382. iwl_setup_scan_deferred_work(priv);
  2383. if (priv->cfg->ops->lib->setup_deferred_work)
  2384. priv->cfg->ops->lib->setup_deferred_work(priv);
  2385. init_timer(&priv->statistics_periodic);
  2386. priv->statistics_periodic.data = (unsigned long)priv;
  2387. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2388. if (!priv->cfg->use_isr_legacy)
  2389. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2390. iwl_irq_tasklet, (unsigned long)priv);
  2391. else
  2392. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2393. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2394. }
  2395. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2396. {
  2397. if (priv->cfg->ops->lib->cancel_deferred_work)
  2398. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2399. cancel_delayed_work_sync(&priv->init_alive_start);
  2400. cancel_delayed_work(&priv->scan_check);
  2401. cancel_delayed_work(&priv->alive_start);
  2402. cancel_work_sync(&priv->beacon_update);
  2403. del_timer_sync(&priv->statistics_periodic);
  2404. }
  2405. static struct attribute *iwl_sysfs_entries[] = {
  2406. &dev_attr_flags.attr,
  2407. &dev_attr_filter_flags.attr,
  2408. &dev_attr_statistics.attr,
  2409. &dev_attr_temperature.attr,
  2410. &dev_attr_tx_power.attr,
  2411. &dev_attr_rts_ht_protection.attr,
  2412. #ifdef CONFIG_IWLWIFI_DEBUG
  2413. &dev_attr_debug_level.attr,
  2414. #endif
  2415. NULL
  2416. };
  2417. static struct attribute_group iwl_attribute_group = {
  2418. .name = NULL, /* put in device directory */
  2419. .attrs = iwl_sysfs_entries,
  2420. };
  2421. static struct ieee80211_ops iwl_hw_ops = {
  2422. .tx = iwl_mac_tx,
  2423. .start = iwl_mac_start,
  2424. .stop = iwl_mac_stop,
  2425. .add_interface = iwl_mac_add_interface,
  2426. .remove_interface = iwl_mac_remove_interface,
  2427. .config = iwl_mac_config,
  2428. .configure_filter = iwl_configure_filter,
  2429. .set_key = iwl_mac_set_key,
  2430. .update_tkip_key = iwl_mac_update_tkip_key,
  2431. .get_stats = iwl_mac_get_stats,
  2432. .get_tx_stats = iwl_mac_get_tx_stats,
  2433. .conf_tx = iwl_mac_conf_tx,
  2434. .reset_tsf = iwl_mac_reset_tsf,
  2435. .bss_info_changed = iwl_bss_info_changed,
  2436. .ampdu_action = iwl_mac_ampdu_action,
  2437. .hw_scan = iwl_mac_hw_scan
  2438. };
  2439. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2440. {
  2441. int err = 0;
  2442. struct iwl_priv *priv;
  2443. struct ieee80211_hw *hw;
  2444. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2445. unsigned long flags;
  2446. u16 pci_cmd;
  2447. /************************
  2448. * 1. Allocating HW data
  2449. ************************/
  2450. /* Disabling hardware scan means that mac80211 will perform scans
  2451. * "the hard way", rather than using device's scan. */
  2452. if (cfg->mod_params->disable_hw_scan) {
  2453. if (iwl_debug_level & IWL_DL_INFO)
  2454. dev_printk(KERN_DEBUG, &(pdev->dev),
  2455. "Disabling hw_scan\n");
  2456. iwl_hw_ops.hw_scan = NULL;
  2457. }
  2458. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2459. if (!hw) {
  2460. err = -ENOMEM;
  2461. goto out;
  2462. }
  2463. priv = hw->priv;
  2464. /* At this point both hw and priv are allocated. */
  2465. SET_IEEE80211_DEV(hw, &pdev->dev);
  2466. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2467. priv->cfg = cfg;
  2468. priv->pci_dev = pdev;
  2469. priv->inta_mask = CSR_INI_SET_MASK;
  2470. #ifdef CONFIG_IWLWIFI_DEBUG
  2471. atomic_set(&priv->restrict_refcnt, 0);
  2472. #endif
  2473. if (iwl_alloc_traffic_mem(priv))
  2474. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  2475. /**************************
  2476. * 2. Initializing PCI bus
  2477. **************************/
  2478. if (pci_enable_device(pdev)) {
  2479. err = -ENODEV;
  2480. goto out_ieee80211_free_hw;
  2481. }
  2482. pci_set_master(pdev);
  2483. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2484. if (!err)
  2485. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2486. if (err) {
  2487. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2488. if (!err)
  2489. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2490. /* both attempts failed: */
  2491. if (err) {
  2492. IWL_WARN(priv, "No suitable DMA available.\n");
  2493. goto out_pci_disable_device;
  2494. }
  2495. }
  2496. err = pci_request_regions(pdev, DRV_NAME);
  2497. if (err)
  2498. goto out_pci_disable_device;
  2499. pci_set_drvdata(pdev, priv);
  2500. /***********************
  2501. * 3. Read REV register
  2502. ***********************/
  2503. priv->hw_base = pci_iomap(pdev, 0, 0);
  2504. if (!priv->hw_base) {
  2505. err = -ENODEV;
  2506. goto out_pci_release_regions;
  2507. }
  2508. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2509. (unsigned long long) pci_resource_len(pdev, 0));
  2510. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2511. /* this spin lock will be used in apm_ops.init and EEPROM access
  2512. * we should init now
  2513. */
  2514. spin_lock_init(&priv->reg_lock);
  2515. iwl_hw_detect(priv);
  2516. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2517. priv->cfg->name, priv->hw_rev);
  2518. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2519. * PCI Tx retries from interfering with C3 CPU state */
  2520. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2521. iwl_prepare_card_hw(priv);
  2522. if (!priv->hw_ready) {
  2523. IWL_WARN(priv, "Failed, HW not ready\n");
  2524. goto out_iounmap;
  2525. }
  2526. /* amp init */
  2527. err = priv->cfg->ops->lib->apm_ops.init(priv);
  2528. if (err < 0) {
  2529. IWL_ERR(priv, "Failed to init APMG\n");
  2530. goto out_iounmap;
  2531. }
  2532. /*****************
  2533. * 4. Read EEPROM
  2534. *****************/
  2535. /* Read the EEPROM */
  2536. err = iwl_eeprom_init(priv);
  2537. if (err) {
  2538. IWL_ERR(priv, "Unable to init EEPROM\n");
  2539. goto out_iounmap;
  2540. }
  2541. err = iwl_eeprom_check_version(priv);
  2542. if (err)
  2543. goto out_free_eeprom;
  2544. /* extract MAC Address */
  2545. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2546. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2547. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2548. /************************
  2549. * 5. Setup HW constants
  2550. ************************/
  2551. if (iwl_set_hw_params(priv)) {
  2552. IWL_ERR(priv, "failed to set hw parameters\n");
  2553. goto out_free_eeprom;
  2554. }
  2555. /*******************
  2556. * 6. Setup priv
  2557. *******************/
  2558. err = iwl_init_drv(priv);
  2559. if (err)
  2560. goto out_free_eeprom;
  2561. /* At this point both hw and priv are initialized. */
  2562. /********************
  2563. * 7. Setup services
  2564. ********************/
  2565. spin_lock_irqsave(&priv->lock, flags);
  2566. iwl_disable_interrupts(priv);
  2567. spin_unlock_irqrestore(&priv->lock, flags);
  2568. pci_enable_msi(priv->pci_dev);
  2569. iwl_alloc_isr_ict(priv);
  2570. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  2571. IRQF_SHARED, DRV_NAME, priv);
  2572. if (err) {
  2573. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2574. goto out_disable_msi;
  2575. }
  2576. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2577. if (err) {
  2578. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2579. goto out_free_irq;
  2580. }
  2581. iwl_setup_deferred_work(priv);
  2582. iwl_setup_rx_handlers(priv);
  2583. /**********************************
  2584. * 8. Setup and register mac80211
  2585. **********************************/
  2586. /* enable interrupts if needed: hw bug w/a */
  2587. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  2588. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  2589. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  2590. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  2591. }
  2592. iwl_enable_interrupts(priv);
  2593. err = iwl_setup_mac(priv);
  2594. if (err)
  2595. goto out_remove_sysfs;
  2596. err = iwl_dbgfs_register(priv, DRV_NAME);
  2597. if (err)
  2598. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  2599. /* If platform's RF_KILL switch is NOT set to KILL */
  2600. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2601. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2602. else
  2603. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2604. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  2605. test_bit(STATUS_RF_KILL_HW, &priv->status));
  2606. iwl_power_initialize(priv);
  2607. iwl_tt_initialize(priv);
  2608. return 0;
  2609. out_remove_sysfs:
  2610. destroy_workqueue(priv->workqueue);
  2611. priv->workqueue = NULL;
  2612. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2613. out_free_irq:
  2614. free_irq(priv->pci_dev->irq, priv);
  2615. iwl_free_isr_ict(priv);
  2616. out_disable_msi:
  2617. pci_disable_msi(priv->pci_dev);
  2618. iwl_uninit_drv(priv);
  2619. out_free_eeprom:
  2620. iwl_eeprom_free(priv);
  2621. out_iounmap:
  2622. pci_iounmap(pdev, priv->hw_base);
  2623. out_pci_release_regions:
  2624. pci_set_drvdata(pdev, NULL);
  2625. pci_release_regions(pdev);
  2626. out_pci_disable_device:
  2627. pci_disable_device(pdev);
  2628. out_ieee80211_free_hw:
  2629. iwl_free_traffic_mem(priv);
  2630. ieee80211_free_hw(priv->hw);
  2631. out:
  2632. return err;
  2633. }
  2634. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  2635. {
  2636. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2637. unsigned long flags;
  2638. if (!priv)
  2639. return;
  2640. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  2641. iwl_dbgfs_unregister(priv);
  2642. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2643. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  2644. * to be called and iwl_down since we are removing the device
  2645. * we need to set STATUS_EXIT_PENDING bit.
  2646. */
  2647. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2648. if (priv->mac80211_registered) {
  2649. ieee80211_unregister_hw(priv->hw);
  2650. priv->mac80211_registered = 0;
  2651. } else {
  2652. iwl_down(priv);
  2653. }
  2654. iwl_tt_exit(priv);
  2655. /* make sure we flush any pending irq or
  2656. * tasklet for the driver
  2657. */
  2658. spin_lock_irqsave(&priv->lock, flags);
  2659. iwl_disable_interrupts(priv);
  2660. spin_unlock_irqrestore(&priv->lock, flags);
  2661. iwl_synchronize_irq(priv);
  2662. iwl_dealloc_ucode_pci(priv);
  2663. if (priv->rxq.bd)
  2664. iwl_rx_queue_free(priv, &priv->rxq);
  2665. iwl_hw_txq_ctx_free(priv);
  2666. iwl_clear_stations_table(priv);
  2667. iwl_eeprom_free(priv);
  2668. /*netif_stop_queue(dev); */
  2669. flush_workqueue(priv->workqueue);
  2670. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  2671. * priv->workqueue... so we can't take down the workqueue
  2672. * until now... */
  2673. destroy_workqueue(priv->workqueue);
  2674. priv->workqueue = NULL;
  2675. iwl_free_traffic_mem(priv);
  2676. free_irq(priv->pci_dev->irq, priv);
  2677. pci_disable_msi(priv->pci_dev);
  2678. pci_iounmap(pdev, priv->hw_base);
  2679. pci_release_regions(pdev);
  2680. pci_disable_device(pdev);
  2681. pci_set_drvdata(pdev, NULL);
  2682. iwl_uninit_drv(priv);
  2683. iwl_free_isr_ict(priv);
  2684. if (priv->ibss_beacon)
  2685. dev_kfree_skb(priv->ibss_beacon);
  2686. ieee80211_free_hw(priv->hw);
  2687. }
  2688. /*****************************************************************************
  2689. *
  2690. * driver and module entry point
  2691. *
  2692. *****************************************************************************/
  2693. /* Hardware specific file defines the PCI IDs table for that hardware module */
  2694. static struct pci_device_id iwl_hw_card_ids[] = {
  2695. #ifdef CONFIG_IWL4965
  2696. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  2697. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  2698. #endif /* CONFIG_IWL4965 */
  2699. #ifdef CONFIG_IWL5000
  2700. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
  2701. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
  2702. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
  2703. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
  2704. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
  2705. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
  2706. {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
  2707. {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
  2708. {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
  2709. {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
  2710. /* 5350 WiFi/WiMax */
  2711. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
  2712. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
  2713. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
  2714. /* 5150 Wifi/WiMax */
  2715. {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
  2716. {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
  2717. /* 6x00 Series */
  2718. {IWL_PCI_DEVICE(0x008D, 0x1301, iwl6000h_2agn_cfg)},
  2719. {IWL_PCI_DEVICE(0x008D, 0x1321, iwl6000h_2agn_cfg)},
  2720. {IWL_PCI_DEVICE(0x008D, 0x1326, iwl6000h_2abg_cfg)},
  2721. {IWL_PCI_DEVICE(0x008D, 0x1306, iwl6000h_2abg_cfg)},
  2722. {IWL_PCI_DEVICE(0x008D, 0x1307, iwl6000h_2bg_cfg)},
  2723. {IWL_PCI_DEVICE(0x008E, 0x1311, iwl6000h_2agn_cfg)},
  2724. {IWL_PCI_DEVICE(0x008E, 0x1316, iwl6000h_2abg_cfg)},
  2725. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  2726. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  2727. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  2728. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  2729. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  2730. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  2731. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  2732. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  2733. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  2734. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  2735. /* 6x50 WiFi/WiMax Series */
  2736. {IWL_PCI_DEVICE(0x0086, 0x1101, iwl6050_3agn_cfg)},
  2737. {IWL_PCI_DEVICE(0x0086, 0x1121, iwl6050_3agn_cfg)},
  2738. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  2739. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  2740. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  2741. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  2742. {IWL_PCI_DEVICE(0x0088, 0x1111, iwl6050_3agn_cfg)},
  2743. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  2744. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  2745. /* 1000 Series WiFi */
  2746. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  2747. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  2748. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  2749. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  2750. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  2751. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  2752. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  2753. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  2754. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  2755. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  2756. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  2757. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  2758. #endif /* CONFIG_IWL5000 */
  2759. {0}
  2760. };
  2761. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  2762. static struct pci_driver iwl_driver = {
  2763. .name = DRV_NAME,
  2764. .id_table = iwl_hw_card_ids,
  2765. .probe = iwl_pci_probe,
  2766. .remove = __devexit_p(iwl_pci_remove),
  2767. #ifdef CONFIG_PM
  2768. .suspend = iwl_pci_suspend,
  2769. .resume = iwl_pci_resume,
  2770. #endif
  2771. };
  2772. static int __init iwl_init(void)
  2773. {
  2774. int ret;
  2775. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  2776. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  2777. ret = iwlagn_rate_control_register();
  2778. if (ret) {
  2779. printk(KERN_ERR DRV_NAME
  2780. "Unable to register rate control algorithm: %d\n", ret);
  2781. return ret;
  2782. }
  2783. ret = pci_register_driver(&iwl_driver);
  2784. if (ret) {
  2785. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  2786. goto error_register;
  2787. }
  2788. return ret;
  2789. error_register:
  2790. iwlagn_rate_control_unregister();
  2791. return ret;
  2792. }
  2793. static void __exit iwl_exit(void)
  2794. {
  2795. pci_unregister_driver(&iwl_driver);
  2796. iwlagn_rate_control_unregister();
  2797. }
  2798. module_exit(iwl_exit);
  2799. module_init(iwl_init);
  2800. #ifdef CONFIG_IWLWIFI_DEBUG
  2801. module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
  2802. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  2803. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  2804. MODULE_PARM_DESC(debug, "debug output mask");
  2805. #endif