iwl-agn.c 82 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/mac80211.h>
  42. #include <asm/div64.h>
  43. #define DRV_NAME "iwlagn"
  44. #include "iwl-eeprom.h"
  45. #include "iwl-dev.h"
  46. #include "iwl-core.h"
  47. #include "iwl-io.h"
  48. #include "iwl-helpers.h"
  49. #include "iwl-sta.h"
  50. #include "iwl-calib.h"
  51. /******************************************************************************
  52. *
  53. * module boiler plate
  54. *
  55. ******************************************************************************/
  56. /*
  57. * module name, copyright, version, etc.
  58. */
  59. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  60. #ifdef CONFIG_IWLWIFI_DEBUG
  61. #define VD "d"
  62. #else
  63. #define VD
  64. #endif
  65. #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
  66. #define VS "s"
  67. #else
  68. #define VS
  69. #endif
  70. #define DRV_VERSION IWLWIFI_VERSION VD VS
  71. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  72. MODULE_VERSION(DRV_VERSION);
  73. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  74. MODULE_LICENSE("GPL");
  75. MODULE_ALIAS("iwl4965");
  76. /*************** STATION TABLE MANAGEMENT ****
  77. * mac80211 should be examined to determine if sta_info is duplicating
  78. * the functionality provided here
  79. */
  80. /**************************************************************/
  81. /**
  82. * iwl_commit_rxon - commit staging_rxon to hardware
  83. *
  84. * The RXON command in staging_rxon is committed to the hardware and
  85. * the active_rxon structure is updated with the new data. This
  86. * function correctly transitions out of the RXON_ASSOC_MSK state if
  87. * a HW tune is required based on the RXON structure changes.
  88. */
  89. int iwl_commit_rxon(struct iwl_priv *priv)
  90. {
  91. /* cast away the const for active_rxon in this function */
  92. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  93. int ret;
  94. bool new_assoc =
  95. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  96. if (!iwl_is_alive(priv))
  97. return -EBUSY;
  98. /* always get timestamp with Rx frame */
  99. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  100. /* allow CTS-to-self if possible. this is relevant only for
  101. * 5000, but will not damage 4965 */
  102. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  103. ret = iwl_check_rxon_cmd(priv);
  104. if (ret) {
  105. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  106. return -EINVAL;
  107. }
  108. /* If we don't need to send a full RXON, we can use
  109. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  110. * and other flags for the current radio configuration. */
  111. if (!iwl_full_rxon_required(priv)) {
  112. ret = iwl_send_rxon_assoc(priv);
  113. if (ret) {
  114. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  115. return ret;
  116. }
  117. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  118. return 0;
  119. }
  120. /* station table will be cleared */
  121. priv->assoc_station_added = 0;
  122. /* If we are currently associated and the new config requires
  123. * an RXON_ASSOC and the new config wants the associated mask enabled,
  124. * we must clear the associated from the active configuration
  125. * before we apply the new config */
  126. if (iwl_is_associated(priv) && new_assoc) {
  127. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  128. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  129. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  130. sizeof(struct iwl_rxon_cmd),
  131. &priv->active_rxon);
  132. /* If the mask clearing failed then we set
  133. * active_rxon back to what it was previously */
  134. if (ret) {
  135. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  136. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  137. return ret;
  138. }
  139. }
  140. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  141. "* with%s RXON_FILTER_ASSOC_MSK\n"
  142. "* channel = %d\n"
  143. "* bssid = %pM\n",
  144. (new_assoc ? "" : "out"),
  145. le16_to_cpu(priv->staging_rxon.channel),
  146. priv->staging_rxon.bssid_addr);
  147. iwl_set_rxon_hwcrypto(priv, !priv->hw_params.sw_crypto);
  148. /* Apply the new configuration
  149. * RXON unassoc clears the station table in uCode, send it before
  150. * we add the bcast station. If assoc bit is set, we will send RXON
  151. * after having added the bcast and bssid station.
  152. */
  153. if (!new_assoc) {
  154. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  155. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  156. if (ret) {
  157. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  158. return ret;
  159. }
  160. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  161. }
  162. priv->cfg->ops->smgmt->clear_station_table(priv);
  163. if (!priv->error_recovering)
  164. priv->start_calib = 0;
  165. /* Add the broadcast address so we can send broadcast frames */
  166. if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
  167. IWL_INVALID_STATION) {
  168. IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
  169. return -EIO;
  170. }
  171. /* If we have set the ASSOC_MSK and we are in BSS mode then
  172. * add the IWL_AP_ID to the station rate table */
  173. if (new_assoc) {
  174. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  175. ret = iwl_rxon_add_station(priv,
  176. priv->active_rxon.bssid_addr, 1);
  177. if (ret == IWL_INVALID_STATION) {
  178. IWL_ERR(priv,
  179. "Error adding AP address for TX.\n");
  180. return -EIO;
  181. }
  182. priv->assoc_station_added = 1;
  183. if (priv->default_wep_key &&
  184. iwl_send_static_wepkey_cmd(priv, 0))
  185. IWL_ERR(priv,
  186. "Could not send WEP static key.\n");
  187. }
  188. /* Apply the new configuration
  189. * RXON assoc doesn't clear the station table in uCode,
  190. */
  191. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  192. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  193. if (ret) {
  194. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  195. return ret;
  196. }
  197. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  198. }
  199. iwl_init_sensitivity(priv);
  200. /* If we issue a new RXON command which required a tune then we must
  201. * send a new TXPOWER command or we won't be able to Tx any frames */
  202. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  203. if (ret) {
  204. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  205. return ret;
  206. }
  207. return 0;
  208. }
  209. void iwl_update_chain_flags(struct iwl_priv *priv)
  210. {
  211. if (priv->cfg->ops->hcmd->set_rxon_chain)
  212. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  213. iwlcore_commit_rxon(priv);
  214. }
  215. static void iwl_clear_free_frames(struct iwl_priv *priv)
  216. {
  217. struct list_head *element;
  218. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  219. priv->frames_count);
  220. while (!list_empty(&priv->free_frames)) {
  221. element = priv->free_frames.next;
  222. list_del(element);
  223. kfree(list_entry(element, struct iwl_frame, list));
  224. priv->frames_count--;
  225. }
  226. if (priv->frames_count) {
  227. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  228. priv->frames_count);
  229. priv->frames_count = 0;
  230. }
  231. }
  232. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  233. {
  234. struct iwl_frame *frame;
  235. struct list_head *element;
  236. if (list_empty(&priv->free_frames)) {
  237. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  238. if (!frame) {
  239. IWL_ERR(priv, "Could not allocate frame!\n");
  240. return NULL;
  241. }
  242. priv->frames_count++;
  243. return frame;
  244. }
  245. element = priv->free_frames.next;
  246. list_del(element);
  247. return list_entry(element, struct iwl_frame, list);
  248. }
  249. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  250. {
  251. memset(frame, 0, sizeof(*frame));
  252. list_add(&frame->list, &priv->free_frames);
  253. }
  254. static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
  255. struct ieee80211_hdr *hdr,
  256. int left)
  257. {
  258. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  259. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  260. (priv->iw_mode != NL80211_IFTYPE_AP)))
  261. return 0;
  262. if (priv->ibss_beacon->len > left)
  263. return 0;
  264. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  265. return priv->ibss_beacon->len;
  266. }
  267. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  268. struct iwl_frame *frame, u8 rate)
  269. {
  270. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  271. unsigned int frame_size;
  272. tx_beacon_cmd = &frame->u.beacon;
  273. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  274. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  275. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  276. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  277. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  278. BUG_ON(frame_size > MAX_MPDU_SIZE);
  279. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  280. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  281. tx_beacon_cmd->tx.rate_n_flags =
  282. iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  283. else
  284. tx_beacon_cmd->tx.rate_n_flags =
  285. iwl_hw_set_rate_n_flags(rate, 0);
  286. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  287. TX_CMD_FLG_TSF_MSK |
  288. TX_CMD_FLG_STA_RATE_MSK;
  289. return sizeof(*tx_beacon_cmd) + frame_size;
  290. }
  291. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  292. {
  293. struct iwl_frame *frame;
  294. unsigned int frame_size;
  295. int rc;
  296. u8 rate;
  297. frame = iwl_get_free_frame(priv);
  298. if (!frame) {
  299. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  300. "command.\n");
  301. return -ENOMEM;
  302. }
  303. rate = iwl_rate_get_lowest_plcp(priv);
  304. frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
  305. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  306. &frame->u.cmd[0]);
  307. iwl_free_frame(priv, frame);
  308. return rc;
  309. }
  310. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  311. {
  312. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  313. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  314. if (sizeof(dma_addr_t) > sizeof(u32))
  315. addr |=
  316. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  317. return addr;
  318. }
  319. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  320. {
  321. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  322. return le16_to_cpu(tb->hi_n_len) >> 4;
  323. }
  324. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  325. dma_addr_t addr, u16 len)
  326. {
  327. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  328. u16 hi_n_len = len << 4;
  329. put_unaligned_le32(addr, &tb->lo);
  330. if (sizeof(dma_addr_t) > sizeof(u32))
  331. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  332. tb->hi_n_len = cpu_to_le16(hi_n_len);
  333. tfd->num_tbs = idx + 1;
  334. }
  335. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  336. {
  337. return tfd->num_tbs & 0x1f;
  338. }
  339. /**
  340. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  341. * @priv - driver private data
  342. * @txq - tx queue
  343. *
  344. * Does NOT advance any TFD circular buffer read/write indexes
  345. * Does NOT free the TFD itself (which is within circular buffer)
  346. */
  347. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  348. {
  349. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  350. struct iwl_tfd *tfd;
  351. struct pci_dev *dev = priv->pci_dev;
  352. int index = txq->q.read_ptr;
  353. int i;
  354. int num_tbs;
  355. tfd = &tfd_tmp[index];
  356. /* Sanity check on number of chunks */
  357. num_tbs = iwl_tfd_get_num_tbs(tfd);
  358. if (num_tbs >= IWL_NUM_OF_TBS) {
  359. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  360. /* @todo issue fatal error, it is quite serious situation */
  361. return;
  362. }
  363. /* Unmap tx_cmd */
  364. if (num_tbs)
  365. pci_unmap_single(dev,
  366. pci_unmap_addr(&txq->cmd[index]->meta, mapping),
  367. pci_unmap_len(&txq->cmd[index]->meta, len),
  368. PCI_DMA_BIDIRECTIONAL);
  369. /* Unmap chunks, if any. */
  370. for (i = 1; i < num_tbs; i++) {
  371. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  372. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  373. if (txq->txb) {
  374. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  375. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  376. }
  377. }
  378. }
  379. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  380. struct iwl_tx_queue *txq,
  381. dma_addr_t addr, u16 len,
  382. u8 reset, u8 pad)
  383. {
  384. struct iwl_queue *q;
  385. struct iwl_tfd *tfd, *tfd_tmp;
  386. u32 num_tbs;
  387. q = &txq->q;
  388. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  389. tfd = &tfd_tmp[q->write_ptr];
  390. if (reset)
  391. memset(tfd, 0, sizeof(*tfd));
  392. num_tbs = iwl_tfd_get_num_tbs(tfd);
  393. /* Each TFD can point to a maximum 20 Tx buffers */
  394. if (num_tbs >= IWL_NUM_OF_TBS) {
  395. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  396. IWL_NUM_OF_TBS);
  397. return -EINVAL;
  398. }
  399. BUG_ON(addr & ~DMA_BIT_MASK(36));
  400. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  401. IWL_ERR(priv, "Unaligned address = %llx\n",
  402. (unsigned long long)addr);
  403. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  404. return 0;
  405. }
  406. /*
  407. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  408. * given Tx queue, and enable the DMA channel used for that queue.
  409. *
  410. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  411. * channels supported in hardware.
  412. */
  413. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  414. struct iwl_tx_queue *txq)
  415. {
  416. int ret;
  417. unsigned long flags;
  418. int txq_id = txq->q.id;
  419. spin_lock_irqsave(&priv->lock, flags);
  420. ret = iwl_grab_nic_access(priv);
  421. if (ret) {
  422. spin_unlock_irqrestore(&priv->lock, flags);
  423. return ret;
  424. }
  425. /* Circular buffer (TFD queue in DRAM) physical base address */
  426. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  427. txq->q.dma_addr >> 8);
  428. iwl_release_nic_access(priv);
  429. spin_unlock_irqrestore(&priv->lock, flags);
  430. return 0;
  431. }
  432. /******************************************************************************
  433. *
  434. * Misc. internal state and helper functions
  435. *
  436. ******************************************************************************/
  437. #define MAX_UCODE_BEACON_INTERVAL 4096
  438. static u16 iwl_adjust_beacon_interval(u16 beacon_val)
  439. {
  440. u16 new_val = 0;
  441. u16 beacon_factor = 0;
  442. beacon_factor = (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  443. / MAX_UCODE_BEACON_INTERVAL;
  444. new_val = beacon_val / beacon_factor;
  445. if (!new_val)
  446. new_val = MAX_UCODE_BEACON_INTERVAL;
  447. return new_val;
  448. }
  449. static void iwl_setup_rxon_timing(struct iwl_priv *priv)
  450. {
  451. u64 tsf;
  452. s32 interval_tm, rem;
  453. unsigned long flags;
  454. struct ieee80211_conf *conf = NULL;
  455. u16 beacon_int = 0;
  456. conf = ieee80211_get_hw_conf(priv->hw);
  457. spin_lock_irqsave(&priv->lock, flags);
  458. priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
  459. priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
  460. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  461. beacon_int = iwl_adjust_beacon_interval(priv->beacon_int);
  462. priv->rxon_timing.atim_window = 0;
  463. } else {
  464. beacon_int = iwl_adjust_beacon_interval(conf->beacon_int);
  465. /* TODO: we need to get atim_window from upper stack
  466. * for now we set to 0 */
  467. priv->rxon_timing.atim_window = 0;
  468. }
  469. priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
  470. tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
  471. interval_tm = beacon_int * 1024;
  472. rem = do_div(tsf, interval_tm);
  473. priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
  474. spin_unlock_irqrestore(&priv->lock, flags);
  475. IWL_DEBUG_ASSOC(priv, "beacon interval %d beacon timer %d beacon tim %d\n",
  476. le16_to_cpu(priv->rxon_timing.beacon_interval),
  477. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  478. le16_to_cpu(priv->rxon_timing.atim_window));
  479. }
  480. /******************************************************************************
  481. *
  482. * Generic RX handler implementations
  483. *
  484. ******************************************************************************/
  485. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  486. struct iwl_rx_mem_buffer *rxb)
  487. {
  488. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  489. struct iwl_alive_resp *palive;
  490. struct delayed_work *pwork;
  491. palive = &pkt->u.alive_frame;
  492. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  493. "0x%01X 0x%01X\n",
  494. palive->is_valid, palive->ver_type,
  495. palive->ver_subtype);
  496. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  497. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  498. memcpy(&priv->card_alive_init,
  499. &pkt->u.alive_frame,
  500. sizeof(struct iwl_init_alive_resp));
  501. pwork = &priv->init_alive_start;
  502. } else {
  503. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  504. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  505. sizeof(struct iwl_alive_resp));
  506. pwork = &priv->alive_start;
  507. }
  508. /* We delay the ALIVE response by 5ms to
  509. * give the HW RF Kill time to activate... */
  510. if (palive->is_valid == UCODE_VALID_OK)
  511. queue_delayed_work(priv->workqueue, pwork,
  512. msecs_to_jiffies(5));
  513. else
  514. IWL_WARN(priv, "uCode did not respond OK.\n");
  515. }
  516. static void iwl_bg_beacon_update(struct work_struct *work)
  517. {
  518. struct iwl_priv *priv =
  519. container_of(work, struct iwl_priv, beacon_update);
  520. struct sk_buff *beacon;
  521. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  522. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  523. if (!beacon) {
  524. IWL_ERR(priv, "update beacon failed\n");
  525. return;
  526. }
  527. mutex_lock(&priv->mutex);
  528. /* new beacon skb is allocated every time; dispose previous.*/
  529. if (priv->ibss_beacon)
  530. dev_kfree_skb(priv->ibss_beacon);
  531. priv->ibss_beacon = beacon;
  532. mutex_unlock(&priv->mutex);
  533. iwl_send_beacon_cmd(priv);
  534. }
  535. /**
  536. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  537. *
  538. * This callback is provided in order to send a statistics request.
  539. *
  540. * This timer function is continually reset to execute within
  541. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  542. * was received. We need to ensure we receive the statistics in order
  543. * to update the temperature used for calibrating the TXPOWER.
  544. */
  545. static void iwl_bg_statistics_periodic(unsigned long data)
  546. {
  547. struct iwl_priv *priv = (struct iwl_priv *)data;
  548. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  549. return;
  550. /* dont send host command if rf-kill is on */
  551. if (!iwl_is_ready_rf(priv))
  552. return;
  553. iwl_send_statistics_request(priv, CMD_ASYNC);
  554. }
  555. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  556. struct iwl_rx_mem_buffer *rxb)
  557. {
  558. #ifdef CONFIG_IWLWIFI_DEBUG
  559. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  560. struct iwl4965_beacon_notif *beacon =
  561. (struct iwl4965_beacon_notif *)pkt->u.raw;
  562. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  563. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  564. "tsf %d %d rate %d\n",
  565. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  566. beacon->beacon_notify_hdr.failure_frame,
  567. le32_to_cpu(beacon->ibss_mgr_status),
  568. le32_to_cpu(beacon->high_tsf),
  569. le32_to_cpu(beacon->low_tsf), rate);
  570. #endif
  571. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  572. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  573. queue_work(priv->workqueue, &priv->beacon_update);
  574. }
  575. /* Handle notification from uCode that card's power state is changing
  576. * due to software, hardware, or critical temperature RFKILL */
  577. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  578. struct iwl_rx_mem_buffer *rxb)
  579. {
  580. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  581. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  582. unsigned long status = priv->status;
  583. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
  584. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  585. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  586. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  587. RF_CARD_DISABLED)) {
  588. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  589. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  590. if (!iwl_grab_nic_access(priv)) {
  591. iwl_write_direct32(
  592. priv, HBUS_TARG_MBX_C,
  593. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  594. iwl_release_nic_access(priv);
  595. }
  596. if (!(flags & RXON_CARD_DISABLED)) {
  597. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  598. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  599. if (!iwl_grab_nic_access(priv)) {
  600. iwl_write_direct32(
  601. priv, HBUS_TARG_MBX_C,
  602. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  603. iwl_release_nic_access(priv);
  604. }
  605. }
  606. if (flags & RF_CARD_DISABLED) {
  607. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  608. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  609. iwl_read32(priv, CSR_UCODE_DRV_GP1);
  610. if (!iwl_grab_nic_access(priv))
  611. iwl_release_nic_access(priv);
  612. }
  613. }
  614. if (flags & HW_CARD_DISABLED)
  615. set_bit(STATUS_RF_KILL_HW, &priv->status);
  616. else
  617. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  618. if (flags & SW_CARD_DISABLED)
  619. set_bit(STATUS_RF_KILL_SW, &priv->status);
  620. else
  621. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  622. if (!(flags & RXON_CARD_DISABLED))
  623. iwl_scan_cancel(priv);
  624. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  625. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  626. (test_bit(STATUS_RF_KILL_SW, &status) !=
  627. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  628. queue_work(priv->workqueue, &priv->rf_kill);
  629. else
  630. wake_up_interruptible(&priv->wait_command_queue);
  631. }
  632. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  633. {
  634. int ret;
  635. unsigned long flags;
  636. spin_lock_irqsave(&priv->lock, flags);
  637. ret = iwl_grab_nic_access(priv);
  638. if (ret)
  639. goto err;
  640. if (src == IWL_PWR_SRC_VAUX) {
  641. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  642. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  643. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  644. ~APMG_PS_CTRL_MSK_PWR_SRC);
  645. } else {
  646. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  647. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  648. ~APMG_PS_CTRL_MSK_PWR_SRC);
  649. }
  650. iwl_release_nic_access(priv);
  651. err:
  652. spin_unlock_irqrestore(&priv->lock, flags);
  653. return ret;
  654. }
  655. /**
  656. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  657. *
  658. * Setup the RX handlers for each of the reply types sent from the uCode
  659. * to the host.
  660. *
  661. * This function chains into the hardware specific files for them to setup
  662. * any hardware specific handlers as well.
  663. */
  664. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  665. {
  666. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  667. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  668. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  669. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  670. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  671. iwl_rx_pm_debug_statistics_notif;
  672. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  673. /*
  674. * The same handler is used for both the REPLY to a discrete
  675. * statistics request from the host as well as for the periodic
  676. * statistics notifications (after received beacons) from the uCode.
  677. */
  678. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
  679. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  680. iwl_setup_spectrum_handlers(priv);
  681. iwl_setup_rx_scan_handlers(priv);
  682. /* status change handler */
  683. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  684. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  685. iwl_rx_missed_beacon_notif;
  686. /* Rx handlers */
  687. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  688. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  689. /* block ack */
  690. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  691. /* Set up hardware specific Rx handlers */
  692. priv->cfg->ops->lib->rx_handler_setup(priv);
  693. }
  694. /**
  695. * iwl_rx_handle - Main entry function for receiving responses from uCode
  696. *
  697. * Uses the priv->rx_handlers callback function array to invoke
  698. * the appropriate handlers, including command responses,
  699. * frame-received notifications, and other notifications.
  700. */
  701. void iwl_rx_handle(struct iwl_priv *priv)
  702. {
  703. struct iwl_rx_mem_buffer *rxb;
  704. struct iwl_rx_packet *pkt;
  705. struct iwl_rx_queue *rxq = &priv->rxq;
  706. u32 r, i;
  707. int reclaim;
  708. unsigned long flags;
  709. u8 fill_rx = 0;
  710. u32 count = 8;
  711. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  712. * buffer that the driver may process (last buffer filled by ucode). */
  713. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  714. i = rxq->read;
  715. /* Rx interrupt, but nothing sent from uCode */
  716. if (i == r)
  717. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  718. if (iwl_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  719. fill_rx = 1;
  720. while (i != r) {
  721. rxb = rxq->queue[i];
  722. /* If an RXB doesn't have a Rx queue slot associated with it,
  723. * then a bug has been introduced in the queue refilling
  724. * routines -- catch it here */
  725. BUG_ON(rxb == NULL);
  726. rxq->queue[i] = NULL;
  727. pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
  728. priv->hw_params.rx_buf_size + 256,
  729. PCI_DMA_FROMDEVICE);
  730. pkt = (struct iwl_rx_packet *)rxb->skb->data;
  731. /* Reclaim a command buffer only if this packet is a response
  732. * to a (driver-originated) command.
  733. * If the packet (e.g. Rx frame) originated from uCode,
  734. * there is no command buffer to reclaim.
  735. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  736. * but apparently a few don't get set; catch them here. */
  737. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  738. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  739. (pkt->hdr.cmd != REPLY_RX) &&
  740. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  741. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  742. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  743. (pkt->hdr.cmd != REPLY_TX);
  744. /* Based on type of command response or notification,
  745. * handle those that need handling via function in
  746. * rx_handlers table. See iwl_setup_rx_handlers() */
  747. if (priv->rx_handlers[pkt->hdr.cmd]) {
  748. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  749. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  750. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  751. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  752. } else {
  753. /* No handling needed */
  754. IWL_DEBUG_RX(priv,
  755. "r %d i %d No handler needed for %s, 0x%02x\n",
  756. r, i, get_cmd_string(pkt->hdr.cmd),
  757. pkt->hdr.cmd);
  758. }
  759. if (reclaim) {
  760. /* Invoke any callbacks, transfer the skb to caller, and
  761. * fire off the (possibly) blocking iwl_send_cmd()
  762. * as we reclaim the driver command queue */
  763. if (rxb && rxb->skb)
  764. iwl_tx_cmd_complete(priv, rxb);
  765. else
  766. IWL_WARN(priv, "Claim null rxb?\n");
  767. }
  768. /* For now we just don't re-use anything. We can tweak this
  769. * later to try and re-use notification packets and SKBs that
  770. * fail to Rx correctly */
  771. if (rxb->skb != NULL) {
  772. priv->alloc_rxb_skb--;
  773. dev_kfree_skb_any(rxb->skb);
  774. rxb->skb = NULL;
  775. }
  776. spin_lock_irqsave(&rxq->lock, flags);
  777. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  778. spin_unlock_irqrestore(&rxq->lock, flags);
  779. i = (i + 1) & RX_QUEUE_MASK;
  780. /* If there are a lot of unused frames,
  781. * restock the Rx queue so ucode wont assert. */
  782. if (fill_rx) {
  783. count++;
  784. if (count >= 8) {
  785. priv->rxq.read = i;
  786. iwl_rx_queue_restock(priv);
  787. count = 0;
  788. }
  789. }
  790. }
  791. /* Backtrack one entry */
  792. priv->rxq.read = i;
  793. iwl_rx_queue_restock(priv);
  794. }
  795. /* call this function to flush any scheduled tasklet */
  796. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  797. {
  798. /* wait to make sure we flush pending tasklet*/
  799. synchronize_irq(priv->pci_dev->irq);
  800. tasklet_kill(&priv->irq_tasklet);
  801. }
  802. static void iwl_error_recovery(struct iwl_priv *priv)
  803. {
  804. unsigned long flags;
  805. memcpy(&priv->staging_rxon, &priv->recovery_rxon,
  806. sizeof(priv->staging_rxon));
  807. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  808. iwlcore_commit_rxon(priv);
  809. iwl_rxon_add_station(priv, priv->bssid, 1);
  810. spin_lock_irqsave(&priv->lock, flags);
  811. priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
  812. priv->error_recovering = 0;
  813. spin_unlock_irqrestore(&priv->lock, flags);
  814. }
  815. static void iwl_irq_tasklet(struct iwl_priv *priv)
  816. {
  817. u32 inta, handled = 0;
  818. u32 inta_fh;
  819. unsigned long flags;
  820. #ifdef CONFIG_IWLWIFI_DEBUG
  821. u32 inta_mask;
  822. #endif
  823. spin_lock_irqsave(&priv->lock, flags);
  824. /* Ack/clear/reset pending uCode interrupts.
  825. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  826. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  827. inta = iwl_read32(priv, CSR_INT);
  828. iwl_write32(priv, CSR_INT, inta);
  829. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  830. * Any new interrupts that happen after this, either while we're
  831. * in this tasklet, or later, will show up in next ISR/tasklet. */
  832. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  833. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  834. #ifdef CONFIG_IWLWIFI_DEBUG
  835. if (priv->debug_level & IWL_DL_ISR) {
  836. /* just for debug */
  837. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  838. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  839. inta, inta_mask, inta_fh);
  840. }
  841. #endif
  842. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  843. * atomic, make sure that inta covers all the interrupts that
  844. * we've discovered, even if FH interrupt came in just after
  845. * reading CSR_INT. */
  846. if (inta_fh & CSR49_FH_INT_RX_MASK)
  847. inta |= CSR_INT_BIT_FH_RX;
  848. if (inta_fh & CSR49_FH_INT_TX_MASK)
  849. inta |= CSR_INT_BIT_FH_TX;
  850. /* Now service all interrupt bits discovered above. */
  851. if (inta & CSR_INT_BIT_HW_ERR) {
  852. IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
  853. /* Tell the device to stop sending interrupts */
  854. iwl_disable_interrupts(priv);
  855. priv->isr_stats.hw++;
  856. iwl_irq_handle_error(priv);
  857. handled |= CSR_INT_BIT_HW_ERR;
  858. spin_unlock_irqrestore(&priv->lock, flags);
  859. return;
  860. }
  861. #ifdef CONFIG_IWLWIFI_DEBUG
  862. if (priv->debug_level & (IWL_DL_ISR)) {
  863. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  864. if (inta & CSR_INT_BIT_SCD) {
  865. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  866. "the frame/frames.\n");
  867. priv->isr_stats.sch++;
  868. }
  869. /* Alive notification via Rx interrupt will do the real work */
  870. if (inta & CSR_INT_BIT_ALIVE) {
  871. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  872. priv->isr_stats.alive++;
  873. }
  874. }
  875. #endif
  876. /* Safely ignore these bits for debug checks below */
  877. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  878. /* HW RF KILL switch toggled */
  879. if (inta & CSR_INT_BIT_RF_KILL) {
  880. int hw_rf_kill = 0;
  881. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  882. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  883. hw_rf_kill = 1;
  884. IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
  885. hw_rf_kill ? "disable radio" : "enable radio");
  886. priv->isr_stats.rfkill++;
  887. /* driver only loads ucode once setting the interface up.
  888. * the driver allows loading the ucode even if the radio
  889. * is killed. Hence update the killswitch state here. The
  890. * rfkill handler will care about restarting if needed.
  891. */
  892. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  893. if (hw_rf_kill)
  894. set_bit(STATUS_RF_KILL_HW, &priv->status);
  895. else
  896. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  897. queue_work(priv->workqueue, &priv->rf_kill);
  898. }
  899. handled |= CSR_INT_BIT_RF_KILL;
  900. }
  901. /* Chip got too hot and stopped itself */
  902. if (inta & CSR_INT_BIT_CT_KILL) {
  903. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  904. priv->isr_stats.ctkill++;
  905. handled |= CSR_INT_BIT_CT_KILL;
  906. }
  907. /* Error detected by uCode */
  908. if (inta & CSR_INT_BIT_SW_ERR) {
  909. IWL_ERR(priv, "Microcode SW error detected. "
  910. " Restarting 0x%X.\n", inta);
  911. priv->isr_stats.sw++;
  912. priv->isr_stats.sw_err = inta;
  913. iwl_irq_handle_error(priv);
  914. handled |= CSR_INT_BIT_SW_ERR;
  915. }
  916. /* uCode wakes up after power-down sleep */
  917. if (inta & CSR_INT_BIT_WAKEUP) {
  918. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  919. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  920. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  921. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  922. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  923. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  924. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  925. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  926. priv->isr_stats.wakeup++;
  927. handled |= CSR_INT_BIT_WAKEUP;
  928. }
  929. /* All uCode command responses, including Tx command responses,
  930. * Rx "responses" (frame-received notification), and other
  931. * notifications from uCode come through here*/
  932. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  933. iwl_rx_handle(priv);
  934. priv->isr_stats.rx++;
  935. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  936. }
  937. if (inta & CSR_INT_BIT_FH_TX) {
  938. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  939. priv->isr_stats.tx++;
  940. handled |= CSR_INT_BIT_FH_TX;
  941. /* FH finished to write, send event */
  942. priv->ucode_write_complete = 1;
  943. wake_up_interruptible(&priv->wait_command_queue);
  944. }
  945. if (inta & ~handled) {
  946. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  947. priv->isr_stats.unhandled++;
  948. }
  949. if (inta & ~CSR_INI_SET_MASK) {
  950. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  951. inta & ~CSR_INI_SET_MASK);
  952. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  953. }
  954. /* Re-enable all interrupts */
  955. /* only Re-enable if diabled by irq */
  956. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  957. iwl_enable_interrupts(priv);
  958. #ifdef CONFIG_IWLWIFI_DEBUG
  959. if (priv->debug_level & (IWL_DL_ISR)) {
  960. inta = iwl_read32(priv, CSR_INT);
  961. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  962. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  963. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  964. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  965. }
  966. #endif
  967. spin_unlock_irqrestore(&priv->lock, flags);
  968. }
  969. /******************************************************************************
  970. *
  971. * uCode download functions
  972. *
  973. ******************************************************************************/
  974. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  975. {
  976. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  977. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  978. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  979. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  980. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  981. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  982. }
  983. static void iwl_nic_start(struct iwl_priv *priv)
  984. {
  985. /* Remove all resets to allow NIC to operate */
  986. iwl_write32(priv, CSR_RESET, 0);
  987. }
  988. /**
  989. * iwl_read_ucode - Read uCode images from disk file.
  990. *
  991. * Copy into buffers for card to fetch via bus-mastering
  992. */
  993. static int iwl_read_ucode(struct iwl_priv *priv)
  994. {
  995. struct iwl_ucode *ucode;
  996. int ret = -EINVAL, index;
  997. const struct firmware *ucode_raw;
  998. const char *name_pre = priv->cfg->fw_name_pre;
  999. const unsigned int api_max = priv->cfg->ucode_api_max;
  1000. const unsigned int api_min = priv->cfg->ucode_api_min;
  1001. char buf[25];
  1002. u8 *src;
  1003. size_t len;
  1004. u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
  1005. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1006. * request_firmware() is synchronous, file is in memory on return. */
  1007. for (index = api_max; index >= api_min; index--) {
  1008. sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
  1009. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1010. if (ret < 0) {
  1011. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1012. buf, ret);
  1013. if (ret == -ENOENT)
  1014. continue;
  1015. else
  1016. goto error;
  1017. } else {
  1018. if (index < api_max)
  1019. IWL_ERR(priv, "Loaded firmware %s, "
  1020. "which is deprecated. "
  1021. "Please use API v%u instead.\n",
  1022. buf, api_max);
  1023. IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
  1024. buf, ucode_raw->size);
  1025. break;
  1026. }
  1027. }
  1028. if (ret < 0)
  1029. goto error;
  1030. /* Make sure that we got at least our header! */
  1031. if (ucode_raw->size < sizeof(*ucode)) {
  1032. IWL_ERR(priv, "File size way too small!\n");
  1033. ret = -EINVAL;
  1034. goto err_release;
  1035. }
  1036. /* Data from ucode file: header followed by uCode images */
  1037. ucode = (void *)ucode_raw->data;
  1038. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1039. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1040. inst_size = le32_to_cpu(ucode->inst_size);
  1041. data_size = le32_to_cpu(ucode->data_size);
  1042. init_size = le32_to_cpu(ucode->init_size);
  1043. init_data_size = le32_to_cpu(ucode->init_data_size);
  1044. boot_size = le32_to_cpu(ucode->boot_size);
  1045. /* api_ver should match the api version forming part of the
  1046. * firmware filename ... but we don't check for that and only rely
  1047. * on the API version read from firmware header from here on forward */
  1048. if (api_ver < api_min || api_ver > api_max) {
  1049. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1050. "Driver supports v%u, firmware is v%u.\n",
  1051. api_max, api_ver);
  1052. priv->ucode_ver = 0;
  1053. ret = -EINVAL;
  1054. goto err_release;
  1055. }
  1056. if (api_ver != api_max)
  1057. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1058. "got v%u. New firmware can be obtained "
  1059. "from http://www.intellinuxwireless.org.\n",
  1060. api_max, api_ver);
  1061. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1062. IWL_UCODE_MAJOR(priv->ucode_ver),
  1063. IWL_UCODE_MINOR(priv->ucode_ver),
  1064. IWL_UCODE_API(priv->ucode_ver),
  1065. IWL_UCODE_SERIAL(priv->ucode_ver));
  1066. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1067. priv->ucode_ver);
  1068. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1069. inst_size);
  1070. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1071. data_size);
  1072. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1073. init_size);
  1074. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1075. init_data_size);
  1076. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1077. boot_size);
  1078. /* Verify size of file vs. image size info in file's header */
  1079. if (ucode_raw->size < sizeof(*ucode) +
  1080. inst_size + data_size + init_size +
  1081. init_data_size + boot_size) {
  1082. IWL_DEBUG_INFO(priv, "uCode file size %d too small\n",
  1083. (int)ucode_raw->size);
  1084. ret = -EINVAL;
  1085. goto err_release;
  1086. }
  1087. /* Verify that uCode images will fit in card's SRAM */
  1088. if (inst_size > priv->hw_params.max_inst_size) {
  1089. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1090. inst_size);
  1091. ret = -EINVAL;
  1092. goto err_release;
  1093. }
  1094. if (data_size > priv->hw_params.max_data_size) {
  1095. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1096. data_size);
  1097. ret = -EINVAL;
  1098. goto err_release;
  1099. }
  1100. if (init_size > priv->hw_params.max_inst_size) {
  1101. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1102. init_size);
  1103. ret = -EINVAL;
  1104. goto err_release;
  1105. }
  1106. if (init_data_size > priv->hw_params.max_data_size) {
  1107. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1108. init_data_size);
  1109. ret = -EINVAL;
  1110. goto err_release;
  1111. }
  1112. if (boot_size > priv->hw_params.max_bsm_size) {
  1113. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1114. boot_size);
  1115. ret = -EINVAL;
  1116. goto err_release;
  1117. }
  1118. /* Allocate ucode buffers for card's bus-master loading ... */
  1119. /* Runtime instructions and 2 copies of data:
  1120. * 1) unmodified from disk
  1121. * 2) backup cache for save/restore during power-downs */
  1122. priv->ucode_code.len = inst_size;
  1123. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1124. priv->ucode_data.len = data_size;
  1125. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1126. priv->ucode_data_backup.len = data_size;
  1127. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1128. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1129. !priv->ucode_data_backup.v_addr)
  1130. goto err_pci_alloc;
  1131. /* Initialization instructions and data */
  1132. if (init_size && init_data_size) {
  1133. priv->ucode_init.len = init_size;
  1134. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1135. priv->ucode_init_data.len = init_data_size;
  1136. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1137. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1138. goto err_pci_alloc;
  1139. }
  1140. /* Bootstrap (instructions only, no data) */
  1141. if (boot_size) {
  1142. priv->ucode_boot.len = boot_size;
  1143. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1144. if (!priv->ucode_boot.v_addr)
  1145. goto err_pci_alloc;
  1146. }
  1147. /* Copy images into buffers for card's bus-master reads ... */
  1148. /* Runtime instructions (first block of data in file) */
  1149. src = &ucode->data[0];
  1150. len = priv->ucode_code.len;
  1151. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1152. memcpy(priv->ucode_code.v_addr, src, len);
  1153. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1154. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1155. /* Runtime data (2nd block)
  1156. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1157. src = &ucode->data[inst_size];
  1158. len = priv->ucode_data.len;
  1159. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1160. memcpy(priv->ucode_data.v_addr, src, len);
  1161. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1162. /* Initialization instructions (3rd block) */
  1163. if (init_size) {
  1164. src = &ucode->data[inst_size + data_size];
  1165. len = priv->ucode_init.len;
  1166. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1167. len);
  1168. memcpy(priv->ucode_init.v_addr, src, len);
  1169. }
  1170. /* Initialization data (4th block) */
  1171. if (init_data_size) {
  1172. src = &ucode->data[inst_size + data_size + init_size];
  1173. len = priv->ucode_init_data.len;
  1174. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1175. len);
  1176. memcpy(priv->ucode_init_data.v_addr, src, len);
  1177. }
  1178. /* Bootstrap instructions (5th block) */
  1179. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  1180. len = priv->ucode_boot.len;
  1181. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1182. memcpy(priv->ucode_boot.v_addr, src, len);
  1183. /* We have our copies now, allow OS release its copies */
  1184. release_firmware(ucode_raw);
  1185. return 0;
  1186. err_pci_alloc:
  1187. IWL_ERR(priv, "failed to allocate pci memory\n");
  1188. ret = -ENOMEM;
  1189. iwl_dealloc_ucode_pci(priv);
  1190. err_release:
  1191. release_firmware(ucode_raw);
  1192. error:
  1193. return ret;
  1194. }
  1195. /**
  1196. * iwl_alive_start - called after REPLY_ALIVE notification received
  1197. * from protocol/runtime uCode (initialization uCode's
  1198. * Alive gets handled by iwl_init_alive_start()).
  1199. */
  1200. static void iwl_alive_start(struct iwl_priv *priv)
  1201. {
  1202. int ret = 0;
  1203. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1204. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1205. /* We had an error bringing up the hardware, so take it
  1206. * all the way back down so we can try again */
  1207. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1208. goto restart;
  1209. }
  1210. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1211. * This is a paranoid check, because we would not have gotten the
  1212. * "runtime" alive if code weren't properly loaded. */
  1213. if (iwl_verify_ucode(priv)) {
  1214. /* Runtime instruction load was bad;
  1215. * take it all the way back down so we can try again */
  1216. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1217. goto restart;
  1218. }
  1219. priv->cfg->ops->smgmt->clear_station_table(priv);
  1220. ret = priv->cfg->ops->lib->alive_notify(priv);
  1221. if (ret) {
  1222. IWL_WARN(priv,
  1223. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1224. goto restart;
  1225. }
  1226. /* After the ALIVE response, we can send host commands to the uCode */
  1227. set_bit(STATUS_ALIVE, &priv->status);
  1228. if (iwl_is_rfkill(priv))
  1229. return;
  1230. ieee80211_wake_queues(priv->hw);
  1231. priv->active_rate = priv->rates_mask;
  1232. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1233. if (iwl_is_associated(priv)) {
  1234. struct iwl_rxon_cmd *active_rxon =
  1235. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1236. /* apply any changes in staging */
  1237. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1238. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1239. } else {
  1240. /* Initialize our rx_config data */
  1241. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1242. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1243. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1244. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1245. }
  1246. /* Configure Bluetooth device coexistence support */
  1247. iwl_send_bt_config(priv);
  1248. iwl_reset_run_time_calib(priv);
  1249. /* Configure the adapter for unassociated operation */
  1250. iwlcore_commit_rxon(priv);
  1251. /* At this point, the NIC is initialized and operational */
  1252. iwl_rf_kill_ct_config(priv);
  1253. iwl_leds_register(priv);
  1254. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1255. set_bit(STATUS_READY, &priv->status);
  1256. wake_up_interruptible(&priv->wait_command_queue);
  1257. if (priv->error_recovering)
  1258. iwl_error_recovery(priv);
  1259. iwl_power_update_mode(priv, 1);
  1260. /* reassociate for ADHOC mode */
  1261. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  1262. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  1263. priv->vif);
  1264. if (beacon)
  1265. iwl_mac_beacon_update(priv->hw, beacon);
  1266. }
  1267. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1268. iwl_set_mode(priv, priv->iw_mode);
  1269. return;
  1270. restart:
  1271. queue_work(priv->workqueue, &priv->restart);
  1272. }
  1273. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1274. static void __iwl_down(struct iwl_priv *priv)
  1275. {
  1276. unsigned long flags;
  1277. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1278. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1279. if (!exit_pending)
  1280. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1281. iwl_leds_unregister(priv);
  1282. priv->cfg->ops->smgmt->clear_station_table(priv);
  1283. /* Unblock any waiting calls */
  1284. wake_up_interruptible_all(&priv->wait_command_queue);
  1285. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1286. * exiting the module */
  1287. if (!exit_pending)
  1288. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1289. /* stop and reset the on-board processor */
  1290. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1291. /* tell the device to stop sending interrupts */
  1292. spin_lock_irqsave(&priv->lock, flags);
  1293. iwl_disable_interrupts(priv);
  1294. spin_unlock_irqrestore(&priv->lock, flags);
  1295. iwl_synchronize_irq(priv);
  1296. if (priv->mac80211_registered)
  1297. ieee80211_stop_queues(priv->hw);
  1298. /* If we have not previously called iwl_init() then
  1299. * clear all bits but the RF Kill bits and return */
  1300. if (!iwl_is_init(priv)) {
  1301. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1302. STATUS_RF_KILL_HW |
  1303. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  1304. STATUS_RF_KILL_SW |
  1305. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1306. STATUS_GEO_CONFIGURED |
  1307. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1308. STATUS_EXIT_PENDING;
  1309. goto exit;
  1310. }
  1311. /* ...otherwise clear out all the status bits but the RF Kill
  1312. * bits and continue taking the NIC down. */
  1313. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1314. STATUS_RF_KILL_HW |
  1315. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  1316. STATUS_RF_KILL_SW |
  1317. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1318. STATUS_GEO_CONFIGURED |
  1319. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1320. STATUS_FW_ERROR |
  1321. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1322. STATUS_EXIT_PENDING;
  1323. spin_lock_irqsave(&priv->lock, flags);
  1324. iwl_clear_bit(priv, CSR_GP_CNTRL,
  1325. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1326. spin_unlock_irqrestore(&priv->lock, flags);
  1327. iwl_txq_ctx_stop(priv);
  1328. iwl_rxq_stop(priv);
  1329. spin_lock_irqsave(&priv->lock, flags);
  1330. if (!iwl_grab_nic_access(priv)) {
  1331. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  1332. APMG_CLK_VAL_DMA_CLK_RQT);
  1333. iwl_release_nic_access(priv);
  1334. }
  1335. spin_unlock_irqrestore(&priv->lock, flags);
  1336. udelay(5);
  1337. /* FIXME: apm_ops.suspend(priv) */
  1338. if (exit_pending)
  1339. priv->cfg->ops->lib->apm_ops.stop(priv);
  1340. else
  1341. priv->cfg->ops->lib->apm_ops.reset(priv);
  1342. exit:
  1343. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1344. if (priv->ibss_beacon)
  1345. dev_kfree_skb(priv->ibss_beacon);
  1346. priv->ibss_beacon = NULL;
  1347. /* clear out any free frames */
  1348. iwl_clear_free_frames(priv);
  1349. }
  1350. static void iwl_down(struct iwl_priv *priv)
  1351. {
  1352. mutex_lock(&priv->mutex);
  1353. __iwl_down(priv);
  1354. mutex_unlock(&priv->mutex);
  1355. iwl_cancel_deferred_work(priv);
  1356. }
  1357. #define MAX_HW_RESTARTS 5
  1358. static int __iwl_up(struct iwl_priv *priv)
  1359. {
  1360. int i;
  1361. int ret;
  1362. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1363. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1364. return -EIO;
  1365. }
  1366. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1367. IWL_ERR(priv, "ucode not available for device bringup\n");
  1368. return -EIO;
  1369. }
  1370. /* If platform's RF_KILL switch is NOT set to KILL */
  1371. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1372. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1373. else
  1374. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1375. if (iwl_is_rfkill(priv)) {
  1376. iwl_enable_interrupts(priv);
  1377. IWL_WARN(priv, "Radio disabled by %s RF Kill switch\n",
  1378. test_bit(STATUS_RF_KILL_HW, &priv->status) ? "HW" : "SW");
  1379. return 0;
  1380. }
  1381. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1382. ret = iwl_hw_nic_init(priv);
  1383. if (ret) {
  1384. IWL_ERR(priv, "Unable to init nic\n");
  1385. return ret;
  1386. }
  1387. /* make sure rfkill handshake bits are cleared */
  1388. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1389. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1390. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1391. /* clear (again), then enable host interrupts */
  1392. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1393. iwl_enable_interrupts(priv);
  1394. /* really make sure rfkill handshake bits are cleared */
  1395. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1396. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1397. /* Copy original ucode data image from disk into backup cache.
  1398. * This will be used to initialize the on-board processor's
  1399. * data SRAM for a clean start when the runtime program first loads. */
  1400. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1401. priv->ucode_data.len);
  1402. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1403. priv->cfg->ops->smgmt->clear_station_table(priv);
  1404. /* load bootstrap state machine,
  1405. * load bootstrap program into processor's memory,
  1406. * prepare to load the "initialize" uCode */
  1407. ret = priv->cfg->ops->lib->load_ucode(priv);
  1408. if (ret) {
  1409. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1410. ret);
  1411. continue;
  1412. }
  1413. /* Clear out the uCode error bit if it is set */
  1414. clear_bit(STATUS_FW_ERROR, &priv->status);
  1415. /* start card; "initialize" will load runtime ucode */
  1416. iwl_nic_start(priv);
  1417. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1418. return 0;
  1419. }
  1420. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1421. __iwl_down(priv);
  1422. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1423. /* tried to restart and config the device for as long as our
  1424. * patience could withstand */
  1425. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1426. return -EIO;
  1427. }
  1428. /*****************************************************************************
  1429. *
  1430. * Workqueue callbacks
  1431. *
  1432. *****************************************************************************/
  1433. static void iwl_bg_init_alive_start(struct work_struct *data)
  1434. {
  1435. struct iwl_priv *priv =
  1436. container_of(data, struct iwl_priv, init_alive_start.work);
  1437. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1438. return;
  1439. mutex_lock(&priv->mutex);
  1440. priv->cfg->ops->lib->init_alive_start(priv);
  1441. mutex_unlock(&priv->mutex);
  1442. }
  1443. static void iwl_bg_alive_start(struct work_struct *data)
  1444. {
  1445. struct iwl_priv *priv =
  1446. container_of(data, struct iwl_priv, alive_start.work);
  1447. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1448. return;
  1449. mutex_lock(&priv->mutex);
  1450. iwl_alive_start(priv);
  1451. mutex_unlock(&priv->mutex);
  1452. }
  1453. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  1454. {
  1455. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1456. run_time_calib_work);
  1457. mutex_lock(&priv->mutex);
  1458. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1459. test_bit(STATUS_SCANNING, &priv->status)) {
  1460. mutex_unlock(&priv->mutex);
  1461. return;
  1462. }
  1463. if (priv->start_calib) {
  1464. iwl_chain_noise_calibration(priv, &priv->statistics);
  1465. iwl_sensitivity_calibration(priv, &priv->statistics);
  1466. }
  1467. mutex_unlock(&priv->mutex);
  1468. return;
  1469. }
  1470. static void iwl_bg_up(struct work_struct *data)
  1471. {
  1472. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  1473. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1474. return;
  1475. mutex_lock(&priv->mutex);
  1476. __iwl_up(priv);
  1477. mutex_unlock(&priv->mutex);
  1478. iwl_rfkill_set_hw_state(priv);
  1479. }
  1480. static void iwl_bg_restart(struct work_struct *data)
  1481. {
  1482. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  1483. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1484. return;
  1485. iwl_down(priv);
  1486. queue_work(priv->workqueue, &priv->up);
  1487. }
  1488. static void iwl_bg_rx_replenish(struct work_struct *data)
  1489. {
  1490. struct iwl_priv *priv =
  1491. container_of(data, struct iwl_priv, rx_replenish);
  1492. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1493. return;
  1494. mutex_lock(&priv->mutex);
  1495. iwl_rx_replenish(priv);
  1496. mutex_unlock(&priv->mutex);
  1497. }
  1498. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  1499. void iwl_post_associate(struct iwl_priv *priv)
  1500. {
  1501. struct ieee80211_conf *conf = NULL;
  1502. int ret = 0;
  1503. unsigned long flags;
  1504. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1505. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  1506. return;
  1507. }
  1508. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  1509. priv->assoc_id, priv->active_rxon.bssid_addr);
  1510. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1511. return;
  1512. if (!priv->vif || !priv->is_open)
  1513. return;
  1514. iwl_power_cancel_timeout(priv);
  1515. iwl_scan_cancel_timeout(priv, 200);
  1516. conf = ieee80211_get_hw_conf(priv->hw);
  1517. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1518. iwlcore_commit_rxon(priv);
  1519. iwl_setup_rxon_timing(priv);
  1520. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1521. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1522. if (ret)
  1523. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1524. "Attempting to continue.\n");
  1525. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1526. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  1527. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1528. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1529. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1530. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  1531. priv->assoc_id, priv->beacon_int);
  1532. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1533. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1534. else
  1535. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1536. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1537. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1538. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1539. else
  1540. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1541. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1542. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1543. }
  1544. iwlcore_commit_rxon(priv);
  1545. switch (priv->iw_mode) {
  1546. case NL80211_IFTYPE_STATION:
  1547. break;
  1548. case NL80211_IFTYPE_ADHOC:
  1549. /* assume default assoc id */
  1550. priv->assoc_id = 1;
  1551. iwl_rxon_add_station(priv, priv->bssid, 0);
  1552. iwl_send_beacon_cmd(priv);
  1553. break;
  1554. default:
  1555. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  1556. __func__, priv->iw_mode);
  1557. break;
  1558. }
  1559. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1560. priv->assoc_station_added = 1;
  1561. spin_lock_irqsave(&priv->lock, flags);
  1562. iwl_activate_qos(priv, 0);
  1563. spin_unlock_irqrestore(&priv->lock, flags);
  1564. /* the chain noise calibration will enabled PM upon completion
  1565. * If chain noise has already been run, then we need to enable
  1566. * power management here */
  1567. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  1568. iwl_power_enable_management(priv);
  1569. /* Enable Rx differential gain and sensitivity calibrations */
  1570. iwl_chain_noise_reset(priv);
  1571. priv->start_calib = 1;
  1572. }
  1573. /*****************************************************************************
  1574. *
  1575. * mac80211 entry point functions
  1576. *
  1577. *****************************************************************************/
  1578. #define UCODE_READY_TIMEOUT (4 * HZ)
  1579. static int iwl_mac_start(struct ieee80211_hw *hw)
  1580. {
  1581. struct iwl_priv *priv = hw->priv;
  1582. int ret;
  1583. IWL_DEBUG_MAC80211(priv, "enter\n");
  1584. /* we should be verifying the device is ready to be opened */
  1585. mutex_lock(&priv->mutex);
  1586. memset(&priv->staging_rxon, 0, sizeof(struct iwl_rxon_cmd));
  1587. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  1588. * ucode filename and max sizes are card-specific. */
  1589. if (!priv->ucode_code.len) {
  1590. ret = iwl_read_ucode(priv);
  1591. if (ret) {
  1592. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  1593. mutex_unlock(&priv->mutex);
  1594. return ret;
  1595. }
  1596. }
  1597. ret = __iwl_up(priv);
  1598. mutex_unlock(&priv->mutex);
  1599. iwl_rfkill_set_hw_state(priv);
  1600. if (ret)
  1601. return ret;
  1602. if (iwl_is_rfkill(priv))
  1603. goto out;
  1604. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  1605. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  1606. * mac80211 will not be run successfully. */
  1607. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  1608. test_bit(STATUS_READY, &priv->status),
  1609. UCODE_READY_TIMEOUT);
  1610. if (!ret) {
  1611. if (!test_bit(STATUS_READY, &priv->status)) {
  1612. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  1613. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  1614. return -ETIMEDOUT;
  1615. }
  1616. }
  1617. out:
  1618. priv->is_open = 1;
  1619. IWL_DEBUG_MAC80211(priv, "leave\n");
  1620. return 0;
  1621. }
  1622. static void iwl_mac_stop(struct ieee80211_hw *hw)
  1623. {
  1624. struct iwl_priv *priv = hw->priv;
  1625. IWL_DEBUG_MAC80211(priv, "enter\n");
  1626. if (!priv->is_open) {
  1627. IWL_DEBUG_MAC80211(priv, "leave - skip\n");
  1628. return;
  1629. }
  1630. priv->is_open = 0;
  1631. if (iwl_is_ready_rf(priv)) {
  1632. /* stop mac, cancel any scan request and clear
  1633. * RXON_FILTER_ASSOC_MSK BIT
  1634. */
  1635. mutex_lock(&priv->mutex);
  1636. iwl_scan_cancel_timeout(priv, 100);
  1637. mutex_unlock(&priv->mutex);
  1638. }
  1639. iwl_down(priv);
  1640. flush_workqueue(priv->workqueue);
  1641. /* enable interrupts again in order to receive rfkill changes */
  1642. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1643. iwl_enable_interrupts(priv);
  1644. IWL_DEBUG_MAC80211(priv, "leave\n");
  1645. }
  1646. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  1647. {
  1648. struct iwl_priv *priv = hw->priv;
  1649. IWL_DEBUG_MACDUMP(priv, "enter\n");
  1650. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  1651. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  1652. if (iwl_tx_skb(priv, skb))
  1653. dev_kfree_skb_any(skb);
  1654. IWL_DEBUG_MACDUMP(priv, "leave\n");
  1655. return NETDEV_TX_OK;
  1656. }
  1657. void iwl_config_ap(struct iwl_priv *priv)
  1658. {
  1659. int ret = 0;
  1660. unsigned long flags;
  1661. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1662. return;
  1663. /* The following should be done only at AP bring up */
  1664. if (!iwl_is_associated(priv)) {
  1665. /* RXON - unassoc (to set timing command) */
  1666. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1667. iwlcore_commit_rxon(priv);
  1668. /* RXON Timing */
  1669. iwl_setup_rxon_timing(priv);
  1670. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1671. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1672. if (ret)
  1673. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1674. "Attempting to continue.\n");
  1675. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1676. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1677. /* FIXME: what should be the assoc_id for AP? */
  1678. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1679. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1680. priv->staging_rxon.flags |=
  1681. RXON_FLG_SHORT_PREAMBLE_MSK;
  1682. else
  1683. priv->staging_rxon.flags &=
  1684. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1685. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1686. if (priv->assoc_capability &
  1687. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1688. priv->staging_rxon.flags |=
  1689. RXON_FLG_SHORT_SLOT_MSK;
  1690. else
  1691. priv->staging_rxon.flags &=
  1692. ~RXON_FLG_SHORT_SLOT_MSK;
  1693. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1694. priv->staging_rxon.flags &=
  1695. ~RXON_FLG_SHORT_SLOT_MSK;
  1696. }
  1697. /* restore RXON assoc */
  1698. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1699. iwlcore_commit_rxon(priv);
  1700. spin_lock_irqsave(&priv->lock, flags);
  1701. iwl_activate_qos(priv, 1);
  1702. spin_unlock_irqrestore(&priv->lock, flags);
  1703. iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
  1704. }
  1705. iwl_send_beacon_cmd(priv);
  1706. /* FIXME - we need to add code here to detect a totally new
  1707. * configuration, reset the AP, unassoc, rxon timing, assoc,
  1708. * clear sta table, add BCAST sta... */
  1709. }
  1710. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  1711. struct ieee80211_key_conf *keyconf, const u8 *addr,
  1712. u32 iv32, u16 *phase1key)
  1713. {
  1714. struct iwl_priv *priv = hw->priv;
  1715. IWL_DEBUG_MAC80211(priv, "enter\n");
  1716. iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
  1717. IWL_DEBUG_MAC80211(priv, "leave\n");
  1718. }
  1719. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  1720. struct ieee80211_vif *vif,
  1721. struct ieee80211_sta *sta,
  1722. struct ieee80211_key_conf *key)
  1723. {
  1724. struct iwl_priv *priv = hw->priv;
  1725. const u8 *addr;
  1726. int ret;
  1727. u8 sta_id;
  1728. bool is_default_wep_key = false;
  1729. IWL_DEBUG_MAC80211(priv, "enter\n");
  1730. if (priv->hw_params.sw_crypto) {
  1731. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  1732. return -EOPNOTSUPP;
  1733. }
  1734. addr = sta ? sta->addr : iwl_bcast_addr;
  1735. sta_id = priv->cfg->ops->smgmt->find_station(priv, addr);
  1736. if (sta_id == IWL_INVALID_STATION) {
  1737. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  1738. addr);
  1739. return -EINVAL;
  1740. }
  1741. mutex_lock(&priv->mutex);
  1742. iwl_scan_cancel_timeout(priv, 100);
  1743. mutex_unlock(&priv->mutex);
  1744. /* If we are getting WEP group key and we didn't receive any key mapping
  1745. * so far, we are in legacy wep mode (group key only), otherwise we are
  1746. * in 1X mode.
  1747. * In legacy wep mode, we use another host command to the uCode */
  1748. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  1749. priv->iw_mode != NL80211_IFTYPE_AP) {
  1750. if (cmd == SET_KEY)
  1751. is_default_wep_key = !priv->key_mapping_key;
  1752. else
  1753. is_default_wep_key =
  1754. (key->hw_key_idx == HW_KEY_DEFAULT);
  1755. }
  1756. switch (cmd) {
  1757. case SET_KEY:
  1758. if (is_default_wep_key)
  1759. ret = iwl_set_default_wep_key(priv, key);
  1760. else
  1761. ret = iwl_set_dynamic_key(priv, key, sta_id);
  1762. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  1763. break;
  1764. case DISABLE_KEY:
  1765. if (is_default_wep_key)
  1766. ret = iwl_remove_default_wep_key(priv, key);
  1767. else
  1768. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  1769. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  1770. break;
  1771. default:
  1772. ret = -EINVAL;
  1773. }
  1774. IWL_DEBUG_MAC80211(priv, "leave\n");
  1775. return ret;
  1776. }
  1777. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  1778. enum ieee80211_ampdu_mlme_action action,
  1779. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  1780. {
  1781. struct iwl_priv *priv = hw->priv;
  1782. int ret;
  1783. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  1784. sta->addr, tid);
  1785. if (!(priv->cfg->sku & IWL_SKU_N))
  1786. return -EACCES;
  1787. switch (action) {
  1788. case IEEE80211_AMPDU_RX_START:
  1789. IWL_DEBUG_HT(priv, "start Rx\n");
  1790. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  1791. case IEEE80211_AMPDU_RX_STOP:
  1792. IWL_DEBUG_HT(priv, "stop Rx\n");
  1793. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  1794. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1795. return 0;
  1796. else
  1797. return ret;
  1798. case IEEE80211_AMPDU_TX_START:
  1799. IWL_DEBUG_HT(priv, "start Tx\n");
  1800. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  1801. case IEEE80211_AMPDU_TX_STOP:
  1802. IWL_DEBUG_HT(priv, "stop Tx\n");
  1803. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  1804. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1805. return 0;
  1806. else
  1807. return ret;
  1808. default:
  1809. IWL_DEBUG_HT(priv, "unknown\n");
  1810. return -EINVAL;
  1811. break;
  1812. }
  1813. return 0;
  1814. }
  1815. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  1816. struct ieee80211_low_level_stats *stats)
  1817. {
  1818. struct iwl_priv *priv = hw->priv;
  1819. priv = hw->priv;
  1820. IWL_DEBUG_MAC80211(priv, "enter\n");
  1821. IWL_DEBUG_MAC80211(priv, "leave\n");
  1822. return 0;
  1823. }
  1824. /*****************************************************************************
  1825. *
  1826. * sysfs attributes
  1827. *
  1828. *****************************************************************************/
  1829. #ifdef CONFIG_IWLWIFI_DEBUG
  1830. /*
  1831. * The following adds a new attribute to the sysfs representation
  1832. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  1833. * used for controlling the debug level.
  1834. *
  1835. * See the level definitions in iwl for details.
  1836. */
  1837. static ssize_t show_debug_level(struct device *d,
  1838. struct device_attribute *attr, char *buf)
  1839. {
  1840. struct iwl_priv *priv = d->driver_data;
  1841. return sprintf(buf, "0x%08X\n", priv->debug_level);
  1842. }
  1843. static ssize_t store_debug_level(struct device *d,
  1844. struct device_attribute *attr,
  1845. const char *buf, size_t count)
  1846. {
  1847. struct iwl_priv *priv = d->driver_data;
  1848. unsigned long val;
  1849. int ret;
  1850. ret = strict_strtoul(buf, 0, &val);
  1851. if (ret)
  1852. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  1853. else
  1854. priv->debug_level = val;
  1855. return strnlen(buf, count);
  1856. }
  1857. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  1858. show_debug_level, store_debug_level);
  1859. #endif /* CONFIG_IWLWIFI_DEBUG */
  1860. static ssize_t show_version(struct device *d,
  1861. struct device_attribute *attr, char *buf)
  1862. {
  1863. struct iwl_priv *priv = d->driver_data;
  1864. struct iwl_alive_resp *palive = &priv->card_alive;
  1865. ssize_t pos = 0;
  1866. u16 eeprom_ver;
  1867. if (palive->is_valid)
  1868. pos += sprintf(buf + pos,
  1869. "fw version: 0x%01X.0x%01X.0x%01X.0x%01X\n"
  1870. "fw type: 0x%01X 0x%01X\n",
  1871. palive->ucode_major, palive->ucode_minor,
  1872. palive->sw_rev[0], palive->sw_rev[1],
  1873. palive->ver_type, palive->ver_subtype);
  1874. else
  1875. pos += sprintf(buf + pos, "fw not loaded\n");
  1876. if (priv->eeprom) {
  1877. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1878. pos += sprintf(buf + pos, "EEPROM version: 0x%x\n",
  1879. eeprom_ver);
  1880. } else {
  1881. pos += sprintf(buf + pos, "EEPROM not initialzed\n");
  1882. }
  1883. return pos;
  1884. }
  1885. static DEVICE_ATTR(version, S_IWUSR | S_IRUGO, show_version, NULL);
  1886. static ssize_t show_temperature(struct device *d,
  1887. struct device_attribute *attr, char *buf)
  1888. {
  1889. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  1890. if (!iwl_is_alive(priv))
  1891. return -EAGAIN;
  1892. return sprintf(buf, "%d\n", priv->temperature);
  1893. }
  1894. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  1895. static ssize_t show_tx_power(struct device *d,
  1896. struct device_attribute *attr, char *buf)
  1897. {
  1898. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  1899. if (!iwl_is_ready_rf(priv))
  1900. return sprintf(buf, "off\n");
  1901. else
  1902. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  1903. }
  1904. static ssize_t store_tx_power(struct device *d,
  1905. struct device_attribute *attr,
  1906. const char *buf, size_t count)
  1907. {
  1908. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  1909. unsigned long val;
  1910. int ret;
  1911. ret = strict_strtoul(buf, 10, &val);
  1912. if (ret)
  1913. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  1914. else
  1915. iwl_set_tx_power(priv, val, false);
  1916. return count;
  1917. }
  1918. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  1919. static ssize_t show_flags(struct device *d,
  1920. struct device_attribute *attr, char *buf)
  1921. {
  1922. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  1923. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  1924. }
  1925. static ssize_t store_flags(struct device *d,
  1926. struct device_attribute *attr,
  1927. const char *buf, size_t count)
  1928. {
  1929. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  1930. unsigned long val;
  1931. u32 flags;
  1932. int ret = strict_strtoul(buf, 0, &val);
  1933. if (ret)
  1934. return ret;
  1935. flags = (u32)val;
  1936. mutex_lock(&priv->mutex);
  1937. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  1938. /* Cancel any currently running scans... */
  1939. if (iwl_scan_cancel_timeout(priv, 100))
  1940. IWL_WARN(priv, "Could not cancel scan.\n");
  1941. else {
  1942. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  1943. priv->staging_rxon.flags = cpu_to_le32(flags);
  1944. iwlcore_commit_rxon(priv);
  1945. }
  1946. }
  1947. mutex_unlock(&priv->mutex);
  1948. return count;
  1949. }
  1950. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  1951. static ssize_t show_filter_flags(struct device *d,
  1952. struct device_attribute *attr, char *buf)
  1953. {
  1954. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  1955. return sprintf(buf, "0x%04X\n",
  1956. le32_to_cpu(priv->active_rxon.filter_flags));
  1957. }
  1958. static ssize_t store_filter_flags(struct device *d,
  1959. struct device_attribute *attr,
  1960. const char *buf, size_t count)
  1961. {
  1962. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  1963. unsigned long val;
  1964. u32 filter_flags;
  1965. int ret = strict_strtoul(buf, 0, &val);
  1966. if (ret)
  1967. return ret;
  1968. filter_flags = (u32)val;
  1969. mutex_lock(&priv->mutex);
  1970. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  1971. /* Cancel any currently running scans... */
  1972. if (iwl_scan_cancel_timeout(priv, 100))
  1973. IWL_WARN(priv, "Could not cancel scan.\n");
  1974. else {
  1975. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  1976. "0x%04X\n", filter_flags);
  1977. priv->staging_rxon.filter_flags =
  1978. cpu_to_le32(filter_flags);
  1979. iwlcore_commit_rxon(priv);
  1980. }
  1981. }
  1982. mutex_unlock(&priv->mutex);
  1983. return count;
  1984. }
  1985. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  1986. store_filter_flags);
  1987. static ssize_t store_power_level(struct device *d,
  1988. struct device_attribute *attr,
  1989. const char *buf, size_t count)
  1990. {
  1991. struct iwl_priv *priv = dev_get_drvdata(d);
  1992. int ret;
  1993. unsigned long mode;
  1994. mutex_lock(&priv->mutex);
  1995. ret = strict_strtoul(buf, 10, &mode);
  1996. if (ret)
  1997. goto out;
  1998. ret = iwl_power_set_user_mode(priv, mode);
  1999. if (ret) {
  2000. IWL_DEBUG_MAC80211(priv, "failed setting power mode.\n");
  2001. goto out;
  2002. }
  2003. ret = count;
  2004. out:
  2005. mutex_unlock(&priv->mutex);
  2006. return ret;
  2007. }
  2008. static ssize_t show_power_level(struct device *d,
  2009. struct device_attribute *attr, char *buf)
  2010. {
  2011. struct iwl_priv *priv = dev_get_drvdata(d);
  2012. int mode = priv->power_data.user_power_setting;
  2013. int system = priv->power_data.system_power_setting;
  2014. int level = priv->power_data.power_mode;
  2015. char *p = buf;
  2016. switch (system) {
  2017. case IWL_POWER_SYS_AUTO:
  2018. p += sprintf(p, "SYSTEM:auto");
  2019. break;
  2020. case IWL_POWER_SYS_AC:
  2021. p += sprintf(p, "SYSTEM:ac");
  2022. break;
  2023. case IWL_POWER_SYS_BATTERY:
  2024. p += sprintf(p, "SYSTEM:battery");
  2025. break;
  2026. }
  2027. p += sprintf(p, "\tMODE:%s", (mode < IWL_POWER_AUTO) ?
  2028. "fixed" : "auto");
  2029. p += sprintf(p, "\tINDEX:%d", level);
  2030. p += sprintf(p, "\n");
  2031. return p - buf + 1;
  2032. }
  2033. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  2034. store_power_level);
  2035. static ssize_t show_statistics(struct device *d,
  2036. struct device_attribute *attr, char *buf)
  2037. {
  2038. struct iwl_priv *priv = dev_get_drvdata(d);
  2039. u32 size = sizeof(struct iwl_notif_statistics);
  2040. u32 len = 0, ofs = 0;
  2041. u8 *data = (u8 *)&priv->statistics;
  2042. int rc = 0;
  2043. if (!iwl_is_alive(priv))
  2044. return -EAGAIN;
  2045. mutex_lock(&priv->mutex);
  2046. rc = iwl_send_statistics_request(priv, 0);
  2047. mutex_unlock(&priv->mutex);
  2048. if (rc) {
  2049. len = sprintf(buf,
  2050. "Error sending statistics request: 0x%08X\n", rc);
  2051. return len;
  2052. }
  2053. while (size && (PAGE_SIZE - len)) {
  2054. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2055. PAGE_SIZE - len, 1);
  2056. len = strlen(buf);
  2057. if (PAGE_SIZE - len)
  2058. buf[len++] = '\n';
  2059. ofs += 16;
  2060. size -= min(size, 16U);
  2061. }
  2062. return len;
  2063. }
  2064. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2065. /*****************************************************************************
  2066. *
  2067. * driver setup and teardown
  2068. *
  2069. *****************************************************************************/
  2070. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2071. {
  2072. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2073. init_waitqueue_head(&priv->wait_command_queue);
  2074. INIT_WORK(&priv->up, iwl_bg_up);
  2075. INIT_WORK(&priv->restart, iwl_bg_restart);
  2076. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2077. INIT_WORK(&priv->rf_kill, iwl_bg_rf_kill);
  2078. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2079. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2080. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2081. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2082. iwl_setup_scan_deferred_work(priv);
  2083. iwl_setup_power_deferred_work(priv);
  2084. if (priv->cfg->ops->lib->setup_deferred_work)
  2085. priv->cfg->ops->lib->setup_deferred_work(priv);
  2086. init_timer(&priv->statistics_periodic);
  2087. priv->statistics_periodic.data = (unsigned long)priv;
  2088. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2089. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2090. iwl_irq_tasklet, (unsigned long)priv);
  2091. }
  2092. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2093. {
  2094. if (priv->cfg->ops->lib->cancel_deferred_work)
  2095. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2096. cancel_delayed_work_sync(&priv->init_alive_start);
  2097. cancel_delayed_work(&priv->scan_check);
  2098. cancel_delayed_work_sync(&priv->set_power_save);
  2099. cancel_delayed_work(&priv->alive_start);
  2100. cancel_work_sync(&priv->beacon_update);
  2101. del_timer_sync(&priv->statistics_periodic);
  2102. }
  2103. static struct attribute *iwl_sysfs_entries[] = {
  2104. &dev_attr_flags.attr,
  2105. &dev_attr_filter_flags.attr,
  2106. &dev_attr_power_level.attr,
  2107. &dev_attr_statistics.attr,
  2108. &dev_attr_temperature.attr,
  2109. &dev_attr_tx_power.attr,
  2110. #ifdef CONFIG_IWLWIFI_DEBUG
  2111. &dev_attr_debug_level.attr,
  2112. #endif
  2113. &dev_attr_version.attr,
  2114. NULL
  2115. };
  2116. static struct attribute_group iwl_attribute_group = {
  2117. .name = NULL, /* put in device directory */
  2118. .attrs = iwl_sysfs_entries,
  2119. };
  2120. static struct ieee80211_ops iwl_hw_ops = {
  2121. .tx = iwl_mac_tx,
  2122. .start = iwl_mac_start,
  2123. .stop = iwl_mac_stop,
  2124. .add_interface = iwl_mac_add_interface,
  2125. .remove_interface = iwl_mac_remove_interface,
  2126. .config = iwl_mac_config,
  2127. .config_interface = iwl_mac_config_interface,
  2128. .configure_filter = iwl_configure_filter,
  2129. .set_key = iwl_mac_set_key,
  2130. .update_tkip_key = iwl_mac_update_tkip_key,
  2131. .get_stats = iwl_mac_get_stats,
  2132. .get_tx_stats = iwl_mac_get_tx_stats,
  2133. .conf_tx = iwl_mac_conf_tx,
  2134. .reset_tsf = iwl_mac_reset_tsf,
  2135. .bss_info_changed = iwl_bss_info_changed,
  2136. .ampdu_action = iwl_mac_ampdu_action,
  2137. .hw_scan = iwl_mac_hw_scan
  2138. };
  2139. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2140. {
  2141. int err = 0;
  2142. struct iwl_priv *priv;
  2143. struct ieee80211_hw *hw;
  2144. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2145. unsigned long flags;
  2146. u16 pci_cmd;
  2147. /************************
  2148. * 1. Allocating HW data
  2149. ************************/
  2150. /* Disabling hardware scan means that mac80211 will perform scans
  2151. * "the hard way", rather than using device's scan. */
  2152. if (cfg->mod_params->disable_hw_scan) {
  2153. if (cfg->mod_params->debug & IWL_DL_INFO)
  2154. dev_printk(KERN_DEBUG, &(pdev->dev),
  2155. "Disabling hw_scan\n");
  2156. iwl_hw_ops.hw_scan = NULL;
  2157. }
  2158. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2159. if (!hw) {
  2160. err = -ENOMEM;
  2161. goto out;
  2162. }
  2163. priv = hw->priv;
  2164. /* At this point both hw and priv are allocated. */
  2165. SET_IEEE80211_DEV(hw, &pdev->dev);
  2166. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2167. priv->cfg = cfg;
  2168. priv->pci_dev = pdev;
  2169. #ifdef CONFIG_IWLWIFI_DEBUG
  2170. priv->debug_level = priv->cfg->mod_params->debug;
  2171. atomic_set(&priv->restrict_refcnt, 0);
  2172. #endif
  2173. /**************************
  2174. * 2. Initializing PCI bus
  2175. **************************/
  2176. if (pci_enable_device(pdev)) {
  2177. err = -ENODEV;
  2178. goto out_ieee80211_free_hw;
  2179. }
  2180. pci_set_master(pdev);
  2181. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2182. if (!err)
  2183. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2184. if (err) {
  2185. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2186. if (!err)
  2187. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2188. /* both attempts failed: */
  2189. if (err) {
  2190. IWL_WARN(priv, "No suitable DMA available.\n");
  2191. goto out_pci_disable_device;
  2192. }
  2193. }
  2194. err = pci_request_regions(pdev, DRV_NAME);
  2195. if (err)
  2196. goto out_pci_disable_device;
  2197. pci_set_drvdata(pdev, priv);
  2198. /***********************
  2199. * 3. Read REV register
  2200. ***********************/
  2201. priv->hw_base = pci_iomap(pdev, 0, 0);
  2202. if (!priv->hw_base) {
  2203. err = -ENODEV;
  2204. goto out_pci_release_regions;
  2205. }
  2206. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2207. (unsigned long long) pci_resource_len(pdev, 0));
  2208. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2209. iwl_hw_detect(priv);
  2210. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2211. priv->cfg->name, priv->hw_rev);
  2212. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2213. * PCI Tx retries from interfering with C3 CPU state */
  2214. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2215. /* amp init */
  2216. err = priv->cfg->ops->lib->apm_ops.init(priv);
  2217. if (err < 0) {
  2218. IWL_ERR(priv, "Failed to init APMG\n");
  2219. goto out_iounmap;
  2220. }
  2221. /*****************
  2222. * 4. Read EEPROM
  2223. *****************/
  2224. /* Read the EEPROM */
  2225. err = iwl_eeprom_init(priv);
  2226. if (err) {
  2227. IWL_ERR(priv, "Unable to init EEPROM\n");
  2228. goto out_iounmap;
  2229. }
  2230. err = iwl_eeprom_check_version(priv);
  2231. if (err)
  2232. goto out_free_eeprom;
  2233. /* extract MAC Address */
  2234. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2235. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2236. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2237. /************************
  2238. * 5. Setup HW constants
  2239. ************************/
  2240. if (iwl_set_hw_params(priv)) {
  2241. IWL_ERR(priv, "failed to set hw parameters\n");
  2242. goto out_free_eeprom;
  2243. }
  2244. /*******************
  2245. * 6. Setup priv
  2246. *******************/
  2247. err = iwl_init_drv(priv);
  2248. if (err)
  2249. goto out_free_eeprom;
  2250. /* At this point both hw and priv are initialized. */
  2251. /********************
  2252. * 7. Setup services
  2253. ********************/
  2254. spin_lock_irqsave(&priv->lock, flags);
  2255. iwl_disable_interrupts(priv);
  2256. spin_unlock_irqrestore(&priv->lock, flags);
  2257. pci_enable_msi(priv->pci_dev);
  2258. err = request_irq(priv->pci_dev->irq, iwl_isr, IRQF_SHARED,
  2259. DRV_NAME, priv);
  2260. if (err) {
  2261. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2262. goto out_disable_msi;
  2263. }
  2264. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2265. if (err) {
  2266. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2267. goto out_free_irq;
  2268. }
  2269. iwl_setup_deferred_work(priv);
  2270. iwl_setup_rx_handlers(priv);
  2271. /**********************************
  2272. * 8. Setup and register mac80211
  2273. **********************************/
  2274. /* enable interrupts if needed: hw bug w/a */
  2275. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  2276. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  2277. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  2278. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  2279. }
  2280. iwl_enable_interrupts(priv);
  2281. err = iwl_setup_mac(priv);
  2282. if (err)
  2283. goto out_remove_sysfs;
  2284. err = iwl_dbgfs_register(priv, DRV_NAME);
  2285. if (err)
  2286. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  2287. /* If platform's RF_KILL switch is NOT set to KILL */
  2288. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2289. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2290. else
  2291. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2292. err = iwl_rfkill_init(priv);
  2293. if (err)
  2294. IWL_ERR(priv, "Unable to initialize RFKILL system. "
  2295. "Ignoring error: %d\n", err);
  2296. else
  2297. iwl_rfkill_set_hw_state(priv);
  2298. iwl_power_initialize(priv);
  2299. return 0;
  2300. out_remove_sysfs:
  2301. destroy_workqueue(priv->workqueue);
  2302. priv->workqueue = NULL;
  2303. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2304. out_free_irq:
  2305. free_irq(priv->pci_dev->irq, priv);
  2306. out_disable_msi:
  2307. pci_disable_msi(priv->pci_dev);
  2308. iwl_uninit_drv(priv);
  2309. out_free_eeprom:
  2310. iwl_eeprom_free(priv);
  2311. out_iounmap:
  2312. pci_iounmap(pdev, priv->hw_base);
  2313. out_pci_release_regions:
  2314. pci_set_drvdata(pdev, NULL);
  2315. pci_release_regions(pdev);
  2316. out_pci_disable_device:
  2317. pci_disable_device(pdev);
  2318. out_ieee80211_free_hw:
  2319. ieee80211_free_hw(priv->hw);
  2320. out:
  2321. return err;
  2322. }
  2323. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  2324. {
  2325. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2326. unsigned long flags;
  2327. if (!priv)
  2328. return;
  2329. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  2330. iwl_dbgfs_unregister(priv);
  2331. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2332. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  2333. * to be called and iwl_down since we are removing the device
  2334. * we need to set STATUS_EXIT_PENDING bit.
  2335. */
  2336. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2337. if (priv->mac80211_registered) {
  2338. ieee80211_unregister_hw(priv->hw);
  2339. priv->mac80211_registered = 0;
  2340. } else {
  2341. iwl_down(priv);
  2342. }
  2343. /* make sure we flush any pending irq or
  2344. * tasklet for the driver
  2345. */
  2346. spin_lock_irqsave(&priv->lock, flags);
  2347. iwl_disable_interrupts(priv);
  2348. spin_unlock_irqrestore(&priv->lock, flags);
  2349. iwl_synchronize_irq(priv);
  2350. iwl_rfkill_unregister(priv);
  2351. iwl_dealloc_ucode_pci(priv);
  2352. if (priv->rxq.bd)
  2353. iwl_rx_queue_free(priv, &priv->rxq);
  2354. iwl_hw_txq_ctx_free(priv);
  2355. priv->cfg->ops->smgmt->clear_station_table(priv);
  2356. iwl_eeprom_free(priv);
  2357. /*netif_stop_queue(dev); */
  2358. flush_workqueue(priv->workqueue);
  2359. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  2360. * priv->workqueue... so we can't take down the workqueue
  2361. * until now... */
  2362. destroy_workqueue(priv->workqueue);
  2363. priv->workqueue = NULL;
  2364. free_irq(priv->pci_dev->irq, priv);
  2365. pci_disable_msi(priv->pci_dev);
  2366. pci_iounmap(pdev, priv->hw_base);
  2367. pci_release_regions(pdev);
  2368. pci_disable_device(pdev);
  2369. pci_set_drvdata(pdev, NULL);
  2370. iwl_uninit_drv(priv);
  2371. if (priv->ibss_beacon)
  2372. dev_kfree_skb(priv->ibss_beacon);
  2373. ieee80211_free_hw(priv->hw);
  2374. }
  2375. /*****************************************************************************
  2376. *
  2377. * driver and module entry point
  2378. *
  2379. *****************************************************************************/
  2380. /* Hardware specific file defines the PCI IDs table for that hardware module */
  2381. static struct pci_device_id iwl_hw_card_ids[] = {
  2382. #ifdef CONFIG_IWL4965
  2383. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  2384. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  2385. #endif /* CONFIG_IWL4965 */
  2386. #ifdef CONFIG_IWL5000
  2387. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
  2388. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
  2389. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
  2390. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
  2391. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
  2392. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
  2393. {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
  2394. {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
  2395. {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
  2396. {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
  2397. /* 5350 WiFi/WiMax */
  2398. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
  2399. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
  2400. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
  2401. /* 5150 Wifi/WiMax */
  2402. {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
  2403. {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
  2404. /* 6000/6050 Series */
  2405. {IWL_PCI_DEVICE(0x0082, 0x1102, iwl6000_2ag_cfg)},
  2406. {IWL_PCI_DEVICE(0x0085, 0x1112, iwl6000_2ag_cfg)},
  2407. {IWL_PCI_DEVICE(0x0082, 0x1122, iwl6000_2ag_cfg)},
  2408. {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2409. {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2410. {IWL_PCI_DEVICE(0x0082, PCI_ANY_ID, iwl6000_2agn_cfg)},
  2411. {IWL_PCI_DEVICE(0x0085, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2412. {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)},
  2413. {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)},
  2414. {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)},
  2415. {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)},
  2416. /* 1000 Series WiFi */
  2417. {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl1000_bgn_cfg)},
  2418. {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl1000_bgn_cfg)},
  2419. #endif /* CONFIG_IWL5000 */
  2420. {0}
  2421. };
  2422. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  2423. static struct pci_driver iwl_driver = {
  2424. .name = DRV_NAME,
  2425. .id_table = iwl_hw_card_ids,
  2426. .probe = iwl_pci_probe,
  2427. .remove = __devexit_p(iwl_pci_remove),
  2428. #ifdef CONFIG_PM
  2429. .suspend = iwl_pci_suspend,
  2430. .resume = iwl_pci_resume,
  2431. #endif
  2432. };
  2433. static int __init iwl_init(void)
  2434. {
  2435. int ret;
  2436. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  2437. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  2438. ret = iwlagn_rate_control_register();
  2439. if (ret) {
  2440. printk(KERN_ERR DRV_NAME
  2441. "Unable to register rate control algorithm: %d\n", ret);
  2442. return ret;
  2443. }
  2444. ret = pci_register_driver(&iwl_driver);
  2445. if (ret) {
  2446. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  2447. goto error_register;
  2448. }
  2449. return ret;
  2450. error_register:
  2451. iwlagn_rate_control_unregister();
  2452. return ret;
  2453. }
  2454. static void __exit iwl_exit(void)
  2455. {
  2456. pci_unregister_driver(&iwl_driver);
  2457. iwlagn_rate_control_unregister();
  2458. }
  2459. module_exit(iwl_exit);
  2460. module_init(iwl_init);