xfp_phy.c 6.3 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2006-2008 Solarflare Communications Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published
  7. * by the Free Software Foundation, incorporated herein by reference.
  8. */
  9. /*
  10. * Driver for SFP+ and XFP optical PHYs plus some support specific to the
  11. * AMCC QT20xx adapters; see www.amcc.com for details
  12. */
  13. #include <linux/timer.h>
  14. #include <linux/delay.h>
  15. #include "efx.h"
  16. #include "mdio_10g.h"
  17. #include "xenpack.h"
  18. #include "phy.h"
  19. #include "falcon.h"
  20. #define XFP_REQUIRED_DEVS (MDIO_DEVS_PCS | \
  21. MDIO_DEVS_PMAPMD | \
  22. MDIO_DEVS_PHYXS)
  23. #define XFP_LOOPBACKS ((1 << LOOPBACK_PCS) | \
  24. (1 << LOOPBACK_PMAPMD) | \
  25. (1 << LOOPBACK_NETWORK))
  26. /****************************************************************************/
  27. /* Quake-specific MDIO registers */
  28. #define MDIO_QUAKE_LED0_REG (0xD006)
  29. /* QT2025C only */
  30. #define PCS_FW_HEARTBEAT_REG 0xd7ee
  31. #define PCS_FW_HEARTB_LBN 0
  32. #define PCS_FW_HEARTB_WIDTH 8
  33. #define PCS_UC8051_STATUS_REG 0xd7fd
  34. #define PCS_UC_STATUS_LBN 0
  35. #define PCS_UC_STATUS_WIDTH 8
  36. #define PCS_UC_STATUS_FW_SAVE 0x20
  37. #define PMA_PMD_FTX_CTRL2_REG 0xc309
  38. #define PMA_PMD_FTX_STATIC_LBN 13
  39. #define PMA_PMD_VEND1_REG 0xc001
  40. #define PMA_PMD_VEND1_LBTXD_LBN 15
  41. #define PCS_VEND1_REG 0xc000
  42. #define PCS_VEND1_LBTXD_LBN 5
  43. void xfp_set_led(struct efx_nic *p, int led, int mode)
  44. {
  45. int addr = MDIO_QUAKE_LED0_REG + led;
  46. efx_mdio_write(p, MDIO_MMD_PMAPMD, addr, mode);
  47. }
  48. struct xfp_phy_data {
  49. enum efx_phy_mode phy_mode;
  50. };
  51. #define XFP_MAX_RESET_TIME 500
  52. #define XFP_RESET_WAIT 10
  53. static int qt2025c_wait_reset(struct efx_nic *efx)
  54. {
  55. unsigned long timeout = jiffies + 10 * HZ;
  56. int reg, old_counter = 0;
  57. /* Wait for firmware heartbeat to start */
  58. for (;;) {
  59. int counter;
  60. reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG);
  61. if (reg < 0)
  62. return reg;
  63. counter = ((reg >> PCS_FW_HEARTB_LBN) &
  64. ((1 << PCS_FW_HEARTB_WIDTH) - 1));
  65. if (old_counter == 0)
  66. old_counter = counter;
  67. else if (counter != old_counter)
  68. break;
  69. if (time_after(jiffies, timeout))
  70. return -ETIMEDOUT;
  71. msleep(10);
  72. }
  73. /* Wait for firmware status to look good */
  74. for (;;) {
  75. reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG);
  76. if (reg < 0)
  77. return reg;
  78. if ((reg &
  79. ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >=
  80. PCS_UC_STATUS_FW_SAVE)
  81. break;
  82. if (time_after(jiffies, timeout))
  83. return -ETIMEDOUT;
  84. msleep(100);
  85. }
  86. return 0;
  87. }
  88. /* Reset the PHYXS MMD. This is documented (for the Quake PHYs) as doing
  89. * a complete soft reset.
  90. */
  91. static int xfp_reset_phy(struct efx_nic *efx)
  92. {
  93. int rc;
  94. rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PHYXS,
  95. XFP_MAX_RESET_TIME / XFP_RESET_WAIT,
  96. XFP_RESET_WAIT);
  97. if (rc < 0)
  98. goto fail;
  99. if (efx->phy_type == PHY_TYPE_QT2025C) {
  100. rc = qt2025c_wait_reset(efx);
  101. if (rc < 0)
  102. goto fail;
  103. }
  104. /* Wait 250ms for the PHY to complete bootup */
  105. msleep(250);
  106. /* Check that all the MMDs we expect are present and responding. We
  107. * expect faults on some if the link is down, but not on the PHY XS */
  108. rc = efx_mdio_check_mmds(efx, XFP_REQUIRED_DEVS, MDIO_DEVS_PHYXS);
  109. if (rc < 0)
  110. goto fail;
  111. efx->board_info.init_leds(efx);
  112. return rc;
  113. fail:
  114. EFX_ERR(efx, "PHY reset timed out\n");
  115. return rc;
  116. }
  117. static int xfp_phy_init(struct efx_nic *efx)
  118. {
  119. struct xfp_phy_data *phy_data;
  120. u32 devid = efx_mdio_read_id(efx, MDIO_MMD_PHYXS);
  121. int rc;
  122. phy_data = kzalloc(sizeof(struct xfp_phy_data), GFP_KERNEL);
  123. if (!phy_data)
  124. return -ENOMEM;
  125. efx->phy_data = phy_data;
  126. EFX_INFO(efx, "PHY ID reg %x (OUI %06x model %02x revision %x)\n",
  127. devid, efx_mdio_id_oui(devid), efx_mdio_id_model(devid),
  128. efx_mdio_id_rev(devid));
  129. phy_data->phy_mode = efx->phy_mode;
  130. rc = xfp_reset_phy(efx);
  131. EFX_INFO(efx, "PHY init %s.\n",
  132. rc ? "failed" : "successful");
  133. if (rc < 0)
  134. goto fail;
  135. return 0;
  136. fail:
  137. kfree(efx->phy_data);
  138. efx->phy_data = NULL;
  139. return rc;
  140. }
  141. static void xfp_phy_clear_interrupt(struct efx_nic *efx)
  142. {
  143. xenpack_clear_lasi_irqs(efx);
  144. }
  145. static int xfp_link_ok(struct efx_nic *efx)
  146. {
  147. return efx_mdio_links_ok(efx, XFP_REQUIRED_DEVS);
  148. }
  149. static void xfp_phy_poll(struct efx_nic *efx)
  150. {
  151. int link_up = xfp_link_ok(efx);
  152. /* Simulate a PHY event if link state has changed */
  153. if (link_up != efx->link_up)
  154. falcon_sim_phy_event(efx);
  155. }
  156. static void xfp_phy_reconfigure(struct efx_nic *efx)
  157. {
  158. struct xfp_phy_data *phy_data = efx->phy_data;
  159. if (efx->phy_type == PHY_TYPE_QT2025C) {
  160. /* There are several different register bits which can
  161. * disable TX (and save power) on direct-attach cables
  162. * or optical transceivers, varying somewhat between
  163. * firmware versions. Only 'static mode' appears to
  164. * cover everything. */
  165. mdio_set_flag(
  166. &efx->mdio, efx->mdio.prtad, MDIO_MMD_PMAPMD,
  167. PMA_PMD_FTX_CTRL2_REG, 1 << PMA_PMD_FTX_STATIC_LBN,
  168. efx->phy_mode & PHY_MODE_TX_DISABLED ||
  169. efx->phy_mode & PHY_MODE_LOW_POWER ||
  170. efx->loopback_mode == LOOPBACK_PCS ||
  171. efx->loopback_mode == LOOPBACK_PMAPMD);
  172. } else {
  173. /* Reset the PHY when moving from tx off to tx on */
  174. if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) &&
  175. (phy_data->phy_mode & PHY_MODE_TX_DISABLED))
  176. xfp_reset_phy(efx);
  177. efx_mdio_transmit_disable(efx);
  178. }
  179. efx_mdio_phy_reconfigure(efx);
  180. phy_data->phy_mode = efx->phy_mode;
  181. efx->link_up = xfp_link_ok(efx);
  182. efx->link_speed = 10000;
  183. efx->link_fd = true;
  184. efx->link_fc = efx->wanted_fc;
  185. }
  186. static void xfp_phy_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
  187. {
  188. mdio45_ethtool_gset(&efx->mdio, ecmd);
  189. }
  190. static void xfp_phy_fini(struct efx_nic *efx)
  191. {
  192. /* Clobber the LED if it was blinking */
  193. efx->board_info.blink(efx, false);
  194. /* Free the context block */
  195. kfree(efx->phy_data);
  196. efx->phy_data = NULL;
  197. }
  198. struct efx_phy_operations falcon_xfp_phy_ops = {
  199. .macs = EFX_XMAC,
  200. .init = xfp_phy_init,
  201. .reconfigure = xfp_phy_reconfigure,
  202. .poll = xfp_phy_poll,
  203. .fini = xfp_phy_fini,
  204. .clear_interrupt = xfp_phy_clear_interrupt,
  205. .get_settings = xfp_phy_get_settings,
  206. .set_settings = efx_mdio_set_settings,
  207. .mmds = XFP_REQUIRED_DEVS,
  208. .loopbacks = XFP_LOOPBACKS,
  209. };