qeth_core_main.c 123 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/string.h>
  13. #include <linux/errno.h>
  14. #include <linux/kernel.h>
  15. #include <linux/ip.h>
  16. #include <linux/ipv6.h>
  17. #include <linux/tcp.h>
  18. #include <linux/mii.h>
  19. #include <linux/kthread.h>
  20. #include <asm-s390/ebcdic.h>
  21. #include <asm-s390/io.h>
  22. #include <asm/s390_rdev.h>
  23. #include "qeth_core.h"
  24. #include "qeth_core_offl.h"
  25. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  26. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  27. /* N P A M L V H */
  28. [QETH_DBF_SETUP] = {"qeth_setup",
  29. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  30. [QETH_DBF_QERR] = {"qeth_qerr",
  31. 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
  32. [QETH_DBF_TRACE] = {"qeth_trace",
  33. 4, 1, 8, 3, &debug_hex_ascii_view, NULL},
  34. [QETH_DBF_MSG] = {"qeth_msg",
  35. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  36. [QETH_DBF_SENSE] = {"qeth_sense",
  37. 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
  38. [QETH_DBF_MISC] = {"qeth_misc",
  39. 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
  40. [QETH_DBF_CTRL] = {"qeth_control",
  41. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  42. };
  43. EXPORT_SYMBOL_GPL(qeth_dbf);
  44. struct qeth_card_list_struct qeth_core_card_list;
  45. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  46. static struct device *qeth_core_root_dev;
  47. static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
  48. static struct lock_class_key qdio_out_skb_queue_key;
  49. static void qeth_send_control_data_cb(struct qeth_channel *,
  50. struct qeth_cmd_buffer *);
  51. static int qeth_issue_next_read(struct qeth_card *);
  52. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  53. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  54. static void qeth_free_buffer_pool(struct qeth_card *);
  55. static int qeth_qdio_establish(struct qeth_card *);
  56. static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
  57. struct qdio_buffer *buffer, int is_tso,
  58. int *next_element_to_fill)
  59. {
  60. struct skb_frag_struct *frag;
  61. int fragno;
  62. unsigned long addr;
  63. int element, cnt, dlen;
  64. fragno = skb_shinfo(skb)->nr_frags;
  65. element = *next_element_to_fill;
  66. dlen = 0;
  67. if (is_tso)
  68. buffer->element[element].flags =
  69. SBAL_FLAGS_MIDDLE_FRAG;
  70. else
  71. buffer->element[element].flags =
  72. SBAL_FLAGS_FIRST_FRAG;
  73. dlen = skb->len - skb->data_len;
  74. if (dlen) {
  75. buffer->element[element].addr = skb->data;
  76. buffer->element[element].length = dlen;
  77. element++;
  78. }
  79. for (cnt = 0; cnt < fragno; cnt++) {
  80. frag = &skb_shinfo(skb)->frags[cnt];
  81. addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
  82. frag->page_offset;
  83. buffer->element[element].addr = (char *)addr;
  84. buffer->element[element].length = frag->size;
  85. if (cnt < (fragno - 1))
  86. buffer->element[element].flags =
  87. SBAL_FLAGS_MIDDLE_FRAG;
  88. else
  89. buffer->element[element].flags =
  90. SBAL_FLAGS_LAST_FRAG;
  91. element++;
  92. }
  93. *next_element_to_fill = element;
  94. }
  95. static inline const char *qeth_get_cardname(struct qeth_card *card)
  96. {
  97. if (card->info.guestlan) {
  98. switch (card->info.type) {
  99. case QETH_CARD_TYPE_OSAE:
  100. return " Guest LAN QDIO";
  101. case QETH_CARD_TYPE_IQD:
  102. return " Guest LAN Hiper";
  103. default:
  104. return " unknown";
  105. }
  106. } else {
  107. switch (card->info.type) {
  108. case QETH_CARD_TYPE_OSAE:
  109. return " OSD Express";
  110. case QETH_CARD_TYPE_IQD:
  111. return " HiperSockets";
  112. case QETH_CARD_TYPE_OSN:
  113. return " OSN QDIO";
  114. default:
  115. return " unknown";
  116. }
  117. }
  118. return " n/a";
  119. }
  120. /* max length to be returned: 14 */
  121. const char *qeth_get_cardname_short(struct qeth_card *card)
  122. {
  123. if (card->info.guestlan) {
  124. switch (card->info.type) {
  125. case QETH_CARD_TYPE_OSAE:
  126. return "GuestLAN QDIO";
  127. case QETH_CARD_TYPE_IQD:
  128. return "GuestLAN Hiper";
  129. default:
  130. return "unknown";
  131. }
  132. } else {
  133. switch (card->info.type) {
  134. case QETH_CARD_TYPE_OSAE:
  135. switch (card->info.link_type) {
  136. case QETH_LINK_TYPE_FAST_ETH:
  137. return "OSD_100";
  138. case QETH_LINK_TYPE_HSTR:
  139. return "HSTR";
  140. case QETH_LINK_TYPE_GBIT_ETH:
  141. return "OSD_1000";
  142. case QETH_LINK_TYPE_10GBIT_ETH:
  143. return "OSD_10GIG";
  144. case QETH_LINK_TYPE_LANE_ETH100:
  145. return "OSD_FE_LANE";
  146. case QETH_LINK_TYPE_LANE_TR:
  147. return "OSD_TR_LANE";
  148. case QETH_LINK_TYPE_LANE_ETH1000:
  149. return "OSD_GbE_LANE";
  150. case QETH_LINK_TYPE_LANE:
  151. return "OSD_ATM_LANE";
  152. default:
  153. return "OSD_Express";
  154. }
  155. case QETH_CARD_TYPE_IQD:
  156. return "HiperSockets";
  157. case QETH_CARD_TYPE_OSN:
  158. return "OSN";
  159. default:
  160. return "unknown";
  161. }
  162. }
  163. return "n/a";
  164. }
  165. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  166. int clear_start_mask)
  167. {
  168. unsigned long flags;
  169. spin_lock_irqsave(&card->thread_mask_lock, flags);
  170. card->thread_allowed_mask = threads;
  171. if (clear_start_mask)
  172. card->thread_start_mask &= threads;
  173. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  174. wake_up(&card->wait_q);
  175. }
  176. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  177. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  178. {
  179. unsigned long flags;
  180. int rc = 0;
  181. spin_lock_irqsave(&card->thread_mask_lock, flags);
  182. rc = (card->thread_running_mask & threads);
  183. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  184. return rc;
  185. }
  186. EXPORT_SYMBOL_GPL(qeth_threads_running);
  187. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  188. {
  189. return wait_event_interruptible(card->wait_q,
  190. qeth_threads_running(card, threads) == 0);
  191. }
  192. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  193. void qeth_clear_working_pool_list(struct qeth_card *card)
  194. {
  195. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  196. QETH_DBF_TEXT(TRACE, 5, "clwrklst");
  197. list_for_each_entry_safe(pool_entry, tmp,
  198. &card->qdio.in_buf_pool.entry_list, list){
  199. list_del(&pool_entry->list);
  200. }
  201. }
  202. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  203. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  204. {
  205. struct qeth_buffer_pool_entry *pool_entry;
  206. void *ptr;
  207. int i, j;
  208. QETH_DBF_TEXT(TRACE, 5, "alocpool");
  209. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  210. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  211. if (!pool_entry) {
  212. qeth_free_buffer_pool(card);
  213. return -ENOMEM;
  214. }
  215. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  216. ptr = (void *) __get_free_page(GFP_KERNEL);
  217. if (!ptr) {
  218. while (j > 0)
  219. free_page((unsigned long)
  220. pool_entry->elements[--j]);
  221. kfree(pool_entry);
  222. qeth_free_buffer_pool(card);
  223. return -ENOMEM;
  224. }
  225. pool_entry->elements[j] = ptr;
  226. }
  227. list_add(&pool_entry->init_list,
  228. &card->qdio.init_pool.entry_list);
  229. }
  230. return 0;
  231. }
  232. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  233. {
  234. QETH_DBF_TEXT(TRACE, 2, "realcbp");
  235. if ((card->state != CARD_STATE_DOWN) &&
  236. (card->state != CARD_STATE_RECOVER))
  237. return -EPERM;
  238. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  239. qeth_clear_working_pool_list(card);
  240. qeth_free_buffer_pool(card);
  241. card->qdio.in_buf_pool.buf_count = bufcnt;
  242. card->qdio.init_pool.buf_count = bufcnt;
  243. return qeth_alloc_buffer_pool(card);
  244. }
  245. int qeth_set_large_send(struct qeth_card *card,
  246. enum qeth_large_send_types type)
  247. {
  248. int rc = 0;
  249. if (card->dev == NULL) {
  250. card->options.large_send = type;
  251. return 0;
  252. }
  253. if (card->state == CARD_STATE_UP)
  254. netif_tx_disable(card->dev);
  255. card->options.large_send = type;
  256. switch (card->options.large_send) {
  257. case QETH_LARGE_SEND_EDDP:
  258. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  259. NETIF_F_HW_CSUM;
  260. break;
  261. case QETH_LARGE_SEND_TSO:
  262. if (qeth_is_supported(card, IPA_OUTBOUND_TSO)) {
  263. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  264. NETIF_F_HW_CSUM;
  265. } else {
  266. PRINT_WARN("TSO not supported on %s. "
  267. "large_send set to 'no'.\n",
  268. card->dev->name);
  269. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  270. NETIF_F_HW_CSUM);
  271. card->options.large_send = QETH_LARGE_SEND_NO;
  272. rc = -EOPNOTSUPP;
  273. }
  274. break;
  275. default: /* includes QETH_LARGE_SEND_NO */
  276. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  277. NETIF_F_HW_CSUM);
  278. break;
  279. }
  280. if (card->state == CARD_STATE_UP)
  281. netif_wake_queue(card->dev);
  282. return rc;
  283. }
  284. EXPORT_SYMBOL_GPL(qeth_set_large_send);
  285. static int qeth_issue_next_read(struct qeth_card *card)
  286. {
  287. int rc;
  288. struct qeth_cmd_buffer *iob;
  289. QETH_DBF_TEXT(TRACE, 5, "issnxrd");
  290. if (card->read.state != CH_STATE_UP)
  291. return -EIO;
  292. iob = qeth_get_buffer(&card->read);
  293. if (!iob) {
  294. PRINT_WARN("issue_next_read failed: no iob available!\n");
  295. return -ENOMEM;
  296. }
  297. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  298. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  299. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  300. (addr_t) iob, 0, 0);
  301. if (rc) {
  302. PRINT_ERR("Error in starting next read ccw! rc=%i\n", rc);
  303. atomic_set(&card->read.irq_pending, 0);
  304. qeth_schedule_recovery(card);
  305. wake_up(&card->wait_q);
  306. }
  307. return rc;
  308. }
  309. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  310. {
  311. struct qeth_reply *reply;
  312. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  313. if (reply) {
  314. atomic_set(&reply->refcnt, 1);
  315. atomic_set(&reply->received, 0);
  316. reply->card = card;
  317. };
  318. return reply;
  319. }
  320. static void qeth_get_reply(struct qeth_reply *reply)
  321. {
  322. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  323. atomic_inc(&reply->refcnt);
  324. }
  325. static void qeth_put_reply(struct qeth_reply *reply)
  326. {
  327. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  328. if (atomic_dec_and_test(&reply->refcnt))
  329. kfree(reply);
  330. }
  331. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  332. struct qeth_card *card)
  333. {
  334. char *ipa_name;
  335. int com = cmd->hdr.command;
  336. ipa_name = qeth_get_ipa_cmd_name(com);
  337. if (rc)
  338. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
  339. ipa_name, com, QETH_CARD_IFNAME(card),
  340. rc, qeth_get_ipa_msg(rc));
  341. else
  342. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
  343. ipa_name, com, QETH_CARD_IFNAME(card));
  344. }
  345. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  346. struct qeth_cmd_buffer *iob)
  347. {
  348. struct qeth_ipa_cmd *cmd = NULL;
  349. QETH_DBF_TEXT(TRACE, 5, "chkipad");
  350. if (IS_IPA(iob->data)) {
  351. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  352. if (IS_IPA_REPLY(cmd)) {
  353. if (cmd->hdr.command < IPA_CMD_SETCCID ||
  354. cmd->hdr.command > IPA_CMD_MODCCID)
  355. qeth_issue_ipa_msg(cmd,
  356. cmd->hdr.return_code, card);
  357. return cmd;
  358. } else {
  359. switch (cmd->hdr.command) {
  360. case IPA_CMD_STOPLAN:
  361. PRINT_WARN("Link failure on %s (CHPID 0x%X) - "
  362. "there is a network problem or "
  363. "someone pulled the cable or "
  364. "disabled the port.\n",
  365. QETH_CARD_IFNAME(card),
  366. card->info.chpid);
  367. card->lan_online = 0;
  368. if (card->dev && netif_carrier_ok(card->dev))
  369. netif_carrier_off(card->dev);
  370. return NULL;
  371. case IPA_CMD_STARTLAN:
  372. PRINT_INFO("Link reestablished on %s "
  373. "(CHPID 0x%X). Scheduling "
  374. "IP address reset.\n",
  375. QETH_CARD_IFNAME(card),
  376. card->info.chpid);
  377. netif_carrier_on(card->dev);
  378. card->lan_online = 1;
  379. qeth_schedule_recovery(card);
  380. return NULL;
  381. case IPA_CMD_MODCCID:
  382. return cmd;
  383. case IPA_CMD_REGISTER_LOCAL_ADDR:
  384. QETH_DBF_TEXT(TRACE, 3, "irla");
  385. break;
  386. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  387. QETH_DBF_TEXT(TRACE, 3, "urla");
  388. break;
  389. default:
  390. PRINT_WARN("Received data is IPA "
  391. "but not a reply!\n");
  392. break;
  393. }
  394. }
  395. }
  396. return cmd;
  397. }
  398. void qeth_clear_ipacmd_list(struct qeth_card *card)
  399. {
  400. struct qeth_reply *reply, *r;
  401. unsigned long flags;
  402. QETH_DBF_TEXT(TRACE, 4, "clipalst");
  403. spin_lock_irqsave(&card->lock, flags);
  404. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  405. qeth_get_reply(reply);
  406. reply->rc = -EIO;
  407. atomic_inc(&reply->received);
  408. list_del_init(&reply->list);
  409. wake_up(&reply->wait_q);
  410. qeth_put_reply(reply);
  411. }
  412. spin_unlock_irqrestore(&card->lock, flags);
  413. }
  414. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  415. static int qeth_check_idx_response(unsigned char *buffer)
  416. {
  417. if (!buffer)
  418. return 0;
  419. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  420. if ((buffer[2] & 0xc0) == 0xc0) {
  421. PRINT_WARN("received an IDX TERMINATE "
  422. "with cause code 0x%02x%s\n",
  423. buffer[4],
  424. ((buffer[4] == 0x22) ?
  425. " -- try another portname" : ""));
  426. QETH_DBF_TEXT(TRACE, 2, "ckidxres");
  427. QETH_DBF_TEXT(TRACE, 2, " idxterm");
  428. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  429. return -EIO;
  430. }
  431. return 0;
  432. }
  433. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  434. __u32 len)
  435. {
  436. struct qeth_card *card;
  437. QETH_DBF_TEXT(TRACE, 4, "setupccw");
  438. card = CARD_FROM_CDEV(channel->ccwdev);
  439. if (channel == &card->read)
  440. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  441. else
  442. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  443. channel->ccw.count = len;
  444. channel->ccw.cda = (__u32) __pa(iob);
  445. }
  446. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  447. {
  448. __u8 index;
  449. QETH_DBF_TEXT(TRACE, 6, "getbuff");
  450. index = channel->io_buf_no;
  451. do {
  452. if (channel->iob[index].state == BUF_STATE_FREE) {
  453. channel->iob[index].state = BUF_STATE_LOCKED;
  454. channel->io_buf_no = (channel->io_buf_no + 1) %
  455. QETH_CMD_BUFFER_NO;
  456. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  457. return channel->iob + index;
  458. }
  459. index = (index + 1) % QETH_CMD_BUFFER_NO;
  460. } while (index != channel->io_buf_no);
  461. return NULL;
  462. }
  463. void qeth_release_buffer(struct qeth_channel *channel,
  464. struct qeth_cmd_buffer *iob)
  465. {
  466. unsigned long flags;
  467. QETH_DBF_TEXT(TRACE, 6, "relbuff");
  468. spin_lock_irqsave(&channel->iob_lock, flags);
  469. memset(iob->data, 0, QETH_BUFSIZE);
  470. iob->state = BUF_STATE_FREE;
  471. iob->callback = qeth_send_control_data_cb;
  472. iob->rc = 0;
  473. spin_unlock_irqrestore(&channel->iob_lock, flags);
  474. }
  475. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  476. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  477. {
  478. struct qeth_cmd_buffer *buffer = NULL;
  479. unsigned long flags;
  480. spin_lock_irqsave(&channel->iob_lock, flags);
  481. buffer = __qeth_get_buffer(channel);
  482. spin_unlock_irqrestore(&channel->iob_lock, flags);
  483. return buffer;
  484. }
  485. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  486. {
  487. struct qeth_cmd_buffer *buffer;
  488. wait_event(channel->wait_q,
  489. ((buffer = qeth_get_buffer(channel)) != NULL));
  490. return buffer;
  491. }
  492. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  493. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  494. {
  495. int cnt;
  496. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  497. qeth_release_buffer(channel, &channel->iob[cnt]);
  498. channel->buf_no = 0;
  499. channel->io_buf_no = 0;
  500. }
  501. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  502. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  503. struct qeth_cmd_buffer *iob)
  504. {
  505. struct qeth_card *card;
  506. struct qeth_reply *reply, *r;
  507. struct qeth_ipa_cmd *cmd;
  508. unsigned long flags;
  509. int keep_reply;
  510. QETH_DBF_TEXT(TRACE, 4, "sndctlcb");
  511. card = CARD_FROM_CDEV(channel->ccwdev);
  512. if (qeth_check_idx_response(iob->data)) {
  513. qeth_clear_ipacmd_list(card);
  514. qeth_schedule_recovery(card);
  515. goto out;
  516. }
  517. cmd = qeth_check_ipa_data(card, iob);
  518. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  519. goto out;
  520. /*in case of OSN : check if cmd is set */
  521. if (card->info.type == QETH_CARD_TYPE_OSN &&
  522. cmd &&
  523. cmd->hdr.command != IPA_CMD_STARTLAN &&
  524. card->osn_info.assist_cb != NULL) {
  525. card->osn_info.assist_cb(card->dev, cmd);
  526. goto out;
  527. }
  528. spin_lock_irqsave(&card->lock, flags);
  529. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  530. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  531. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  532. qeth_get_reply(reply);
  533. list_del_init(&reply->list);
  534. spin_unlock_irqrestore(&card->lock, flags);
  535. keep_reply = 0;
  536. if (reply->callback != NULL) {
  537. if (cmd) {
  538. reply->offset = (__u16)((char *)cmd -
  539. (char *)iob->data);
  540. keep_reply = reply->callback(card,
  541. reply,
  542. (unsigned long)cmd);
  543. } else
  544. keep_reply = reply->callback(card,
  545. reply,
  546. (unsigned long)iob);
  547. }
  548. if (cmd)
  549. reply->rc = (u16) cmd->hdr.return_code;
  550. else if (iob->rc)
  551. reply->rc = iob->rc;
  552. if (keep_reply) {
  553. spin_lock_irqsave(&card->lock, flags);
  554. list_add_tail(&reply->list,
  555. &card->cmd_waiter_list);
  556. spin_unlock_irqrestore(&card->lock, flags);
  557. } else {
  558. atomic_inc(&reply->received);
  559. wake_up(&reply->wait_q);
  560. }
  561. qeth_put_reply(reply);
  562. goto out;
  563. }
  564. }
  565. spin_unlock_irqrestore(&card->lock, flags);
  566. out:
  567. memcpy(&card->seqno.pdu_hdr_ack,
  568. QETH_PDU_HEADER_SEQ_NO(iob->data),
  569. QETH_SEQ_NO_LENGTH);
  570. qeth_release_buffer(channel, iob);
  571. }
  572. static int qeth_setup_channel(struct qeth_channel *channel)
  573. {
  574. int cnt;
  575. QETH_DBF_TEXT(SETUP, 2, "setupch");
  576. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  577. channel->iob[cnt].data = (char *)
  578. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  579. if (channel->iob[cnt].data == NULL)
  580. break;
  581. channel->iob[cnt].state = BUF_STATE_FREE;
  582. channel->iob[cnt].channel = channel;
  583. channel->iob[cnt].callback = qeth_send_control_data_cb;
  584. channel->iob[cnt].rc = 0;
  585. }
  586. if (cnt < QETH_CMD_BUFFER_NO) {
  587. while (cnt-- > 0)
  588. kfree(channel->iob[cnt].data);
  589. return -ENOMEM;
  590. }
  591. channel->buf_no = 0;
  592. channel->io_buf_no = 0;
  593. atomic_set(&channel->irq_pending, 0);
  594. spin_lock_init(&channel->iob_lock);
  595. init_waitqueue_head(&channel->wait_q);
  596. return 0;
  597. }
  598. static int qeth_set_thread_start_bit(struct qeth_card *card,
  599. unsigned long thread)
  600. {
  601. unsigned long flags;
  602. spin_lock_irqsave(&card->thread_mask_lock, flags);
  603. if (!(card->thread_allowed_mask & thread) ||
  604. (card->thread_start_mask & thread)) {
  605. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  606. return -EPERM;
  607. }
  608. card->thread_start_mask |= thread;
  609. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  610. return 0;
  611. }
  612. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  613. {
  614. unsigned long flags;
  615. spin_lock_irqsave(&card->thread_mask_lock, flags);
  616. card->thread_start_mask &= ~thread;
  617. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  618. wake_up(&card->wait_q);
  619. }
  620. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  621. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  622. {
  623. unsigned long flags;
  624. spin_lock_irqsave(&card->thread_mask_lock, flags);
  625. card->thread_running_mask &= ~thread;
  626. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  627. wake_up(&card->wait_q);
  628. }
  629. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  630. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  631. {
  632. unsigned long flags;
  633. int rc = 0;
  634. spin_lock_irqsave(&card->thread_mask_lock, flags);
  635. if (card->thread_start_mask & thread) {
  636. if ((card->thread_allowed_mask & thread) &&
  637. !(card->thread_running_mask & thread)) {
  638. rc = 1;
  639. card->thread_start_mask &= ~thread;
  640. card->thread_running_mask |= thread;
  641. } else
  642. rc = -EPERM;
  643. }
  644. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  645. return rc;
  646. }
  647. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  648. {
  649. int rc = 0;
  650. wait_event(card->wait_q,
  651. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  652. return rc;
  653. }
  654. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  655. void qeth_schedule_recovery(struct qeth_card *card)
  656. {
  657. QETH_DBF_TEXT(TRACE, 2, "startrec");
  658. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  659. schedule_work(&card->kernel_thread_starter);
  660. }
  661. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  662. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  663. {
  664. int dstat, cstat;
  665. char *sense;
  666. sense = (char *) irb->ecw;
  667. cstat = irb->scsw.cstat;
  668. dstat = irb->scsw.dstat;
  669. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  670. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  671. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  672. QETH_DBF_TEXT(TRACE, 2, "CGENCHK");
  673. PRINT_WARN("check on device %s, dstat=x%x, cstat=x%x ",
  674. cdev->dev.bus_id, dstat, cstat);
  675. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  676. 16, 1, irb, 64, 1);
  677. return 1;
  678. }
  679. if (dstat & DEV_STAT_UNIT_CHECK) {
  680. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  681. SENSE_RESETTING_EVENT_FLAG) {
  682. QETH_DBF_TEXT(TRACE, 2, "REVIND");
  683. return 1;
  684. }
  685. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  686. SENSE_COMMAND_REJECT_FLAG) {
  687. QETH_DBF_TEXT(TRACE, 2, "CMDREJi");
  688. return 0;
  689. }
  690. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  691. QETH_DBF_TEXT(TRACE, 2, "AFFE");
  692. return 1;
  693. }
  694. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  695. QETH_DBF_TEXT(TRACE, 2, "ZEROSEN");
  696. return 0;
  697. }
  698. QETH_DBF_TEXT(TRACE, 2, "DGENCHK");
  699. return 1;
  700. }
  701. return 0;
  702. }
  703. static long __qeth_check_irb_error(struct ccw_device *cdev,
  704. unsigned long intparm, struct irb *irb)
  705. {
  706. if (!IS_ERR(irb))
  707. return 0;
  708. switch (PTR_ERR(irb)) {
  709. case -EIO:
  710. PRINT_WARN("i/o-error on device %s\n", cdev->dev.bus_id);
  711. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  712. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  713. break;
  714. case -ETIMEDOUT:
  715. PRINT_WARN("timeout on device %s\n", cdev->dev.bus_id);
  716. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  717. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT);
  718. if (intparm == QETH_RCD_PARM) {
  719. struct qeth_card *card = CARD_FROM_CDEV(cdev);
  720. if (card && (card->data.ccwdev == cdev)) {
  721. card->data.state = CH_STATE_DOWN;
  722. wake_up(&card->wait_q);
  723. }
  724. }
  725. break;
  726. default:
  727. PRINT_WARN("unknown error %ld on device %s\n", PTR_ERR(irb),
  728. cdev->dev.bus_id);
  729. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  730. QETH_DBF_TEXT(TRACE, 2, " rc???");
  731. }
  732. return PTR_ERR(irb);
  733. }
  734. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  735. struct irb *irb)
  736. {
  737. int rc;
  738. int cstat, dstat;
  739. struct qeth_cmd_buffer *buffer;
  740. struct qeth_channel *channel;
  741. struct qeth_card *card;
  742. struct qeth_cmd_buffer *iob;
  743. __u8 index;
  744. QETH_DBF_TEXT(TRACE, 5, "irq");
  745. if (__qeth_check_irb_error(cdev, intparm, irb))
  746. return;
  747. cstat = irb->scsw.cstat;
  748. dstat = irb->scsw.dstat;
  749. card = CARD_FROM_CDEV(cdev);
  750. if (!card)
  751. return;
  752. if (card->read.ccwdev == cdev) {
  753. channel = &card->read;
  754. QETH_DBF_TEXT(TRACE, 5, "read");
  755. } else if (card->write.ccwdev == cdev) {
  756. channel = &card->write;
  757. QETH_DBF_TEXT(TRACE, 5, "write");
  758. } else {
  759. channel = &card->data;
  760. QETH_DBF_TEXT(TRACE, 5, "data");
  761. }
  762. atomic_set(&channel->irq_pending, 0);
  763. if (irb->scsw.fctl & (SCSW_FCTL_CLEAR_FUNC))
  764. channel->state = CH_STATE_STOPPED;
  765. if (irb->scsw.fctl & (SCSW_FCTL_HALT_FUNC))
  766. channel->state = CH_STATE_HALTED;
  767. /*let's wake up immediately on data channel*/
  768. if ((channel == &card->data) && (intparm != 0) &&
  769. (intparm != QETH_RCD_PARM))
  770. goto out;
  771. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  772. QETH_DBF_TEXT(TRACE, 6, "clrchpar");
  773. /* we don't have to handle this further */
  774. intparm = 0;
  775. }
  776. if (intparm == QETH_HALT_CHANNEL_PARM) {
  777. QETH_DBF_TEXT(TRACE, 6, "hltchpar");
  778. /* we don't have to handle this further */
  779. intparm = 0;
  780. }
  781. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  782. (dstat & DEV_STAT_UNIT_CHECK) ||
  783. (cstat)) {
  784. if (irb->esw.esw0.erw.cons) {
  785. /* TODO: we should make this s390dbf */
  786. PRINT_WARN("sense data available on channel %s.\n",
  787. CHANNEL_ID(channel));
  788. PRINT_WARN(" cstat 0x%X\n dstat 0x%X\n", cstat, dstat);
  789. print_hex_dump(KERN_WARNING, "qeth: irb ",
  790. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  791. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  792. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  793. }
  794. if (intparm == QETH_RCD_PARM) {
  795. channel->state = CH_STATE_DOWN;
  796. goto out;
  797. }
  798. rc = qeth_get_problem(cdev, irb);
  799. if (rc) {
  800. qeth_schedule_recovery(card);
  801. goto out;
  802. }
  803. }
  804. if (intparm == QETH_RCD_PARM) {
  805. channel->state = CH_STATE_RCD_DONE;
  806. goto out;
  807. }
  808. if (intparm) {
  809. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  810. buffer->state = BUF_STATE_PROCESSED;
  811. }
  812. if (channel == &card->data)
  813. return;
  814. if (channel == &card->read &&
  815. channel->state == CH_STATE_UP)
  816. qeth_issue_next_read(card);
  817. iob = channel->iob;
  818. index = channel->buf_no;
  819. while (iob[index].state == BUF_STATE_PROCESSED) {
  820. if (iob[index].callback != NULL)
  821. iob[index].callback(channel, iob + index);
  822. index = (index + 1) % QETH_CMD_BUFFER_NO;
  823. }
  824. channel->buf_no = index;
  825. out:
  826. wake_up(&card->wait_q);
  827. return;
  828. }
  829. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  830. struct qeth_qdio_out_buffer *buf)
  831. {
  832. int i;
  833. struct sk_buff *skb;
  834. /* is PCI flag set on buffer? */
  835. if (buf->buffer->element[0].flags & 0x40)
  836. atomic_dec(&queue->set_pci_flags_count);
  837. skb = skb_dequeue(&buf->skb_list);
  838. while (skb) {
  839. atomic_dec(&skb->users);
  840. dev_kfree_skb_any(skb);
  841. skb = skb_dequeue(&buf->skb_list);
  842. }
  843. qeth_eddp_buf_release_contexts(buf);
  844. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  845. buf->buffer->element[i].length = 0;
  846. buf->buffer->element[i].addr = NULL;
  847. buf->buffer->element[i].flags = 0;
  848. }
  849. buf->next_element_to_fill = 0;
  850. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  851. }
  852. void qeth_clear_qdio_buffers(struct qeth_card *card)
  853. {
  854. int i, j;
  855. QETH_DBF_TEXT(TRACE, 2, "clearqdbf");
  856. /* clear outbound buffers to free skbs */
  857. for (i = 0; i < card->qdio.no_out_queues; ++i)
  858. if (card->qdio.out_qs[i]) {
  859. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  860. qeth_clear_output_buffer(card->qdio.out_qs[i],
  861. &card->qdio.out_qs[i]->bufs[j]);
  862. }
  863. }
  864. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  865. static void qeth_free_buffer_pool(struct qeth_card *card)
  866. {
  867. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  868. int i = 0;
  869. QETH_DBF_TEXT(TRACE, 5, "freepool");
  870. list_for_each_entry_safe(pool_entry, tmp,
  871. &card->qdio.init_pool.entry_list, init_list){
  872. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  873. free_page((unsigned long)pool_entry->elements[i]);
  874. list_del(&pool_entry->init_list);
  875. kfree(pool_entry);
  876. }
  877. }
  878. static void qeth_free_qdio_buffers(struct qeth_card *card)
  879. {
  880. int i, j;
  881. QETH_DBF_TEXT(TRACE, 2, "freeqdbf");
  882. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  883. QETH_QDIO_UNINITIALIZED)
  884. return;
  885. kfree(card->qdio.in_q);
  886. card->qdio.in_q = NULL;
  887. /* inbound buffer pool */
  888. qeth_free_buffer_pool(card);
  889. /* free outbound qdio_qs */
  890. if (card->qdio.out_qs) {
  891. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  892. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  893. qeth_clear_output_buffer(card->qdio.out_qs[i],
  894. &card->qdio.out_qs[i]->bufs[j]);
  895. kfree(card->qdio.out_qs[i]);
  896. }
  897. kfree(card->qdio.out_qs);
  898. card->qdio.out_qs = NULL;
  899. }
  900. }
  901. static void qeth_clean_channel(struct qeth_channel *channel)
  902. {
  903. int cnt;
  904. QETH_DBF_TEXT(SETUP, 2, "freech");
  905. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  906. kfree(channel->iob[cnt].data);
  907. }
  908. static int qeth_is_1920_device(struct qeth_card *card)
  909. {
  910. int single_queue = 0;
  911. struct ccw_device *ccwdev;
  912. struct channelPath_dsc {
  913. u8 flags;
  914. u8 lsn;
  915. u8 desc;
  916. u8 chpid;
  917. u8 swla;
  918. u8 zeroes;
  919. u8 chla;
  920. u8 chpp;
  921. } *chp_dsc;
  922. QETH_DBF_TEXT(SETUP, 2, "chk_1920");
  923. ccwdev = card->data.ccwdev;
  924. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  925. if (chp_dsc != NULL) {
  926. /* CHPP field bit 6 == 1 -> single queue */
  927. single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
  928. kfree(chp_dsc);
  929. }
  930. QETH_DBF_TEXT_(SETUP, 2, "rc:%x", single_queue);
  931. return single_queue;
  932. }
  933. static void qeth_init_qdio_info(struct qeth_card *card)
  934. {
  935. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  936. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  937. /* inbound */
  938. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  939. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  940. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  941. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  942. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  943. }
  944. static void qeth_set_intial_options(struct qeth_card *card)
  945. {
  946. card->options.route4.type = NO_ROUTER;
  947. card->options.route6.type = NO_ROUTER;
  948. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  949. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  950. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  951. card->options.fake_broadcast = 0;
  952. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  953. card->options.fake_ll = 0;
  954. card->options.performance_stats = 0;
  955. card->options.rx_sg_cb = QETH_RX_SG_CB;
  956. }
  957. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  958. {
  959. unsigned long flags;
  960. int rc = 0;
  961. spin_lock_irqsave(&card->thread_mask_lock, flags);
  962. QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x",
  963. (u8) card->thread_start_mask,
  964. (u8) card->thread_allowed_mask,
  965. (u8) card->thread_running_mask);
  966. rc = (card->thread_start_mask & thread);
  967. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  968. return rc;
  969. }
  970. static void qeth_start_kernel_thread(struct work_struct *work)
  971. {
  972. struct qeth_card *card = container_of(work, struct qeth_card,
  973. kernel_thread_starter);
  974. QETH_DBF_TEXT(TRACE , 2, "strthrd");
  975. if (card->read.state != CH_STATE_UP &&
  976. card->write.state != CH_STATE_UP)
  977. return;
  978. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  979. kthread_run(card->discipline.recover, (void *) card,
  980. "qeth_recover");
  981. }
  982. static int qeth_setup_card(struct qeth_card *card)
  983. {
  984. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  985. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  986. card->read.state = CH_STATE_DOWN;
  987. card->write.state = CH_STATE_DOWN;
  988. card->data.state = CH_STATE_DOWN;
  989. card->state = CARD_STATE_DOWN;
  990. card->lan_online = 0;
  991. card->use_hard_stop = 0;
  992. card->dev = NULL;
  993. spin_lock_init(&card->vlanlock);
  994. spin_lock_init(&card->mclock);
  995. card->vlangrp = NULL;
  996. spin_lock_init(&card->lock);
  997. spin_lock_init(&card->ip_lock);
  998. spin_lock_init(&card->thread_mask_lock);
  999. card->thread_start_mask = 0;
  1000. card->thread_allowed_mask = 0;
  1001. card->thread_running_mask = 0;
  1002. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1003. INIT_LIST_HEAD(&card->ip_list);
  1004. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1005. if (!card->ip_tbd_list) {
  1006. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1007. return -ENOMEM;
  1008. }
  1009. INIT_LIST_HEAD(card->ip_tbd_list);
  1010. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1011. init_waitqueue_head(&card->wait_q);
  1012. /* intial options */
  1013. qeth_set_intial_options(card);
  1014. /* IP address takeover */
  1015. INIT_LIST_HEAD(&card->ipato.entries);
  1016. card->ipato.enabled = 0;
  1017. card->ipato.invert4 = 0;
  1018. card->ipato.invert6 = 0;
  1019. /* init QDIO stuff */
  1020. qeth_init_qdio_info(card);
  1021. return 0;
  1022. }
  1023. static struct qeth_card *qeth_alloc_card(void)
  1024. {
  1025. struct qeth_card *card;
  1026. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1027. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1028. if (!card)
  1029. return NULL;
  1030. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1031. if (qeth_setup_channel(&card->read)) {
  1032. kfree(card);
  1033. return NULL;
  1034. }
  1035. if (qeth_setup_channel(&card->write)) {
  1036. qeth_clean_channel(&card->read);
  1037. kfree(card);
  1038. return NULL;
  1039. }
  1040. card->options.layer2 = -1;
  1041. return card;
  1042. }
  1043. static int qeth_determine_card_type(struct qeth_card *card)
  1044. {
  1045. int i = 0;
  1046. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1047. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1048. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1049. while (known_devices[i][4]) {
  1050. if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
  1051. (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
  1052. card->info.type = known_devices[i][4];
  1053. card->qdio.no_out_queues = known_devices[i][8];
  1054. card->info.is_multicast_different = known_devices[i][9];
  1055. if (qeth_is_1920_device(card)) {
  1056. PRINT_INFO("Priority Queueing not able "
  1057. "due to hardware limitations!\n");
  1058. card->qdio.no_out_queues = 1;
  1059. card->qdio.default_out_queue = 0;
  1060. }
  1061. return 0;
  1062. }
  1063. i++;
  1064. }
  1065. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1066. PRINT_ERR("unknown card type on device %s\n", CARD_BUS_ID(card));
  1067. return -ENOENT;
  1068. }
  1069. static int qeth_clear_channel(struct qeth_channel *channel)
  1070. {
  1071. unsigned long flags;
  1072. struct qeth_card *card;
  1073. int rc;
  1074. QETH_DBF_TEXT(TRACE, 3, "clearch");
  1075. card = CARD_FROM_CDEV(channel->ccwdev);
  1076. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1077. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1078. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1079. if (rc)
  1080. return rc;
  1081. rc = wait_event_interruptible_timeout(card->wait_q,
  1082. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1083. if (rc == -ERESTARTSYS)
  1084. return rc;
  1085. if (channel->state != CH_STATE_STOPPED)
  1086. return -ETIME;
  1087. channel->state = CH_STATE_DOWN;
  1088. return 0;
  1089. }
  1090. static int qeth_halt_channel(struct qeth_channel *channel)
  1091. {
  1092. unsigned long flags;
  1093. struct qeth_card *card;
  1094. int rc;
  1095. QETH_DBF_TEXT(TRACE, 3, "haltch");
  1096. card = CARD_FROM_CDEV(channel->ccwdev);
  1097. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1098. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1099. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1100. if (rc)
  1101. return rc;
  1102. rc = wait_event_interruptible_timeout(card->wait_q,
  1103. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1104. if (rc == -ERESTARTSYS)
  1105. return rc;
  1106. if (channel->state != CH_STATE_HALTED)
  1107. return -ETIME;
  1108. return 0;
  1109. }
  1110. static int qeth_halt_channels(struct qeth_card *card)
  1111. {
  1112. int rc1 = 0, rc2 = 0, rc3 = 0;
  1113. QETH_DBF_TEXT(TRACE, 3, "haltchs");
  1114. rc1 = qeth_halt_channel(&card->read);
  1115. rc2 = qeth_halt_channel(&card->write);
  1116. rc3 = qeth_halt_channel(&card->data);
  1117. if (rc1)
  1118. return rc1;
  1119. if (rc2)
  1120. return rc2;
  1121. return rc3;
  1122. }
  1123. static int qeth_clear_channels(struct qeth_card *card)
  1124. {
  1125. int rc1 = 0, rc2 = 0, rc3 = 0;
  1126. QETH_DBF_TEXT(TRACE, 3, "clearchs");
  1127. rc1 = qeth_clear_channel(&card->read);
  1128. rc2 = qeth_clear_channel(&card->write);
  1129. rc3 = qeth_clear_channel(&card->data);
  1130. if (rc1)
  1131. return rc1;
  1132. if (rc2)
  1133. return rc2;
  1134. return rc3;
  1135. }
  1136. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1137. {
  1138. int rc = 0;
  1139. QETH_DBF_TEXT(TRACE, 3, "clhacrd");
  1140. QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *));
  1141. if (halt)
  1142. rc = qeth_halt_channels(card);
  1143. if (rc)
  1144. return rc;
  1145. return qeth_clear_channels(card);
  1146. }
  1147. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1148. {
  1149. int rc = 0;
  1150. QETH_DBF_TEXT(TRACE, 3, "qdioclr");
  1151. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1152. QETH_QDIO_CLEANING)) {
  1153. case QETH_QDIO_ESTABLISHED:
  1154. if (card->info.type == QETH_CARD_TYPE_IQD)
  1155. rc = qdio_cleanup(CARD_DDEV(card),
  1156. QDIO_FLAG_CLEANUP_USING_HALT);
  1157. else
  1158. rc = qdio_cleanup(CARD_DDEV(card),
  1159. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1160. if (rc)
  1161. QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc);
  1162. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1163. break;
  1164. case QETH_QDIO_CLEANING:
  1165. return rc;
  1166. default:
  1167. break;
  1168. }
  1169. rc = qeth_clear_halt_card(card, use_halt);
  1170. if (rc)
  1171. QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc);
  1172. card->state = CARD_STATE_DOWN;
  1173. return rc;
  1174. }
  1175. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1176. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1177. int *length)
  1178. {
  1179. struct ciw *ciw;
  1180. char *rcd_buf;
  1181. int ret;
  1182. struct qeth_channel *channel = &card->data;
  1183. unsigned long flags;
  1184. /*
  1185. * scan for RCD command in extended SenseID data
  1186. */
  1187. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1188. if (!ciw || ciw->cmd == 0)
  1189. return -EOPNOTSUPP;
  1190. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1191. if (!rcd_buf)
  1192. return -ENOMEM;
  1193. channel->ccw.cmd_code = ciw->cmd;
  1194. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1195. channel->ccw.count = ciw->count;
  1196. channel->ccw.flags = CCW_FLAG_SLI;
  1197. channel->state = CH_STATE_RCD;
  1198. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1199. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1200. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1201. QETH_RCD_TIMEOUT);
  1202. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1203. if (!ret)
  1204. wait_event(card->wait_q,
  1205. (channel->state == CH_STATE_RCD_DONE ||
  1206. channel->state == CH_STATE_DOWN));
  1207. if (channel->state == CH_STATE_DOWN)
  1208. ret = -EIO;
  1209. else
  1210. channel->state = CH_STATE_DOWN;
  1211. if (ret) {
  1212. kfree(rcd_buf);
  1213. *buffer = NULL;
  1214. *length = 0;
  1215. } else {
  1216. *length = ciw->count;
  1217. *buffer = rcd_buf;
  1218. }
  1219. return ret;
  1220. }
  1221. static int qeth_get_unitaddr(struct qeth_card *card)
  1222. {
  1223. int length;
  1224. char *prcd;
  1225. int rc;
  1226. QETH_DBF_TEXT(SETUP, 2, "getunit");
  1227. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  1228. if (rc) {
  1229. PRINT_ERR("qeth_read_conf_data for device %s returned %i\n",
  1230. CARD_DDEV_ID(card), rc);
  1231. return rc;
  1232. }
  1233. card->info.chpid = prcd[30];
  1234. card->info.unit_addr2 = prcd[31];
  1235. card->info.cula = prcd[63];
  1236. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1237. (prcd[0x11] == _ascebc['M']));
  1238. kfree(prcd);
  1239. return 0;
  1240. }
  1241. static void qeth_init_tokens(struct qeth_card *card)
  1242. {
  1243. card->token.issuer_rm_w = 0x00010103UL;
  1244. card->token.cm_filter_w = 0x00010108UL;
  1245. card->token.cm_connection_w = 0x0001010aUL;
  1246. card->token.ulp_filter_w = 0x0001010bUL;
  1247. card->token.ulp_connection_w = 0x0001010dUL;
  1248. }
  1249. static void qeth_init_func_level(struct qeth_card *card)
  1250. {
  1251. if (card->ipato.enabled) {
  1252. if (card->info.type == QETH_CARD_TYPE_IQD)
  1253. card->info.func_level =
  1254. QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
  1255. else
  1256. card->info.func_level =
  1257. QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
  1258. } else {
  1259. if (card->info.type == QETH_CARD_TYPE_IQD)
  1260. /*FIXME:why do we have same values for dis and ena for
  1261. osae??? */
  1262. card->info.func_level =
  1263. QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
  1264. else
  1265. card->info.func_level =
  1266. QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
  1267. }
  1268. }
  1269. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1270. void (*idx_reply_cb)(struct qeth_channel *,
  1271. struct qeth_cmd_buffer *))
  1272. {
  1273. struct qeth_cmd_buffer *iob;
  1274. unsigned long flags;
  1275. int rc;
  1276. struct qeth_card *card;
  1277. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1278. card = CARD_FROM_CDEV(channel->ccwdev);
  1279. iob = qeth_get_buffer(channel);
  1280. iob->callback = idx_reply_cb;
  1281. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1282. channel->ccw.count = QETH_BUFSIZE;
  1283. channel->ccw.cda = (__u32) __pa(iob->data);
  1284. wait_event(card->wait_q,
  1285. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1286. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1287. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1288. rc = ccw_device_start(channel->ccwdev,
  1289. &channel->ccw, (addr_t) iob, 0, 0);
  1290. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1291. if (rc) {
  1292. PRINT_ERR("Error2 in activating channel rc=%d\n", rc);
  1293. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1294. atomic_set(&channel->irq_pending, 0);
  1295. wake_up(&card->wait_q);
  1296. return rc;
  1297. }
  1298. rc = wait_event_interruptible_timeout(card->wait_q,
  1299. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1300. if (rc == -ERESTARTSYS)
  1301. return rc;
  1302. if (channel->state != CH_STATE_UP) {
  1303. rc = -ETIME;
  1304. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1305. qeth_clear_cmd_buffers(channel);
  1306. } else
  1307. rc = 0;
  1308. return rc;
  1309. }
  1310. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1311. void (*idx_reply_cb)(struct qeth_channel *,
  1312. struct qeth_cmd_buffer *))
  1313. {
  1314. struct qeth_card *card;
  1315. struct qeth_cmd_buffer *iob;
  1316. unsigned long flags;
  1317. __u16 temp;
  1318. __u8 tmp;
  1319. int rc;
  1320. struct ccw_dev_id temp_devid;
  1321. card = CARD_FROM_CDEV(channel->ccwdev);
  1322. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1323. iob = qeth_get_buffer(channel);
  1324. iob->callback = idx_reply_cb;
  1325. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1326. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1327. channel->ccw.cda = (__u32) __pa(iob->data);
  1328. if (channel == &card->write) {
  1329. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1330. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1331. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1332. card->seqno.trans_hdr++;
  1333. } else {
  1334. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1335. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1336. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1337. }
  1338. tmp = ((__u8)card->info.portno) | 0x80;
  1339. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1340. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1341. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1342. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1343. &card->info.func_level, sizeof(__u16));
  1344. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1345. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1346. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1347. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1348. wait_event(card->wait_q,
  1349. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1350. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1351. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1352. rc = ccw_device_start(channel->ccwdev,
  1353. &channel->ccw, (addr_t) iob, 0, 0);
  1354. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1355. if (rc) {
  1356. PRINT_ERR("Error1 in activating channel. rc=%d\n", rc);
  1357. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1358. atomic_set(&channel->irq_pending, 0);
  1359. wake_up(&card->wait_q);
  1360. return rc;
  1361. }
  1362. rc = wait_event_interruptible_timeout(card->wait_q,
  1363. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1364. if (rc == -ERESTARTSYS)
  1365. return rc;
  1366. if (channel->state != CH_STATE_ACTIVATING) {
  1367. PRINT_WARN("IDX activate timed out!\n");
  1368. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1369. qeth_clear_cmd_buffers(channel);
  1370. return -ETIME;
  1371. }
  1372. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1373. }
  1374. static int qeth_peer_func_level(int level)
  1375. {
  1376. if ((level & 0xff) == 8)
  1377. return (level & 0xff) + 0x400;
  1378. if (((level >> 8) & 3) == 1)
  1379. return (level & 0xff) + 0x200;
  1380. return level;
  1381. }
  1382. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1383. struct qeth_cmd_buffer *iob)
  1384. {
  1385. struct qeth_card *card;
  1386. __u16 temp;
  1387. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1388. if (channel->state == CH_STATE_DOWN) {
  1389. channel->state = CH_STATE_ACTIVATING;
  1390. goto out;
  1391. }
  1392. card = CARD_FROM_CDEV(channel->ccwdev);
  1393. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1394. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1395. PRINT_ERR("IDX_ACTIVATE on write channel device %s: "
  1396. "adapter exclusively used by another host\n",
  1397. CARD_WDEV_ID(card));
  1398. else
  1399. PRINT_ERR("IDX_ACTIVATE on write channel device %s: "
  1400. "negative reply\n", CARD_WDEV_ID(card));
  1401. goto out;
  1402. }
  1403. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1404. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1405. PRINT_WARN("IDX_ACTIVATE on write channel device %s: "
  1406. "function level mismatch "
  1407. "(sent: 0x%x, received: 0x%x)\n",
  1408. CARD_WDEV_ID(card), card->info.func_level, temp);
  1409. goto out;
  1410. }
  1411. channel->state = CH_STATE_UP;
  1412. out:
  1413. qeth_release_buffer(channel, iob);
  1414. }
  1415. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1416. struct qeth_cmd_buffer *iob)
  1417. {
  1418. struct qeth_card *card;
  1419. __u16 temp;
  1420. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1421. if (channel->state == CH_STATE_DOWN) {
  1422. channel->state = CH_STATE_ACTIVATING;
  1423. goto out;
  1424. }
  1425. card = CARD_FROM_CDEV(channel->ccwdev);
  1426. if (qeth_check_idx_response(iob->data))
  1427. goto out;
  1428. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1429. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1430. PRINT_ERR("IDX_ACTIVATE on read channel device %s: "
  1431. "adapter exclusively used by another host\n",
  1432. CARD_RDEV_ID(card));
  1433. else
  1434. PRINT_ERR("IDX_ACTIVATE on read channel device %s: "
  1435. "negative reply\n", CARD_RDEV_ID(card));
  1436. goto out;
  1437. }
  1438. /**
  1439. * temporary fix for microcode bug
  1440. * to revert it,replace OR by AND
  1441. */
  1442. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1443. (card->info.type == QETH_CARD_TYPE_OSAE))
  1444. card->info.portname_required = 1;
  1445. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1446. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1447. PRINT_WARN("IDX_ACTIVATE on read channel device %s: function "
  1448. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1449. CARD_RDEV_ID(card), card->info.func_level, temp);
  1450. goto out;
  1451. }
  1452. memcpy(&card->token.issuer_rm_r,
  1453. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1454. QETH_MPC_TOKEN_LENGTH);
  1455. memcpy(&card->info.mcl_level[0],
  1456. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1457. channel->state = CH_STATE_UP;
  1458. out:
  1459. qeth_release_buffer(channel, iob);
  1460. }
  1461. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1462. struct qeth_cmd_buffer *iob)
  1463. {
  1464. qeth_setup_ccw(&card->write, iob->data, len);
  1465. iob->callback = qeth_release_buffer;
  1466. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1467. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1468. card->seqno.trans_hdr++;
  1469. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1470. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1471. card->seqno.pdu_hdr++;
  1472. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1473. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1474. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1475. }
  1476. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1477. int qeth_send_control_data(struct qeth_card *card, int len,
  1478. struct qeth_cmd_buffer *iob,
  1479. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1480. unsigned long),
  1481. void *reply_param)
  1482. {
  1483. int rc;
  1484. unsigned long flags;
  1485. struct qeth_reply *reply = NULL;
  1486. unsigned long timeout;
  1487. QETH_DBF_TEXT(TRACE, 2, "sendctl");
  1488. reply = qeth_alloc_reply(card);
  1489. if (!reply) {
  1490. PRINT_WARN("Could not alloc qeth_reply!\n");
  1491. return -ENOMEM;
  1492. }
  1493. reply->callback = reply_cb;
  1494. reply->param = reply_param;
  1495. if (card->state == CARD_STATE_DOWN)
  1496. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1497. else
  1498. reply->seqno = card->seqno.ipa++;
  1499. init_waitqueue_head(&reply->wait_q);
  1500. spin_lock_irqsave(&card->lock, flags);
  1501. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1502. spin_unlock_irqrestore(&card->lock, flags);
  1503. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1504. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1505. qeth_prepare_control_data(card, len, iob);
  1506. if (IS_IPA(iob->data))
  1507. timeout = jiffies + QETH_IPA_TIMEOUT;
  1508. else
  1509. timeout = jiffies + QETH_TIMEOUT;
  1510. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  1511. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1512. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1513. (addr_t) iob, 0, 0);
  1514. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1515. if (rc) {
  1516. PRINT_WARN("qeth_send_control_data: "
  1517. "ccw_device_start rc = %i\n", rc);
  1518. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  1519. spin_lock_irqsave(&card->lock, flags);
  1520. list_del_init(&reply->list);
  1521. qeth_put_reply(reply);
  1522. spin_unlock_irqrestore(&card->lock, flags);
  1523. qeth_release_buffer(iob->channel, iob);
  1524. atomic_set(&card->write.irq_pending, 0);
  1525. wake_up(&card->wait_q);
  1526. return rc;
  1527. }
  1528. while (!atomic_read(&reply->received)) {
  1529. if (time_after(jiffies, timeout)) {
  1530. spin_lock_irqsave(&reply->card->lock, flags);
  1531. list_del_init(&reply->list);
  1532. spin_unlock_irqrestore(&reply->card->lock, flags);
  1533. reply->rc = -ETIME;
  1534. atomic_inc(&reply->received);
  1535. wake_up(&reply->wait_q);
  1536. }
  1537. cpu_relax();
  1538. };
  1539. rc = reply->rc;
  1540. qeth_put_reply(reply);
  1541. return rc;
  1542. }
  1543. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1544. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1545. unsigned long data)
  1546. {
  1547. struct qeth_cmd_buffer *iob;
  1548. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1549. iob = (struct qeth_cmd_buffer *) data;
  1550. memcpy(&card->token.cm_filter_r,
  1551. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1552. QETH_MPC_TOKEN_LENGTH);
  1553. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1554. return 0;
  1555. }
  1556. static int qeth_cm_enable(struct qeth_card *card)
  1557. {
  1558. int rc;
  1559. struct qeth_cmd_buffer *iob;
  1560. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1561. iob = qeth_wait_for_buffer(&card->write);
  1562. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1563. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1564. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1565. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1566. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1567. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1568. qeth_cm_enable_cb, NULL);
  1569. return rc;
  1570. }
  1571. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1572. unsigned long data)
  1573. {
  1574. struct qeth_cmd_buffer *iob;
  1575. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1576. iob = (struct qeth_cmd_buffer *) data;
  1577. memcpy(&card->token.cm_connection_r,
  1578. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1579. QETH_MPC_TOKEN_LENGTH);
  1580. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1581. return 0;
  1582. }
  1583. static int qeth_cm_setup(struct qeth_card *card)
  1584. {
  1585. int rc;
  1586. struct qeth_cmd_buffer *iob;
  1587. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1588. iob = qeth_wait_for_buffer(&card->write);
  1589. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1590. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1591. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1592. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1593. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1594. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1595. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1596. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1597. qeth_cm_setup_cb, NULL);
  1598. return rc;
  1599. }
  1600. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1601. {
  1602. switch (card->info.type) {
  1603. case QETH_CARD_TYPE_UNKNOWN:
  1604. return 1500;
  1605. case QETH_CARD_TYPE_IQD:
  1606. return card->info.max_mtu;
  1607. case QETH_CARD_TYPE_OSAE:
  1608. switch (card->info.link_type) {
  1609. case QETH_LINK_TYPE_HSTR:
  1610. case QETH_LINK_TYPE_LANE_TR:
  1611. return 2000;
  1612. default:
  1613. return 1492;
  1614. }
  1615. default:
  1616. return 1500;
  1617. }
  1618. }
  1619. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1620. {
  1621. switch (cardtype) {
  1622. case QETH_CARD_TYPE_UNKNOWN:
  1623. case QETH_CARD_TYPE_OSAE:
  1624. case QETH_CARD_TYPE_OSN:
  1625. return 61440;
  1626. case QETH_CARD_TYPE_IQD:
  1627. return 57344;
  1628. default:
  1629. return 1500;
  1630. }
  1631. }
  1632. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1633. {
  1634. switch (cardtype) {
  1635. case QETH_CARD_TYPE_IQD:
  1636. return 1;
  1637. default:
  1638. return 0;
  1639. }
  1640. }
  1641. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1642. {
  1643. switch (framesize) {
  1644. case 0x4000:
  1645. return 8192;
  1646. case 0x6000:
  1647. return 16384;
  1648. case 0xa000:
  1649. return 32768;
  1650. case 0xffff:
  1651. return 57344;
  1652. default:
  1653. return 0;
  1654. }
  1655. }
  1656. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1657. {
  1658. switch (card->info.type) {
  1659. case QETH_CARD_TYPE_OSAE:
  1660. return ((mtu >= 576) && (mtu <= 61440));
  1661. case QETH_CARD_TYPE_IQD:
  1662. return ((mtu >= 576) &&
  1663. (mtu <= card->info.max_mtu + 4096 - 32));
  1664. case QETH_CARD_TYPE_OSN:
  1665. case QETH_CARD_TYPE_UNKNOWN:
  1666. default:
  1667. return 1;
  1668. }
  1669. }
  1670. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1671. unsigned long data)
  1672. {
  1673. __u16 mtu, framesize;
  1674. __u16 len;
  1675. __u8 link_type;
  1676. struct qeth_cmd_buffer *iob;
  1677. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1678. iob = (struct qeth_cmd_buffer *) data;
  1679. memcpy(&card->token.ulp_filter_r,
  1680. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1681. QETH_MPC_TOKEN_LENGTH);
  1682. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1683. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1684. mtu = qeth_get_mtu_outof_framesize(framesize);
  1685. if (!mtu) {
  1686. iob->rc = -EINVAL;
  1687. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1688. return 0;
  1689. }
  1690. card->info.max_mtu = mtu;
  1691. card->info.initial_mtu = mtu;
  1692. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1693. } else {
  1694. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1695. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1696. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1697. }
  1698. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1699. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1700. memcpy(&link_type,
  1701. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1702. card->info.link_type = link_type;
  1703. } else
  1704. card->info.link_type = 0;
  1705. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1706. return 0;
  1707. }
  1708. static int qeth_ulp_enable(struct qeth_card *card)
  1709. {
  1710. int rc;
  1711. char prot_type;
  1712. struct qeth_cmd_buffer *iob;
  1713. /*FIXME: trace view callbacks*/
  1714. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1715. iob = qeth_wait_for_buffer(&card->write);
  1716. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1717. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1718. (__u8) card->info.portno;
  1719. if (card->options.layer2)
  1720. if (card->info.type == QETH_CARD_TYPE_OSN)
  1721. prot_type = QETH_PROT_OSN2;
  1722. else
  1723. prot_type = QETH_PROT_LAYER2;
  1724. else
  1725. prot_type = QETH_PROT_TCPIP;
  1726. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1727. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1728. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1729. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1730. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1731. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1732. card->info.portname, 9);
  1733. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1734. qeth_ulp_enable_cb, NULL);
  1735. return rc;
  1736. }
  1737. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1738. unsigned long data)
  1739. {
  1740. struct qeth_cmd_buffer *iob;
  1741. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1742. iob = (struct qeth_cmd_buffer *) data;
  1743. memcpy(&card->token.ulp_connection_r,
  1744. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1745. QETH_MPC_TOKEN_LENGTH);
  1746. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1747. return 0;
  1748. }
  1749. static int qeth_ulp_setup(struct qeth_card *card)
  1750. {
  1751. int rc;
  1752. __u16 temp;
  1753. struct qeth_cmd_buffer *iob;
  1754. struct ccw_dev_id dev_id;
  1755. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1756. iob = qeth_wait_for_buffer(&card->write);
  1757. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1758. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1759. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1760. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1761. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1762. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1763. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1764. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1765. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1766. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1767. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1768. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1769. qeth_ulp_setup_cb, NULL);
  1770. return rc;
  1771. }
  1772. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1773. {
  1774. int i, j;
  1775. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1776. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1777. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1778. return 0;
  1779. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1780. GFP_KERNEL);
  1781. if (!card->qdio.in_q)
  1782. goto out_nomem;
  1783. QETH_DBF_TEXT(SETUP, 2, "inq");
  1784. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1785. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1786. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1787. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1788. card->qdio.in_q->bufs[i].buffer =
  1789. &card->qdio.in_q->qdio_bufs[i];
  1790. /* inbound buffer pool */
  1791. if (qeth_alloc_buffer_pool(card))
  1792. goto out_freeinq;
  1793. /* outbound */
  1794. card->qdio.out_qs =
  1795. kmalloc(card->qdio.no_out_queues *
  1796. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1797. if (!card->qdio.out_qs)
  1798. goto out_freepool;
  1799. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1800. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1801. GFP_KERNEL);
  1802. if (!card->qdio.out_qs[i])
  1803. goto out_freeoutq;
  1804. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1805. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1806. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1807. card->qdio.out_qs[i]->queue_no = i;
  1808. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1809. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1810. card->qdio.out_qs[i]->bufs[j].buffer =
  1811. &card->qdio.out_qs[i]->qdio_bufs[j];
  1812. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1813. skb_list);
  1814. lockdep_set_class(
  1815. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1816. &qdio_out_skb_queue_key);
  1817. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1818. }
  1819. }
  1820. return 0;
  1821. out_freeoutq:
  1822. while (i > 0)
  1823. kfree(card->qdio.out_qs[--i]);
  1824. kfree(card->qdio.out_qs);
  1825. card->qdio.out_qs = NULL;
  1826. out_freepool:
  1827. qeth_free_buffer_pool(card);
  1828. out_freeinq:
  1829. kfree(card->qdio.in_q);
  1830. card->qdio.in_q = NULL;
  1831. out_nomem:
  1832. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1833. return -ENOMEM;
  1834. }
  1835. static void qeth_create_qib_param_field(struct qeth_card *card,
  1836. char *param_field)
  1837. {
  1838. param_field[0] = _ascebc['P'];
  1839. param_field[1] = _ascebc['C'];
  1840. param_field[2] = _ascebc['I'];
  1841. param_field[3] = _ascebc['T'];
  1842. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1843. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1844. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1845. }
  1846. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1847. char *param_field)
  1848. {
  1849. param_field[16] = _ascebc['B'];
  1850. param_field[17] = _ascebc['L'];
  1851. param_field[18] = _ascebc['K'];
  1852. param_field[19] = _ascebc['T'];
  1853. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1854. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1855. *((unsigned int *) (&param_field[28])) =
  1856. card->info.blkt.inter_packet_jumbo;
  1857. }
  1858. static int qeth_qdio_activate(struct qeth_card *card)
  1859. {
  1860. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1861. return qdio_activate(CARD_DDEV(card), 0);
  1862. }
  1863. static int qeth_dm_act(struct qeth_card *card)
  1864. {
  1865. int rc;
  1866. struct qeth_cmd_buffer *iob;
  1867. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1868. iob = qeth_wait_for_buffer(&card->write);
  1869. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1870. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1871. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1872. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1873. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1874. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1875. return rc;
  1876. }
  1877. static int qeth_mpc_initialize(struct qeth_card *card)
  1878. {
  1879. int rc;
  1880. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1881. rc = qeth_issue_next_read(card);
  1882. if (rc) {
  1883. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1884. return rc;
  1885. }
  1886. rc = qeth_cm_enable(card);
  1887. if (rc) {
  1888. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1889. goto out_qdio;
  1890. }
  1891. rc = qeth_cm_setup(card);
  1892. if (rc) {
  1893. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1894. goto out_qdio;
  1895. }
  1896. rc = qeth_ulp_enable(card);
  1897. if (rc) {
  1898. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1899. goto out_qdio;
  1900. }
  1901. rc = qeth_ulp_setup(card);
  1902. if (rc) {
  1903. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1904. goto out_qdio;
  1905. }
  1906. rc = qeth_alloc_qdio_buffers(card);
  1907. if (rc) {
  1908. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1909. goto out_qdio;
  1910. }
  1911. rc = qeth_qdio_establish(card);
  1912. if (rc) {
  1913. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1914. qeth_free_qdio_buffers(card);
  1915. goto out_qdio;
  1916. }
  1917. rc = qeth_qdio_activate(card);
  1918. if (rc) {
  1919. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1920. goto out_qdio;
  1921. }
  1922. rc = qeth_dm_act(card);
  1923. if (rc) {
  1924. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1925. goto out_qdio;
  1926. }
  1927. return 0;
  1928. out_qdio:
  1929. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1930. return rc;
  1931. }
  1932. static void qeth_print_status_with_portname(struct qeth_card *card)
  1933. {
  1934. char dbf_text[15];
  1935. int i;
  1936. sprintf(dbf_text, "%s", card->info.portname + 1);
  1937. for (i = 0; i < 8; i++)
  1938. dbf_text[i] =
  1939. (char) _ebcasc[(__u8) dbf_text[i]];
  1940. dbf_text[8] = 0;
  1941. PRINT_INFO("Device %s/%s/%s is a%s card%s%s%s\n"
  1942. "with link type %s (portname: %s)\n",
  1943. CARD_RDEV_ID(card),
  1944. CARD_WDEV_ID(card),
  1945. CARD_DDEV_ID(card),
  1946. qeth_get_cardname(card),
  1947. (card->info.mcl_level[0]) ? " (level: " : "",
  1948. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1949. (card->info.mcl_level[0]) ? ")" : "",
  1950. qeth_get_cardname_short(card),
  1951. dbf_text);
  1952. }
  1953. static void qeth_print_status_no_portname(struct qeth_card *card)
  1954. {
  1955. if (card->info.portname[0])
  1956. PRINT_INFO("Device %s/%s/%s is a%s "
  1957. "card%s%s%s\nwith link type %s "
  1958. "(no portname needed by interface).\n",
  1959. CARD_RDEV_ID(card),
  1960. CARD_WDEV_ID(card),
  1961. CARD_DDEV_ID(card),
  1962. qeth_get_cardname(card),
  1963. (card->info.mcl_level[0]) ? " (level: " : "",
  1964. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1965. (card->info.mcl_level[0]) ? ")" : "",
  1966. qeth_get_cardname_short(card));
  1967. else
  1968. PRINT_INFO("Device %s/%s/%s is a%s "
  1969. "card%s%s%s\nwith link type %s.\n",
  1970. CARD_RDEV_ID(card),
  1971. CARD_WDEV_ID(card),
  1972. CARD_DDEV_ID(card),
  1973. qeth_get_cardname(card),
  1974. (card->info.mcl_level[0]) ? " (level: " : "",
  1975. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1976. (card->info.mcl_level[0]) ? ")" : "",
  1977. qeth_get_cardname_short(card));
  1978. }
  1979. void qeth_print_status_message(struct qeth_card *card)
  1980. {
  1981. switch (card->info.type) {
  1982. case QETH_CARD_TYPE_OSAE:
  1983. /* VM will use a non-zero first character
  1984. * to indicate a HiperSockets like reporting
  1985. * of the level OSA sets the first character to zero
  1986. * */
  1987. if (!card->info.mcl_level[0]) {
  1988. sprintf(card->info.mcl_level, "%02x%02x",
  1989. card->info.mcl_level[2],
  1990. card->info.mcl_level[3]);
  1991. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  1992. break;
  1993. }
  1994. /* fallthrough */
  1995. case QETH_CARD_TYPE_IQD:
  1996. if (card->info.guestlan) {
  1997. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  1998. card->info.mcl_level[0]];
  1999. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2000. card->info.mcl_level[1]];
  2001. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2002. card->info.mcl_level[2]];
  2003. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2004. card->info.mcl_level[3]];
  2005. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2006. }
  2007. break;
  2008. default:
  2009. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2010. }
  2011. if (card->info.portname_required)
  2012. qeth_print_status_with_portname(card);
  2013. else
  2014. qeth_print_status_no_portname(card);
  2015. }
  2016. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2017. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2018. {
  2019. struct qeth_buffer_pool_entry *entry;
  2020. QETH_DBF_TEXT(TRACE, 5, "inwrklst");
  2021. list_for_each_entry(entry,
  2022. &card->qdio.init_pool.entry_list, init_list) {
  2023. qeth_put_buffer_pool_entry(card, entry);
  2024. }
  2025. }
  2026. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2027. struct qeth_card *card)
  2028. {
  2029. struct list_head *plh;
  2030. struct qeth_buffer_pool_entry *entry;
  2031. int i, free;
  2032. struct page *page;
  2033. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2034. return NULL;
  2035. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2036. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2037. free = 1;
  2038. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2039. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2040. free = 0;
  2041. break;
  2042. }
  2043. }
  2044. if (free) {
  2045. list_del_init(&entry->list);
  2046. return entry;
  2047. }
  2048. }
  2049. /* no free buffer in pool so take first one and swap pages */
  2050. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2051. struct qeth_buffer_pool_entry, list);
  2052. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2053. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2054. page = alloc_page(GFP_ATOMIC);
  2055. if (!page) {
  2056. return NULL;
  2057. } else {
  2058. free_page((unsigned long)entry->elements[i]);
  2059. entry->elements[i] = page_address(page);
  2060. if (card->options.performance_stats)
  2061. card->perf_stats.sg_alloc_page_rx++;
  2062. }
  2063. }
  2064. }
  2065. list_del_init(&entry->list);
  2066. return entry;
  2067. }
  2068. static int qeth_init_input_buffer(struct qeth_card *card,
  2069. struct qeth_qdio_buffer *buf)
  2070. {
  2071. struct qeth_buffer_pool_entry *pool_entry;
  2072. int i;
  2073. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2074. if (!pool_entry)
  2075. return 1;
  2076. /*
  2077. * since the buffer is accessed only from the input_tasklet
  2078. * there shouldn't be a need to synchronize; also, since we use
  2079. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2080. * buffers
  2081. */
  2082. BUG_ON(!pool_entry);
  2083. buf->pool_entry = pool_entry;
  2084. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2085. buf->buffer->element[i].length = PAGE_SIZE;
  2086. buf->buffer->element[i].addr = pool_entry->elements[i];
  2087. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2088. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2089. else
  2090. buf->buffer->element[i].flags = 0;
  2091. }
  2092. return 0;
  2093. }
  2094. int qeth_init_qdio_queues(struct qeth_card *card)
  2095. {
  2096. int i, j;
  2097. int rc;
  2098. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2099. /* inbound queue */
  2100. memset(card->qdio.in_q->qdio_bufs, 0,
  2101. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2102. qeth_initialize_working_pool_list(card);
  2103. /*give only as many buffers to hardware as we have buffer pool entries*/
  2104. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2105. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2106. card->qdio.in_q->next_buf_to_init =
  2107. card->qdio.in_buf_pool.buf_count - 1;
  2108. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2109. card->qdio.in_buf_pool.buf_count - 1, NULL);
  2110. if (rc) {
  2111. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2112. return rc;
  2113. }
  2114. rc = qdio_synchronize(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0);
  2115. if (rc) {
  2116. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  2117. return rc;
  2118. }
  2119. /* outbound queue */
  2120. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2121. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2122. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2123. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2124. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2125. &card->qdio.out_qs[i]->bufs[j]);
  2126. }
  2127. card->qdio.out_qs[i]->card = card;
  2128. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2129. card->qdio.out_qs[i]->do_pack = 0;
  2130. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2131. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2132. atomic_set(&card->qdio.out_qs[i]->state,
  2133. QETH_OUT_Q_UNLOCKED);
  2134. }
  2135. return 0;
  2136. }
  2137. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2138. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2139. {
  2140. switch (link_type) {
  2141. case QETH_LINK_TYPE_HSTR:
  2142. return 2;
  2143. default:
  2144. return 1;
  2145. }
  2146. }
  2147. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2148. struct qeth_ipa_cmd *cmd, __u8 command,
  2149. enum qeth_prot_versions prot)
  2150. {
  2151. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2152. cmd->hdr.command = command;
  2153. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2154. cmd->hdr.seqno = card->seqno.ipa;
  2155. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2156. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2157. if (card->options.layer2)
  2158. cmd->hdr.prim_version_no = 2;
  2159. else
  2160. cmd->hdr.prim_version_no = 1;
  2161. cmd->hdr.param_count = 1;
  2162. cmd->hdr.prot_version = prot;
  2163. cmd->hdr.ipa_supported = 0;
  2164. cmd->hdr.ipa_enabled = 0;
  2165. }
  2166. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2167. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2168. {
  2169. struct qeth_cmd_buffer *iob;
  2170. struct qeth_ipa_cmd *cmd;
  2171. iob = qeth_wait_for_buffer(&card->write);
  2172. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2173. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2174. return iob;
  2175. }
  2176. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2177. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2178. char prot_type)
  2179. {
  2180. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2181. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2182. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2183. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2184. }
  2185. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2186. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2187. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2188. unsigned long),
  2189. void *reply_param)
  2190. {
  2191. int rc;
  2192. char prot_type;
  2193. QETH_DBF_TEXT(TRACE, 4, "sendipa");
  2194. if (card->options.layer2)
  2195. if (card->info.type == QETH_CARD_TYPE_OSN)
  2196. prot_type = QETH_PROT_OSN2;
  2197. else
  2198. prot_type = QETH_PROT_LAYER2;
  2199. else
  2200. prot_type = QETH_PROT_TCPIP;
  2201. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2202. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2203. iob, reply_cb, reply_param);
  2204. return rc;
  2205. }
  2206. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2207. static int qeth_send_startstoplan(struct qeth_card *card,
  2208. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2209. {
  2210. int rc;
  2211. struct qeth_cmd_buffer *iob;
  2212. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2213. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2214. return rc;
  2215. }
  2216. int qeth_send_startlan(struct qeth_card *card)
  2217. {
  2218. int rc;
  2219. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2220. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2221. return rc;
  2222. }
  2223. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2224. int qeth_send_stoplan(struct qeth_card *card)
  2225. {
  2226. int rc = 0;
  2227. /*
  2228. * TODO: according to the IPA format document page 14,
  2229. * TCP/IP (we!) never issue a STOPLAN
  2230. * is this right ?!?
  2231. */
  2232. QETH_DBF_TEXT(SETUP, 2, "stoplan");
  2233. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2234. return rc;
  2235. }
  2236. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2237. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2238. struct qeth_reply *reply, unsigned long data)
  2239. {
  2240. struct qeth_ipa_cmd *cmd;
  2241. QETH_DBF_TEXT(TRACE, 4, "defadpcb");
  2242. cmd = (struct qeth_ipa_cmd *) data;
  2243. if (cmd->hdr.return_code == 0)
  2244. cmd->hdr.return_code =
  2245. cmd->data.setadapterparms.hdr.return_code;
  2246. return 0;
  2247. }
  2248. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2249. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2250. struct qeth_reply *reply, unsigned long data)
  2251. {
  2252. struct qeth_ipa_cmd *cmd;
  2253. QETH_DBF_TEXT(TRACE, 3, "quyadpcb");
  2254. cmd = (struct qeth_ipa_cmd *) data;
  2255. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
  2256. card->info.link_type =
  2257. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2258. card->options.adp.supported_funcs =
  2259. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2260. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2261. }
  2262. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2263. __u32 command, __u32 cmdlen)
  2264. {
  2265. struct qeth_cmd_buffer *iob;
  2266. struct qeth_ipa_cmd *cmd;
  2267. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2268. QETH_PROT_IPV4);
  2269. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2270. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2271. cmd->data.setadapterparms.hdr.command_code = command;
  2272. cmd->data.setadapterparms.hdr.used_total = 1;
  2273. cmd->data.setadapterparms.hdr.seq_no = 1;
  2274. return iob;
  2275. }
  2276. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2277. int qeth_query_setadapterparms(struct qeth_card *card)
  2278. {
  2279. int rc;
  2280. struct qeth_cmd_buffer *iob;
  2281. QETH_DBF_TEXT(TRACE, 3, "queryadp");
  2282. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2283. sizeof(struct qeth_ipacmd_setadpparms));
  2284. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2285. return rc;
  2286. }
  2287. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2288. int qeth_check_qdio_errors(struct qdio_buffer *buf, unsigned int qdio_error,
  2289. unsigned int siga_error, const char *dbftext)
  2290. {
  2291. if (qdio_error || siga_error) {
  2292. QETH_DBF_TEXT(TRACE, 2, dbftext);
  2293. QETH_DBF_TEXT(QERR, 2, dbftext);
  2294. QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
  2295. buf->element[15].flags & 0xff);
  2296. QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
  2297. buf->element[14].flags & 0xff);
  2298. QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
  2299. QETH_DBF_TEXT_(QERR, 2, " serr=%X", siga_error);
  2300. return 1;
  2301. }
  2302. return 0;
  2303. }
  2304. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2305. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2306. {
  2307. struct qeth_qdio_q *queue = card->qdio.in_q;
  2308. int count;
  2309. int i;
  2310. int rc;
  2311. int newcount = 0;
  2312. count = (index < queue->next_buf_to_init)?
  2313. card->qdio.in_buf_pool.buf_count -
  2314. (queue->next_buf_to_init - index) :
  2315. card->qdio.in_buf_pool.buf_count -
  2316. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2317. /* only requeue at a certain threshold to avoid SIGAs */
  2318. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2319. for (i = queue->next_buf_to_init;
  2320. i < queue->next_buf_to_init + count; ++i) {
  2321. if (qeth_init_input_buffer(card,
  2322. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2323. break;
  2324. } else {
  2325. newcount++;
  2326. }
  2327. }
  2328. if (newcount < count) {
  2329. /* we are in memory shortage so we switch back to
  2330. traditional skb allocation and drop packages */
  2331. if (!atomic_read(&card->force_alloc_skb) &&
  2332. net_ratelimit())
  2333. PRINT_WARN("Switch to alloc skb\n");
  2334. atomic_set(&card->force_alloc_skb, 3);
  2335. count = newcount;
  2336. } else {
  2337. if ((atomic_read(&card->force_alloc_skb) == 1) &&
  2338. net_ratelimit())
  2339. PRINT_WARN("Switch to sg\n");
  2340. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2341. }
  2342. /*
  2343. * according to old code it should be avoided to requeue all
  2344. * 128 buffers in order to benefit from PCI avoidance.
  2345. * this function keeps at least one buffer (the buffer at
  2346. * 'index') un-requeued -> this buffer is the first buffer that
  2347. * will be requeued the next time
  2348. */
  2349. if (card->options.performance_stats) {
  2350. card->perf_stats.inbound_do_qdio_cnt++;
  2351. card->perf_stats.inbound_do_qdio_start_time =
  2352. qeth_get_micros();
  2353. }
  2354. rc = do_QDIO(CARD_DDEV(card),
  2355. QDIO_FLAG_SYNC_INPUT | QDIO_FLAG_UNDER_INTERRUPT,
  2356. 0, queue->next_buf_to_init, count, NULL);
  2357. if (card->options.performance_stats)
  2358. card->perf_stats.inbound_do_qdio_time +=
  2359. qeth_get_micros() -
  2360. card->perf_stats.inbound_do_qdio_start_time;
  2361. if (rc) {
  2362. PRINT_WARN("qeth_queue_input_buffer's do_QDIO "
  2363. "return %i (device %s).\n",
  2364. rc, CARD_DDEV_ID(card));
  2365. QETH_DBF_TEXT(TRACE, 2, "qinberr");
  2366. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2367. }
  2368. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2369. QDIO_MAX_BUFFERS_PER_Q;
  2370. }
  2371. }
  2372. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2373. static int qeth_handle_send_error(struct qeth_card *card,
  2374. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err,
  2375. unsigned int siga_err)
  2376. {
  2377. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2378. int cc = siga_err & 3;
  2379. QETH_DBF_TEXT(TRACE, 6, "hdsnderr");
  2380. qeth_check_qdio_errors(buffer->buffer, qdio_err, siga_err, "qouterr");
  2381. switch (cc) {
  2382. case 0:
  2383. if (qdio_err) {
  2384. QETH_DBF_TEXT(TRACE, 1, "lnkfail");
  2385. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2386. QETH_DBF_TEXT_(TRACE, 1, "%04x %02x",
  2387. (u16)qdio_err, (u8)sbalf15);
  2388. return QETH_SEND_ERROR_LINK_FAILURE;
  2389. }
  2390. return QETH_SEND_ERROR_NONE;
  2391. case 2:
  2392. if (siga_err & QDIO_SIGA_ERROR_B_BIT_SET) {
  2393. QETH_DBF_TEXT(TRACE, 1, "SIGAcc2B");
  2394. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2395. return QETH_SEND_ERROR_KICK_IT;
  2396. }
  2397. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2398. return QETH_SEND_ERROR_RETRY;
  2399. return QETH_SEND_ERROR_LINK_FAILURE;
  2400. /* look at qdio_error and sbalf 15 */
  2401. case 1:
  2402. QETH_DBF_TEXT(TRACE, 1, "SIGAcc1");
  2403. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2404. return QETH_SEND_ERROR_LINK_FAILURE;
  2405. case 3:
  2406. default:
  2407. QETH_DBF_TEXT(TRACE, 1, "SIGAcc3");
  2408. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2409. return QETH_SEND_ERROR_KICK_IT;
  2410. }
  2411. }
  2412. /*
  2413. * Switched to packing state if the number of used buffers on a queue
  2414. * reaches a certain limit.
  2415. */
  2416. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2417. {
  2418. if (!queue->do_pack) {
  2419. if (atomic_read(&queue->used_buffers)
  2420. >= QETH_HIGH_WATERMARK_PACK){
  2421. /* switch non-PACKING -> PACKING */
  2422. QETH_DBF_TEXT(TRACE, 6, "np->pack");
  2423. if (queue->card->options.performance_stats)
  2424. queue->card->perf_stats.sc_dp_p++;
  2425. queue->do_pack = 1;
  2426. }
  2427. }
  2428. }
  2429. /*
  2430. * Switches from packing to non-packing mode. If there is a packing
  2431. * buffer on the queue this buffer will be prepared to be flushed.
  2432. * In that case 1 is returned to inform the caller. If no buffer
  2433. * has to be flushed, zero is returned.
  2434. */
  2435. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2436. {
  2437. struct qeth_qdio_out_buffer *buffer;
  2438. int flush_count = 0;
  2439. if (queue->do_pack) {
  2440. if (atomic_read(&queue->used_buffers)
  2441. <= QETH_LOW_WATERMARK_PACK) {
  2442. /* switch PACKING -> non-PACKING */
  2443. QETH_DBF_TEXT(TRACE, 6, "pack->np");
  2444. if (queue->card->options.performance_stats)
  2445. queue->card->perf_stats.sc_p_dp++;
  2446. queue->do_pack = 0;
  2447. /* flush packing buffers */
  2448. buffer = &queue->bufs[queue->next_buf_to_fill];
  2449. if ((atomic_read(&buffer->state) ==
  2450. QETH_QDIO_BUF_EMPTY) &&
  2451. (buffer->next_element_to_fill > 0)) {
  2452. atomic_set(&buffer->state,
  2453. QETH_QDIO_BUF_PRIMED);
  2454. flush_count++;
  2455. queue->next_buf_to_fill =
  2456. (queue->next_buf_to_fill + 1) %
  2457. QDIO_MAX_BUFFERS_PER_Q;
  2458. }
  2459. }
  2460. }
  2461. return flush_count;
  2462. }
  2463. /*
  2464. * Called to flush a packing buffer if no more pci flags are on the queue.
  2465. * Checks if there is a packing buffer and prepares it to be flushed.
  2466. * In that case returns 1, otherwise zero.
  2467. */
  2468. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2469. {
  2470. struct qeth_qdio_out_buffer *buffer;
  2471. buffer = &queue->bufs[queue->next_buf_to_fill];
  2472. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2473. (buffer->next_element_to_fill > 0)) {
  2474. /* it's a packing buffer */
  2475. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2476. queue->next_buf_to_fill =
  2477. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2478. return 1;
  2479. }
  2480. return 0;
  2481. }
  2482. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int under_int,
  2483. int index, int count)
  2484. {
  2485. struct qeth_qdio_out_buffer *buf;
  2486. int rc;
  2487. int i;
  2488. unsigned int qdio_flags;
  2489. for (i = index; i < index + count; ++i) {
  2490. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2491. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2492. SBAL_FLAGS_LAST_ENTRY;
  2493. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2494. continue;
  2495. if (!queue->do_pack) {
  2496. if ((atomic_read(&queue->used_buffers) >=
  2497. (QETH_HIGH_WATERMARK_PACK -
  2498. QETH_WATERMARK_PACK_FUZZ)) &&
  2499. !atomic_read(&queue->set_pci_flags_count)) {
  2500. /* it's likely that we'll go to packing
  2501. * mode soon */
  2502. atomic_inc(&queue->set_pci_flags_count);
  2503. buf->buffer->element[0].flags |= 0x40;
  2504. }
  2505. } else {
  2506. if (!atomic_read(&queue->set_pci_flags_count)) {
  2507. /*
  2508. * there's no outstanding PCI any more, so we
  2509. * have to request a PCI to be sure the the PCI
  2510. * will wake at some time in the future then we
  2511. * can flush packed buffers that might still be
  2512. * hanging around, which can happen if no
  2513. * further send was requested by the stack
  2514. */
  2515. atomic_inc(&queue->set_pci_flags_count);
  2516. buf->buffer->element[0].flags |= 0x40;
  2517. }
  2518. }
  2519. }
  2520. queue->card->dev->trans_start = jiffies;
  2521. if (queue->card->options.performance_stats) {
  2522. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2523. queue->card->perf_stats.outbound_do_qdio_start_time =
  2524. qeth_get_micros();
  2525. }
  2526. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2527. if (under_int)
  2528. qdio_flags |= QDIO_FLAG_UNDER_INTERRUPT;
  2529. if (atomic_read(&queue->set_pci_flags_count))
  2530. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2531. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2532. queue->queue_no, index, count, NULL);
  2533. if (queue->card->options.performance_stats)
  2534. queue->card->perf_stats.outbound_do_qdio_time +=
  2535. qeth_get_micros() -
  2536. queue->card->perf_stats.outbound_do_qdio_start_time;
  2537. if (rc) {
  2538. QETH_DBF_TEXT(TRACE, 2, "flushbuf");
  2539. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  2540. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card));
  2541. queue->card->stats.tx_errors += count;
  2542. /* this must not happen under normal circumstances. if it
  2543. * happens something is really wrong -> recover */
  2544. qeth_schedule_recovery(queue->card);
  2545. return;
  2546. }
  2547. atomic_add(count, &queue->used_buffers);
  2548. if (queue->card->options.performance_stats)
  2549. queue->card->perf_stats.bufs_sent += count;
  2550. }
  2551. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2552. {
  2553. int index;
  2554. int flush_cnt = 0;
  2555. int q_was_packing = 0;
  2556. /*
  2557. * check if weed have to switch to non-packing mode or if
  2558. * we have to get a pci flag out on the queue
  2559. */
  2560. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2561. !atomic_read(&queue->set_pci_flags_count)) {
  2562. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2563. QETH_OUT_Q_UNLOCKED) {
  2564. /*
  2565. * If we get in here, there was no action in
  2566. * do_send_packet. So, we check if there is a
  2567. * packing buffer to be flushed here.
  2568. */
  2569. netif_stop_queue(queue->card->dev);
  2570. index = queue->next_buf_to_fill;
  2571. q_was_packing = queue->do_pack;
  2572. /* queue->do_pack may change */
  2573. barrier();
  2574. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2575. if (!flush_cnt &&
  2576. !atomic_read(&queue->set_pci_flags_count))
  2577. flush_cnt +=
  2578. qeth_flush_buffers_on_no_pci(queue);
  2579. if (queue->card->options.performance_stats &&
  2580. q_was_packing)
  2581. queue->card->perf_stats.bufs_sent_pack +=
  2582. flush_cnt;
  2583. if (flush_cnt)
  2584. qeth_flush_buffers(queue, 1, index, flush_cnt);
  2585. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2586. }
  2587. }
  2588. }
  2589. void qeth_qdio_output_handler(struct ccw_device *ccwdev, unsigned int status,
  2590. unsigned int qdio_error, unsigned int siga_error,
  2591. unsigned int __queue, int first_element, int count,
  2592. unsigned long card_ptr)
  2593. {
  2594. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2595. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2596. struct qeth_qdio_out_buffer *buffer;
  2597. int i;
  2598. QETH_DBF_TEXT(TRACE, 6, "qdouhdl");
  2599. if (status & QDIO_STATUS_LOOK_FOR_ERROR) {
  2600. if (status & QDIO_STATUS_ACTIVATE_CHECK_CONDITION) {
  2601. QETH_DBF_TEXT(TRACE, 2, "achkcond");
  2602. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2603. QETH_DBF_TEXT_(TRACE, 2, "%08x", status);
  2604. netif_stop_queue(card->dev);
  2605. qeth_schedule_recovery(card);
  2606. return;
  2607. }
  2608. }
  2609. if (card->options.performance_stats) {
  2610. card->perf_stats.outbound_handler_cnt++;
  2611. card->perf_stats.outbound_handler_start_time =
  2612. qeth_get_micros();
  2613. }
  2614. for (i = first_element; i < (first_element + count); ++i) {
  2615. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2616. /*we only handle the KICK_IT error by doing a recovery */
  2617. if (qeth_handle_send_error(card, buffer,
  2618. qdio_error, siga_error)
  2619. == QETH_SEND_ERROR_KICK_IT){
  2620. netif_stop_queue(card->dev);
  2621. qeth_schedule_recovery(card);
  2622. return;
  2623. }
  2624. qeth_clear_output_buffer(queue, buffer);
  2625. }
  2626. atomic_sub(count, &queue->used_buffers);
  2627. /* check if we need to do something on this outbound queue */
  2628. if (card->info.type != QETH_CARD_TYPE_IQD)
  2629. qeth_check_outbound_queue(queue);
  2630. netif_wake_queue(queue->card->dev);
  2631. if (card->options.performance_stats)
  2632. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2633. card->perf_stats.outbound_handler_start_time;
  2634. }
  2635. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2636. int qeth_get_cast_type(struct qeth_card *card, struct sk_buff *skb)
  2637. {
  2638. int cast_type = RTN_UNSPEC;
  2639. if (card->info.type == QETH_CARD_TYPE_OSN)
  2640. return cast_type;
  2641. if (skb->dst && skb->dst->neighbour) {
  2642. cast_type = skb->dst->neighbour->type;
  2643. if ((cast_type == RTN_BROADCAST) ||
  2644. (cast_type == RTN_MULTICAST) ||
  2645. (cast_type == RTN_ANYCAST))
  2646. return cast_type;
  2647. else
  2648. return RTN_UNSPEC;
  2649. }
  2650. /* try something else */
  2651. if (skb->protocol == ETH_P_IPV6)
  2652. return (skb_network_header(skb)[24] == 0xff) ?
  2653. RTN_MULTICAST : 0;
  2654. else if (skb->protocol == ETH_P_IP)
  2655. return ((skb_network_header(skb)[16] & 0xf0) == 0xe0) ?
  2656. RTN_MULTICAST : 0;
  2657. /* ... */
  2658. if (!memcmp(skb->data, skb->dev->broadcast, 6))
  2659. return RTN_BROADCAST;
  2660. else {
  2661. u16 hdr_mac;
  2662. hdr_mac = *((u16 *)skb->data);
  2663. /* tr multicast? */
  2664. switch (card->info.link_type) {
  2665. case QETH_LINK_TYPE_HSTR:
  2666. case QETH_LINK_TYPE_LANE_TR:
  2667. if ((hdr_mac == QETH_TR_MAC_NC) ||
  2668. (hdr_mac == QETH_TR_MAC_C))
  2669. return RTN_MULTICAST;
  2670. break;
  2671. /* eth or so multicast? */
  2672. default:
  2673. if ((hdr_mac == QETH_ETH_MAC_V4) ||
  2674. (hdr_mac == QETH_ETH_MAC_V6))
  2675. return RTN_MULTICAST;
  2676. }
  2677. }
  2678. return cast_type;
  2679. }
  2680. EXPORT_SYMBOL_GPL(qeth_get_cast_type);
  2681. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2682. int ipv, int cast_type)
  2683. {
  2684. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
  2685. return card->qdio.default_out_queue;
  2686. switch (card->qdio.no_out_queues) {
  2687. case 4:
  2688. if (cast_type && card->info.is_multicast_different)
  2689. return card->info.is_multicast_different &
  2690. (card->qdio.no_out_queues - 1);
  2691. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2692. const u8 tos = ip_hdr(skb)->tos;
  2693. if (card->qdio.do_prio_queueing ==
  2694. QETH_PRIO_Q_ING_TOS) {
  2695. if (tos & IP_TOS_NOTIMPORTANT)
  2696. return 3;
  2697. if (tos & IP_TOS_HIGHRELIABILITY)
  2698. return 2;
  2699. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2700. return 1;
  2701. if (tos & IP_TOS_LOWDELAY)
  2702. return 0;
  2703. }
  2704. if (card->qdio.do_prio_queueing ==
  2705. QETH_PRIO_Q_ING_PREC)
  2706. return 3 - (tos >> 6);
  2707. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2708. /* TODO: IPv6!!! */
  2709. }
  2710. return card->qdio.default_out_queue;
  2711. case 1: /* fallthrough for single-out-queue 1920-device */
  2712. default:
  2713. return card->qdio.default_out_queue;
  2714. }
  2715. }
  2716. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2717. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2718. struct sk_buff *skb, int elems)
  2719. {
  2720. int elements_needed = 0;
  2721. if (skb_shinfo(skb)->nr_frags > 0)
  2722. elements_needed = (skb_shinfo(skb)->nr_frags + 1);
  2723. if (elements_needed == 0)
  2724. elements_needed = 1 + (((((unsigned long) hdr) % PAGE_SIZE)
  2725. + skb->len) >> PAGE_SHIFT);
  2726. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2727. PRINT_ERR("Invalid size of IP packet "
  2728. "(Number=%d / Length=%d). Discarded.\n",
  2729. (elements_needed+elems), skb->len);
  2730. return 0;
  2731. }
  2732. return elements_needed;
  2733. }
  2734. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2735. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2736. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill)
  2737. {
  2738. int length = skb->len;
  2739. int length_here;
  2740. int element;
  2741. char *data;
  2742. int first_lap ;
  2743. element = *next_element_to_fill;
  2744. data = skb->data;
  2745. first_lap = (is_tso == 0 ? 1 : 0);
  2746. while (length > 0) {
  2747. /* length_here is the remaining amount of data in this page */
  2748. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2749. if (length < length_here)
  2750. length_here = length;
  2751. buffer->element[element].addr = data;
  2752. buffer->element[element].length = length_here;
  2753. length -= length_here;
  2754. if (!length) {
  2755. if (first_lap)
  2756. buffer->element[element].flags = 0;
  2757. else
  2758. buffer->element[element].flags =
  2759. SBAL_FLAGS_LAST_FRAG;
  2760. } else {
  2761. if (first_lap)
  2762. buffer->element[element].flags =
  2763. SBAL_FLAGS_FIRST_FRAG;
  2764. else
  2765. buffer->element[element].flags =
  2766. SBAL_FLAGS_MIDDLE_FRAG;
  2767. }
  2768. data += length_here;
  2769. element++;
  2770. first_lap = 0;
  2771. }
  2772. *next_element_to_fill = element;
  2773. }
  2774. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2775. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb)
  2776. {
  2777. struct qdio_buffer *buffer;
  2778. struct qeth_hdr_tso *hdr;
  2779. int flush_cnt = 0, hdr_len, large_send = 0;
  2780. buffer = buf->buffer;
  2781. atomic_inc(&skb->users);
  2782. skb_queue_tail(&buf->skb_list, skb);
  2783. hdr = (struct qeth_hdr_tso *) skb->data;
  2784. /*check first on TSO ....*/
  2785. if (hdr->hdr.hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2786. int element = buf->next_element_to_fill;
  2787. hdr_len = sizeof(struct qeth_hdr_tso) + hdr->ext.dg_hdr_len;
  2788. /*fill first buffer entry only with header information */
  2789. buffer->element[element].addr = skb->data;
  2790. buffer->element[element].length = hdr_len;
  2791. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2792. buf->next_element_to_fill++;
  2793. skb->data += hdr_len;
  2794. skb->len -= hdr_len;
  2795. large_send = 1;
  2796. }
  2797. if (skb_shinfo(skb)->nr_frags == 0)
  2798. __qeth_fill_buffer(skb, buffer, large_send,
  2799. (int *)&buf->next_element_to_fill);
  2800. else
  2801. __qeth_fill_buffer_frag(skb, buffer, large_send,
  2802. (int *)&buf->next_element_to_fill);
  2803. if (!queue->do_pack) {
  2804. QETH_DBF_TEXT(TRACE, 6, "fillbfnp");
  2805. /* set state to PRIMED -> will be flushed */
  2806. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2807. flush_cnt = 1;
  2808. } else {
  2809. QETH_DBF_TEXT(TRACE, 6, "fillbfpa");
  2810. if (queue->card->options.performance_stats)
  2811. queue->card->perf_stats.skbs_sent_pack++;
  2812. if (buf->next_element_to_fill >=
  2813. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2814. /*
  2815. * packed buffer if full -> set state PRIMED
  2816. * -> will be flushed
  2817. */
  2818. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2819. flush_cnt = 1;
  2820. }
  2821. }
  2822. return flush_cnt;
  2823. }
  2824. int qeth_do_send_packet_fast(struct qeth_card *card,
  2825. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2826. struct qeth_hdr *hdr, int elements_needed,
  2827. struct qeth_eddp_context *ctx)
  2828. {
  2829. struct qeth_qdio_out_buffer *buffer;
  2830. int buffers_needed = 0;
  2831. int flush_cnt = 0;
  2832. int index;
  2833. /* spin until we get the queue ... */
  2834. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2835. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2836. /* ... now we've got the queue */
  2837. index = queue->next_buf_to_fill;
  2838. buffer = &queue->bufs[queue->next_buf_to_fill];
  2839. /*
  2840. * check if buffer is empty to make sure that we do not 'overtake'
  2841. * ourselves and try to fill a buffer that is already primed
  2842. */
  2843. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2844. goto out;
  2845. if (ctx == NULL)
  2846. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2847. QDIO_MAX_BUFFERS_PER_Q;
  2848. else {
  2849. buffers_needed = qeth_eddp_check_buffers_for_context(queue,
  2850. ctx);
  2851. if (buffers_needed < 0)
  2852. goto out;
  2853. queue->next_buf_to_fill =
  2854. (queue->next_buf_to_fill + buffers_needed) %
  2855. QDIO_MAX_BUFFERS_PER_Q;
  2856. }
  2857. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2858. if (ctx == NULL) {
  2859. qeth_fill_buffer(queue, buffer, skb);
  2860. qeth_flush_buffers(queue, 0, index, 1);
  2861. } else {
  2862. flush_cnt = qeth_eddp_fill_buffer(queue, ctx, index);
  2863. WARN_ON(buffers_needed != flush_cnt);
  2864. qeth_flush_buffers(queue, 0, index, flush_cnt);
  2865. }
  2866. return 0;
  2867. out:
  2868. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2869. return -EBUSY;
  2870. }
  2871. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2872. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2873. struct sk_buff *skb, struct qeth_hdr *hdr,
  2874. int elements_needed, struct qeth_eddp_context *ctx)
  2875. {
  2876. struct qeth_qdio_out_buffer *buffer;
  2877. int start_index;
  2878. int flush_count = 0;
  2879. int do_pack = 0;
  2880. int tmp;
  2881. int rc = 0;
  2882. /* spin until we get the queue ... */
  2883. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2884. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2885. start_index = queue->next_buf_to_fill;
  2886. buffer = &queue->bufs[queue->next_buf_to_fill];
  2887. /*
  2888. * check if buffer is empty to make sure that we do not 'overtake'
  2889. * ourselves and try to fill a buffer that is already primed
  2890. */
  2891. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2892. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2893. return -EBUSY;
  2894. }
  2895. /* check if we need to switch packing state of this queue */
  2896. qeth_switch_to_packing_if_needed(queue);
  2897. if (queue->do_pack) {
  2898. do_pack = 1;
  2899. if (ctx == NULL) {
  2900. /* does packet fit in current buffer? */
  2901. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2902. buffer->next_element_to_fill) < elements_needed) {
  2903. /* ... no -> set state PRIMED */
  2904. atomic_set(&buffer->state,
  2905. QETH_QDIO_BUF_PRIMED);
  2906. flush_count++;
  2907. queue->next_buf_to_fill =
  2908. (queue->next_buf_to_fill + 1) %
  2909. QDIO_MAX_BUFFERS_PER_Q;
  2910. buffer = &queue->bufs[queue->next_buf_to_fill];
  2911. /* we did a step forward, so check buffer state
  2912. * again */
  2913. if (atomic_read(&buffer->state) !=
  2914. QETH_QDIO_BUF_EMPTY){
  2915. qeth_flush_buffers(queue, 0,
  2916. start_index, flush_count);
  2917. atomic_set(&queue->state,
  2918. QETH_OUT_Q_UNLOCKED);
  2919. return -EBUSY;
  2920. }
  2921. }
  2922. } else {
  2923. /* check if we have enough elements (including following
  2924. * free buffers) to handle eddp context */
  2925. if (qeth_eddp_check_buffers_for_context(queue, ctx)
  2926. < 0) {
  2927. if (net_ratelimit())
  2928. PRINT_WARN("eddp tx_dropped 1\n");
  2929. rc = -EBUSY;
  2930. goto out;
  2931. }
  2932. }
  2933. }
  2934. if (ctx == NULL)
  2935. tmp = qeth_fill_buffer(queue, buffer, skb);
  2936. else {
  2937. tmp = qeth_eddp_fill_buffer(queue, ctx,
  2938. queue->next_buf_to_fill);
  2939. if (tmp < 0) {
  2940. PRINT_ERR("eddp tx_dropped 2\n");
  2941. rc = -EBUSY;
  2942. goto out;
  2943. }
  2944. }
  2945. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2946. QDIO_MAX_BUFFERS_PER_Q;
  2947. flush_count += tmp;
  2948. out:
  2949. if (flush_count)
  2950. qeth_flush_buffers(queue, 0, start_index, flush_count);
  2951. else if (!atomic_read(&queue->set_pci_flags_count))
  2952. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2953. /*
  2954. * queue->state will go from LOCKED -> UNLOCKED or from
  2955. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2956. * (switch packing state or flush buffer to get another pci flag out).
  2957. * In that case we will enter this loop
  2958. */
  2959. while (atomic_dec_return(&queue->state)) {
  2960. flush_count = 0;
  2961. start_index = queue->next_buf_to_fill;
  2962. /* check if we can go back to non-packing state */
  2963. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  2964. /*
  2965. * check if we need to flush a packing buffer to get a pci
  2966. * flag out on the queue
  2967. */
  2968. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  2969. flush_count += qeth_flush_buffers_on_no_pci(queue);
  2970. if (flush_count)
  2971. qeth_flush_buffers(queue, 0, start_index, flush_count);
  2972. }
  2973. /* at this point the queue is UNLOCKED again */
  2974. if (queue->card->options.performance_stats && do_pack)
  2975. queue->card->perf_stats.bufs_sent_pack += flush_count;
  2976. return rc;
  2977. }
  2978. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  2979. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  2980. struct qeth_reply *reply, unsigned long data)
  2981. {
  2982. struct qeth_ipa_cmd *cmd;
  2983. struct qeth_ipacmd_setadpparms *setparms;
  2984. QETH_DBF_TEXT(TRACE, 4, "prmadpcb");
  2985. cmd = (struct qeth_ipa_cmd *) data;
  2986. setparms = &(cmd->data.setadapterparms);
  2987. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2988. if (cmd->hdr.return_code) {
  2989. QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code);
  2990. setparms->data.mode = SET_PROMISC_MODE_OFF;
  2991. }
  2992. card->info.promisc_mode = setparms->data.mode;
  2993. return 0;
  2994. }
  2995. void qeth_setadp_promisc_mode(struct qeth_card *card)
  2996. {
  2997. enum qeth_ipa_promisc_modes mode;
  2998. struct net_device *dev = card->dev;
  2999. struct qeth_cmd_buffer *iob;
  3000. struct qeth_ipa_cmd *cmd;
  3001. QETH_DBF_TEXT(TRACE, 4, "setprom");
  3002. if (((dev->flags & IFF_PROMISC) &&
  3003. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  3004. (!(dev->flags & IFF_PROMISC) &&
  3005. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  3006. return;
  3007. mode = SET_PROMISC_MODE_OFF;
  3008. if (dev->flags & IFF_PROMISC)
  3009. mode = SET_PROMISC_MODE_ON;
  3010. QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode);
  3011. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3012. sizeof(struct qeth_ipacmd_setadpparms));
  3013. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3014. cmd->data.setadapterparms.data.mode = mode;
  3015. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3016. }
  3017. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3018. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3019. {
  3020. struct qeth_card *card;
  3021. char dbf_text[15];
  3022. card = netdev_priv(dev);
  3023. QETH_DBF_TEXT(TRACE, 4, "chgmtu");
  3024. sprintf(dbf_text, "%8x", new_mtu);
  3025. QETH_DBF_TEXT(TRACE, 4, dbf_text);
  3026. if (new_mtu < 64)
  3027. return -EINVAL;
  3028. if (new_mtu > 65535)
  3029. return -EINVAL;
  3030. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3031. (!qeth_mtu_is_valid(card, new_mtu)))
  3032. return -EINVAL;
  3033. dev->mtu = new_mtu;
  3034. return 0;
  3035. }
  3036. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3037. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3038. {
  3039. struct qeth_card *card;
  3040. card = netdev_priv(dev);
  3041. QETH_DBF_TEXT(TRACE, 5, "getstat");
  3042. return &card->stats;
  3043. }
  3044. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3045. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3046. struct qeth_reply *reply, unsigned long data)
  3047. {
  3048. struct qeth_ipa_cmd *cmd;
  3049. QETH_DBF_TEXT(TRACE, 4, "chgmaccb");
  3050. cmd = (struct qeth_ipa_cmd *) data;
  3051. if (!card->options.layer2 ||
  3052. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3053. memcpy(card->dev->dev_addr,
  3054. &cmd->data.setadapterparms.data.change_addr.addr,
  3055. OSA_ADDR_LEN);
  3056. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3057. }
  3058. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3059. return 0;
  3060. }
  3061. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3062. {
  3063. int rc;
  3064. struct qeth_cmd_buffer *iob;
  3065. struct qeth_ipa_cmd *cmd;
  3066. QETH_DBF_TEXT(TRACE, 4, "chgmac");
  3067. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3068. sizeof(struct qeth_ipacmd_setadpparms));
  3069. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3070. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3071. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3072. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3073. card->dev->dev_addr, OSA_ADDR_LEN);
  3074. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3075. NULL);
  3076. return rc;
  3077. }
  3078. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3079. void qeth_tx_timeout(struct net_device *dev)
  3080. {
  3081. struct qeth_card *card;
  3082. card = netdev_priv(dev);
  3083. card->stats.tx_errors++;
  3084. qeth_schedule_recovery(card);
  3085. }
  3086. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3087. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3088. {
  3089. struct qeth_card *card = netdev_priv(dev);
  3090. int rc = 0;
  3091. switch (regnum) {
  3092. case MII_BMCR: /* Basic mode control register */
  3093. rc = BMCR_FULLDPLX;
  3094. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3095. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3096. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3097. rc |= BMCR_SPEED100;
  3098. break;
  3099. case MII_BMSR: /* Basic mode status register */
  3100. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3101. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3102. BMSR_100BASE4;
  3103. break;
  3104. case MII_PHYSID1: /* PHYS ID 1 */
  3105. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3106. dev->dev_addr[2];
  3107. rc = (rc >> 5) & 0xFFFF;
  3108. break;
  3109. case MII_PHYSID2: /* PHYS ID 2 */
  3110. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3111. break;
  3112. case MII_ADVERTISE: /* Advertisement control reg */
  3113. rc = ADVERTISE_ALL;
  3114. break;
  3115. case MII_LPA: /* Link partner ability reg */
  3116. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3117. LPA_100BASE4 | LPA_LPACK;
  3118. break;
  3119. case MII_EXPANSION: /* Expansion register */
  3120. break;
  3121. case MII_DCOUNTER: /* disconnect counter */
  3122. break;
  3123. case MII_FCSCOUNTER: /* false carrier counter */
  3124. break;
  3125. case MII_NWAYTEST: /* N-way auto-neg test register */
  3126. break;
  3127. case MII_RERRCOUNTER: /* rx error counter */
  3128. rc = card->stats.rx_errors;
  3129. break;
  3130. case MII_SREVISION: /* silicon revision */
  3131. break;
  3132. case MII_RESV1: /* reserved 1 */
  3133. break;
  3134. case MII_LBRERROR: /* loopback, rx, bypass error */
  3135. break;
  3136. case MII_PHYADDR: /* physical address */
  3137. break;
  3138. case MII_RESV2: /* reserved 2 */
  3139. break;
  3140. case MII_TPISTATUS: /* TPI status for 10mbps */
  3141. break;
  3142. case MII_NCONFIG: /* network interface config */
  3143. break;
  3144. default:
  3145. break;
  3146. }
  3147. return rc;
  3148. }
  3149. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3150. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3151. struct qeth_cmd_buffer *iob, int len,
  3152. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3153. unsigned long),
  3154. void *reply_param)
  3155. {
  3156. u16 s1, s2;
  3157. QETH_DBF_TEXT(TRACE, 4, "sendsnmp");
  3158. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3159. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3160. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3161. /* adjust PDU length fields in IPA_PDU_HEADER */
  3162. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3163. s2 = (u32) len;
  3164. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3165. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3166. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3167. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3168. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3169. reply_cb, reply_param);
  3170. }
  3171. static int qeth_snmp_command_cb(struct qeth_card *card,
  3172. struct qeth_reply *reply, unsigned long sdata)
  3173. {
  3174. struct qeth_ipa_cmd *cmd;
  3175. struct qeth_arp_query_info *qinfo;
  3176. struct qeth_snmp_cmd *snmp;
  3177. unsigned char *data;
  3178. __u16 data_len;
  3179. QETH_DBF_TEXT(TRACE, 3, "snpcmdcb");
  3180. cmd = (struct qeth_ipa_cmd *) sdata;
  3181. data = (unsigned char *)((char *)cmd - reply->offset);
  3182. qinfo = (struct qeth_arp_query_info *) reply->param;
  3183. snmp = &cmd->data.setadapterparms.data.snmp;
  3184. if (cmd->hdr.return_code) {
  3185. QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code);
  3186. return 0;
  3187. }
  3188. if (cmd->data.setadapterparms.hdr.return_code) {
  3189. cmd->hdr.return_code =
  3190. cmd->data.setadapterparms.hdr.return_code;
  3191. QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code);
  3192. return 0;
  3193. }
  3194. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3195. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3196. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3197. else
  3198. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3199. /* check if there is enough room in userspace */
  3200. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3201. QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM);
  3202. cmd->hdr.return_code = -ENOMEM;
  3203. return 0;
  3204. }
  3205. QETH_DBF_TEXT_(TRACE, 4, "snore%i",
  3206. cmd->data.setadapterparms.hdr.used_total);
  3207. QETH_DBF_TEXT_(TRACE, 4, "sseqn%i",
  3208. cmd->data.setadapterparms.hdr.seq_no);
  3209. /*copy entries to user buffer*/
  3210. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3211. memcpy(qinfo->udata + qinfo->udata_offset,
  3212. (char *)snmp,
  3213. data_len + offsetof(struct qeth_snmp_cmd, data));
  3214. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3215. } else {
  3216. memcpy(qinfo->udata + qinfo->udata_offset,
  3217. (char *)&snmp->request, data_len);
  3218. }
  3219. qinfo->udata_offset += data_len;
  3220. /* check if all replies received ... */
  3221. QETH_DBF_TEXT_(TRACE, 4, "srtot%i",
  3222. cmd->data.setadapterparms.hdr.used_total);
  3223. QETH_DBF_TEXT_(TRACE, 4, "srseq%i",
  3224. cmd->data.setadapterparms.hdr.seq_no);
  3225. if (cmd->data.setadapterparms.hdr.seq_no <
  3226. cmd->data.setadapterparms.hdr.used_total)
  3227. return 1;
  3228. return 0;
  3229. }
  3230. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3231. {
  3232. struct qeth_cmd_buffer *iob;
  3233. struct qeth_ipa_cmd *cmd;
  3234. struct qeth_snmp_ureq *ureq;
  3235. int req_len;
  3236. struct qeth_arp_query_info qinfo = {0, };
  3237. int rc = 0;
  3238. QETH_DBF_TEXT(TRACE, 3, "snmpcmd");
  3239. if (card->info.guestlan)
  3240. return -EOPNOTSUPP;
  3241. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3242. (!card->options.layer2)) {
  3243. PRINT_WARN("SNMP Query MIBS not supported "
  3244. "on %s!\n", QETH_CARD_IFNAME(card));
  3245. return -EOPNOTSUPP;
  3246. }
  3247. /* skip 4 bytes (data_len struct member) to get req_len */
  3248. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3249. return -EFAULT;
  3250. ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
  3251. if (!ureq) {
  3252. QETH_DBF_TEXT(TRACE, 2, "snmpnome");
  3253. return -ENOMEM;
  3254. }
  3255. if (copy_from_user(ureq, udata,
  3256. req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
  3257. kfree(ureq);
  3258. return -EFAULT;
  3259. }
  3260. qinfo.udata_len = ureq->hdr.data_len;
  3261. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3262. if (!qinfo.udata) {
  3263. kfree(ureq);
  3264. return -ENOMEM;
  3265. }
  3266. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3267. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3268. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3269. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3270. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3271. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3272. qeth_snmp_command_cb, (void *)&qinfo);
  3273. if (rc)
  3274. PRINT_WARN("SNMP command failed on %s: (0x%x)\n",
  3275. QETH_CARD_IFNAME(card), rc);
  3276. else {
  3277. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3278. rc = -EFAULT;
  3279. }
  3280. kfree(ureq);
  3281. kfree(qinfo.udata);
  3282. return rc;
  3283. }
  3284. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3285. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3286. {
  3287. switch (card->info.type) {
  3288. case QETH_CARD_TYPE_IQD:
  3289. return 2;
  3290. default:
  3291. return 0;
  3292. }
  3293. }
  3294. static int qeth_qdio_establish(struct qeth_card *card)
  3295. {
  3296. struct qdio_initialize init_data;
  3297. char *qib_param_field;
  3298. struct qdio_buffer **in_sbal_ptrs;
  3299. struct qdio_buffer **out_sbal_ptrs;
  3300. int i, j, k;
  3301. int rc = 0;
  3302. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3303. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3304. GFP_KERNEL);
  3305. if (!qib_param_field)
  3306. return -ENOMEM;
  3307. qeth_create_qib_param_field(card, qib_param_field);
  3308. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3309. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3310. GFP_KERNEL);
  3311. if (!in_sbal_ptrs) {
  3312. kfree(qib_param_field);
  3313. return -ENOMEM;
  3314. }
  3315. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3316. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3317. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3318. out_sbal_ptrs =
  3319. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3320. sizeof(void *), GFP_KERNEL);
  3321. if (!out_sbal_ptrs) {
  3322. kfree(in_sbal_ptrs);
  3323. kfree(qib_param_field);
  3324. return -ENOMEM;
  3325. }
  3326. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3327. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3328. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3329. card->qdio.out_qs[i]->bufs[j].buffer);
  3330. }
  3331. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3332. init_data.cdev = CARD_DDEV(card);
  3333. init_data.q_format = qeth_get_qdio_q_format(card);
  3334. init_data.qib_param_field_format = 0;
  3335. init_data.qib_param_field = qib_param_field;
  3336. init_data.min_input_threshold = QETH_MIN_INPUT_THRESHOLD;
  3337. init_data.max_input_threshold = QETH_MAX_INPUT_THRESHOLD;
  3338. init_data.min_output_threshold = QETH_MIN_OUTPUT_THRESHOLD;
  3339. init_data.max_output_threshold = QETH_MAX_OUTPUT_THRESHOLD;
  3340. init_data.no_input_qs = 1;
  3341. init_data.no_output_qs = card->qdio.no_out_queues;
  3342. init_data.input_handler = card->discipline.input_handler;
  3343. init_data.output_handler = card->discipline.output_handler;
  3344. init_data.int_parm = (unsigned long) card;
  3345. init_data.flags = QDIO_INBOUND_0COPY_SBALS |
  3346. QDIO_OUTBOUND_0COPY_SBALS |
  3347. QDIO_USE_OUTBOUND_PCIS;
  3348. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3349. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3350. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3351. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3352. rc = qdio_initialize(&init_data);
  3353. if (rc)
  3354. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3355. }
  3356. kfree(out_sbal_ptrs);
  3357. kfree(in_sbal_ptrs);
  3358. kfree(qib_param_field);
  3359. return rc;
  3360. }
  3361. static void qeth_core_free_card(struct qeth_card *card)
  3362. {
  3363. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3364. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3365. qeth_clean_channel(&card->read);
  3366. qeth_clean_channel(&card->write);
  3367. if (card->dev)
  3368. free_netdev(card->dev);
  3369. kfree(card->ip_tbd_list);
  3370. qeth_free_qdio_buffers(card);
  3371. kfree(card);
  3372. }
  3373. static struct ccw_device_id qeth_ids[] = {
  3374. {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
  3375. {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
  3376. {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
  3377. {},
  3378. };
  3379. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3380. static struct ccw_driver qeth_ccw_driver = {
  3381. .name = "qeth",
  3382. .ids = qeth_ids,
  3383. .probe = ccwgroup_probe_ccwdev,
  3384. .remove = ccwgroup_remove_ccwdev,
  3385. };
  3386. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3387. unsigned long driver_id)
  3388. {
  3389. return ccwgroup_create_from_string(root_dev, driver_id,
  3390. &qeth_ccw_driver, 3, buf);
  3391. }
  3392. int qeth_core_hardsetup_card(struct qeth_card *card)
  3393. {
  3394. int retries = 3;
  3395. int mpno;
  3396. int rc;
  3397. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3398. atomic_set(&card->force_alloc_skb, 0);
  3399. retry:
  3400. if (retries < 3) {
  3401. PRINT_WARN("Retrying to do IDX activates.\n");
  3402. ccw_device_set_offline(CARD_DDEV(card));
  3403. ccw_device_set_offline(CARD_WDEV(card));
  3404. ccw_device_set_offline(CARD_RDEV(card));
  3405. ccw_device_set_online(CARD_RDEV(card));
  3406. ccw_device_set_online(CARD_WDEV(card));
  3407. ccw_device_set_online(CARD_DDEV(card));
  3408. }
  3409. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3410. if (rc == -ERESTARTSYS) {
  3411. QETH_DBF_TEXT(SETUP, 2, "break1");
  3412. return rc;
  3413. } else if (rc) {
  3414. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3415. if (--retries < 0)
  3416. goto out;
  3417. else
  3418. goto retry;
  3419. }
  3420. rc = qeth_get_unitaddr(card);
  3421. if (rc) {
  3422. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3423. return rc;
  3424. }
  3425. mpno = qdio_get_ssqd_pct(CARD_DDEV(card));
  3426. if (mpno)
  3427. mpno = min(mpno - 1, QETH_MAX_PORTNO);
  3428. if (card->info.portno > mpno) {
  3429. PRINT_ERR("Device %s does not offer port number %d \n.",
  3430. CARD_BUS_ID(card), card->info.portno);
  3431. rc = -ENODEV;
  3432. goto out;
  3433. }
  3434. qeth_init_tokens(card);
  3435. qeth_init_func_level(card);
  3436. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3437. if (rc == -ERESTARTSYS) {
  3438. QETH_DBF_TEXT(SETUP, 2, "break2");
  3439. return rc;
  3440. } else if (rc) {
  3441. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3442. if (--retries < 0)
  3443. goto out;
  3444. else
  3445. goto retry;
  3446. }
  3447. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3448. if (rc == -ERESTARTSYS) {
  3449. QETH_DBF_TEXT(SETUP, 2, "break3");
  3450. return rc;
  3451. } else if (rc) {
  3452. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3453. if (--retries < 0)
  3454. goto out;
  3455. else
  3456. goto retry;
  3457. }
  3458. rc = qeth_mpc_initialize(card);
  3459. if (rc) {
  3460. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3461. goto out;
  3462. }
  3463. return 0;
  3464. out:
  3465. PRINT_ERR("Initialization in hardsetup failed! rc=%d\n", rc);
  3466. return rc;
  3467. }
  3468. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3469. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3470. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3471. {
  3472. struct page *page = virt_to_page(element->addr);
  3473. if (*pskb == NULL) {
  3474. /* the upper protocol layers assume that there is data in the
  3475. * skb itself. Copy a small amount (64 bytes) to make them
  3476. * happy. */
  3477. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3478. if (!(*pskb))
  3479. return -ENOMEM;
  3480. skb_reserve(*pskb, ETH_HLEN);
  3481. if (data_len <= 64) {
  3482. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3483. data_len);
  3484. } else {
  3485. get_page(page);
  3486. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3487. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3488. data_len - 64);
  3489. (*pskb)->data_len += data_len - 64;
  3490. (*pskb)->len += data_len - 64;
  3491. (*pskb)->truesize += data_len - 64;
  3492. (*pfrag)++;
  3493. }
  3494. } else {
  3495. get_page(page);
  3496. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3497. (*pskb)->data_len += data_len;
  3498. (*pskb)->len += data_len;
  3499. (*pskb)->truesize += data_len;
  3500. (*pfrag)++;
  3501. }
  3502. return 0;
  3503. }
  3504. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3505. struct qdio_buffer *buffer,
  3506. struct qdio_buffer_element **__element, int *__offset,
  3507. struct qeth_hdr **hdr)
  3508. {
  3509. struct qdio_buffer_element *element = *__element;
  3510. int offset = *__offset;
  3511. struct sk_buff *skb = NULL;
  3512. int skb_len;
  3513. void *data_ptr;
  3514. int data_len;
  3515. int headroom = 0;
  3516. int use_rx_sg = 0;
  3517. int frag = 0;
  3518. /* qeth_hdr must not cross element boundaries */
  3519. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3520. if (qeth_is_last_sbale(element))
  3521. return NULL;
  3522. element++;
  3523. offset = 0;
  3524. if (element->length < sizeof(struct qeth_hdr))
  3525. return NULL;
  3526. }
  3527. *hdr = element->addr + offset;
  3528. offset += sizeof(struct qeth_hdr);
  3529. if (card->options.layer2) {
  3530. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3531. skb_len = (*hdr)->hdr.osn.pdu_length;
  3532. headroom = sizeof(struct qeth_hdr);
  3533. } else {
  3534. skb_len = (*hdr)->hdr.l2.pkt_length;
  3535. }
  3536. } else {
  3537. skb_len = (*hdr)->hdr.l3.length;
  3538. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3539. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3540. headroom = TR_HLEN;
  3541. else
  3542. headroom = ETH_HLEN;
  3543. }
  3544. if (!skb_len)
  3545. return NULL;
  3546. if ((skb_len >= card->options.rx_sg_cb) &&
  3547. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3548. (!atomic_read(&card->force_alloc_skb))) {
  3549. use_rx_sg = 1;
  3550. } else {
  3551. skb = dev_alloc_skb(skb_len + headroom);
  3552. if (!skb)
  3553. goto no_mem;
  3554. if (headroom)
  3555. skb_reserve(skb, headroom);
  3556. }
  3557. data_ptr = element->addr + offset;
  3558. while (skb_len) {
  3559. data_len = min(skb_len, (int)(element->length - offset));
  3560. if (data_len) {
  3561. if (use_rx_sg) {
  3562. if (qeth_create_skb_frag(element, &skb, offset,
  3563. &frag, data_len))
  3564. goto no_mem;
  3565. } else {
  3566. memcpy(skb_put(skb, data_len), data_ptr,
  3567. data_len);
  3568. }
  3569. }
  3570. skb_len -= data_len;
  3571. if (skb_len) {
  3572. if (qeth_is_last_sbale(element)) {
  3573. QETH_DBF_TEXT(TRACE, 4, "unexeob");
  3574. QETH_DBF_TEXT_(TRACE, 4, "%s",
  3575. CARD_BUS_ID(card));
  3576. QETH_DBF_TEXT(QERR, 2, "unexeob");
  3577. QETH_DBF_TEXT_(QERR, 2, "%s",
  3578. CARD_BUS_ID(card));
  3579. QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
  3580. dev_kfree_skb_any(skb);
  3581. card->stats.rx_errors++;
  3582. return NULL;
  3583. }
  3584. element++;
  3585. offset = 0;
  3586. data_ptr = element->addr;
  3587. } else {
  3588. offset += data_len;
  3589. }
  3590. }
  3591. *__element = element;
  3592. *__offset = offset;
  3593. if (use_rx_sg && card->options.performance_stats) {
  3594. card->perf_stats.sg_skbs_rx++;
  3595. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3596. }
  3597. return skb;
  3598. no_mem:
  3599. if (net_ratelimit()) {
  3600. PRINT_WARN("No memory for packet received on %s.\n",
  3601. QETH_CARD_IFNAME(card));
  3602. QETH_DBF_TEXT(TRACE, 2, "noskbmem");
  3603. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  3604. }
  3605. card->stats.rx_dropped++;
  3606. return NULL;
  3607. }
  3608. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3609. static void qeth_unregister_dbf_views(void)
  3610. {
  3611. int x;
  3612. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3613. debug_unregister(qeth_dbf[x].id);
  3614. qeth_dbf[x].id = NULL;
  3615. }
  3616. }
  3617. void qeth_dbf_longtext(enum qeth_dbf_names dbf_nix, int level, char *text, ...)
  3618. {
  3619. char dbf_txt_buf[32];
  3620. if (level > (qeth_dbf[dbf_nix].id)->level)
  3621. return;
  3622. snprintf(dbf_txt_buf, sizeof(dbf_txt_buf), text);
  3623. debug_text_event(qeth_dbf[dbf_nix].id, level, dbf_txt_buf);
  3624. }
  3625. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3626. static int qeth_register_dbf_views(void)
  3627. {
  3628. int ret;
  3629. int x;
  3630. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3631. /* register the areas */
  3632. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3633. qeth_dbf[x].pages,
  3634. qeth_dbf[x].areas,
  3635. qeth_dbf[x].len);
  3636. if (qeth_dbf[x].id == NULL) {
  3637. qeth_unregister_dbf_views();
  3638. return -ENOMEM;
  3639. }
  3640. /* register a view */
  3641. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3642. if (ret) {
  3643. qeth_unregister_dbf_views();
  3644. return ret;
  3645. }
  3646. /* set a passing level */
  3647. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3648. }
  3649. return 0;
  3650. }
  3651. int qeth_core_load_discipline(struct qeth_card *card,
  3652. enum qeth_discipline_id discipline)
  3653. {
  3654. int rc = 0;
  3655. switch (discipline) {
  3656. case QETH_DISCIPLINE_LAYER3:
  3657. card->discipline.ccwgdriver = try_then_request_module(
  3658. symbol_get(qeth_l3_ccwgroup_driver),
  3659. "qeth_l3");
  3660. break;
  3661. case QETH_DISCIPLINE_LAYER2:
  3662. card->discipline.ccwgdriver = try_then_request_module(
  3663. symbol_get(qeth_l2_ccwgroup_driver),
  3664. "qeth_l2");
  3665. break;
  3666. }
  3667. if (!card->discipline.ccwgdriver) {
  3668. PRINT_ERR("Support for discipline %d not present\n",
  3669. discipline);
  3670. rc = -EINVAL;
  3671. }
  3672. return rc;
  3673. }
  3674. void qeth_core_free_discipline(struct qeth_card *card)
  3675. {
  3676. if (card->options.layer2)
  3677. symbol_put(qeth_l2_ccwgroup_driver);
  3678. else
  3679. symbol_put(qeth_l3_ccwgroup_driver);
  3680. card->discipline.ccwgdriver = NULL;
  3681. }
  3682. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3683. {
  3684. struct qeth_card *card;
  3685. struct device *dev;
  3686. int rc;
  3687. unsigned long flags;
  3688. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3689. dev = &gdev->dev;
  3690. if (!get_device(dev))
  3691. return -ENODEV;
  3692. QETH_DBF_TEXT_(SETUP, 2, "%s", gdev->dev.bus_id);
  3693. card = qeth_alloc_card();
  3694. if (!card) {
  3695. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3696. rc = -ENOMEM;
  3697. goto err_dev;
  3698. }
  3699. card->read.ccwdev = gdev->cdev[0];
  3700. card->write.ccwdev = gdev->cdev[1];
  3701. card->data.ccwdev = gdev->cdev[2];
  3702. dev_set_drvdata(&gdev->dev, card);
  3703. card->gdev = gdev;
  3704. gdev->cdev[0]->handler = qeth_irq;
  3705. gdev->cdev[1]->handler = qeth_irq;
  3706. gdev->cdev[2]->handler = qeth_irq;
  3707. rc = qeth_determine_card_type(card);
  3708. if (rc) {
  3709. PRINT_WARN("%s: not a valid card type\n", __func__);
  3710. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3711. goto err_card;
  3712. }
  3713. rc = qeth_setup_card(card);
  3714. if (rc) {
  3715. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3716. goto err_card;
  3717. }
  3718. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3719. rc = qeth_core_create_osn_attributes(dev);
  3720. if (rc)
  3721. goto err_card;
  3722. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3723. if (rc) {
  3724. qeth_core_remove_osn_attributes(dev);
  3725. goto err_card;
  3726. }
  3727. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3728. if (rc) {
  3729. qeth_core_free_discipline(card);
  3730. qeth_core_remove_osn_attributes(dev);
  3731. goto err_card;
  3732. }
  3733. } else {
  3734. rc = qeth_core_create_device_attributes(dev);
  3735. if (rc)
  3736. goto err_card;
  3737. }
  3738. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3739. list_add_tail(&card->list, &qeth_core_card_list.list);
  3740. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3741. return 0;
  3742. err_card:
  3743. qeth_core_free_card(card);
  3744. err_dev:
  3745. put_device(dev);
  3746. return rc;
  3747. }
  3748. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3749. {
  3750. unsigned long flags;
  3751. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3752. if (card->discipline.ccwgdriver) {
  3753. card->discipline.ccwgdriver->remove(gdev);
  3754. qeth_core_free_discipline(card);
  3755. }
  3756. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3757. qeth_core_remove_osn_attributes(&gdev->dev);
  3758. } else {
  3759. qeth_core_remove_device_attributes(&gdev->dev);
  3760. }
  3761. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3762. list_del(&card->list);
  3763. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3764. qeth_core_free_card(card);
  3765. dev_set_drvdata(&gdev->dev, NULL);
  3766. put_device(&gdev->dev);
  3767. return;
  3768. }
  3769. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3770. {
  3771. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3772. int rc = 0;
  3773. int def_discipline;
  3774. if (!card->discipline.ccwgdriver) {
  3775. if (card->info.type == QETH_CARD_TYPE_IQD)
  3776. def_discipline = QETH_DISCIPLINE_LAYER3;
  3777. else
  3778. def_discipline = QETH_DISCIPLINE_LAYER2;
  3779. rc = qeth_core_load_discipline(card, def_discipline);
  3780. if (rc)
  3781. goto err;
  3782. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3783. if (rc)
  3784. goto err;
  3785. }
  3786. rc = card->discipline.ccwgdriver->set_online(gdev);
  3787. err:
  3788. return rc;
  3789. }
  3790. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3791. {
  3792. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3793. return card->discipline.ccwgdriver->set_offline(gdev);
  3794. }
  3795. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3796. {
  3797. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3798. if (card->discipline.ccwgdriver &&
  3799. card->discipline.ccwgdriver->shutdown)
  3800. card->discipline.ccwgdriver->shutdown(gdev);
  3801. }
  3802. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  3803. .owner = THIS_MODULE,
  3804. .name = "qeth",
  3805. .driver_id = 0xD8C5E3C8,
  3806. .probe = qeth_core_probe_device,
  3807. .remove = qeth_core_remove_device,
  3808. .set_online = qeth_core_set_online,
  3809. .set_offline = qeth_core_set_offline,
  3810. .shutdown = qeth_core_shutdown,
  3811. };
  3812. static ssize_t
  3813. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  3814. size_t count)
  3815. {
  3816. int err;
  3817. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  3818. qeth_core_ccwgroup_driver.driver_id);
  3819. if (err)
  3820. return err;
  3821. else
  3822. return count;
  3823. }
  3824. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  3825. static struct {
  3826. const char str[ETH_GSTRING_LEN];
  3827. } qeth_ethtool_stats_keys[] = {
  3828. /* 0 */{"rx skbs"},
  3829. {"rx buffers"},
  3830. {"tx skbs"},
  3831. {"tx buffers"},
  3832. {"tx skbs no packing"},
  3833. {"tx buffers no packing"},
  3834. {"tx skbs packing"},
  3835. {"tx buffers packing"},
  3836. {"tx sg skbs"},
  3837. {"tx sg frags"},
  3838. /* 10 */{"rx sg skbs"},
  3839. {"rx sg frags"},
  3840. {"rx sg page allocs"},
  3841. {"tx large kbytes"},
  3842. {"tx large count"},
  3843. {"tx pk state ch n->p"},
  3844. {"tx pk state ch p->n"},
  3845. {"tx pk watermark low"},
  3846. {"tx pk watermark high"},
  3847. {"queue 0 buffer usage"},
  3848. /* 20 */{"queue 1 buffer usage"},
  3849. {"queue 2 buffer usage"},
  3850. {"queue 3 buffer usage"},
  3851. {"rx handler time"},
  3852. {"rx handler count"},
  3853. {"rx do_QDIO time"},
  3854. {"rx do_QDIO count"},
  3855. {"tx handler time"},
  3856. {"tx handler count"},
  3857. {"tx time"},
  3858. /* 30 */{"tx count"},
  3859. {"tx do_QDIO time"},
  3860. {"tx do_QDIO count"},
  3861. };
  3862. int qeth_core_get_stats_count(struct net_device *dev)
  3863. {
  3864. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  3865. }
  3866. EXPORT_SYMBOL_GPL(qeth_core_get_stats_count);
  3867. void qeth_core_get_ethtool_stats(struct net_device *dev,
  3868. struct ethtool_stats *stats, u64 *data)
  3869. {
  3870. struct qeth_card *card = netdev_priv(dev);
  3871. data[0] = card->stats.rx_packets -
  3872. card->perf_stats.initial_rx_packets;
  3873. data[1] = card->perf_stats.bufs_rec;
  3874. data[2] = card->stats.tx_packets -
  3875. card->perf_stats.initial_tx_packets;
  3876. data[3] = card->perf_stats.bufs_sent;
  3877. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  3878. - card->perf_stats.skbs_sent_pack;
  3879. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  3880. data[6] = card->perf_stats.skbs_sent_pack;
  3881. data[7] = card->perf_stats.bufs_sent_pack;
  3882. data[8] = card->perf_stats.sg_skbs_sent;
  3883. data[9] = card->perf_stats.sg_frags_sent;
  3884. data[10] = card->perf_stats.sg_skbs_rx;
  3885. data[11] = card->perf_stats.sg_frags_rx;
  3886. data[12] = card->perf_stats.sg_alloc_page_rx;
  3887. data[13] = (card->perf_stats.large_send_bytes >> 10);
  3888. data[14] = card->perf_stats.large_send_cnt;
  3889. data[15] = card->perf_stats.sc_dp_p;
  3890. data[16] = card->perf_stats.sc_p_dp;
  3891. data[17] = QETH_LOW_WATERMARK_PACK;
  3892. data[18] = QETH_HIGH_WATERMARK_PACK;
  3893. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  3894. data[20] = (card->qdio.no_out_queues > 1) ?
  3895. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  3896. data[21] = (card->qdio.no_out_queues > 2) ?
  3897. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  3898. data[22] = (card->qdio.no_out_queues > 3) ?
  3899. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  3900. data[23] = card->perf_stats.inbound_time;
  3901. data[24] = card->perf_stats.inbound_cnt;
  3902. data[25] = card->perf_stats.inbound_do_qdio_time;
  3903. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  3904. data[27] = card->perf_stats.outbound_handler_time;
  3905. data[28] = card->perf_stats.outbound_handler_cnt;
  3906. data[29] = card->perf_stats.outbound_time;
  3907. data[30] = card->perf_stats.outbound_cnt;
  3908. data[31] = card->perf_stats.outbound_do_qdio_time;
  3909. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  3910. }
  3911. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  3912. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  3913. {
  3914. switch (stringset) {
  3915. case ETH_SS_STATS:
  3916. memcpy(data, &qeth_ethtool_stats_keys,
  3917. sizeof(qeth_ethtool_stats_keys));
  3918. break;
  3919. default:
  3920. WARN_ON(1);
  3921. break;
  3922. }
  3923. }
  3924. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  3925. void qeth_core_get_drvinfo(struct net_device *dev,
  3926. struct ethtool_drvinfo *info)
  3927. {
  3928. struct qeth_card *card = netdev_priv(dev);
  3929. if (card->options.layer2)
  3930. strcpy(info->driver, "qeth_l2");
  3931. else
  3932. strcpy(info->driver, "qeth_l3");
  3933. strcpy(info->version, "1.0");
  3934. strcpy(info->fw_version, card->info.mcl_level);
  3935. sprintf(info->bus_info, "%s/%s/%s",
  3936. CARD_RDEV_ID(card),
  3937. CARD_WDEV_ID(card),
  3938. CARD_DDEV_ID(card));
  3939. }
  3940. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  3941. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  3942. struct ethtool_cmd *ecmd)
  3943. {
  3944. struct qeth_card *card = netdev_priv(netdev);
  3945. enum qeth_link_types link_type;
  3946. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  3947. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  3948. else
  3949. link_type = card->info.link_type;
  3950. ecmd->transceiver = XCVR_INTERNAL;
  3951. ecmd->supported = SUPPORTED_Autoneg;
  3952. ecmd->advertising = ADVERTISED_Autoneg;
  3953. ecmd->duplex = DUPLEX_FULL;
  3954. ecmd->autoneg = AUTONEG_ENABLE;
  3955. switch (link_type) {
  3956. case QETH_LINK_TYPE_FAST_ETH:
  3957. case QETH_LINK_TYPE_LANE_ETH100:
  3958. ecmd->supported |= SUPPORTED_10baseT_Half |
  3959. SUPPORTED_10baseT_Full |
  3960. SUPPORTED_100baseT_Half |
  3961. SUPPORTED_100baseT_Full |
  3962. SUPPORTED_TP;
  3963. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3964. ADVERTISED_10baseT_Full |
  3965. ADVERTISED_100baseT_Half |
  3966. ADVERTISED_100baseT_Full |
  3967. ADVERTISED_TP;
  3968. ecmd->speed = SPEED_100;
  3969. ecmd->port = PORT_TP;
  3970. break;
  3971. case QETH_LINK_TYPE_GBIT_ETH:
  3972. case QETH_LINK_TYPE_LANE_ETH1000:
  3973. ecmd->supported |= SUPPORTED_10baseT_Half |
  3974. SUPPORTED_10baseT_Full |
  3975. SUPPORTED_100baseT_Half |
  3976. SUPPORTED_100baseT_Full |
  3977. SUPPORTED_1000baseT_Half |
  3978. SUPPORTED_1000baseT_Full |
  3979. SUPPORTED_FIBRE;
  3980. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3981. ADVERTISED_10baseT_Full |
  3982. ADVERTISED_100baseT_Half |
  3983. ADVERTISED_100baseT_Full |
  3984. ADVERTISED_1000baseT_Half |
  3985. ADVERTISED_1000baseT_Full |
  3986. ADVERTISED_FIBRE;
  3987. ecmd->speed = SPEED_1000;
  3988. ecmd->port = PORT_FIBRE;
  3989. break;
  3990. case QETH_LINK_TYPE_10GBIT_ETH:
  3991. ecmd->supported |= SUPPORTED_10baseT_Half |
  3992. SUPPORTED_10baseT_Full |
  3993. SUPPORTED_100baseT_Half |
  3994. SUPPORTED_100baseT_Full |
  3995. SUPPORTED_1000baseT_Half |
  3996. SUPPORTED_1000baseT_Full |
  3997. SUPPORTED_10000baseT_Full |
  3998. SUPPORTED_FIBRE;
  3999. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4000. ADVERTISED_10baseT_Full |
  4001. ADVERTISED_100baseT_Half |
  4002. ADVERTISED_100baseT_Full |
  4003. ADVERTISED_1000baseT_Half |
  4004. ADVERTISED_1000baseT_Full |
  4005. ADVERTISED_10000baseT_Full |
  4006. ADVERTISED_FIBRE;
  4007. ecmd->speed = SPEED_10000;
  4008. ecmd->port = PORT_FIBRE;
  4009. break;
  4010. default:
  4011. ecmd->supported |= SUPPORTED_10baseT_Half |
  4012. SUPPORTED_10baseT_Full |
  4013. SUPPORTED_TP;
  4014. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4015. ADVERTISED_10baseT_Full |
  4016. ADVERTISED_TP;
  4017. ecmd->speed = SPEED_10;
  4018. ecmd->port = PORT_TP;
  4019. }
  4020. return 0;
  4021. }
  4022. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4023. static int __init qeth_core_init(void)
  4024. {
  4025. int rc;
  4026. PRINT_INFO("loading core functions\n");
  4027. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4028. rwlock_init(&qeth_core_card_list.rwlock);
  4029. rc = qeth_register_dbf_views();
  4030. if (rc)
  4031. goto out_err;
  4032. rc = ccw_driver_register(&qeth_ccw_driver);
  4033. if (rc)
  4034. goto ccw_err;
  4035. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4036. if (rc)
  4037. goto ccwgroup_err;
  4038. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4039. &driver_attr_group);
  4040. if (rc)
  4041. goto driver_err;
  4042. qeth_core_root_dev = s390_root_dev_register("qeth");
  4043. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4044. if (rc)
  4045. goto register_err;
  4046. return 0;
  4047. register_err:
  4048. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4049. &driver_attr_group);
  4050. driver_err:
  4051. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4052. ccwgroup_err:
  4053. ccw_driver_unregister(&qeth_ccw_driver);
  4054. ccw_err:
  4055. qeth_unregister_dbf_views();
  4056. out_err:
  4057. PRINT_ERR("Initialization failed with code %d\n", rc);
  4058. return rc;
  4059. }
  4060. static void __exit qeth_core_exit(void)
  4061. {
  4062. s390_root_dev_unregister(qeth_core_root_dev);
  4063. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4064. &driver_attr_group);
  4065. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4066. ccw_driver_unregister(&qeth_ccw_driver);
  4067. qeth_unregister_dbf_views();
  4068. PRINT_INFO("core functions removed\n");
  4069. }
  4070. module_init(qeth_core_init);
  4071. module_exit(qeth_core_exit);
  4072. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4073. MODULE_DESCRIPTION("qeth core functions");
  4074. MODULE_LICENSE("GPL");