cm2xxx_3xxx.c 13 KB

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  1. /*
  2. * OMAP2/3 CM module functions
  3. *
  4. * Copyright (C) 2009 Nokia Corporation
  5. * Paul Walmsley
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/types.h>
  13. #include <linux/delay.h>
  14. #include <linux/spinlock.h>
  15. #include <linux/list.h>
  16. #include <linux/errno.h>
  17. #include <linux/err.h>
  18. #include <linux/io.h>
  19. #include <plat/common.h>
  20. #include "cm.h"
  21. #include "cm2xxx_3xxx.h"
  22. #include "cm-regbits-24xx.h"
  23. #include "cm-regbits-34xx.h"
  24. static const u8 cm_idlest_offs[] = {
  25. CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
  26. };
  27. u32 cm_read_mod_reg(s16 module, u16 idx)
  28. {
  29. return __raw_readl(cm_base + module + idx);
  30. }
  31. void cm_write_mod_reg(u32 val, s16 module, u16 idx)
  32. {
  33. __raw_writel(val, cm_base + module + idx);
  34. }
  35. /* Read-modify-write a register in a CM module. Caller must lock */
  36. u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
  37. {
  38. u32 v;
  39. v = cm_read_mod_reg(module, idx);
  40. v &= ~mask;
  41. v |= bits;
  42. cm_write_mod_reg(v, module, idx);
  43. return v;
  44. }
  45. u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
  46. {
  47. return cm_rmw_mod_reg_bits(bits, bits, module, idx);
  48. }
  49. u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
  50. {
  51. return cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
  52. }
  53. /**
  54. * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
  55. * @prcm_mod: PRCM module offset
  56. * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
  57. * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
  58. *
  59. * XXX document
  60. */
  61. int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
  62. {
  63. int ena = 0, i = 0;
  64. u8 cm_idlest_reg;
  65. u32 mask;
  66. if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs)))
  67. return -EINVAL;
  68. cm_idlest_reg = cm_idlest_offs[idlest_id - 1];
  69. mask = 1 << idlest_shift;
  70. if (cpu_is_omap24xx())
  71. ena = mask;
  72. else if (cpu_is_omap34xx())
  73. ena = 0;
  74. else
  75. BUG();
  76. omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
  77. MAX_MODULE_READY_TIME, i);
  78. return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
  79. }
  80. /*
  81. * Context save/restore code - OMAP3 only
  82. */
  83. #ifdef CONFIG_ARCH_OMAP3
  84. struct omap3_cm_regs {
  85. u32 iva2_cm_clksel1;
  86. u32 iva2_cm_clksel2;
  87. u32 cm_sysconfig;
  88. u32 sgx_cm_clksel;
  89. u32 dss_cm_clksel;
  90. u32 cam_cm_clksel;
  91. u32 per_cm_clksel;
  92. u32 emu_cm_clksel;
  93. u32 emu_cm_clkstctrl;
  94. u32 pll_cm_autoidle2;
  95. u32 pll_cm_clksel4;
  96. u32 pll_cm_clksel5;
  97. u32 pll_cm_clken2;
  98. u32 cm_polctrl;
  99. u32 iva2_cm_fclken;
  100. u32 iva2_cm_clken_pll;
  101. u32 core_cm_fclken1;
  102. u32 core_cm_fclken3;
  103. u32 sgx_cm_fclken;
  104. u32 wkup_cm_fclken;
  105. u32 dss_cm_fclken;
  106. u32 cam_cm_fclken;
  107. u32 per_cm_fclken;
  108. u32 usbhost_cm_fclken;
  109. u32 core_cm_iclken1;
  110. u32 core_cm_iclken2;
  111. u32 core_cm_iclken3;
  112. u32 sgx_cm_iclken;
  113. u32 wkup_cm_iclken;
  114. u32 dss_cm_iclken;
  115. u32 cam_cm_iclken;
  116. u32 per_cm_iclken;
  117. u32 usbhost_cm_iclken;
  118. u32 iva2_cm_autoidle2;
  119. u32 mpu_cm_autoidle2;
  120. u32 iva2_cm_clkstctrl;
  121. u32 mpu_cm_clkstctrl;
  122. u32 core_cm_clkstctrl;
  123. u32 sgx_cm_clkstctrl;
  124. u32 dss_cm_clkstctrl;
  125. u32 cam_cm_clkstctrl;
  126. u32 per_cm_clkstctrl;
  127. u32 neon_cm_clkstctrl;
  128. u32 usbhost_cm_clkstctrl;
  129. u32 core_cm_autoidle1;
  130. u32 core_cm_autoidle2;
  131. u32 core_cm_autoidle3;
  132. u32 wkup_cm_autoidle;
  133. u32 dss_cm_autoidle;
  134. u32 cam_cm_autoidle;
  135. u32 per_cm_autoidle;
  136. u32 usbhost_cm_autoidle;
  137. u32 sgx_cm_sleepdep;
  138. u32 dss_cm_sleepdep;
  139. u32 cam_cm_sleepdep;
  140. u32 per_cm_sleepdep;
  141. u32 usbhost_cm_sleepdep;
  142. u32 cm_clkout_ctrl;
  143. };
  144. static struct omap3_cm_regs cm_context;
  145. void omap3_cm_save_context(void)
  146. {
  147. cm_context.iva2_cm_clksel1 =
  148. cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
  149. cm_context.iva2_cm_clksel2 =
  150. cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
  151. cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
  152. cm_context.sgx_cm_clksel =
  153. cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
  154. cm_context.dss_cm_clksel =
  155. cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
  156. cm_context.cam_cm_clksel =
  157. cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
  158. cm_context.per_cm_clksel =
  159. cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
  160. cm_context.emu_cm_clksel =
  161. cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
  162. cm_context.emu_cm_clkstctrl =
  163. cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
  164. cm_context.pll_cm_autoidle2 =
  165. cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
  166. cm_context.pll_cm_clksel4 =
  167. cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
  168. cm_context.pll_cm_clksel5 =
  169. cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
  170. cm_context.pll_cm_clken2 =
  171. cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
  172. cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
  173. cm_context.iva2_cm_fclken =
  174. cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
  175. cm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
  176. OMAP3430_CM_CLKEN_PLL);
  177. cm_context.core_cm_fclken1 =
  178. cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  179. cm_context.core_cm_fclken3 =
  180. cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
  181. cm_context.sgx_cm_fclken =
  182. cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
  183. cm_context.wkup_cm_fclken =
  184. cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
  185. cm_context.dss_cm_fclken =
  186. cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
  187. cm_context.cam_cm_fclken =
  188. cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
  189. cm_context.per_cm_fclken =
  190. cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
  191. cm_context.usbhost_cm_fclken =
  192. cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
  193. cm_context.core_cm_iclken1 =
  194. cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
  195. cm_context.core_cm_iclken2 =
  196. cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
  197. cm_context.core_cm_iclken3 =
  198. cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
  199. cm_context.sgx_cm_iclken =
  200. cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
  201. cm_context.wkup_cm_iclken =
  202. cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
  203. cm_context.dss_cm_iclken =
  204. cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
  205. cm_context.cam_cm_iclken =
  206. cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
  207. cm_context.per_cm_iclken =
  208. cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
  209. cm_context.usbhost_cm_iclken =
  210. cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
  211. cm_context.iva2_cm_autoidle2 =
  212. cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
  213. cm_context.mpu_cm_autoidle2 =
  214. cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
  215. cm_context.iva2_cm_clkstctrl =
  216. cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
  217. cm_context.mpu_cm_clkstctrl =
  218. cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
  219. cm_context.core_cm_clkstctrl =
  220. cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
  221. cm_context.sgx_cm_clkstctrl =
  222. cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
  223. cm_context.dss_cm_clkstctrl =
  224. cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
  225. cm_context.cam_cm_clkstctrl =
  226. cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
  227. cm_context.per_cm_clkstctrl =
  228. cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
  229. cm_context.neon_cm_clkstctrl =
  230. cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
  231. cm_context.usbhost_cm_clkstctrl =
  232. cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
  233. cm_context.core_cm_autoidle1 =
  234. cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
  235. cm_context.core_cm_autoidle2 =
  236. cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
  237. cm_context.core_cm_autoidle3 =
  238. cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
  239. cm_context.wkup_cm_autoidle =
  240. cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
  241. cm_context.dss_cm_autoidle =
  242. cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
  243. cm_context.cam_cm_autoidle =
  244. cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
  245. cm_context.per_cm_autoidle =
  246. cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
  247. cm_context.usbhost_cm_autoidle =
  248. cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
  249. cm_context.sgx_cm_sleepdep =
  250. cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
  251. cm_context.dss_cm_sleepdep =
  252. cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
  253. cm_context.cam_cm_sleepdep =
  254. cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
  255. cm_context.per_cm_sleepdep =
  256. cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
  257. cm_context.usbhost_cm_sleepdep =
  258. cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
  259. cm_context.cm_clkout_ctrl =
  260. cm_read_mod_reg(OMAP3430_CCR_MOD, OMAP3_CM_CLKOUT_CTRL_OFFSET);
  261. }
  262. void omap3_cm_restore_context(void)
  263. {
  264. cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
  265. CM_CLKSEL1);
  266. cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
  267. CM_CLKSEL2);
  268. __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
  269. cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
  270. CM_CLKSEL);
  271. cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
  272. CM_CLKSEL);
  273. cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
  274. CM_CLKSEL);
  275. cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
  276. CM_CLKSEL);
  277. cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
  278. CM_CLKSEL1);
  279. cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
  280. OMAP2_CM_CLKSTCTRL);
  281. cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
  282. CM_AUTOIDLE2);
  283. cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
  284. OMAP3430ES2_CM_CLKSEL4);
  285. cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
  286. OMAP3430ES2_CM_CLKSEL5);
  287. cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
  288. OMAP3430ES2_CM_CLKEN2);
  289. __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
  290. cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
  291. CM_FCLKEN);
  292. cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
  293. OMAP3430_CM_CLKEN_PLL);
  294. cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);
  295. cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
  296. OMAP3430ES2_CM_FCLKEN3);
  297. cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
  298. CM_FCLKEN);
  299. cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
  300. cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
  301. CM_FCLKEN);
  302. cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
  303. CM_FCLKEN);
  304. cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
  305. CM_FCLKEN);
  306. cm_write_mod_reg(cm_context.usbhost_cm_fclken,
  307. OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
  308. cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);
  309. cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);
  310. cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);
  311. cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
  312. CM_ICLKEN);
  313. cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
  314. cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
  315. CM_ICLKEN);
  316. cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
  317. CM_ICLKEN);
  318. cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
  319. CM_ICLKEN);
  320. cm_write_mod_reg(cm_context.usbhost_cm_iclken,
  321. OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
  322. cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
  323. CM_AUTOIDLE2);
  324. cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
  325. cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
  326. OMAP2_CM_CLKSTCTRL);
  327. cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
  328. OMAP2_CM_CLKSTCTRL);
  329. cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
  330. OMAP2_CM_CLKSTCTRL);
  331. cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
  332. OMAP2_CM_CLKSTCTRL);
  333. cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
  334. OMAP2_CM_CLKSTCTRL);
  335. cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
  336. OMAP2_CM_CLKSTCTRL);
  337. cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
  338. OMAP2_CM_CLKSTCTRL);
  339. cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
  340. OMAP2_CM_CLKSTCTRL);
  341. cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
  342. OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
  343. cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
  344. CM_AUTOIDLE1);
  345. cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
  346. CM_AUTOIDLE2);
  347. cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
  348. CM_AUTOIDLE3);
  349. cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);
  350. cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
  351. CM_AUTOIDLE);
  352. cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
  353. CM_AUTOIDLE);
  354. cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
  355. CM_AUTOIDLE);
  356. cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
  357. OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
  358. cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
  359. OMAP3430_CM_SLEEPDEP);
  360. cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
  361. OMAP3430_CM_SLEEPDEP);
  362. cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
  363. OMAP3430_CM_SLEEPDEP);
  364. cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
  365. OMAP3430_CM_SLEEPDEP);
  366. cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
  367. OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
  368. cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
  369. OMAP3_CM_CLKOUT_CTRL_OFFSET);
  370. }
  371. #endif