adg.c 4.7 KB

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  1. /*
  2. * Helper routines for R-Car sound ADG.
  3. *
  4. * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/sh_clk.h>
  11. #include <mach/clock.h>
  12. #include "rsnd.h"
  13. #define CLKA 0
  14. #define CLKB 1
  15. #define CLKC 2
  16. #define CLKI 3
  17. #define CLKMAX 4
  18. struct rsnd_adg {
  19. struct clk *clk[CLKMAX];
  20. int rate_of_441khz_div_6;
  21. int rate_of_48khz_div_6;
  22. };
  23. #define for_each_rsnd_clk(pos, adg, i) \
  24. for (i = 0, (pos) = adg->clk[i]; \
  25. i < CLKMAX; \
  26. i++, (pos) = adg->clk[i])
  27. #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
  28. static enum rsnd_reg rsnd_adg_ssi_reg_get(int id)
  29. {
  30. enum rsnd_reg reg;
  31. /*
  32. * SSI 8 is not connected to ADG.
  33. * it works with SSI 7
  34. */
  35. if (id == 8)
  36. return RSND_REG_MAX;
  37. if (0 <= id && id <= 3)
  38. reg = RSND_REG_AUDIO_CLK_SEL0;
  39. else if (4 <= id && id <= 7)
  40. reg = RSND_REG_AUDIO_CLK_SEL1;
  41. else
  42. reg = RSND_REG_AUDIO_CLK_SEL2;
  43. return reg;
  44. }
  45. int rsnd_adg_ssi_clk_stop(struct rsnd_mod *mod)
  46. {
  47. struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
  48. enum rsnd_reg reg;
  49. int id;
  50. /*
  51. * "mod" = "ssi" here.
  52. * we can get "ssi id" from mod
  53. */
  54. id = rsnd_mod_id(mod);
  55. reg = rsnd_adg_ssi_reg_get(id);
  56. rsnd_write(priv, mod, reg, 0);
  57. return 0;
  58. }
  59. int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate)
  60. {
  61. struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
  62. struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
  63. struct device *dev = rsnd_priv_to_dev(priv);
  64. struct clk *clk;
  65. enum rsnd_reg reg;
  66. int id, shift, i;
  67. u32 data;
  68. int sel_table[] = {
  69. [CLKA] = 0x1,
  70. [CLKB] = 0x2,
  71. [CLKC] = 0x3,
  72. [CLKI] = 0x0,
  73. };
  74. dev_dbg(dev, "request clock = %d\n", rate);
  75. /*
  76. * find suitable clock from
  77. * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
  78. */
  79. data = 0;
  80. for_each_rsnd_clk(clk, adg, i) {
  81. if (rate == clk_get_rate(clk)) {
  82. data = sel_table[i];
  83. goto found_clock;
  84. }
  85. }
  86. /*
  87. * find 1/6 clock from BRGA/BRGB
  88. */
  89. if (rate == adg->rate_of_441khz_div_6) {
  90. data = 0x10;
  91. goto found_clock;
  92. }
  93. if (rate == adg->rate_of_48khz_div_6) {
  94. data = 0x20;
  95. goto found_clock;
  96. }
  97. return -EIO;
  98. found_clock:
  99. /*
  100. * This "mod" = "ssi" here.
  101. * we can get "ssi id" from mod
  102. */
  103. id = rsnd_mod_id(mod);
  104. reg = rsnd_adg_ssi_reg_get(id);
  105. dev_dbg(dev, "ADG: ssi%d selects clk%d = %d", id, i, rate);
  106. /*
  107. * Enable SSIx clock
  108. */
  109. shift = (id % 4) * 8;
  110. rsnd_bset(priv, mod, reg,
  111. 0xFF << shift,
  112. data << shift);
  113. return 0;
  114. }
  115. static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg)
  116. {
  117. struct clk *clk;
  118. unsigned long rate;
  119. u32 ckr;
  120. int i;
  121. int brg_table[] = {
  122. [CLKA] = 0x0,
  123. [CLKB] = 0x1,
  124. [CLKC] = 0x4,
  125. [CLKI] = 0x2,
  126. };
  127. /*
  128. * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
  129. * have 44.1kHz or 48kHz base clocks for now.
  130. *
  131. * SSI itself can divide parent clock by 1/1 - 1/16
  132. * So, BRGA outputs 44.1kHz base parent clock 1/32,
  133. * and, BRGB outputs 48.0kHz base parent clock 1/32 here.
  134. * see
  135. * rsnd_adg_ssi_clk_try_start()
  136. */
  137. ckr = 0;
  138. adg->rate_of_441khz_div_6 = 0;
  139. adg->rate_of_48khz_div_6 = 0;
  140. for_each_rsnd_clk(clk, adg, i) {
  141. rate = clk_get_rate(clk);
  142. if (0 == rate) /* not used */
  143. continue;
  144. /* RBGA */
  145. if (!adg->rate_of_441khz_div_6 && (0 == rate % 44100)) {
  146. adg->rate_of_441khz_div_6 = rate / 6;
  147. ckr |= brg_table[i] << 20;
  148. }
  149. /* RBGB */
  150. if (!adg->rate_of_48khz_div_6 && (0 == rate % 48000)) {
  151. adg->rate_of_48khz_div_6 = rate / 6;
  152. ckr |= brg_table[i] << 16;
  153. }
  154. }
  155. rsnd_priv_bset(priv, SSICKR, 0x00FF0000, ckr);
  156. rsnd_priv_write(priv, BRRA, 0x00000002); /* 1/6 */
  157. rsnd_priv_write(priv, BRRB, 0x00000002); /* 1/6 */
  158. }
  159. int rsnd_adg_probe(struct platform_device *pdev,
  160. struct rcar_snd_info *info,
  161. struct rsnd_priv *priv)
  162. {
  163. struct rsnd_adg *adg;
  164. struct device *dev = rsnd_priv_to_dev(priv);
  165. struct clk *clk;
  166. int i;
  167. adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
  168. if (!adg) {
  169. dev_err(dev, "ADG allocate failed\n");
  170. return -ENOMEM;
  171. }
  172. adg->clk[CLKA] = clk_get(NULL, "audio_clk_a");
  173. adg->clk[CLKB] = clk_get(NULL, "audio_clk_b");
  174. adg->clk[CLKC] = clk_get(NULL, "audio_clk_c");
  175. adg->clk[CLKI] = clk_get(NULL, "audio_clk_internal");
  176. for_each_rsnd_clk(clk, adg, i) {
  177. if (IS_ERR(clk)) {
  178. dev_err(dev, "Audio clock failed\n");
  179. return -EIO;
  180. }
  181. }
  182. rsnd_adg_ssi_clk_init(priv, adg);
  183. priv->adg = adg;
  184. dev_dbg(dev, "adg probed\n");
  185. return 0;
  186. }
  187. void rsnd_adg_remove(struct platform_device *pdev,
  188. struct rsnd_priv *priv)
  189. {
  190. struct rsnd_adg *adg = priv->adg;
  191. struct clk *clk;
  192. int i;
  193. for_each_rsnd_clk(clk, adg, i)
  194. clk_put(clk);
  195. }