ep93xx-i2s.c 11 KB

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  1. /*
  2. * linux/sound/soc/ep93xx-i2s.c
  3. * EP93xx I2S driver
  4. *
  5. * Copyright (C) 2010 Ryan Mallon
  6. *
  7. * Based on the original driver by:
  8. * Copyright (C) 2007 Chase Douglas <chasedouglas@gmail>
  9. * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. *
  15. */
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/slab.h>
  19. #include <linux/clk.h>
  20. #include <linux/io.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/initval.h>
  25. #include <sound/soc.h>
  26. #include <mach/hardware.h>
  27. #include <mach/ep93xx-regs.h>
  28. #include <linux/platform_data/dma-ep93xx.h>
  29. #define EP93XX_I2S_TXCLKCFG 0x00
  30. #define EP93XX_I2S_RXCLKCFG 0x04
  31. #define EP93XX_I2S_GLCTRL 0x0C
  32. #define EP93XX_I2S_TXLINCTRLDATA 0x28
  33. #define EP93XX_I2S_TXCTRL 0x2C
  34. #define EP93XX_I2S_TXWRDLEN 0x30
  35. #define EP93XX_I2S_TX0EN 0x34
  36. #define EP93XX_I2S_RXLINCTRLDATA 0x58
  37. #define EP93XX_I2S_RXCTRL 0x5C
  38. #define EP93XX_I2S_RXWRDLEN 0x60
  39. #define EP93XX_I2S_RX0EN 0x64
  40. #define EP93XX_I2S_WRDLEN_16 (0 << 0)
  41. #define EP93XX_I2S_WRDLEN_24 (1 << 0)
  42. #define EP93XX_I2S_WRDLEN_32 (2 << 0)
  43. #define EP93XX_I2S_LINCTRLDATA_R_JUST (1 << 2) /* Right justify */
  44. #define EP93XX_I2S_CLKCFG_LRS (1 << 0) /* lrclk polarity */
  45. #define EP93XX_I2S_CLKCFG_CKP (1 << 1) /* Bit clock polarity */
  46. #define EP93XX_I2S_CLKCFG_REL (1 << 2) /* First bit transition */
  47. #define EP93XX_I2S_CLKCFG_MASTER (1 << 3) /* Master mode */
  48. #define EP93XX_I2S_CLKCFG_NBCG (1 << 4) /* Not bit clock gating */
  49. struct ep93xx_i2s_info {
  50. struct clk *mclk;
  51. struct clk *sclk;
  52. struct clk *lrclk;
  53. void __iomem *regs;
  54. };
  55. static struct ep93xx_dma_data ep93xx_i2s_dma_data[] = {
  56. [SNDRV_PCM_STREAM_PLAYBACK] = {
  57. .name = "i2s-pcm-out",
  58. .port = EP93XX_DMA_I2S1,
  59. .direction = DMA_MEM_TO_DEV,
  60. },
  61. [SNDRV_PCM_STREAM_CAPTURE] = {
  62. .name = "i2s-pcm-in",
  63. .port = EP93XX_DMA_I2S1,
  64. .direction = DMA_DEV_TO_MEM,
  65. },
  66. };
  67. static inline void ep93xx_i2s_write_reg(struct ep93xx_i2s_info *info,
  68. unsigned reg, unsigned val)
  69. {
  70. __raw_writel(val, info->regs + reg);
  71. }
  72. static inline unsigned ep93xx_i2s_read_reg(struct ep93xx_i2s_info *info,
  73. unsigned reg)
  74. {
  75. return __raw_readl(info->regs + reg);
  76. }
  77. static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream)
  78. {
  79. unsigned base_reg;
  80. int i;
  81. if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
  82. (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
  83. /* Enable clocks */
  84. clk_enable(info->mclk);
  85. clk_enable(info->sclk);
  86. clk_enable(info->lrclk);
  87. /* Enable i2s */
  88. ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 1);
  89. }
  90. /* Enable fifos */
  91. if (stream == SNDRV_PCM_STREAM_PLAYBACK)
  92. base_reg = EP93XX_I2S_TX0EN;
  93. else
  94. base_reg = EP93XX_I2S_RX0EN;
  95. for (i = 0; i < 3; i++)
  96. ep93xx_i2s_write_reg(info, base_reg + (i * 4), 1);
  97. }
  98. static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream)
  99. {
  100. unsigned base_reg;
  101. int i;
  102. /* Disable fifos */
  103. if (stream == SNDRV_PCM_STREAM_PLAYBACK)
  104. base_reg = EP93XX_I2S_TX0EN;
  105. else
  106. base_reg = EP93XX_I2S_RX0EN;
  107. for (i = 0; i < 3; i++)
  108. ep93xx_i2s_write_reg(info, base_reg + (i * 4), 0);
  109. if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
  110. (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
  111. /* Disable i2s */
  112. ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 0);
  113. /* Disable clocks */
  114. clk_disable(info->lrclk);
  115. clk_disable(info->sclk);
  116. clk_disable(info->mclk);
  117. }
  118. }
  119. static int ep93xx_i2s_dai_probe(struct snd_soc_dai *dai)
  120. {
  121. dai->playback_dma_data = &ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_PLAYBACK];
  122. dai->capture_dma_data = &ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_CAPTURE];
  123. return 0;
  124. }
  125. static void ep93xx_i2s_shutdown(struct snd_pcm_substream *substream,
  126. struct snd_soc_dai *dai)
  127. {
  128. struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
  129. ep93xx_i2s_disable(info, substream->stream);
  130. }
  131. static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
  132. unsigned int fmt)
  133. {
  134. struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
  135. unsigned int clk_cfg, lin_ctrl;
  136. clk_cfg = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG);
  137. lin_ctrl = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXLINCTRLDATA);
  138. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  139. case SND_SOC_DAIFMT_I2S:
  140. clk_cfg |= EP93XX_I2S_CLKCFG_REL;
  141. lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
  142. break;
  143. case SND_SOC_DAIFMT_LEFT_J:
  144. clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
  145. lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
  146. break;
  147. case SND_SOC_DAIFMT_RIGHT_J:
  148. clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
  149. lin_ctrl |= EP93XX_I2S_LINCTRLDATA_R_JUST;
  150. break;
  151. default:
  152. return -EINVAL;
  153. }
  154. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  155. case SND_SOC_DAIFMT_CBS_CFS:
  156. /* CPU is master */
  157. clk_cfg |= EP93XX_I2S_CLKCFG_MASTER;
  158. break;
  159. case SND_SOC_DAIFMT_CBM_CFM:
  160. /* Codec is master */
  161. clk_cfg &= ~EP93XX_I2S_CLKCFG_MASTER;
  162. break;
  163. default:
  164. return -EINVAL;
  165. }
  166. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  167. case SND_SOC_DAIFMT_NB_NF:
  168. /* Negative bit clock, lrclk low on left word */
  169. clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_REL);
  170. break;
  171. case SND_SOC_DAIFMT_NB_IF:
  172. /* Negative bit clock, lrclk low on right word */
  173. clk_cfg &= ~EP93XX_I2S_CLKCFG_CKP;
  174. clk_cfg |= EP93XX_I2S_CLKCFG_REL;
  175. break;
  176. case SND_SOC_DAIFMT_IB_NF:
  177. /* Positive bit clock, lrclk low on left word */
  178. clk_cfg |= EP93XX_I2S_CLKCFG_CKP;
  179. clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
  180. break;
  181. case SND_SOC_DAIFMT_IB_IF:
  182. /* Positive bit clock, lrclk low on right word */
  183. clk_cfg |= EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_REL;
  184. break;
  185. }
  186. /* Write new register values */
  187. ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg);
  188. ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg);
  189. ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, lin_ctrl);
  190. ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, lin_ctrl);
  191. return 0;
  192. }
  193. static int ep93xx_i2s_hw_params(struct snd_pcm_substream *substream,
  194. struct snd_pcm_hw_params *params,
  195. struct snd_soc_dai *dai)
  196. {
  197. struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
  198. unsigned word_len, div, sdiv, lrdiv;
  199. int err;
  200. switch (params_format(params)) {
  201. case SNDRV_PCM_FORMAT_S16_LE:
  202. word_len = EP93XX_I2S_WRDLEN_16;
  203. break;
  204. case SNDRV_PCM_FORMAT_S24_LE:
  205. word_len = EP93XX_I2S_WRDLEN_24;
  206. break;
  207. case SNDRV_PCM_FORMAT_S32_LE:
  208. word_len = EP93XX_I2S_WRDLEN_32;
  209. break;
  210. default:
  211. return -EINVAL;
  212. }
  213. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  214. ep93xx_i2s_write_reg(info, EP93XX_I2S_TXWRDLEN, word_len);
  215. else
  216. ep93xx_i2s_write_reg(info, EP93XX_I2S_RXWRDLEN, word_len);
  217. /*
  218. * EP93xx I2S module can be setup so SCLK / LRCLK value can be
  219. * 32, 64, 128. MCLK / SCLK value can be 2 and 4.
  220. * We set LRCLK equal to `rate' and minimum SCLK / LRCLK
  221. * value is 64, because our sample size is 32 bit * 2 channels.
  222. * I2S standard permits us to transmit more bits than
  223. * the codec uses.
  224. */
  225. div = clk_get_rate(info->mclk) / params_rate(params);
  226. sdiv = 4;
  227. if (div > (256 + 512) / 2) {
  228. lrdiv = 128;
  229. } else {
  230. lrdiv = 64;
  231. if (div < (128 + 256) / 2)
  232. sdiv = 2;
  233. }
  234. err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv);
  235. if (err)
  236. return err;
  237. err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv);
  238. if (err)
  239. return err;
  240. ep93xx_i2s_enable(info, substream->stream);
  241. return 0;
  242. }
  243. static int ep93xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
  244. unsigned int freq, int dir)
  245. {
  246. struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
  247. if (dir == SND_SOC_CLOCK_IN || clk_id != 0)
  248. return -EINVAL;
  249. return clk_set_rate(info->mclk, freq);
  250. }
  251. #ifdef CONFIG_PM
  252. static int ep93xx_i2s_suspend(struct snd_soc_dai *dai)
  253. {
  254. struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
  255. if (!dai->active)
  256. return 0;
  257. ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_PLAYBACK);
  258. ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_CAPTURE);
  259. return 0;
  260. }
  261. static int ep93xx_i2s_resume(struct snd_soc_dai *dai)
  262. {
  263. struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
  264. if (!dai->active)
  265. return 0;
  266. ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_PLAYBACK);
  267. ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_CAPTURE);
  268. return 0;
  269. }
  270. #else
  271. #define ep93xx_i2s_suspend NULL
  272. #define ep93xx_i2s_resume NULL
  273. #endif
  274. static const struct snd_soc_dai_ops ep93xx_i2s_dai_ops = {
  275. .shutdown = ep93xx_i2s_shutdown,
  276. .hw_params = ep93xx_i2s_hw_params,
  277. .set_sysclk = ep93xx_i2s_set_sysclk,
  278. .set_fmt = ep93xx_i2s_set_dai_fmt,
  279. };
  280. #define EP93XX_I2S_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
  281. static struct snd_soc_dai_driver ep93xx_i2s_dai = {
  282. .symmetric_rates= 1,
  283. .probe = ep93xx_i2s_dai_probe,
  284. .suspend = ep93xx_i2s_suspend,
  285. .resume = ep93xx_i2s_resume,
  286. .playback = {
  287. .channels_min = 2,
  288. .channels_max = 2,
  289. .rates = SNDRV_PCM_RATE_8000_192000,
  290. .formats = EP93XX_I2S_FORMATS,
  291. },
  292. .capture = {
  293. .channels_min = 2,
  294. .channels_max = 2,
  295. .rates = SNDRV_PCM_RATE_8000_192000,
  296. .formats = EP93XX_I2S_FORMATS,
  297. },
  298. .ops = &ep93xx_i2s_dai_ops,
  299. };
  300. static const struct snd_soc_component_driver ep93xx_i2s_component = {
  301. .name = "ep93xx-i2s",
  302. };
  303. static int ep93xx_i2s_probe(struct platform_device *pdev)
  304. {
  305. struct ep93xx_i2s_info *info;
  306. struct resource *res;
  307. int err;
  308. info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
  309. if (!info)
  310. return -ENOMEM;
  311. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  312. info->regs = devm_ioremap_resource(&pdev->dev, res);
  313. if (IS_ERR(info->regs))
  314. return PTR_ERR(info->regs);
  315. info->mclk = clk_get(&pdev->dev, "mclk");
  316. if (IS_ERR(info->mclk)) {
  317. err = PTR_ERR(info->mclk);
  318. goto fail;
  319. }
  320. info->sclk = clk_get(&pdev->dev, "sclk");
  321. if (IS_ERR(info->sclk)) {
  322. err = PTR_ERR(info->sclk);
  323. goto fail_put_mclk;
  324. }
  325. info->lrclk = clk_get(&pdev->dev, "lrclk");
  326. if (IS_ERR(info->lrclk)) {
  327. err = PTR_ERR(info->lrclk);
  328. goto fail_put_sclk;
  329. }
  330. dev_set_drvdata(&pdev->dev, info);
  331. err = snd_soc_register_component(&pdev->dev, &ep93xx_i2s_component,
  332. &ep93xx_i2s_dai, 1);
  333. if (err)
  334. goto fail_put_lrclk;
  335. return 0;
  336. fail_put_lrclk:
  337. clk_put(info->lrclk);
  338. fail_put_sclk:
  339. clk_put(info->sclk);
  340. fail_put_mclk:
  341. clk_put(info->mclk);
  342. fail:
  343. return err;
  344. }
  345. static int ep93xx_i2s_remove(struct platform_device *pdev)
  346. {
  347. struct ep93xx_i2s_info *info = dev_get_drvdata(&pdev->dev);
  348. snd_soc_unregister_component(&pdev->dev);
  349. clk_put(info->lrclk);
  350. clk_put(info->sclk);
  351. clk_put(info->mclk);
  352. return 0;
  353. }
  354. static struct platform_driver ep93xx_i2s_driver = {
  355. .probe = ep93xx_i2s_probe,
  356. .remove = ep93xx_i2s_remove,
  357. .driver = {
  358. .name = "ep93xx-i2s",
  359. .owner = THIS_MODULE,
  360. },
  361. };
  362. module_platform_driver(ep93xx_i2s_driver);
  363. MODULE_ALIAS("platform:ep93xx-i2s");
  364. MODULE_AUTHOR("Ryan Mallon");
  365. MODULE_DESCRIPTION("EP93XX I2S driver");
  366. MODULE_LICENSE("GPL");