s3c2410_wdt.c 14 KB

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  1. /* linux/drivers/char/watchdog/s3c2410_wdt.c
  2. *
  3. * Copyright (c) 2004 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2410 Watchdog Timer Support
  7. *
  8. * Based on, softdog.c by Alan Cox,
  9. * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. */
  25. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  26. #include <linux/module.h>
  27. #include <linux/moduleparam.h>
  28. #include <linux/types.h>
  29. #include <linux/timer.h>
  30. #include <linux/miscdevice.h> /* for MODULE_ALIAS_MISCDEV */
  31. #include <linux/watchdog.h>
  32. #include <linux/init.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/interrupt.h>
  35. #include <linux/clk.h>
  36. #include <linux/uaccess.h>
  37. #include <linux/io.h>
  38. #include <linux/cpufreq.h>
  39. #include <linux/slab.h>
  40. #include <linux/err.h>
  41. #include <linux/of.h>
  42. #define S3C2410_WTCON 0x00
  43. #define S3C2410_WTDAT 0x04
  44. #define S3C2410_WTCNT 0x08
  45. #define S3C2410_WTCON_RSTEN (1 << 0)
  46. #define S3C2410_WTCON_INTEN (1 << 2)
  47. #define S3C2410_WTCON_ENABLE (1 << 5)
  48. #define S3C2410_WTCON_DIV16 (0 << 3)
  49. #define S3C2410_WTCON_DIV32 (1 << 3)
  50. #define S3C2410_WTCON_DIV64 (2 << 3)
  51. #define S3C2410_WTCON_DIV128 (3 << 3)
  52. #define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
  53. #define S3C2410_WTCON_PRESCALE_MASK (0xff << 8)
  54. #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0)
  55. #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
  56. static bool nowayout = WATCHDOG_NOWAYOUT;
  57. static int tmr_margin;
  58. static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT;
  59. static int soft_noboot;
  60. static int debug;
  61. module_param(tmr_margin, int, 0);
  62. module_param(tmr_atboot, int, 0);
  63. module_param(nowayout, bool, 0);
  64. module_param(soft_noboot, int, 0);
  65. module_param(debug, int, 0);
  66. MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
  67. __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")");
  68. MODULE_PARM_DESC(tmr_atboot,
  69. "Watchdog is started at boot time if set to 1, default="
  70. __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
  71. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  72. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  73. MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, "
  74. "0 to reboot (default 0)");
  75. MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)");
  76. struct s3c2410_wdt {
  77. struct device *dev;
  78. struct clk *clock;
  79. void __iomem *reg_base;
  80. unsigned int count;
  81. spinlock_t lock;
  82. unsigned long wtcon_save;
  83. unsigned long wtdat_save;
  84. struct watchdog_device wdt_device;
  85. struct notifier_block freq_transition;
  86. };
  87. /* watchdog control routines */
  88. #define DBG(fmt, ...) \
  89. do { \
  90. if (debug) \
  91. pr_info(fmt, ##__VA_ARGS__); \
  92. } while (0)
  93. /* functions */
  94. static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb)
  95. {
  96. return container_of(nb, struct s3c2410_wdt, freq_transition);
  97. }
  98. static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
  99. {
  100. struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
  101. spin_lock(&wdt->lock);
  102. writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
  103. spin_unlock(&wdt->lock);
  104. return 0;
  105. }
  106. static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt)
  107. {
  108. unsigned long wtcon;
  109. wtcon = readl(wdt->reg_base + S3C2410_WTCON);
  110. wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
  111. writel(wtcon, wdt->reg_base + S3C2410_WTCON);
  112. }
  113. static int s3c2410wdt_stop(struct watchdog_device *wdd)
  114. {
  115. struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
  116. spin_lock(&wdt->lock);
  117. __s3c2410wdt_stop(wdt);
  118. spin_unlock(&wdt->lock);
  119. return 0;
  120. }
  121. static int s3c2410wdt_start(struct watchdog_device *wdd)
  122. {
  123. unsigned long wtcon;
  124. struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
  125. spin_lock(&wdt->lock);
  126. __s3c2410wdt_stop(wdt);
  127. wtcon = readl(wdt->reg_base + S3C2410_WTCON);
  128. wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
  129. if (soft_noboot) {
  130. wtcon |= S3C2410_WTCON_INTEN;
  131. wtcon &= ~S3C2410_WTCON_RSTEN;
  132. } else {
  133. wtcon &= ~S3C2410_WTCON_INTEN;
  134. wtcon |= S3C2410_WTCON_RSTEN;
  135. }
  136. DBG("%s: count=0x%08x, wtcon=%08lx\n",
  137. __func__, wdt->count, wtcon);
  138. writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
  139. writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
  140. writel(wtcon, wdt->reg_base + S3C2410_WTCON);
  141. spin_unlock(&wdt->lock);
  142. return 0;
  143. }
  144. static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt)
  145. {
  146. return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
  147. }
  148. static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout)
  149. {
  150. struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
  151. unsigned long freq = clk_get_rate(wdt->clock);
  152. unsigned int count;
  153. unsigned int divisor = 1;
  154. unsigned long wtcon;
  155. if (timeout < 1)
  156. return -EINVAL;
  157. freq /= 128;
  158. count = timeout * freq;
  159. DBG("%s: count=%d, timeout=%d, freq=%lu\n",
  160. __func__, count, timeout, freq);
  161. /* if the count is bigger than the watchdog register,
  162. then work out what we need to do (and if) we can
  163. actually make this value
  164. */
  165. if (count >= 0x10000) {
  166. for (divisor = 1; divisor <= 0x100; divisor++) {
  167. if ((count / divisor) < 0x10000)
  168. break;
  169. }
  170. if ((count / divisor) >= 0x10000) {
  171. dev_err(wdt->dev, "timeout %d too big\n", timeout);
  172. return -EINVAL;
  173. }
  174. }
  175. DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n",
  176. __func__, timeout, divisor, count, count/divisor);
  177. count /= divisor;
  178. wdt->count = count;
  179. /* update the pre-scaler */
  180. wtcon = readl(wdt->reg_base + S3C2410_WTCON);
  181. wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
  182. wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
  183. writel(count, wdt->reg_base + S3C2410_WTDAT);
  184. writel(wtcon, wdt->reg_base + S3C2410_WTCON);
  185. wdd->timeout = (count * divisor) / freq;
  186. return 0;
  187. }
  188. #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
  189. static const struct watchdog_info s3c2410_wdt_ident = {
  190. .options = OPTIONS,
  191. .firmware_version = 0,
  192. .identity = "S3C2410 Watchdog",
  193. };
  194. static struct watchdog_ops s3c2410wdt_ops = {
  195. .owner = THIS_MODULE,
  196. .start = s3c2410wdt_start,
  197. .stop = s3c2410wdt_stop,
  198. .ping = s3c2410wdt_keepalive,
  199. .set_timeout = s3c2410wdt_set_heartbeat,
  200. };
  201. static struct watchdog_device s3c2410_wdd = {
  202. .info = &s3c2410_wdt_ident,
  203. .ops = &s3c2410wdt_ops,
  204. .timeout = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME,
  205. };
  206. /* interrupt handler code */
  207. static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
  208. {
  209. struct s3c2410_wdt *wdt = platform_get_drvdata(param);
  210. dev_info(wdt->dev, "watchdog timer expired (irq)\n");
  211. s3c2410wdt_keepalive(&wdt->wdt_device);
  212. return IRQ_HANDLED;
  213. }
  214. #ifdef CONFIG_CPU_FREQ
  215. static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
  216. unsigned long val, void *data)
  217. {
  218. int ret;
  219. struct s3c2410_wdt *wdt = freq_to_wdt(nb);
  220. if (!s3c2410wdt_is_running(wdt))
  221. goto done;
  222. if (val == CPUFREQ_PRECHANGE) {
  223. /* To ensure that over the change we don't cause the
  224. * watchdog to trigger, we perform an keep-alive if
  225. * the watchdog is running.
  226. */
  227. s3c2410wdt_keepalive(&wdt->wdt_device);
  228. } else if (val == CPUFREQ_POSTCHANGE) {
  229. s3c2410wdt_stop(&wdt->wdt_device);
  230. ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
  231. wdt->wdt_device.timeout);
  232. if (ret >= 0)
  233. s3c2410wdt_start(&wdt->wdt_device);
  234. else
  235. goto err;
  236. }
  237. done:
  238. return 0;
  239. err:
  240. dev_err(wdt->dev, "cannot set new value for timeout %d\n",
  241. wdt->wdt_device.timeout);
  242. return ret;
  243. }
  244. static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
  245. {
  246. wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
  247. return cpufreq_register_notifier(&wdt->freq_transition,
  248. CPUFREQ_TRANSITION_NOTIFIER);
  249. }
  250. static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
  251. {
  252. wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
  253. cpufreq_unregister_notifier(&wdt->freq_transition,
  254. CPUFREQ_TRANSITION_NOTIFIER);
  255. }
  256. #else
  257. static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
  258. {
  259. return 0;
  260. }
  261. static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
  262. {
  263. }
  264. #endif
  265. static int s3c2410wdt_probe(struct platform_device *pdev)
  266. {
  267. struct device *dev;
  268. struct s3c2410_wdt *wdt;
  269. struct resource *wdt_mem;
  270. struct resource *wdt_irq;
  271. unsigned int wtcon;
  272. int started = 0;
  273. int ret;
  274. DBG("%s: probe=%p\n", __func__, pdev);
  275. dev = &pdev->dev;
  276. wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
  277. if (!wdt)
  278. return -ENOMEM;
  279. wdt->dev = &pdev->dev;
  280. spin_lock_init(&wdt->lock);
  281. wdt->wdt_device = s3c2410_wdd;
  282. wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  283. if (wdt_irq == NULL) {
  284. dev_err(dev, "no irq resource specified\n");
  285. ret = -ENOENT;
  286. goto err;
  287. }
  288. /* get the memory region for the watchdog timer */
  289. wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  290. wdt->reg_base = devm_ioremap_resource(dev, wdt_mem);
  291. if (IS_ERR(wdt->reg_base)) {
  292. ret = PTR_ERR(wdt->reg_base);
  293. goto err;
  294. }
  295. DBG("probe: mapped reg_base=%p\n", wdt->reg_base);
  296. wdt->clock = devm_clk_get(dev, "watchdog");
  297. if (IS_ERR(wdt->clock)) {
  298. dev_err(dev, "failed to find watchdog clock source\n");
  299. ret = PTR_ERR(wdt->clock);
  300. goto err;
  301. }
  302. clk_prepare_enable(wdt->clock);
  303. ret = s3c2410wdt_cpufreq_register(wdt);
  304. if (ret < 0) {
  305. dev_err(dev, "failed to register cpufreq\n");
  306. goto err_clk;
  307. }
  308. watchdog_set_drvdata(&wdt->wdt_device, wdt);
  309. /* see if we can actually set the requested timer margin, and if
  310. * not, try the default value */
  311. watchdog_init_timeout(&wdt->wdt_device, tmr_margin, &pdev->dev);
  312. ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
  313. wdt->wdt_device.timeout);
  314. if (ret) {
  315. started = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
  316. CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
  317. if (started == 0)
  318. dev_info(dev,
  319. "tmr_margin value out of range, default %d used\n",
  320. CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
  321. else
  322. dev_info(dev, "default timer value is out of range, "
  323. "cannot start\n");
  324. }
  325. ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0,
  326. pdev->name, pdev);
  327. if (ret != 0) {
  328. dev_err(dev, "failed to install irq (%d)\n", ret);
  329. goto err_cpufreq;
  330. }
  331. watchdog_set_nowayout(&wdt->wdt_device, nowayout);
  332. ret = watchdog_register_device(&wdt->wdt_device);
  333. if (ret) {
  334. dev_err(dev, "cannot register watchdog (%d)\n", ret);
  335. goto err_cpufreq;
  336. }
  337. if (tmr_atboot && started == 0) {
  338. dev_info(dev, "starting watchdog timer\n");
  339. s3c2410wdt_start(&wdt->wdt_device);
  340. } else if (!tmr_atboot) {
  341. /* if we're not enabling the watchdog, then ensure it is
  342. * disabled if it has been left running from the bootloader
  343. * or other source */
  344. s3c2410wdt_stop(&wdt->wdt_device);
  345. }
  346. platform_set_drvdata(pdev, wdt);
  347. /* print out a statement of readiness */
  348. wtcon = readl(wdt->reg_base + S3C2410_WTCON);
  349. dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
  350. (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
  351. (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
  352. (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
  353. return 0;
  354. err_cpufreq:
  355. s3c2410wdt_cpufreq_deregister(wdt);
  356. err_clk:
  357. clk_disable_unprepare(wdt->clock);
  358. wdt->clock = NULL;
  359. err:
  360. return ret;
  361. }
  362. static int s3c2410wdt_remove(struct platform_device *dev)
  363. {
  364. struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
  365. watchdog_unregister_device(&wdt->wdt_device);
  366. s3c2410wdt_cpufreq_deregister(wdt);
  367. clk_disable_unprepare(wdt->clock);
  368. wdt->clock = NULL;
  369. return 0;
  370. }
  371. static void s3c2410wdt_shutdown(struct platform_device *dev)
  372. {
  373. struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
  374. s3c2410wdt_stop(&wdt->wdt_device);
  375. }
  376. #ifdef CONFIG_PM_SLEEP
  377. static int s3c2410wdt_suspend(struct device *dev)
  378. {
  379. struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
  380. /* Save watchdog state, and turn it off. */
  381. wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON);
  382. wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT);
  383. /* Note that WTCNT doesn't need to be saved. */
  384. s3c2410wdt_stop(&wdt->wdt_device);
  385. return 0;
  386. }
  387. static int s3c2410wdt_resume(struct device *dev)
  388. {
  389. struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
  390. /* Restore watchdog state. */
  391. writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT);
  392. writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */
  393. writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON);
  394. dev_info(dev, "watchdog %sabled\n",
  395. (wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
  396. return 0;
  397. }
  398. #endif
  399. static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend,
  400. s3c2410wdt_resume);
  401. #ifdef CONFIG_OF
  402. static const struct of_device_id s3c2410_wdt_match[] = {
  403. { .compatible = "samsung,s3c2410-wdt" },
  404. {},
  405. };
  406. MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
  407. #endif
  408. static struct platform_driver s3c2410wdt_driver = {
  409. .probe = s3c2410wdt_probe,
  410. .remove = s3c2410wdt_remove,
  411. .shutdown = s3c2410wdt_shutdown,
  412. .driver = {
  413. .owner = THIS_MODULE,
  414. .name = "s3c2410-wdt",
  415. .pm = &s3c2410wdt_pm_ops,
  416. .of_match_table = of_match_ptr(s3c2410_wdt_match),
  417. },
  418. };
  419. module_platform_driver(s3c2410wdt_driver);
  420. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
  421. "Dimitry Andric <dimitry.andric@tomtom.com>");
  422. MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
  423. MODULE_LICENSE("GPL");
  424. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
  425. MODULE_ALIAS("platform:s3c2410-wdt");