xhci.c 149 KB

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  1. /*
  2. * xHCI host controller driver
  3. *
  4. * Copyright (C) 2008 Intel Corp.
  5. *
  6. * Author: Sarah Sharp
  7. * Some code borrowed from the Linux EHCI driver.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/pci.h>
  23. #include <linux/irq.h>
  24. #include <linux/log2.h>
  25. #include <linux/module.h>
  26. #include <linux/moduleparam.h>
  27. #include <linux/slab.h>
  28. #include <linux/dmi.h>
  29. #include <linux/dma-mapping.h>
  30. #include "xhci.h"
  31. #include "xhci-trace.h"
  32. #define DRIVER_AUTHOR "Sarah Sharp"
  33. #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
  34. /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
  35. static int link_quirk;
  36. module_param(link_quirk, int, S_IRUGO | S_IWUSR);
  37. MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
  38. /* TODO: copied from ehci-hcd.c - can this be refactored? */
  39. /*
  40. * xhci_handshake - spin reading hc until handshake completes or fails
  41. * @ptr: address of hc register to be read
  42. * @mask: bits to look at in result of read
  43. * @done: value of those bits when handshake succeeds
  44. * @usec: timeout in microseconds
  45. *
  46. * Returns negative errno, or zero on success
  47. *
  48. * Success happens when the "mask" bits have the specified value (hardware
  49. * handshake done). There are two failure modes: "usec" have passed (major
  50. * hardware flakeout), or the register reads as all-ones (hardware removed).
  51. */
  52. int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr,
  53. u32 mask, u32 done, int usec)
  54. {
  55. u32 result;
  56. do {
  57. result = xhci_readl(xhci, ptr);
  58. if (result == ~(u32)0) /* card removed */
  59. return -ENODEV;
  60. result &= mask;
  61. if (result == done)
  62. return 0;
  63. udelay(1);
  64. usec--;
  65. } while (usec > 0);
  66. return -ETIMEDOUT;
  67. }
  68. /*
  69. * Disable interrupts and begin the xHCI halting process.
  70. */
  71. void xhci_quiesce(struct xhci_hcd *xhci)
  72. {
  73. u32 halted;
  74. u32 cmd;
  75. u32 mask;
  76. mask = ~(XHCI_IRQS);
  77. halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT;
  78. if (!halted)
  79. mask &= ~CMD_RUN;
  80. cmd = xhci_readl(xhci, &xhci->op_regs->command);
  81. cmd &= mask;
  82. xhci_writel(xhci, cmd, &xhci->op_regs->command);
  83. }
  84. /*
  85. * Force HC into halt state.
  86. *
  87. * Disable any IRQs and clear the run/stop bit.
  88. * HC will complete any current and actively pipelined transactions, and
  89. * should halt within 16 ms of the run/stop bit being cleared.
  90. * Read HC Halted bit in the status register to see when the HC is finished.
  91. */
  92. int xhci_halt(struct xhci_hcd *xhci)
  93. {
  94. int ret;
  95. xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
  96. xhci_quiesce(xhci);
  97. ret = xhci_handshake(xhci, &xhci->op_regs->status,
  98. STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
  99. if (!ret) {
  100. xhci->xhc_state |= XHCI_STATE_HALTED;
  101. xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
  102. } else
  103. xhci_warn(xhci, "Host not halted after %u microseconds.\n",
  104. XHCI_MAX_HALT_USEC);
  105. return ret;
  106. }
  107. /*
  108. * Set the run bit and wait for the host to be running.
  109. */
  110. static int xhci_start(struct xhci_hcd *xhci)
  111. {
  112. u32 temp;
  113. int ret;
  114. temp = xhci_readl(xhci, &xhci->op_regs->command);
  115. temp |= (CMD_RUN);
  116. xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
  117. temp);
  118. xhci_writel(xhci, temp, &xhci->op_regs->command);
  119. /*
  120. * Wait for the HCHalted Status bit to be 0 to indicate the host is
  121. * running.
  122. */
  123. ret = xhci_handshake(xhci, &xhci->op_regs->status,
  124. STS_HALT, 0, XHCI_MAX_HALT_USEC);
  125. if (ret == -ETIMEDOUT)
  126. xhci_err(xhci, "Host took too long to start, "
  127. "waited %u microseconds.\n",
  128. XHCI_MAX_HALT_USEC);
  129. if (!ret)
  130. xhci->xhc_state &= ~XHCI_STATE_HALTED;
  131. return ret;
  132. }
  133. /*
  134. * Reset a halted HC.
  135. *
  136. * This resets pipelines, timers, counters, state machines, etc.
  137. * Transactions will be terminated immediately, and operational registers
  138. * will be set to their defaults.
  139. */
  140. int xhci_reset(struct xhci_hcd *xhci)
  141. {
  142. u32 command;
  143. u32 state;
  144. int ret, i;
  145. state = xhci_readl(xhci, &xhci->op_regs->status);
  146. if ((state & STS_HALT) == 0) {
  147. xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
  148. return 0;
  149. }
  150. xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
  151. command = xhci_readl(xhci, &xhci->op_regs->command);
  152. command |= CMD_RESET;
  153. xhci_writel(xhci, command, &xhci->op_regs->command);
  154. ret = xhci_handshake(xhci, &xhci->op_regs->command,
  155. CMD_RESET, 0, 10 * 1000 * 1000);
  156. if (ret)
  157. return ret;
  158. xhci_dbg_trace(xhci, trace_xhci_dbg_init,
  159. "Wait for controller to be ready for doorbell rings");
  160. /*
  161. * xHCI cannot write to any doorbells or operational registers other
  162. * than status until the "Controller Not Ready" flag is cleared.
  163. */
  164. ret = xhci_handshake(xhci, &xhci->op_regs->status,
  165. STS_CNR, 0, 10 * 1000 * 1000);
  166. for (i = 0; i < 2; ++i) {
  167. xhci->bus_state[i].port_c_suspend = 0;
  168. xhci->bus_state[i].suspended_ports = 0;
  169. xhci->bus_state[i].resuming_ports = 0;
  170. }
  171. return ret;
  172. }
  173. #ifdef CONFIG_PCI
  174. static int xhci_free_msi(struct xhci_hcd *xhci)
  175. {
  176. int i;
  177. if (!xhci->msix_entries)
  178. return -EINVAL;
  179. for (i = 0; i < xhci->msix_count; i++)
  180. if (xhci->msix_entries[i].vector)
  181. free_irq(xhci->msix_entries[i].vector,
  182. xhci_to_hcd(xhci));
  183. return 0;
  184. }
  185. /*
  186. * Set up MSI
  187. */
  188. static int xhci_setup_msi(struct xhci_hcd *xhci)
  189. {
  190. int ret;
  191. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  192. ret = pci_enable_msi(pdev);
  193. if (ret) {
  194. xhci_dbg_trace(xhci, trace_xhci_dbg_init,
  195. "failed to allocate MSI entry");
  196. return ret;
  197. }
  198. ret = request_irq(pdev->irq, xhci_msi_irq,
  199. 0, "xhci_hcd", xhci_to_hcd(xhci));
  200. if (ret) {
  201. xhci_dbg_trace(xhci, trace_xhci_dbg_init,
  202. "disable MSI interrupt");
  203. pci_disable_msi(pdev);
  204. }
  205. return ret;
  206. }
  207. /*
  208. * Free IRQs
  209. * free all IRQs request
  210. */
  211. static void xhci_free_irq(struct xhci_hcd *xhci)
  212. {
  213. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  214. int ret;
  215. /* return if using legacy interrupt */
  216. if (xhci_to_hcd(xhci)->irq > 0)
  217. return;
  218. ret = xhci_free_msi(xhci);
  219. if (!ret)
  220. return;
  221. if (pdev->irq > 0)
  222. free_irq(pdev->irq, xhci_to_hcd(xhci));
  223. return;
  224. }
  225. /*
  226. * Set up MSI-X
  227. */
  228. static int xhci_setup_msix(struct xhci_hcd *xhci)
  229. {
  230. int i, ret = 0;
  231. struct usb_hcd *hcd = xhci_to_hcd(xhci);
  232. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  233. /*
  234. * calculate number of msi-x vectors supported.
  235. * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
  236. * with max number of interrupters based on the xhci HCSPARAMS1.
  237. * - num_online_cpus: maximum msi-x vectors per CPUs core.
  238. * Add additional 1 vector to ensure always available interrupt.
  239. */
  240. xhci->msix_count = min(num_online_cpus() + 1,
  241. HCS_MAX_INTRS(xhci->hcs_params1));
  242. xhci->msix_entries =
  243. kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
  244. GFP_KERNEL);
  245. if (!xhci->msix_entries) {
  246. xhci_err(xhci, "Failed to allocate MSI-X entries\n");
  247. return -ENOMEM;
  248. }
  249. for (i = 0; i < xhci->msix_count; i++) {
  250. xhci->msix_entries[i].entry = i;
  251. xhci->msix_entries[i].vector = 0;
  252. }
  253. ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count);
  254. if (ret) {
  255. xhci_dbg_trace(xhci, trace_xhci_dbg_init,
  256. "Failed to enable MSI-X");
  257. goto free_entries;
  258. }
  259. for (i = 0; i < xhci->msix_count; i++) {
  260. ret = request_irq(xhci->msix_entries[i].vector,
  261. xhci_msi_irq,
  262. 0, "xhci_hcd", xhci_to_hcd(xhci));
  263. if (ret)
  264. goto disable_msix;
  265. }
  266. hcd->msix_enabled = 1;
  267. return ret;
  268. disable_msix:
  269. xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
  270. xhci_free_irq(xhci);
  271. pci_disable_msix(pdev);
  272. free_entries:
  273. kfree(xhci->msix_entries);
  274. xhci->msix_entries = NULL;
  275. return ret;
  276. }
  277. /* Free any IRQs and disable MSI-X */
  278. static void xhci_cleanup_msix(struct xhci_hcd *xhci)
  279. {
  280. struct usb_hcd *hcd = xhci_to_hcd(xhci);
  281. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  282. xhci_free_irq(xhci);
  283. if (xhci->msix_entries) {
  284. pci_disable_msix(pdev);
  285. kfree(xhci->msix_entries);
  286. xhci->msix_entries = NULL;
  287. } else {
  288. pci_disable_msi(pdev);
  289. }
  290. hcd->msix_enabled = 0;
  291. return;
  292. }
  293. static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
  294. {
  295. int i;
  296. if (xhci->msix_entries) {
  297. for (i = 0; i < xhci->msix_count; i++)
  298. synchronize_irq(xhci->msix_entries[i].vector);
  299. }
  300. }
  301. static int xhci_try_enable_msi(struct usb_hcd *hcd)
  302. {
  303. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  304. struct pci_dev *pdev;
  305. int ret;
  306. /* The xhci platform device has set up IRQs through usb_add_hcd. */
  307. if (xhci->quirks & XHCI_PLAT)
  308. return 0;
  309. pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  310. /*
  311. * Some Fresco Logic host controllers advertise MSI, but fail to
  312. * generate interrupts. Don't even try to enable MSI.
  313. */
  314. if (xhci->quirks & XHCI_BROKEN_MSI)
  315. goto legacy_irq;
  316. /* unregister the legacy interrupt */
  317. if (hcd->irq)
  318. free_irq(hcd->irq, hcd);
  319. hcd->irq = 0;
  320. ret = xhci_setup_msix(xhci);
  321. if (ret)
  322. /* fall back to msi*/
  323. ret = xhci_setup_msi(xhci);
  324. if (!ret)
  325. /* hcd->irq is 0, we have MSI */
  326. return 0;
  327. if (!pdev->irq) {
  328. xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
  329. return -EINVAL;
  330. }
  331. legacy_irq:
  332. /* fall back to legacy interrupt*/
  333. ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
  334. hcd->irq_descr, hcd);
  335. if (ret) {
  336. xhci_err(xhci, "request interrupt %d failed\n",
  337. pdev->irq);
  338. return ret;
  339. }
  340. hcd->irq = pdev->irq;
  341. return 0;
  342. }
  343. #else
  344. static int xhci_try_enable_msi(struct usb_hcd *hcd)
  345. {
  346. return 0;
  347. }
  348. static void xhci_cleanup_msix(struct xhci_hcd *xhci)
  349. {
  350. }
  351. static void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
  352. {
  353. }
  354. #endif
  355. static void compliance_mode_recovery(unsigned long arg)
  356. {
  357. struct xhci_hcd *xhci;
  358. struct usb_hcd *hcd;
  359. u32 temp;
  360. int i;
  361. xhci = (struct xhci_hcd *)arg;
  362. for (i = 0; i < xhci->num_usb3_ports; i++) {
  363. temp = xhci_readl(xhci, xhci->usb3_ports[i]);
  364. if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
  365. /*
  366. * Compliance Mode Detected. Letting USB Core
  367. * handle the Warm Reset
  368. */
  369. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  370. "Compliance mode detected->port %d",
  371. i + 1);
  372. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  373. "Attempting compliance mode recovery");
  374. hcd = xhci->shared_hcd;
  375. if (hcd->state == HC_STATE_SUSPENDED)
  376. usb_hcd_resume_root_hub(hcd);
  377. usb_hcd_poll_rh_status(hcd);
  378. }
  379. }
  380. if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
  381. mod_timer(&xhci->comp_mode_recovery_timer,
  382. jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
  383. }
  384. /*
  385. * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
  386. * that causes ports behind that hardware to enter compliance mode sometimes.
  387. * The quirk creates a timer that polls every 2 seconds the link state of
  388. * each host controller's port and recovers it by issuing a Warm reset
  389. * if Compliance mode is detected, otherwise the port will become "dead" (no
  390. * device connections or disconnections will be detected anymore). Becasue no
  391. * status event is generated when entering compliance mode (per xhci spec),
  392. * this quirk is needed on systems that have the failing hardware installed.
  393. */
  394. static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
  395. {
  396. xhci->port_status_u0 = 0;
  397. init_timer(&xhci->comp_mode_recovery_timer);
  398. xhci->comp_mode_recovery_timer.data = (unsigned long) xhci;
  399. xhci->comp_mode_recovery_timer.function = compliance_mode_recovery;
  400. xhci->comp_mode_recovery_timer.expires = jiffies +
  401. msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
  402. set_timer_slack(&xhci->comp_mode_recovery_timer,
  403. msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
  404. add_timer(&xhci->comp_mode_recovery_timer);
  405. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  406. "Compliance mode recovery timer initialized");
  407. }
  408. /*
  409. * This function identifies the systems that have installed the SN65LVPE502CP
  410. * USB3.0 re-driver and that need the Compliance Mode Quirk.
  411. * Systems:
  412. * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
  413. */
  414. bool xhci_compliance_mode_recovery_timer_quirk_check(void)
  415. {
  416. const char *dmi_product_name, *dmi_sys_vendor;
  417. dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
  418. dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
  419. if (!dmi_product_name || !dmi_sys_vendor)
  420. return false;
  421. if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
  422. return false;
  423. if (strstr(dmi_product_name, "Z420") ||
  424. strstr(dmi_product_name, "Z620") ||
  425. strstr(dmi_product_name, "Z820") ||
  426. strstr(dmi_product_name, "Z1 Workstation"))
  427. return true;
  428. return false;
  429. }
  430. static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
  431. {
  432. return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
  433. }
  434. /*
  435. * Initialize memory for HCD and xHC (one-time init).
  436. *
  437. * Program the PAGESIZE register, initialize the device context array, create
  438. * device contexts (?), set up a command ring segment (or two?), create event
  439. * ring (one for now).
  440. */
  441. int xhci_init(struct usb_hcd *hcd)
  442. {
  443. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  444. int retval = 0;
  445. xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
  446. spin_lock_init(&xhci->lock);
  447. if (xhci->hci_version == 0x95 && link_quirk) {
  448. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  449. "QUIRK: Not clearing Link TRB chain bits.");
  450. xhci->quirks |= XHCI_LINK_TRB_QUIRK;
  451. } else {
  452. xhci_dbg_trace(xhci, trace_xhci_dbg_init,
  453. "xHCI doesn't need link TRB QUIRK");
  454. }
  455. retval = xhci_mem_init(xhci, GFP_KERNEL);
  456. xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
  457. /* Initializing Compliance Mode Recovery Data If Needed */
  458. if (xhci_compliance_mode_recovery_timer_quirk_check()) {
  459. xhci->quirks |= XHCI_COMP_MODE_QUIRK;
  460. compliance_mode_recovery_timer_init(xhci);
  461. }
  462. return retval;
  463. }
  464. /*-------------------------------------------------------------------------*/
  465. static int xhci_run_finished(struct xhci_hcd *xhci)
  466. {
  467. if (xhci_start(xhci)) {
  468. xhci_halt(xhci);
  469. return -ENODEV;
  470. }
  471. xhci->shared_hcd->state = HC_STATE_RUNNING;
  472. xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
  473. if (xhci->quirks & XHCI_NEC_HOST)
  474. xhci_ring_cmd_db(xhci);
  475. xhci_dbg_trace(xhci, trace_xhci_dbg_init,
  476. "Finished xhci_run for USB3 roothub");
  477. return 0;
  478. }
  479. /*
  480. * Start the HC after it was halted.
  481. *
  482. * This function is called by the USB core when the HC driver is added.
  483. * Its opposite is xhci_stop().
  484. *
  485. * xhci_init() must be called once before this function can be called.
  486. * Reset the HC, enable device slot contexts, program DCBAAP, and
  487. * set command ring pointer and event ring pointer.
  488. *
  489. * Setup MSI-X vectors and enable interrupts.
  490. */
  491. int xhci_run(struct usb_hcd *hcd)
  492. {
  493. u32 temp;
  494. u64 temp_64;
  495. int ret;
  496. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  497. /* Start the xHCI host controller running only after the USB 2.0 roothub
  498. * is setup.
  499. */
  500. hcd->uses_new_polling = 1;
  501. if (!usb_hcd_is_primary_hcd(hcd))
  502. return xhci_run_finished(xhci);
  503. xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
  504. ret = xhci_try_enable_msi(hcd);
  505. if (ret)
  506. return ret;
  507. xhci_dbg(xhci, "Command ring memory map follows:\n");
  508. xhci_debug_ring(xhci, xhci->cmd_ring);
  509. xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
  510. xhci_dbg_cmd_ptrs(xhci);
  511. xhci_dbg(xhci, "ERST memory map follows:\n");
  512. xhci_dbg_erst(xhci, &xhci->erst);
  513. xhci_dbg(xhci, "Event ring:\n");
  514. xhci_debug_ring(xhci, xhci->event_ring);
  515. xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
  516. temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
  517. temp_64 &= ~ERST_PTR_MASK;
  518. xhci_dbg_trace(xhci, trace_xhci_dbg_init,
  519. "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
  520. xhci_dbg_trace(xhci, trace_xhci_dbg_init,
  521. "// Set the interrupt modulation register");
  522. temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
  523. temp &= ~ER_IRQ_INTERVAL_MASK;
  524. temp |= (u32) 160;
  525. xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
  526. /* Set the HCD state before we enable the irqs */
  527. temp = xhci_readl(xhci, &xhci->op_regs->command);
  528. temp |= (CMD_EIE);
  529. xhci_dbg_trace(xhci, trace_xhci_dbg_init,
  530. "// Enable interrupts, cmd = 0x%x.", temp);
  531. xhci_writel(xhci, temp, &xhci->op_regs->command);
  532. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  533. xhci_dbg_trace(xhci, trace_xhci_dbg_init,
  534. "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
  535. xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
  536. xhci_writel(xhci, ER_IRQ_ENABLE(temp),
  537. &xhci->ir_set->irq_pending);
  538. xhci_print_ir_set(xhci, 0);
  539. if (xhci->quirks & XHCI_NEC_HOST)
  540. xhci_queue_vendor_command(xhci, 0, 0, 0,
  541. TRB_TYPE(TRB_NEC_GET_FW));
  542. xhci_dbg_trace(xhci, trace_xhci_dbg_init,
  543. "Finished xhci_run for USB2 roothub");
  544. return 0;
  545. }
  546. static void xhci_only_stop_hcd(struct usb_hcd *hcd)
  547. {
  548. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  549. spin_lock_irq(&xhci->lock);
  550. xhci_halt(xhci);
  551. /* The shared_hcd is going to be deallocated shortly (the USB core only
  552. * calls this function when allocation fails in usb_add_hcd(), or
  553. * usb_remove_hcd() is called). So we need to unset xHCI's pointer.
  554. */
  555. xhci->shared_hcd = NULL;
  556. spin_unlock_irq(&xhci->lock);
  557. }
  558. /*
  559. * Stop xHCI driver.
  560. *
  561. * This function is called by the USB core when the HC driver is removed.
  562. * Its opposite is xhci_run().
  563. *
  564. * Disable device contexts, disable IRQs, and quiesce the HC.
  565. * Reset the HC, finish any completed transactions, and cleanup memory.
  566. */
  567. void xhci_stop(struct usb_hcd *hcd)
  568. {
  569. u32 temp;
  570. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  571. if (!usb_hcd_is_primary_hcd(hcd)) {
  572. xhci_only_stop_hcd(xhci->shared_hcd);
  573. return;
  574. }
  575. spin_lock_irq(&xhci->lock);
  576. /* Make sure the xHC is halted for a USB3 roothub
  577. * (xhci_stop() could be called as part of failed init).
  578. */
  579. xhci_halt(xhci);
  580. xhci_reset(xhci);
  581. spin_unlock_irq(&xhci->lock);
  582. xhci_cleanup_msix(xhci);
  583. /* Deleting Compliance Mode Recovery Timer */
  584. if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
  585. (!(xhci_all_ports_seen_u0(xhci)))) {
  586. del_timer_sync(&xhci->comp_mode_recovery_timer);
  587. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  588. "%s: compliance mode recovery timer deleted",
  589. __func__);
  590. }
  591. if (xhci->quirks & XHCI_AMD_PLL_FIX)
  592. usb_amd_dev_put();
  593. xhci_dbg_trace(xhci, trace_xhci_dbg_init,
  594. "// Disabling event ring interrupts");
  595. temp = xhci_readl(xhci, &xhci->op_regs->status);
  596. xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
  597. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  598. xhci_writel(xhci, ER_IRQ_DISABLE(temp),
  599. &xhci->ir_set->irq_pending);
  600. xhci_print_ir_set(xhci, 0);
  601. xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
  602. xhci_mem_cleanup(xhci);
  603. xhci_dbg_trace(xhci, trace_xhci_dbg_init,
  604. "xhci_stop completed - status = %x",
  605. xhci_readl(xhci, &xhci->op_regs->status));
  606. }
  607. /*
  608. * Shutdown HC (not bus-specific)
  609. *
  610. * This is called when the machine is rebooting or halting. We assume that the
  611. * machine will be powered off, and the HC's internal state will be reset.
  612. * Don't bother to free memory.
  613. *
  614. * This will only ever be called with the main usb_hcd (the USB3 roothub).
  615. */
  616. void xhci_shutdown(struct usb_hcd *hcd)
  617. {
  618. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  619. if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
  620. usb_disable_xhci_ports(to_pci_dev(hcd->self.controller));
  621. spin_lock_irq(&xhci->lock);
  622. xhci_halt(xhci);
  623. spin_unlock_irq(&xhci->lock);
  624. xhci_cleanup_msix(xhci);
  625. xhci_dbg_trace(xhci, trace_xhci_dbg_init,
  626. "xhci_shutdown completed - status = %x",
  627. xhci_readl(xhci, &xhci->op_regs->status));
  628. }
  629. #ifdef CONFIG_PM
  630. static void xhci_save_registers(struct xhci_hcd *xhci)
  631. {
  632. xhci->s3.command = xhci_readl(xhci, &xhci->op_regs->command);
  633. xhci->s3.dev_nt = xhci_readl(xhci, &xhci->op_regs->dev_notification);
  634. xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
  635. xhci->s3.config_reg = xhci_readl(xhci, &xhci->op_regs->config_reg);
  636. xhci->s3.erst_size = xhci_readl(xhci, &xhci->ir_set->erst_size);
  637. xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
  638. xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
  639. xhci->s3.irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  640. xhci->s3.irq_control = xhci_readl(xhci, &xhci->ir_set->irq_control);
  641. }
  642. static void xhci_restore_registers(struct xhci_hcd *xhci)
  643. {
  644. xhci_writel(xhci, xhci->s3.command, &xhci->op_regs->command);
  645. xhci_writel(xhci, xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
  646. xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
  647. xhci_writel(xhci, xhci->s3.config_reg, &xhci->op_regs->config_reg);
  648. xhci_writel(xhci, xhci->s3.erst_size, &xhci->ir_set->erst_size);
  649. xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
  650. xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
  651. xhci_writel(xhci, xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
  652. xhci_writel(xhci, xhci->s3.irq_control, &xhci->ir_set->irq_control);
  653. }
  654. static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
  655. {
  656. u64 val_64;
  657. /* step 2: initialize command ring buffer */
  658. val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
  659. val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
  660. (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
  661. xhci->cmd_ring->dequeue) &
  662. (u64) ~CMD_RING_RSVD_BITS) |
  663. xhci->cmd_ring->cycle_state;
  664. xhci_dbg_trace(xhci, trace_xhci_dbg_init,
  665. "// Setting command ring address to 0x%llx",
  666. (long unsigned long) val_64);
  667. xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
  668. }
  669. /*
  670. * The whole command ring must be cleared to zero when we suspend the host.
  671. *
  672. * The host doesn't save the command ring pointer in the suspend well, so we
  673. * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
  674. * aligned, because of the reserved bits in the command ring dequeue pointer
  675. * register. Therefore, we can't just set the dequeue pointer back in the
  676. * middle of the ring (TRBs are 16-byte aligned).
  677. */
  678. static void xhci_clear_command_ring(struct xhci_hcd *xhci)
  679. {
  680. struct xhci_ring *ring;
  681. struct xhci_segment *seg;
  682. ring = xhci->cmd_ring;
  683. seg = ring->deq_seg;
  684. do {
  685. memset(seg->trbs, 0,
  686. sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
  687. seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
  688. cpu_to_le32(~TRB_CYCLE);
  689. seg = seg->next;
  690. } while (seg != ring->deq_seg);
  691. /* Reset the software enqueue and dequeue pointers */
  692. ring->deq_seg = ring->first_seg;
  693. ring->dequeue = ring->first_seg->trbs;
  694. ring->enq_seg = ring->deq_seg;
  695. ring->enqueue = ring->dequeue;
  696. ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
  697. /*
  698. * Ring is now zeroed, so the HW should look for change of ownership
  699. * when the cycle bit is set to 1.
  700. */
  701. ring->cycle_state = 1;
  702. /*
  703. * Reset the hardware dequeue pointer.
  704. * Yes, this will need to be re-written after resume, but we're paranoid
  705. * and want to make sure the hardware doesn't access bogus memory
  706. * because, say, the BIOS or an SMI started the host without changing
  707. * the command ring pointers.
  708. */
  709. xhci_set_cmd_ring_deq(xhci);
  710. }
  711. /*
  712. * Stop HC (not bus-specific)
  713. *
  714. * This is called when the machine transition into S3/S4 mode.
  715. *
  716. */
  717. int xhci_suspend(struct xhci_hcd *xhci)
  718. {
  719. int rc = 0;
  720. struct usb_hcd *hcd = xhci_to_hcd(xhci);
  721. u32 command;
  722. if (hcd->state != HC_STATE_SUSPENDED ||
  723. xhci->shared_hcd->state != HC_STATE_SUSPENDED)
  724. return -EINVAL;
  725. /* Don't poll the roothubs on bus suspend. */
  726. xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
  727. clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
  728. del_timer_sync(&hcd->rh_timer);
  729. spin_lock_irq(&xhci->lock);
  730. clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  731. clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
  732. /* step 1: stop endpoint */
  733. /* skipped assuming that port suspend has done */
  734. /* step 2: clear Run/Stop bit */
  735. command = xhci_readl(xhci, &xhci->op_regs->command);
  736. command &= ~CMD_RUN;
  737. xhci_writel(xhci, command, &xhci->op_regs->command);
  738. if (xhci_handshake(xhci, &xhci->op_regs->status,
  739. STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC)) {
  740. xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
  741. spin_unlock_irq(&xhci->lock);
  742. return -ETIMEDOUT;
  743. }
  744. xhci_clear_command_ring(xhci);
  745. /* step 3: save registers */
  746. xhci_save_registers(xhci);
  747. /* step 4: set CSS flag */
  748. command = xhci_readl(xhci, &xhci->op_regs->command);
  749. command |= CMD_CSS;
  750. xhci_writel(xhci, command, &xhci->op_regs->command);
  751. if (xhci_handshake(xhci, &xhci->op_regs->status,
  752. STS_SAVE, 0, 10 * 1000)) {
  753. xhci_warn(xhci, "WARN: xHC save state timeout\n");
  754. spin_unlock_irq(&xhci->lock);
  755. return -ETIMEDOUT;
  756. }
  757. spin_unlock_irq(&xhci->lock);
  758. /*
  759. * Deleting Compliance Mode Recovery Timer because the xHCI Host
  760. * is about to be suspended.
  761. */
  762. if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
  763. (!(xhci_all_ports_seen_u0(xhci)))) {
  764. del_timer_sync(&xhci->comp_mode_recovery_timer);
  765. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  766. "%s: compliance mode recovery timer deleted",
  767. __func__);
  768. }
  769. /* step 5: remove core well power */
  770. /* synchronize irq when using MSI-X */
  771. xhci_msix_sync_irqs(xhci);
  772. return rc;
  773. }
  774. /*
  775. * start xHC (not bus-specific)
  776. *
  777. * This is called when the machine transition from S3/S4 mode.
  778. *
  779. */
  780. int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
  781. {
  782. u32 command, temp = 0;
  783. struct usb_hcd *hcd = xhci_to_hcd(xhci);
  784. struct usb_hcd *secondary_hcd;
  785. int retval = 0;
  786. bool comp_timer_running = false;
  787. /* Wait a bit if either of the roothubs need to settle from the
  788. * transition into bus suspend.
  789. */
  790. if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
  791. time_before(jiffies,
  792. xhci->bus_state[1].next_statechange))
  793. msleep(100);
  794. set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  795. set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
  796. spin_lock_irq(&xhci->lock);
  797. if (xhci->quirks & XHCI_RESET_ON_RESUME)
  798. hibernated = true;
  799. if (!hibernated) {
  800. /* step 1: restore register */
  801. xhci_restore_registers(xhci);
  802. /* step 2: initialize command ring buffer */
  803. xhci_set_cmd_ring_deq(xhci);
  804. /* step 3: restore state and start state*/
  805. /* step 3: set CRS flag */
  806. command = xhci_readl(xhci, &xhci->op_regs->command);
  807. command |= CMD_CRS;
  808. xhci_writel(xhci, command, &xhci->op_regs->command);
  809. if (xhci_handshake(xhci, &xhci->op_regs->status,
  810. STS_RESTORE, 0, 10 * 1000)) {
  811. xhci_warn(xhci, "WARN: xHC restore state timeout\n");
  812. spin_unlock_irq(&xhci->lock);
  813. return -ETIMEDOUT;
  814. }
  815. temp = xhci_readl(xhci, &xhci->op_regs->status);
  816. }
  817. /* If restore operation fails, re-initialize the HC during resume */
  818. if ((temp & STS_SRE) || hibernated) {
  819. if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
  820. !(xhci_all_ports_seen_u0(xhci))) {
  821. del_timer_sync(&xhci->comp_mode_recovery_timer);
  822. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  823. "Compliance Mode Recovery Timer deleted!");
  824. }
  825. /* Let the USB core know _both_ roothubs lost power. */
  826. usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
  827. usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
  828. xhci_dbg(xhci, "Stop HCD\n");
  829. xhci_halt(xhci);
  830. xhci_reset(xhci);
  831. spin_unlock_irq(&xhci->lock);
  832. xhci_cleanup_msix(xhci);
  833. xhci_dbg(xhci, "// Disabling event ring interrupts\n");
  834. temp = xhci_readl(xhci, &xhci->op_regs->status);
  835. xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
  836. temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
  837. xhci_writel(xhci, ER_IRQ_DISABLE(temp),
  838. &xhci->ir_set->irq_pending);
  839. xhci_print_ir_set(xhci, 0);
  840. xhci_dbg(xhci, "cleaning up memory\n");
  841. xhci_mem_cleanup(xhci);
  842. xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
  843. xhci_readl(xhci, &xhci->op_regs->status));
  844. /* USB core calls the PCI reinit and start functions twice:
  845. * first with the primary HCD, and then with the secondary HCD.
  846. * If we don't do the same, the host will never be started.
  847. */
  848. if (!usb_hcd_is_primary_hcd(hcd))
  849. secondary_hcd = hcd;
  850. else
  851. secondary_hcd = xhci->shared_hcd;
  852. xhci_dbg(xhci, "Initialize the xhci_hcd\n");
  853. retval = xhci_init(hcd->primary_hcd);
  854. if (retval)
  855. return retval;
  856. comp_timer_running = true;
  857. xhci_dbg(xhci, "Start the primary HCD\n");
  858. retval = xhci_run(hcd->primary_hcd);
  859. if (!retval) {
  860. xhci_dbg(xhci, "Start the secondary HCD\n");
  861. retval = xhci_run(secondary_hcd);
  862. }
  863. hcd->state = HC_STATE_SUSPENDED;
  864. xhci->shared_hcd->state = HC_STATE_SUSPENDED;
  865. goto done;
  866. }
  867. /* step 4: set Run/Stop bit */
  868. command = xhci_readl(xhci, &xhci->op_regs->command);
  869. command |= CMD_RUN;
  870. xhci_writel(xhci, command, &xhci->op_regs->command);
  871. xhci_handshake(xhci, &xhci->op_regs->status, STS_HALT,
  872. 0, 250 * 1000);
  873. /* step 5: walk topology and initialize portsc,
  874. * portpmsc and portli
  875. */
  876. /* this is done in bus_resume */
  877. /* step 6: restart each of the previously
  878. * Running endpoints by ringing their doorbells
  879. */
  880. spin_unlock_irq(&xhci->lock);
  881. done:
  882. if (retval == 0) {
  883. usb_hcd_resume_root_hub(hcd);
  884. usb_hcd_resume_root_hub(xhci->shared_hcd);
  885. }
  886. /*
  887. * If system is subject to the Quirk, Compliance Mode Timer needs to
  888. * be re-initialized Always after a system resume. Ports are subject
  889. * to suffer the Compliance Mode issue again. It doesn't matter if
  890. * ports have entered previously to U0 before system's suspension.
  891. */
  892. if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
  893. compliance_mode_recovery_timer_init(xhci);
  894. /* Re-enable port polling. */
  895. xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
  896. set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
  897. usb_hcd_poll_rh_status(hcd);
  898. return retval;
  899. }
  900. #endif /* CONFIG_PM */
  901. /*-------------------------------------------------------------------------*/
  902. /**
  903. * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
  904. * HCDs. Find the index for an endpoint given its descriptor. Use the return
  905. * value to right shift 1 for the bitmask.
  906. *
  907. * Index = (epnum * 2) + direction - 1,
  908. * where direction = 0 for OUT, 1 for IN.
  909. * For control endpoints, the IN index is used (OUT index is unused), so
  910. * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
  911. */
  912. unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
  913. {
  914. unsigned int index;
  915. if (usb_endpoint_xfer_control(desc))
  916. index = (unsigned int) (usb_endpoint_num(desc)*2);
  917. else
  918. index = (unsigned int) (usb_endpoint_num(desc)*2) +
  919. (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
  920. return index;
  921. }
  922. /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
  923. * address from the XHCI endpoint index.
  924. */
  925. unsigned int xhci_get_endpoint_address(unsigned int ep_index)
  926. {
  927. unsigned int number = DIV_ROUND_UP(ep_index, 2);
  928. unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
  929. return direction | number;
  930. }
  931. /* Find the flag for this endpoint (for use in the control context). Use the
  932. * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
  933. * bit 1, etc.
  934. */
  935. unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
  936. {
  937. return 1 << (xhci_get_endpoint_index(desc) + 1);
  938. }
  939. /* Find the flag for this endpoint (for use in the control context). Use the
  940. * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
  941. * bit 1, etc.
  942. */
  943. unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
  944. {
  945. return 1 << (ep_index + 1);
  946. }
  947. /* Compute the last valid endpoint context index. Basically, this is the
  948. * endpoint index plus one. For slot contexts with more than valid endpoint,
  949. * we find the most significant bit set in the added contexts flags.
  950. * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
  951. * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
  952. */
  953. unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
  954. {
  955. return fls(added_ctxs) - 1;
  956. }
  957. /* Returns 1 if the arguments are OK;
  958. * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
  959. */
  960. static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
  961. struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
  962. const char *func) {
  963. struct xhci_hcd *xhci;
  964. struct xhci_virt_device *virt_dev;
  965. if (!hcd || (check_ep && !ep) || !udev) {
  966. pr_debug("xHCI %s called with invalid args\n", func);
  967. return -EINVAL;
  968. }
  969. if (!udev->parent) {
  970. pr_debug("xHCI %s called for root hub\n", func);
  971. return 0;
  972. }
  973. xhci = hcd_to_xhci(hcd);
  974. if (check_virt_dev) {
  975. if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
  976. xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
  977. func);
  978. return -EINVAL;
  979. }
  980. virt_dev = xhci->devs[udev->slot_id];
  981. if (virt_dev->udev != udev) {
  982. xhci_dbg(xhci, "xHCI %s called with udev and "
  983. "virt_dev does not match\n", func);
  984. return -EINVAL;
  985. }
  986. }
  987. if (xhci->xhc_state & XHCI_STATE_HALTED)
  988. return -ENODEV;
  989. return 1;
  990. }
  991. static int xhci_configure_endpoint(struct xhci_hcd *xhci,
  992. struct usb_device *udev, struct xhci_command *command,
  993. bool ctx_change, bool must_succeed);
  994. /*
  995. * Full speed devices may have a max packet size greater than 8 bytes, but the
  996. * USB core doesn't know that until it reads the first 8 bytes of the
  997. * descriptor. If the usb_device's max packet size changes after that point,
  998. * we need to issue an evaluate context command and wait on it.
  999. */
  1000. static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
  1001. unsigned int ep_index, struct urb *urb)
  1002. {
  1003. struct xhci_container_ctx *in_ctx;
  1004. struct xhci_container_ctx *out_ctx;
  1005. struct xhci_input_control_ctx *ctrl_ctx;
  1006. struct xhci_ep_ctx *ep_ctx;
  1007. int max_packet_size;
  1008. int hw_max_packet_size;
  1009. int ret = 0;
  1010. out_ctx = xhci->devs[slot_id]->out_ctx;
  1011. ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
  1012. hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
  1013. max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
  1014. if (hw_max_packet_size != max_packet_size) {
  1015. xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
  1016. "Max Packet Size for ep 0 changed.");
  1017. xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
  1018. "Max packet size in usb_device = %d",
  1019. max_packet_size);
  1020. xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
  1021. "Max packet size in xHCI HW = %d",
  1022. hw_max_packet_size);
  1023. xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
  1024. "Issuing evaluate context command.");
  1025. /* Set up the input context flags for the command */
  1026. /* FIXME: This won't work if a non-default control endpoint
  1027. * changes max packet sizes.
  1028. */
  1029. in_ctx = xhci->devs[slot_id]->in_ctx;
  1030. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  1031. if (!ctrl_ctx) {
  1032. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  1033. __func__);
  1034. return -ENOMEM;
  1035. }
  1036. /* Set up the modified control endpoint 0 */
  1037. xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
  1038. xhci->devs[slot_id]->out_ctx, ep_index);
  1039. ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
  1040. ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
  1041. ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
  1042. ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
  1043. ctrl_ctx->drop_flags = 0;
  1044. xhci_dbg(xhci, "Slot %d input context\n", slot_id);
  1045. xhci_dbg_ctx(xhci, in_ctx, ep_index);
  1046. xhci_dbg(xhci, "Slot %d output context\n", slot_id);
  1047. xhci_dbg_ctx(xhci, out_ctx, ep_index);
  1048. ret = xhci_configure_endpoint(xhci, urb->dev, NULL,
  1049. true, false);
  1050. /* Clean up the input context for later use by bandwidth
  1051. * functions.
  1052. */
  1053. ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
  1054. }
  1055. return ret;
  1056. }
  1057. /*
  1058. * non-error returns are a promise to giveback() the urb later
  1059. * we drop ownership so next owner (or urb unlink) can get it
  1060. */
  1061. int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
  1062. {
  1063. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  1064. struct xhci_td *buffer;
  1065. unsigned long flags;
  1066. int ret = 0;
  1067. unsigned int slot_id, ep_index;
  1068. struct urb_priv *urb_priv;
  1069. int size, i;
  1070. if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
  1071. true, true, __func__) <= 0)
  1072. return -EINVAL;
  1073. slot_id = urb->dev->slot_id;
  1074. ep_index = xhci_get_endpoint_index(&urb->ep->desc);
  1075. if (!HCD_HW_ACCESSIBLE(hcd)) {
  1076. if (!in_interrupt())
  1077. xhci_dbg(xhci, "urb submitted during PCI suspend\n");
  1078. ret = -ESHUTDOWN;
  1079. goto exit;
  1080. }
  1081. if (usb_endpoint_xfer_isoc(&urb->ep->desc))
  1082. size = urb->number_of_packets;
  1083. else
  1084. size = 1;
  1085. urb_priv = kzalloc(sizeof(struct urb_priv) +
  1086. size * sizeof(struct xhci_td *), mem_flags);
  1087. if (!urb_priv)
  1088. return -ENOMEM;
  1089. buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
  1090. if (!buffer) {
  1091. kfree(urb_priv);
  1092. return -ENOMEM;
  1093. }
  1094. for (i = 0; i < size; i++) {
  1095. urb_priv->td[i] = buffer;
  1096. buffer++;
  1097. }
  1098. urb_priv->length = size;
  1099. urb_priv->td_cnt = 0;
  1100. urb->hcpriv = urb_priv;
  1101. if (usb_endpoint_xfer_control(&urb->ep->desc)) {
  1102. /* Check to see if the max packet size for the default control
  1103. * endpoint changed during FS device enumeration
  1104. */
  1105. if (urb->dev->speed == USB_SPEED_FULL) {
  1106. ret = xhci_check_maxpacket(xhci, slot_id,
  1107. ep_index, urb);
  1108. if (ret < 0) {
  1109. xhci_urb_free_priv(xhci, urb_priv);
  1110. urb->hcpriv = NULL;
  1111. return ret;
  1112. }
  1113. }
  1114. /* We have a spinlock and interrupts disabled, so we must pass
  1115. * atomic context to this function, which may allocate memory.
  1116. */
  1117. spin_lock_irqsave(&xhci->lock, flags);
  1118. if (xhci->xhc_state & XHCI_STATE_DYING)
  1119. goto dying;
  1120. ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
  1121. slot_id, ep_index);
  1122. if (ret)
  1123. goto free_priv;
  1124. spin_unlock_irqrestore(&xhci->lock, flags);
  1125. } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
  1126. spin_lock_irqsave(&xhci->lock, flags);
  1127. if (xhci->xhc_state & XHCI_STATE_DYING)
  1128. goto dying;
  1129. if (xhci->devs[slot_id]->eps[ep_index].ep_state &
  1130. EP_GETTING_STREAMS) {
  1131. xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
  1132. "is transitioning to using streams.\n");
  1133. ret = -EINVAL;
  1134. } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
  1135. EP_GETTING_NO_STREAMS) {
  1136. xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
  1137. "is transitioning to "
  1138. "not having streams.\n");
  1139. ret = -EINVAL;
  1140. } else {
  1141. ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
  1142. slot_id, ep_index);
  1143. }
  1144. if (ret)
  1145. goto free_priv;
  1146. spin_unlock_irqrestore(&xhci->lock, flags);
  1147. } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
  1148. spin_lock_irqsave(&xhci->lock, flags);
  1149. if (xhci->xhc_state & XHCI_STATE_DYING)
  1150. goto dying;
  1151. ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
  1152. slot_id, ep_index);
  1153. if (ret)
  1154. goto free_priv;
  1155. spin_unlock_irqrestore(&xhci->lock, flags);
  1156. } else {
  1157. spin_lock_irqsave(&xhci->lock, flags);
  1158. if (xhci->xhc_state & XHCI_STATE_DYING)
  1159. goto dying;
  1160. ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
  1161. slot_id, ep_index);
  1162. if (ret)
  1163. goto free_priv;
  1164. spin_unlock_irqrestore(&xhci->lock, flags);
  1165. }
  1166. exit:
  1167. return ret;
  1168. dying:
  1169. xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
  1170. "non-responsive xHCI host.\n",
  1171. urb->ep->desc.bEndpointAddress, urb);
  1172. ret = -ESHUTDOWN;
  1173. free_priv:
  1174. xhci_urb_free_priv(xhci, urb_priv);
  1175. urb->hcpriv = NULL;
  1176. spin_unlock_irqrestore(&xhci->lock, flags);
  1177. return ret;
  1178. }
  1179. /* Get the right ring for the given URB.
  1180. * If the endpoint supports streams, boundary check the URB's stream ID.
  1181. * If the endpoint doesn't support streams, return the singular endpoint ring.
  1182. */
  1183. static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
  1184. struct urb *urb)
  1185. {
  1186. unsigned int slot_id;
  1187. unsigned int ep_index;
  1188. unsigned int stream_id;
  1189. struct xhci_virt_ep *ep;
  1190. slot_id = urb->dev->slot_id;
  1191. ep_index = xhci_get_endpoint_index(&urb->ep->desc);
  1192. stream_id = urb->stream_id;
  1193. ep = &xhci->devs[slot_id]->eps[ep_index];
  1194. /* Common case: no streams */
  1195. if (!(ep->ep_state & EP_HAS_STREAMS))
  1196. return ep->ring;
  1197. if (stream_id == 0) {
  1198. xhci_warn(xhci,
  1199. "WARN: Slot ID %u, ep index %u has streams, "
  1200. "but URB has no stream ID.\n",
  1201. slot_id, ep_index);
  1202. return NULL;
  1203. }
  1204. if (stream_id < ep->stream_info->num_streams)
  1205. return ep->stream_info->stream_rings[stream_id];
  1206. xhci_warn(xhci,
  1207. "WARN: Slot ID %u, ep index %u has "
  1208. "stream IDs 1 to %u allocated, "
  1209. "but stream ID %u is requested.\n",
  1210. slot_id, ep_index,
  1211. ep->stream_info->num_streams - 1,
  1212. stream_id);
  1213. return NULL;
  1214. }
  1215. /*
  1216. * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
  1217. * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
  1218. * should pick up where it left off in the TD, unless a Set Transfer Ring
  1219. * Dequeue Pointer is issued.
  1220. *
  1221. * The TRBs that make up the buffers for the canceled URB will be "removed" from
  1222. * the ring. Since the ring is a contiguous structure, they can't be physically
  1223. * removed. Instead, there are two options:
  1224. *
  1225. * 1) If the HC is in the middle of processing the URB to be canceled, we
  1226. * simply move the ring's dequeue pointer past those TRBs using the Set
  1227. * Transfer Ring Dequeue Pointer command. This will be the common case,
  1228. * when drivers timeout on the last submitted URB and attempt to cancel.
  1229. *
  1230. * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
  1231. * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
  1232. * HC will need to invalidate the any TRBs it has cached after the stop
  1233. * endpoint command, as noted in the xHCI 0.95 errata.
  1234. *
  1235. * 3) The TD may have completed by the time the Stop Endpoint Command
  1236. * completes, so software needs to handle that case too.
  1237. *
  1238. * This function should protect against the TD enqueueing code ringing the
  1239. * doorbell while this code is waiting for a Stop Endpoint command to complete.
  1240. * It also needs to account for multiple cancellations on happening at the same
  1241. * time for the same endpoint.
  1242. *
  1243. * Note that this function can be called in any context, or so says
  1244. * usb_hcd_unlink_urb()
  1245. */
  1246. int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
  1247. {
  1248. unsigned long flags;
  1249. int ret, i;
  1250. u32 temp;
  1251. struct xhci_hcd *xhci;
  1252. struct urb_priv *urb_priv;
  1253. struct xhci_td *td;
  1254. unsigned int ep_index;
  1255. struct xhci_ring *ep_ring;
  1256. struct xhci_virt_ep *ep;
  1257. xhci = hcd_to_xhci(hcd);
  1258. spin_lock_irqsave(&xhci->lock, flags);
  1259. /* Make sure the URB hasn't completed or been unlinked already */
  1260. ret = usb_hcd_check_unlink_urb(hcd, urb, status);
  1261. if (ret || !urb->hcpriv)
  1262. goto done;
  1263. temp = xhci_readl(xhci, &xhci->op_regs->status);
  1264. if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
  1265. xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
  1266. "HW died, freeing TD.");
  1267. urb_priv = urb->hcpriv;
  1268. for (i = urb_priv->td_cnt; i < urb_priv->length; i++) {
  1269. td = urb_priv->td[i];
  1270. if (!list_empty(&td->td_list))
  1271. list_del_init(&td->td_list);
  1272. if (!list_empty(&td->cancelled_td_list))
  1273. list_del_init(&td->cancelled_td_list);
  1274. }
  1275. usb_hcd_unlink_urb_from_ep(hcd, urb);
  1276. spin_unlock_irqrestore(&xhci->lock, flags);
  1277. usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
  1278. xhci_urb_free_priv(xhci, urb_priv);
  1279. return ret;
  1280. }
  1281. if ((xhci->xhc_state & XHCI_STATE_DYING) ||
  1282. (xhci->xhc_state & XHCI_STATE_HALTED)) {
  1283. xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
  1284. "Ep 0x%x: URB %p to be canceled on "
  1285. "non-responsive xHCI host.",
  1286. urb->ep->desc.bEndpointAddress, urb);
  1287. /* Let the stop endpoint command watchdog timer (which set this
  1288. * state) finish cleaning up the endpoint TD lists. We must
  1289. * have caught it in the middle of dropping a lock and giving
  1290. * back an URB.
  1291. */
  1292. goto done;
  1293. }
  1294. ep_index = xhci_get_endpoint_index(&urb->ep->desc);
  1295. ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
  1296. ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
  1297. if (!ep_ring) {
  1298. ret = -EINVAL;
  1299. goto done;
  1300. }
  1301. urb_priv = urb->hcpriv;
  1302. i = urb_priv->td_cnt;
  1303. if (i < urb_priv->length)
  1304. xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
  1305. "Cancel URB %p, dev %s, ep 0x%x, "
  1306. "starting at offset 0x%llx",
  1307. urb, urb->dev->devpath,
  1308. urb->ep->desc.bEndpointAddress,
  1309. (unsigned long long) xhci_trb_virt_to_dma(
  1310. urb_priv->td[i]->start_seg,
  1311. urb_priv->td[i]->first_trb));
  1312. for (; i < urb_priv->length; i++) {
  1313. td = urb_priv->td[i];
  1314. list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
  1315. }
  1316. /* Queue a stop endpoint command, but only if this is
  1317. * the first cancellation to be handled.
  1318. */
  1319. if (!(ep->ep_state & EP_HALT_PENDING)) {
  1320. ep->ep_state |= EP_HALT_PENDING;
  1321. ep->stop_cmds_pending++;
  1322. ep->stop_cmd_timer.expires = jiffies +
  1323. XHCI_STOP_EP_CMD_TIMEOUT * HZ;
  1324. add_timer(&ep->stop_cmd_timer);
  1325. xhci_queue_stop_endpoint(xhci, urb->dev->slot_id, ep_index, 0);
  1326. xhci_ring_cmd_db(xhci);
  1327. }
  1328. done:
  1329. spin_unlock_irqrestore(&xhci->lock, flags);
  1330. return ret;
  1331. }
  1332. /* Drop an endpoint from a new bandwidth configuration for this device.
  1333. * Only one call to this function is allowed per endpoint before
  1334. * check_bandwidth() or reset_bandwidth() must be called.
  1335. * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
  1336. * add the endpoint to the schedule with possibly new parameters denoted by a
  1337. * different endpoint descriptor in usb_host_endpoint.
  1338. * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
  1339. * not allowed.
  1340. *
  1341. * The USB core will not allow URBs to be queued to an endpoint that is being
  1342. * disabled, so there's no need for mutual exclusion to protect
  1343. * the xhci->devs[slot_id] structure.
  1344. */
  1345. int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
  1346. struct usb_host_endpoint *ep)
  1347. {
  1348. struct xhci_hcd *xhci;
  1349. struct xhci_container_ctx *in_ctx, *out_ctx;
  1350. struct xhci_input_control_ctx *ctrl_ctx;
  1351. struct xhci_slot_ctx *slot_ctx;
  1352. unsigned int last_ctx;
  1353. unsigned int ep_index;
  1354. struct xhci_ep_ctx *ep_ctx;
  1355. u32 drop_flag;
  1356. u32 new_add_flags, new_drop_flags, new_slot_info;
  1357. int ret;
  1358. ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
  1359. if (ret <= 0)
  1360. return ret;
  1361. xhci = hcd_to_xhci(hcd);
  1362. if (xhci->xhc_state & XHCI_STATE_DYING)
  1363. return -ENODEV;
  1364. xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
  1365. drop_flag = xhci_get_endpoint_flag(&ep->desc);
  1366. if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
  1367. xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
  1368. __func__, drop_flag);
  1369. return 0;
  1370. }
  1371. in_ctx = xhci->devs[udev->slot_id]->in_ctx;
  1372. out_ctx = xhci->devs[udev->slot_id]->out_ctx;
  1373. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  1374. if (!ctrl_ctx) {
  1375. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  1376. __func__);
  1377. return 0;
  1378. }
  1379. ep_index = xhci_get_endpoint_index(&ep->desc);
  1380. ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
  1381. /* If the HC already knows the endpoint is disabled,
  1382. * or the HCD has noted it is disabled, ignore this request
  1383. */
  1384. if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
  1385. cpu_to_le32(EP_STATE_DISABLED)) ||
  1386. le32_to_cpu(ctrl_ctx->drop_flags) &
  1387. xhci_get_endpoint_flag(&ep->desc)) {
  1388. xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
  1389. __func__, ep);
  1390. return 0;
  1391. }
  1392. ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
  1393. new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
  1394. ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
  1395. new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
  1396. last_ctx = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags));
  1397. slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
  1398. /* Update the last valid endpoint context, if we deleted the last one */
  1399. if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) >
  1400. LAST_CTX(last_ctx)) {
  1401. slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
  1402. slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
  1403. }
  1404. new_slot_info = le32_to_cpu(slot_ctx->dev_info);
  1405. xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
  1406. xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
  1407. (unsigned int) ep->desc.bEndpointAddress,
  1408. udev->slot_id,
  1409. (unsigned int) new_drop_flags,
  1410. (unsigned int) new_add_flags,
  1411. (unsigned int) new_slot_info);
  1412. return 0;
  1413. }
  1414. /* Add an endpoint to a new possible bandwidth configuration for this device.
  1415. * Only one call to this function is allowed per endpoint before
  1416. * check_bandwidth() or reset_bandwidth() must be called.
  1417. * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
  1418. * add the endpoint to the schedule with possibly new parameters denoted by a
  1419. * different endpoint descriptor in usb_host_endpoint.
  1420. * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
  1421. * not allowed.
  1422. *
  1423. * The USB core will not allow URBs to be queued to an endpoint until the
  1424. * configuration or alt setting is installed in the device, so there's no need
  1425. * for mutual exclusion to protect the xhci->devs[slot_id] structure.
  1426. */
  1427. int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
  1428. struct usb_host_endpoint *ep)
  1429. {
  1430. struct xhci_hcd *xhci;
  1431. struct xhci_container_ctx *in_ctx, *out_ctx;
  1432. unsigned int ep_index;
  1433. struct xhci_slot_ctx *slot_ctx;
  1434. struct xhci_input_control_ctx *ctrl_ctx;
  1435. u32 added_ctxs;
  1436. unsigned int last_ctx;
  1437. u32 new_add_flags, new_drop_flags, new_slot_info;
  1438. struct xhci_virt_device *virt_dev;
  1439. int ret = 0;
  1440. ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
  1441. if (ret <= 0) {
  1442. /* So we won't queue a reset ep command for a root hub */
  1443. ep->hcpriv = NULL;
  1444. return ret;
  1445. }
  1446. xhci = hcd_to_xhci(hcd);
  1447. if (xhci->xhc_state & XHCI_STATE_DYING)
  1448. return -ENODEV;
  1449. added_ctxs = xhci_get_endpoint_flag(&ep->desc);
  1450. last_ctx = xhci_last_valid_endpoint(added_ctxs);
  1451. if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
  1452. /* FIXME when we have to issue an evaluate endpoint command to
  1453. * deal with ep0 max packet size changing once we get the
  1454. * descriptors
  1455. */
  1456. xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
  1457. __func__, added_ctxs);
  1458. return 0;
  1459. }
  1460. virt_dev = xhci->devs[udev->slot_id];
  1461. in_ctx = virt_dev->in_ctx;
  1462. out_ctx = virt_dev->out_ctx;
  1463. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  1464. if (!ctrl_ctx) {
  1465. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  1466. __func__);
  1467. return 0;
  1468. }
  1469. ep_index = xhci_get_endpoint_index(&ep->desc);
  1470. /* If this endpoint is already in use, and the upper layers are trying
  1471. * to add it again without dropping it, reject the addition.
  1472. */
  1473. if (virt_dev->eps[ep_index].ring &&
  1474. !(le32_to_cpu(ctrl_ctx->drop_flags) &
  1475. xhci_get_endpoint_flag(&ep->desc))) {
  1476. xhci_warn(xhci, "Trying to add endpoint 0x%x "
  1477. "without dropping it.\n",
  1478. (unsigned int) ep->desc.bEndpointAddress);
  1479. return -EINVAL;
  1480. }
  1481. /* If the HCD has already noted the endpoint is enabled,
  1482. * ignore this request.
  1483. */
  1484. if (le32_to_cpu(ctrl_ctx->add_flags) &
  1485. xhci_get_endpoint_flag(&ep->desc)) {
  1486. xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
  1487. __func__, ep);
  1488. return 0;
  1489. }
  1490. /*
  1491. * Configuration and alternate setting changes must be done in
  1492. * process context, not interrupt context (or so documenation
  1493. * for usb_set_interface() and usb_set_configuration() claim).
  1494. */
  1495. if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
  1496. dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
  1497. __func__, ep->desc.bEndpointAddress);
  1498. return -ENOMEM;
  1499. }
  1500. ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
  1501. new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
  1502. /* If xhci_endpoint_disable() was called for this endpoint, but the
  1503. * xHC hasn't been notified yet through the check_bandwidth() call,
  1504. * this re-adds a new state for the endpoint from the new endpoint
  1505. * descriptors. We must drop and re-add this endpoint, so we leave the
  1506. * drop flags alone.
  1507. */
  1508. new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
  1509. slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
  1510. /* Update the last valid endpoint context, if we just added one past */
  1511. if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) <
  1512. LAST_CTX(last_ctx)) {
  1513. slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
  1514. slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
  1515. }
  1516. new_slot_info = le32_to_cpu(slot_ctx->dev_info);
  1517. /* Store the usb_device pointer for later use */
  1518. ep->hcpriv = udev;
  1519. xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
  1520. (unsigned int) ep->desc.bEndpointAddress,
  1521. udev->slot_id,
  1522. (unsigned int) new_drop_flags,
  1523. (unsigned int) new_add_flags,
  1524. (unsigned int) new_slot_info);
  1525. return 0;
  1526. }
  1527. static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
  1528. {
  1529. struct xhci_input_control_ctx *ctrl_ctx;
  1530. struct xhci_ep_ctx *ep_ctx;
  1531. struct xhci_slot_ctx *slot_ctx;
  1532. int i;
  1533. ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
  1534. if (!ctrl_ctx) {
  1535. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  1536. __func__);
  1537. return;
  1538. }
  1539. /* When a device's add flag and drop flag are zero, any subsequent
  1540. * configure endpoint command will leave that endpoint's state
  1541. * untouched. Make sure we don't leave any old state in the input
  1542. * endpoint contexts.
  1543. */
  1544. ctrl_ctx->drop_flags = 0;
  1545. ctrl_ctx->add_flags = 0;
  1546. slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
  1547. slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
  1548. /* Endpoint 0 is always valid */
  1549. slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
  1550. for (i = 1; i < 31; ++i) {
  1551. ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
  1552. ep_ctx->ep_info = 0;
  1553. ep_ctx->ep_info2 = 0;
  1554. ep_ctx->deq = 0;
  1555. ep_ctx->tx_info = 0;
  1556. }
  1557. }
  1558. static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
  1559. struct usb_device *udev, u32 *cmd_status)
  1560. {
  1561. int ret;
  1562. switch (*cmd_status) {
  1563. case COMP_ENOMEM:
  1564. dev_warn(&udev->dev, "Not enough host controller resources "
  1565. "for new device state.\n");
  1566. ret = -ENOMEM;
  1567. /* FIXME: can we allocate more resources for the HC? */
  1568. break;
  1569. case COMP_BW_ERR:
  1570. case COMP_2ND_BW_ERR:
  1571. dev_warn(&udev->dev, "Not enough bandwidth "
  1572. "for new device state.\n");
  1573. ret = -ENOSPC;
  1574. /* FIXME: can we go back to the old state? */
  1575. break;
  1576. case COMP_TRB_ERR:
  1577. /* the HCD set up something wrong */
  1578. dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
  1579. "add flag = 1, "
  1580. "and endpoint is not disabled.\n");
  1581. ret = -EINVAL;
  1582. break;
  1583. case COMP_DEV_ERR:
  1584. dev_warn(&udev->dev, "ERROR: Incompatible device for endpoint "
  1585. "configure command.\n");
  1586. ret = -ENODEV;
  1587. break;
  1588. case COMP_SUCCESS:
  1589. xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
  1590. "Successful Endpoint Configure command");
  1591. ret = 0;
  1592. break;
  1593. default:
  1594. xhci_err(xhci, "ERROR: unexpected command completion "
  1595. "code 0x%x.\n", *cmd_status);
  1596. ret = -EINVAL;
  1597. break;
  1598. }
  1599. return ret;
  1600. }
  1601. static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
  1602. struct usb_device *udev, u32 *cmd_status)
  1603. {
  1604. int ret;
  1605. struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
  1606. switch (*cmd_status) {
  1607. case COMP_EINVAL:
  1608. dev_warn(&udev->dev, "WARN: xHCI driver setup invalid evaluate "
  1609. "context command.\n");
  1610. ret = -EINVAL;
  1611. break;
  1612. case COMP_EBADSLT:
  1613. dev_warn(&udev->dev, "WARN: slot not enabled for"
  1614. "evaluate context command.\n");
  1615. ret = -EINVAL;
  1616. break;
  1617. case COMP_CTX_STATE:
  1618. dev_warn(&udev->dev, "WARN: invalid context state for "
  1619. "evaluate context command.\n");
  1620. xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
  1621. ret = -EINVAL;
  1622. break;
  1623. case COMP_DEV_ERR:
  1624. dev_warn(&udev->dev, "ERROR: Incompatible device for evaluate "
  1625. "context command.\n");
  1626. ret = -ENODEV;
  1627. break;
  1628. case COMP_MEL_ERR:
  1629. /* Max Exit Latency too large error */
  1630. dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
  1631. ret = -EINVAL;
  1632. break;
  1633. case COMP_SUCCESS:
  1634. xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
  1635. "Successful evaluate context command");
  1636. ret = 0;
  1637. break;
  1638. default:
  1639. xhci_err(xhci, "ERROR: unexpected command completion "
  1640. "code 0x%x.\n", *cmd_status);
  1641. ret = -EINVAL;
  1642. break;
  1643. }
  1644. return ret;
  1645. }
  1646. static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
  1647. struct xhci_input_control_ctx *ctrl_ctx)
  1648. {
  1649. u32 valid_add_flags;
  1650. u32 valid_drop_flags;
  1651. /* Ignore the slot flag (bit 0), and the default control endpoint flag
  1652. * (bit 1). The default control endpoint is added during the Address
  1653. * Device command and is never removed until the slot is disabled.
  1654. */
  1655. valid_add_flags = ctrl_ctx->add_flags >> 2;
  1656. valid_drop_flags = ctrl_ctx->drop_flags >> 2;
  1657. /* Use hweight32 to count the number of ones in the add flags, or
  1658. * number of endpoints added. Don't count endpoints that are changed
  1659. * (both added and dropped).
  1660. */
  1661. return hweight32(valid_add_flags) -
  1662. hweight32(valid_add_flags & valid_drop_flags);
  1663. }
  1664. static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
  1665. struct xhci_input_control_ctx *ctrl_ctx)
  1666. {
  1667. u32 valid_add_flags;
  1668. u32 valid_drop_flags;
  1669. valid_add_flags = ctrl_ctx->add_flags >> 2;
  1670. valid_drop_flags = ctrl_ctx->drop_flags >> 2;
  1671. return hweight32(valid_drop_flags) -
  1672. hweight32(valid_add_flags & valid_drop_flags);
  1673. }
  1674. /*
  1675. * We need to reserve the new number of endpoints before the configure endpoint
  1676. * command completes. We can't subtract the dropped endpoints from the number
  1677. * of active endpoints until the command completes because we can oversubscribe
  1678. * the host in this case:
  1679. *
  1680. * - the first configure endpoint command drops more endpoints than it adds
  1681. * - a second configure endpoint command that adds more endpoints is queued
  1682. * - the first configure endpoint command fails, so the config is unchanged
  1683. * - the second command may succeed, even though there isn't enough resources
  1684. *
  1685. * Must be called with xhci->lock held.
  1686. */
  1687. static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
  1688. struct xhci_input_control_ctx *ctrl_ctx)
  1689. {
  1690. u32 added_eps;
  1691. added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
  1692. if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
  1693. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  1694. "Not enough ep ctxs: "
  1695. "%u active, need to add %u, limit is %u.",
  1696. xhci->num_active_eps, added_eps,
  1697. xhci->limit_active_eps);
  1698. return -ENOMEM;
  1699. }
  1700. xhci->num_active_eps += added_eps;
  1701. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  1702. "Adding %u ep ctxs, %u now active.", added_eps,
  1703. xhci->num_active_eps);
  1704. return 0;
  1705. }
  1706. /*
  1707. * The configure endpoint was failed by the xHC for some other reason, so we
  1708. * need to revert the resources that failed configuration would have used.
  1709. *
  1710. * Must be called with xhci->lock held.
  1711. */
  1712. static void xhci_free_host_resources(struct xhci_hcd *xhci,
  1713. struct xhci_input_control_ctx *ctrl_ctx)
  1714. {
  1715. u32 num_failed_eps;
  1716. num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
  1717. xhci->num_active_eps -= num_failed_eps;
  1718. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  1719. "Removing %u failed ep ctxs, %u now active.",
  1720. num_failed_eps,
  1721. xhci->num_active_eps);
  1722. }
  1723. /*
  1724. * Now that the command has completed, clean up the active endpoint count by
  1725. * subtracting out the endpoints that were dropped (but not changed).
  1726. *
  1727. * Must be called with xhci->lock held.
  1728. */
  1729. static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
  1730. struct xhci_input_control_ctx *ctrl_ctx)
  1731. {
  1732. u32 num_dropped_eps;
  1733. num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
  1734. xhci->num_active_eps -= num_dropped_eps;
  1735. if (num_dropped_eps)
  1736. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  1737. "Removing %u dropped ep ctxs, %u now active.",
  1738. num_dropped_eps,
  1739. xhci->num_active_eps);
  1740. }
  1741. static unsigned int xhci_get_block_size(struct usb_device *udev)
  1742. {
  1743. switch (udev->speed) {
  1744. case USB_SPEED_LOW:
  1745. case USB_SPEED_FULL:
  1746. return FS_BLOCK;
  1747. case USB_SPEED_HIGH:
  1748. return HS_BLOCK;
  1749. case USB_SPEED_SUPER:
  1750. return SS_BLOCK;
  1751. case USB_SPEED_UNKNOWN:
  1752. case USB_SPEED_WIRELESS:
  1753. default:
  1754. /* Should never happen */
  1755. return 1;
  1756. }
  1757. }
  1758. static unsigned int
  1759. xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
  1760. {
  1761. if (interval_bw->overhead[LS_OVERHEAD_TYPE])
  1762. return LS_OVERHEAD;
  1763. if (interval_bw->overhead[FS_OVERHEAD_TYPE])
  1764. return FS_OVERHEAD;
  1765. return HS_OVERHEAD;
  1766. }
  1767. /* If we are changing a LS/FS device under a HS hub,
  1768. * make sure (if we are activating a new TT) that the HS bus has enough
  1769. * bandwidth for this new TT.
  1770. */
  1771. static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
  1772. struct xhci_virt_device *virt_dev,
  1773. int old_active_eps)
  1774. {
  1775. struct xhci_interval_bw_table *bw_table;
  1776. struct xhci_tt_bw_info *tt_info;
  1777. /* Find the bandwidth table for the root port this TT is attached to. */
  1778. bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
  1779. tt_info = virt_dev->tt_info;
  1780. /* If this TT already had active endpoints, the bandwidth for this TT
  1781. * has already been added. Removing all periodic endpoints (and thus
  1782. * making the TT enactive) will only decrease the bandwidth used.
  1783. */
  1784. if (old_active_eps)
  1785. return 0;
  1786. if (old_active_eps == 0 && tt_info->active_eps != 0) {
  1787. if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
  1788. return -ENOMEM;
  1789. return 0;
  1790. }
  1791. /* Not sure why we would have no new active endpoints...
  1792. *
  1793. * Maybe because of an Evaluate Context change for a hub update or a
  1794. * control endpoint 0 max packet size change?
  1795. * FIXME: skip the bandwidth calculation in that case.
  1796. */
  1797. return 0;
  1798. }
  1799. static int xhci_check_ss_bw(struct xhci_hcd *xhci,
  1800. struct xhci_virt_device *virt_dev)
  1801. {
  1802. unsigned int bw_reserved;
  1803. bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
  1804. if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
  1805. return -ENOMEM;
  1806. bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
  1807. if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
  1808. return -ENOMEM;
  1809. return 0;
  1810. }
  1811. /*
  1812. * This algorithm is a very conservative estimate of the worst-case scheduling
  1813. * scenario for any one interval. The hardware dynamically schedules the
  1814. * packets, so we can't tell which microframe could be the limiting factor in
  1815. * the bandwidth scheduling. This only takes into account periodic endpoints.
  1816. *
  1817. * Obviously, we can't solve an NP complete problem to find the minimum worst
  1818. * case scenario. Instead, we come up with an estimate that is no less than
  1819. * the worst case bandwidth used for any one microframe, but may be an
  1820. * over-estimate.
  1821. *
  1822. * We walk the requirements for each endpoint by interval, starting with the
  1823. * smallest interval, and place packets in the schedule where there is only one
  1824. * possible way to schedule packets for that interval. In order to simplify
  1825. * this algorithm, we record the largest max packet size for each interval, and
  1826. * assume all packets will be that size.
  1827. *
  1828. * For interval 0, we obviously must schedule all packets for each interval.
  1829. * The bandwidth for interval 0 is just the amount of data to be transmitted
  1830. * (the sum of all max ESIT payload sizes, plus any overhead per packet times
  1831. * the number of packets).
  1832. *
  1833. * For interval 1, we have two possible microframes to schedule those packets
  1834. * in. For this algorithm, if we can schedule the same number of packets for
  1835. * each possible scheduling opportunity (each microframe), we will do so. The
  1836. * remaining number of packets will be saved to be transmitted in the gaps in
  1837. * the next interval's scheduling sequence.
  1838. *
  1839. * As we move those remaining packets to be scheduled with interval 2 packets,
  1840. * we have to double the number of remaining packets to transmit. This is
  1841. * because the intervals are actually powers of 2, and we would be transmitting
  1842. * the previous interval's packets twice in this interval. We also have to be
  1843. * sure that when we look at the largest max packet size for this interval, we
  1844. * also look at the largest max packet size for the remaining packets and take
  1845. * the greater of the two.
  1846. *
  1847. * The algorithm continues to evenly distribute packets in each scheduling
  1848. * opportunity, and push the remaining packets out, until we get to the last
  1849. * interval. Then those packets and their associated overhead are just added
  1850. * to the bandwidth used.
  1851. */
  1852. static int xhci_check_bw_table(struct xhci_hcd *xhci,
  1853. struct xhci_virt_device *virt_dev,
  1854. int old_active_eps)
  1855. {
  1856. unsigned int bw_reserved;
  1857. unsigned int max_bandwidth;
  1858. unsigned int bw_used;
  1859. unsigned int block_size;
  1860. struct xhci_interval_bw_table *bw_table;
  1861. unsigned int packet_size = 0;
  1862. unsigned int overhead = 0;
  1863. unsigned int packets_transmitted = 0;
  1864. unsigned int packets_remaining = 0;
  1865. unsigned int i;
  1866. if (virt_dev->udev->speed == USB_SPEED_SUPER)
  1867. return xhci_check_ss_bw(xhci, virt_dev);
  1868. if (virt_dev->udev->speed == USB_SPEED_HIGH) {
  1869. max_bandwidth = HS_BW_LIMIT;
  1870. /* Convert percent of bus BW reserved to blocks reserved */
  1871. bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
  1872. } else {
  1873. max_bandwidth = FS_BW_LIMIT;
  1874. bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
  1875. }
  1876. bw_table = virt_dev->bw_table;
  1877. /* We need to translate the max packet size and max ESIT payloads into
  1878. * the units the hardware uses.
  1879. */
  1880. block_size = xhci_get_block_size(virt_dev->udev);
  1881. /* If we are manipulating a LS/FS device under a HS hub, double check
  1882. * that the HS bus has enough bandwidth if we are activing a new TT.
  1883. */
  1884. if (virt_dev->tt_info) {
  1885. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  1886. "Recalculating BW for rootport %u",
  1887. virt_dev->real_port);
  1888. if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
  1889. xhci_warn(xhci, "Not enough bandwidth on HS bus for "
  1890. "newly activated TT.\n");
  1891. return -ENOMEM;
  1892. }
  1893. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  1894. "Recalculating BW for TT slot %u port %u",
  1895. virt_dev->tt_info->slot_id,
  1896. virt_dev->tt_info->ttport);
  1897. } else {
  1898. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  1899. "Recalculating BW for rootport %u",
  1900. virt_dev->real_port);
  1901. }
  1902. /* Add in how much bandwidth will be used for interval zero, or the
  1903. * rounded max ESIT payload + number of packets * largest overhead.
  1904. */
  1905. bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
  1906. bw_table->interval_bw[0].num_packets *
  1907. xhci_get_largest_overhead(&bw_table->interval_bw[0]);
  1908. for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
  1909. unsigned int bw_added;
  1910. unsigned int largest_mps;
  1911. unsigned int interval_overhead;
  1912. /*
  1913. * How many packets could we transmit in this interval?
  1914. * If packets didn't fit in the previous interval, we will need
  1915. * to transmit that many packets twice within this interval.
  1916. */
  1917. packets_remaining = 2 * packets_remaining +
  1918. bw_table->interval_bw[i].num_packets;
  1919. /* Find the largest max packet size of this or the previous
  1920. * interval.
  1921. */
  1922. if (list_empty(&bw_table->interval_bw[i].endpoints))
  1923. largest_mps = 0;
  1924. else {
  1925. struct xhci_virt_ep *virt_ep;
  1926. struct list_head *ep_entry;
  1927. ep_entry = bw_table->interval_bw[i].endpoints.next;
  1928. virt_ep = list_entry(ep_entry,
  1929. struct xhci_virt_ep, bw_endpoint_list);
  1930. /* Convert to blocks, rounding up */
  1931. largest_mps = DIV_ROUND_UP(
  1932. virt_ep->bw_info.max_packet_size,
  1933. block_size);
  1934. }
  1935. if (largest_mps > packet_size)
  1936. packet_size = largest_mps;
  1937. /* Use the larger overhead of this or the previous interval. */
  1938. interval_overhead = xhci_get_largest_overhead(
  1939. &bw_table->interval_bw[i]);
  1940. if (interval_overhead > overhead)
  1941. overhead = interval_overhead;
  1942. /* How many packets can we evenly distribute across
  1943. * (1 << (i + 1)) possible scheduling opportunities?
  1944. */
  1945. packets_transmitted = packets_remaining >> (i + 1);
  1946. /* Add in the bandwidth used for those scheduled packets */
  1947. bw_added = packets_transmitted * (overhead + packet_size);
  1948. /* How many packets do we have remaining to transmit? */
  1949. packets_remaining = packets_remaining % (1 << (i + 1));
  1950. /* What largest max packet size should those packets have? */
  1951. /* If we've transmitted all packets, don't carry over the
  1952. * largest packet size.
  1953. */
  1954. if (packets_remaining == 0) {
  1955. packet_size = 0;
  1956. overhead = 0;
  1957. } else if (packets_transmitted > 0) {
  1958. /* Otherwise if we do have remaining packets, and we've
  1959. * scheduled some packets in this interval, take the
  1960. * largest max packet size from endpoints with this
  1961. * interval.
  1962. */
  1963. packet_size = largest_mps;
  1964. overhead = interval_overhead;
  1965. }
  1966. /* Otherwise carry over packet_size and overhead from the last
  1967. * time we had a remainder.
  1968. */
  1969. bw_used += bw_added;
  1970. if (bw_used > max_bandwidth) {
  1971. xhci_warn(xhci, "Not enough bandwidth. "
  1972. "Proposed: %u, Max: %u\n",
  1973. bw_used, max_bandwidth);
  1974. return -ENOMEM;
  1975. }
  1976. }
  1977. /*
  1978. * Ok, we know we have some packets left over after even-handedly
  1979. * scheduling interval 15. We don't know which microframes they will
  1980. * fit into, so we over-schedule and say they will be scheduled every
  1981. * microframe.
  1982. */
  1983. if (packets_remaining > 0)
  1984. bw_used += overhead + packet_size;
  1985. if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
  1986. unsigned int port_index = virt_dev->real_port - 1;
  1987. /* OK, we're manipulating a HS device attached to a
  1988. * root port bandwidth domain. Include the number of active TTs
  1989. * in the bandwidth used.
  1990. */
  1991. bw_used += TT_HS_OVERHEAD *
  1992. xhci->rh_bw[port_index].num_active_tts;
  1993. }
  1994. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  1995. "Final bandwidth: %u, Limit: %u, Reserved: %u, "
  1996. "Available: %u " "percent",
  1997. bw_used, max_bandwidth, bw_reserved,
  1998. (max_bandwidth - bw_used - bw_reserved) * 100 /
  1999. max_bandwidth);
  2000. bw_used += bw_reserved;
  2001. if (bw_used > max_bandwidth) {
  2002. xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
  2003. bw_used, max_bandwidth);
  2004. return -ENOMEM;
  2005. }
  2006. bw_table->bw_used = bw_used;
  2007. return 0;
  2008. }
  2009. static bool xhci_is_async_ep(unsigned int ep_type)
  2010. {
  2011. return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
  2012. ep_type != ISOC_IN_EP &&
  2013. ep_type != INT_IN_EP);
  2014. }
  2015. static bool xhci_is_sync_in_ep(unsigned int ep_type)
  2016. {
  2017. return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
  2018. }
  2019. static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
  2020. {
  2021. unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
  2022. if (ep_bw->ep_interval == 0)
  2023. return SS_OVERHEAD_BURST +
  2024. (ep_bw->mult * ep_bw->num_packets *
  2025. (SS_OVERHEAD + mps));
  2026. return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
  2027. (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
  2028. 1 << ep_bw->ep_interval);
  2029. }
  2030. void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
  2031. struct xhci_bw_info *ep_bw,
  2032. struct xhci_interval_bw_table *bw_table,
  2033. struct usb_device *udev,
  2034. struct xhci_virt_ep *virt_ep,
  2035. struct xhci_tt_bw_info *tt_info)
  2036. {
  2037. struct xhci_interval_bw *interval_bw;
  2038. int normalized_interval;
  2039. if (xhci_is_async_ep(ep_bw->type))
  2040. return;
  2041. if (udev->speed == USB_SPEED_SUPER) {
  2042. if (xhci_is_sync_in_ep(ep_bw->type))
  2043. xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
  2044. xhci_get_ss_bw_consumed(ep_bw);
  2045. else
  2046. xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
  2047. xhci_get_ss_bw_consumed(ep_bw);
  2048. return;
  2049. }
  2050. /* SuperSpeed endpoints never get added to intervals in the table, so
  2051. * this check is only valid for HS/FS/LS devices.
  2052. */
  2053. if (list_empty(&virt_ep->bw_endpoint_list))
  2054. return;
  2055. /* For LS/FS devices, we need to translate the interval expressed in
  2056. * microframes to frames.
  2057. */
  2058. if (udev->speed == USB_SPEED_HIGH)
  2059. normalized_interval = ep_bw->ep_interval;
  2060. else
  2061. normalized_interval = ep_bw->ep_interval - 3;
  2062. if (normalized_interval == 0)
  2063. bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
  2064. interval_bw = &bw_table->interval_bw[normalized_interval];
  2065. interval_bw->num_packets -= ep_bw->num_packets;
  2066. switch (udev->speed) {
  2067. case USB_SPEED_LOW:
  2068. interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
  2069. break;
  2070. case USB_SPEED_FULL:
  2071. interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
  2072. break;
  2073. case USB_SPEED_HIGH:
  2074. interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
  2075. break;
  2076. case USB_SPEED_SUPER:
  2077. case USB_SPEED_UNKNOWN:
  2078. case USB_SPEED_WIRELESS:
  2079. /* Should never happen because only LS/FS/HS endpoints will get
  2080. * added to the endpoint list.
  2081. */
  2082. return;
  2083. }
  2084. if (tt_info)
  2085. tt_info->active_eps -= 1;
  2086. list_del_init(&virt_ep->bw_endpoint_list);
  2087. }
  2088. static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
  2089. struct xhci_bw_info *ep_bw,
  2090. struct xhci_interval_bw_table *bw_table,
  2091. struct usb_device *udev,
  2092. struct xhci_virt_ep *virt_ep,
  2093. struct xhci_tt_bw_info *tt_info)
  2094. {
  2095. struct xhci_interval_bw *interval_bw;
  2096. struct xhci_virt_ep *smaller_ep;
  2097. int normalized_interval;
  2098. if (xhci_is_async_ep(ep_bw->type))
  2099. return;
  2100. if (udev->speed == USB_SPEED_SUPER) {
  2101. if (xhci_is_sync_in_ep(ep_bw->type))
  2102. xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
  2103. xhci_get_ss_bw_consumed(ep_bw);
  2104. else
  2105. xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
  2106. xhci_get_ss_bw_consumed(ep_bw);
  2107. return;
  2108. }
  2109. /* For LS/FS devices, we need to translate the interval expressed in
  2110. * microframes to frames.
  2111. */
  2112. if (udev->speed == USB_SPEED_HIGH)
  2113. normalized_interval = ep_bw->ep_interval;
  2114. else
  2115. normalized_interval = ep_bw->ep_interval - 3;
  2116. if (normalized_interval == 0)
  2117. bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
  2118. interval_bw = &bw_table->interval_bw[normalized_interval];
  2119. interval_bw->num_packets += ep_bw->num_packets;
  2120. switch (udev->speed) {
  2121. case USB_SPEED_LOW:
  2122. interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
  2123. break;
  2124. case USB_SPEED_FULL:
  2125. interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
  2126. break;
  2127. case USB_SPEED_HIGH:
  2128. interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
  2129. break;
  2130. case USB_SPEED_SUPER:
  2131. case USB_SPEED_UNKNOWN:
  2132. case USB_SPEED_WIRELESS:
  2133. /* Should never happen because only LS/FS/HS endpoints will get
  2134. * added to the endpoint list.
  2135. */
  2136. return;
  2137. }
  2138. if (tt_info)
  2139. tt_info->active_eps += 1;
  2140. /* Insert the endpoint into the list, largest max packet size first. */
  2141. list_for_each_entry(smaller_ep, &interval_bw->endpoints,
  2142. bw_endpoint_list) {
  2143. if (ep_bw->max_packet_size >=
  2144. smaller_ep->bw_info.max_packet_size) {
  2145. /* Add the new ep before the smaller endpoint */
  2146. list_add_tail(&virt_ep->bw_endpoint_list,
  2147. &smaller_ep->bw_endpoint_list);
  2148. return;
  2149. }
  2150. }
  2151. /* Add the new endpoint at the end of the list. */
  2152. list_add_tail(&virt_ep->bw_endpoint_list,
  2153. &interval_bw->endpoints);
  2154. }
  2155. void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
  2156. struct xhci_virt_device *virt_dev,
  2157. int old_active_eps)
  2158. {
  2159. struct xhci_root_port_bw_info *rh_bw_info;
  2160. if (!virt_dev->tt_info)
  2161. return;
  2162. rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
  2163. if (old_active_eps == 0 &&
  2164. virt_dev->tt_info->active_eps != 0) {
  2165. rh_bw_info->num_active_tts += 1;
  2166. rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
  2167. } else if (old_active_eps != 0 &&
  2168. virt_dev->tt_info->active_eps == 0) {
  2169. rh_bw_info->num_active_tts -= 1;
  2170. rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
  2171. }
  2172. }
  2173. static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
  2174. struct xhci_virt_device *virt_dev,
  2175. struct xhci_container_ctx *in_ctx)
  2176. {
  2177. struct xhci_bw_info ep_bw_info[31];
  2178. int i;
  2179. struct xhci_input_control_ctx *ctrl_ctx;
  2180. int old_active_eps = 0;
  2181. if (virt_dev->tt_info)
  2182. old_active_eps = virt_dev->tt_info->active_eps;
  2183. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  2184. if (!ctrl_ctx) {
  2185. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  2186. __func__);
  2187. return -ENOMEM;
  2188. }
  2189. for (i = 0; i < 31; i++) {
  2190. if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
  2191. continue;
  2192. /* Make a copy of the BW info in case we need to revert this */
  2193. memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
  2194. sizeof(ep_bw_info[i]));
  2195. /* Drop the endpoint from the interval table if the endpoint is
  2196. * being dropped or changed.
  2197. */
  2198. if (EP_IS_DROPPED(ctrl_ctx, i))
  2199. xhci_drop_ep_from_interval_table(xhci,
  2200. &virt_dev->eps[i].bw_info,
  2201. virt_dev->bw_table,
  2202. virt_dev->udev,
  2203. &virt_dev->eps[i],
  2204. virt_dev->tt_info);
  2205. }
  2206. /* Overwrite the information stored in the endpoints' bw_info */
  2207. xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
  2208. for (i = 0; i < 31; i++) {
  2209. /* Add any changed or added endpoints to the interval table */
  2210. if (EP_IS_ADDED(ctrl_ctx, i))
  2211. xhci_add_ep_to_interval_table(xhci,
  2212. &virt_dev->eps[i].bw_info,
  2213. virt_dev->bw_table,
  2214. virt_dev->udev,
  2215. &virt_dev->eps[i],
  2216. virt_dev->tt_info);
  2217. }
  2218. if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
  2219. /* Ok, this fits in the bandwidth we have.
  2220. * Update the number of active TTs.
  2221. */
  2222. xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
  2223. return 0;
  2224. }
  2225. /* We don't have enough bandwidth for this, revert the stored info. */
  2226. for (i = 0; i < 31; i++) {
  2227. if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
  2228. continue;
  2229. /* Drop the new copies of any added or changed endpoints from
  2230. * the interval table.
  2231. */
  2232. if (EP_IS_ADDED(ctrl_ctx, i)) {
  2233. xhci_drop_ep_from_interval_table(xhci,
  2234. &virt_dev->eps[i].bw_info,
  2235. virt_dev->bw_table,
  2236. virt_dev->udev,
  2237. &virt_dev->eps[i],
  2238. virt_dev->tt_info);
  2239. }
  2240. /* Revert the endpoint back to its old information */
  2241. memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
  2242. sizeof(ep_bw_info[i]));
  2243. /* Add any changed or dropped endpoints back into the table */
  2244. if (EP_IS_DROPPED(ctrl_ctx, i))
  2245. xhci_add_ep_to_interval_table(xhci,
  2246. &virt_dev->eps[i].bw_info,
  2247. virt_dev->bw_table,
  2248. virt_dev->udev,
  2249. &virt_dev->eps[i],
  2250. virt_dev->tt_info);
  2251. }
  2252. return -ENOMEM;
  2253. }
  2254. /* Issue a configure endpoint command or evaluate context command
  2255. * and wait for it to finish.
  2256. */
  2257. static int xhci_configure_endpoint(struct xhci_hcd *xhci,
  2258. struct usb_device *udev,
  2259. struct xhci_command *command,
  2260. bool ctx_change, bool must_succeed)
  2261. {
  2262. int ret;
  2263. int timeleft;
  2264. unsigned long flags;
  2265. struct xhci_container_ctx *in_ctx;
  2266. struct xhci_input_control_ctx *ctrl_ctx;
  2267. struct completion *cmd_completion;
  2268. u32 *cmd_status;
  2269. struct xhci_virt_device *virt_dev;
  2270. union xhci_trb *cmd_trb;
  2271. spin_lock_irqsave(&xhci->lock, flags);
  2272. virt_dev = xhci->devs[udev->slot_id];
  2273. if (command)
  2274. in_ctx = command->in_ctx;
  2275. else
  2276. in_ctx = virt_dev->in_ctx;
  2277. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  2278. if (!ctrl_ctx) {
  2279. spin_unlock_irqrestore(&xhci->lock, flags);
  2280. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  2281. __func__);
  2282. return -ENOMEM;
  2283. }
  2284. if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
  2285. xhci_reserve_host_resources(xhci, ctrl_ctx)) {
  2286. spin_unlock_irqrestore(&xhci->lock, flags);
  2287. xhci_warn(xhci, "Not enough host resources, "
  2288. "active endpoint contexts = %u\n",
  2289. xhci->num_active_eps);
  2290. return -ENOMEM;
  2291. }
  2292. if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
  2293. xhci_reserve_bandwidth(xhci, virt_dev, in_ctx)) {
  2294. if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
  2295. xhci_free_host_resources(xhci, ctrl_ctx);
  2296. spin_unlock_irqrestore(&xhci->lock, flags);
  2297. xhci_warn(xhci, "Not enough bandwidth\n");
  2298. return -ENOMEM;
  2299. }
  2300. if (command) {
  2301. cmd_completion = command->completion;
  2302. cmd_status = &command->status;
  2303. command->command_trb = xhci->cmd_ring->enqueue;
  2304. /* Enqueue pointer can be left pointing to the link TRB,
  2305. * we must handle that
  2306. */
  2307. if (TRB_TYPE_LINK_LE32(command->command_trb->link.control))
  2308. command->command_trb =
  2309. xhci->cmd_ring->enq_seg->next->trbs;
  2310. list_add_tail(&command->cmd_list, &virt_dev->cmd_list);
  2311. } else {
  2312. cmd_completion = &virt_dev->cmd_completion;
  2313. cmd_status = &virt_dev->cmd_status;
  2314. }
  2315. init_completion(cmd_completion);
  2316. cmd_trb = xhci->cmd_ring->dequeue;
  2317. if (!ctx_change)
  2318. ret = xhci_queue_configure_endpoint(xhci, in_ctx->dma,
  2319. udev->slot_id, must_succeed);
  2320. else
  2321. ret = xhci_queue_evaluate_context(xhci, in_ctx->dma,
  2322. udev->slot_id, must_succeed);
  2323. if (ret < 0) {
  2324. if (command)
  2325. list_del(&command->cmd_list);
  2326. if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
  2327. xhci_free_host_resources(xhci, ctrl_ctx);
  2328. spin_unlock_irqrestore(&xhci->lock, flags);
  2329. xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
  2330. "FIXME allocate a new ring segment");
  2331. return -ENOMEM;
  2332. }
  2333. xhci_ring_cmd_db(xhci);
  2334. spin_unlock_irqrestore(&xhci->lock, flags);
  2335. /* Wait for the configure endpoint command to complete */
  2336. timeleft = wait_for_completion_interruptible_timeout(
  2337. cmd_completion,
  2338. XHCI_CMD_DEFAULT_TIMEOUT);
  2339. if (timeleft <= 0) {
  2340. xhci_warn(xhci, "%s while waiting for %s command\n",
  2341. timeleft == 0 ? "Timeout" : "Signal",
  2342. ctx_change == 0 ?
  2343. "configure endpoint" :
  2344. "evaluate context");
  2345. /* cancel the configure endpoint command */
  2346. ret = xhci_cancel_cmd(xhci, command, cmd_trb);
  2347. if (ret < 0)
  2348. return ret;
  2349. return -ETIME;
  2350. }
  2351. if (!ctx_change)
  2352. ret = xhci_configure_endpoint_result(xhci, udev, cmd_status);
  2353. else
  2354. ret = xhci_evaluate_context_result(xhci, udev, cmd_status);
  2355. if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
  2356. spin_lock_irqsave(&xhci->lock, flags);
  2357. /* If the command failed, remove the reserved resources.
  2358. * Otherwise, clean up the estimate to include dropped eps.
  2359. */
  2360. if (ret)
  2361. xhci_free_host_resources(xhci, ctrl_ctx);
  2362. else
  2363. xhci_finish_resource_reservation(xhci, ctrl_ctx);
  2364. spin_unlock_irqrestore(&xhci->lock, flags);
  2365. }
  2366. return ret;
  2367. }
  2368. /* Called after one or more calls to xhci_add_endpoint() or
  2369. * xhci_drop_endpoint(). If this call fails, the USB core is expected
  2370. * to call xhci_reset_bandwidth().
  2371. *
  2372. * Since we are in the middle of changing either configuration or
  2373. * installing a new alt setting, the USB core won't allow URBs to be
  2374. * enqueued for any endpoint on the old config or interface. Nothing
  2375. * else should be touching the xhci->devs[slot_id] structure, so we
  2376. * don't need to take the xhci->lock for manipulating that.
  2377. */
  2378. int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
  2379. {
  2380. int i;
  2381. int ret = 0;
  2382. struct xhci_hcd *xhci;
  2383. struct xhci_virt_device *virt_dev;
  2384. struct xhci_input_control_ctx *ctrl_ctx;
  2385. struct xhci_slot_ctx *slot_ctx;
  2386. ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
  2387. if (ret <= 0)
  2388. return ret;
  2389. xhci = hcd_to_xhci(hcd);
  2390. if (xhci->xhc_state & XHCI_STATE_DYING)
  2391. return -ENODEV;
  2392. xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
  2393. virt_dev = xhci->devs[udev->slot_id];
  2394. /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
  2395. ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
  2396. if (!ctrl_ctx) {
  2397. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  2398. __func__);
  2399. return -ENOMEM;
  2400. }
  2401. ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
  2402. ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
  2403. ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
  2404. /* Don't issue the command if there's no endpoints to update. */
  2405. if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
  2406. ctrl_ctx->drop_flags == 0)
  2407. return 0;
  2408. xhci_dbg(xhci, "New Input Control Context:\n");
  2409. slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
  2410. xhci_dbg_ctx(xhci, virt_dev->in_ctx,
  2411. LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
  2412. ret = xhci_configure_endpoint(xhci, udev, NULL,
  2413. false, false);
  2414. if (ret) {
  2415. /* Callee should call reset_bandwidth() */
  2416. return ret;
  2417. }
  2418. xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
  2419. xhci_dbg_ctx(xhci, virt_dev->out_ctx,
  2420. LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
  2421. /* Free any rings that were dropped, but not changed. */
  2422. for (i = 1; i < 31; ++i) {
  2423. if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
  2424. !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))))
  2425. xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
  2426. }
  2427. xhci_zero_in_ctx(xhci, virt_dev);
  2428. /*
  2429. * Install any rings for completely new endpoints or changed endpoints,
  2430. * and free or cache any old rings from changed endpoints.
  2431. */
  2432. for (i = 1; i < 31; ++i) {
  2433. if (!virt_dev->eps[i].new_ring)
  2434. continue;
  2435. /* Only cache or free the old ring if it exists.
  2436. * It may not if this is the first add of an endpoint.
  2437. */
  2438. if (virt_dev->eps[i].ring) {
  2439. xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
  2440. }
  2441. virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
  2442. virt_dev->eps[i].new_ring = NULL;
  2443. }
  2444. return ret;
  2445. }
  2446. void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
  2447. {
  2448. struct xhci_hcd *xhci;
  2449. struct xhci_virt_device *virt_dev;
  2450. int i, ret;
  2451. ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
  2452. if (ret <= 0)
  2453. return;
  2454. xhci = hcd_to_xhci(hcd);
  2455. xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
  2456. virt_dev = xhci->devs[udev->slot_id];
  2457. /* Free any rings allocated for added endpoints */
  2458. for (i = 0; i < 31; ++i) {
  2459. if (virt_dev->eps[i].new_ring) {
  2460. xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
  2461. virt_dev->eps[i].new_ring = NULL;
  2462. }
  2463. }
  2464. xhci_zero_in_ctx(xhci, virt_dev);
  2465. }
  2466. static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
  2467. struct xhci_container_ctx *in_ctx,
  2468. struct xhci_container_ctx *out_ctx,
  2469. struct xhci_input_control_ctx *ctrl_ctx,
  2470. u32 add_flags, u32 drop_flags)
  2471. {
  2472. ctrl_ctx->add_flags = cpu_to_le32(add_flags);
  2473. ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
  2474. xhci_slot_copy(xhci, in_ctx, out_ctx);
  2475. ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
  2476. xhci_dbg(xhci, "Input Context:\n");
  2477. xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
  2478. }
  2479. static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
  2480. unsigned int slot_id, unsigned int ep_index,
  2481. struct xhci_dequeue_state *deq_state)
  2482. {
  2483. struct xhci_input_control_ctx *ctrl_ctx;
  2484. struct xhci_container_ctx *in_ctx;
  2485. struct xhci_ep_ctx *ep_ctx;
  2486. u32 added_ctxs;
  2487. dma_addr_t addr;
  2488. in_ctx = xhci->devs[slot_id]->in_ctx;
  2489. ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
  2490. if (!ctrl_ctx) {
  2491. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  2492. __func__);
  2493. return;
  2494. }
  2495. xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
  2496. xhci->devs[slot_id]->out_ctx, ep_index);
  2497. ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
  2498. addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
  2499. deq_state->new_deq_ptr);
  2500. if (addr == 0) {
  2501. xhci_warn(xhci, "WARN Cannot submit config ep after "
  2502. "reset ep command\n");
  2503. xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
  2504. deq_state->new_deq_seg,
  2505. deq_state->new_deq_ptr);
  2506. return;
  2507. }
  2508. ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
  2509. added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
  2510. xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
  2511. xhci->devs[slot_id]->out_ctx, ctrl_ctx,
  2512. added_ctxs, added_ctxs);
  2513. }
  2514. void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
  2515. struct usb_device *udev, unsigned int ep_index)
  2516. {
  2517. struct xhci_dequeue_state deq_state;
  2518. struct xhci_virt_ep *ep;
  2519. xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
  2520. "Cleaning up stalled endpoint ring");
  2521. ep = &xhci->devs[udev->slot_id]->eps[ep_index];
  2522. /* We need to move the HW's dequeue pointer past this TD,
  2523. * or it will attempt to resend it on the next doorbell ring.
  2524. */
  2525. xhci_find_new_dequeue_state(xhci, udev->slot_id,
  2526. ep_index, ep->stopped_stream, ep->stopped_td,
  2527. &deq_state);
  2528. /* HW with the reset endpoint quirk will use the saved dequeue state to
  2529. * issue a configure endpoint command later.
  2530. */
  2531. if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
  2532. xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
  2533. "Queueing new dequeue state");
  2534. xhci_queue_new_dequeue_state(xhci, udev->slot_id,
  2535. ep_index, ep->stopped_stream, &deq_state);
  2536. } else {
  2537. /* Better hope no one uses the input context between now and the
  2538. * reset endpoint completion!
  2539. * XXX: No idea how this hardware will react when stream rings
  2540. * are enabled.
  2541. */
  2542. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  2543. "Setting up input context for "
  2544. "configure endpoint command");
  2545. xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
  2546. ep_index, &deq_state);
  2547. }
  2548. }
  2549. /* Deal with stalled endpoints. The core should have sent the control message
  2550. * to clear the halt condition. However, we need to make the xHCI hardware
  2551. * reset its sequence number, since a device will expect a sequence number of
  2552. * zero after the halt condition is cleared.
  2553. * Context: in_interrupt
  2554. */
  2555. void xhci_endpoint_reset(struct usb_hcd *hcd,
  2556. struct usb_host_endpoint *ep)
  2557. {
  2558. struct xhci_hcd *xhci;
  2559. struct usb_device *udev;
  2560. unsigned int ep_index;
  2561. unsigned long flags;
  2562. int ret;
  2563. struct xhci_virt_ep *virt_ep;
  2564. xhci = hcd_to_xhci(hcd);
  2565. udev = (struct usb_device *) ep->hcpriv;
  2566. /* Called with a root hub endpoint (or an endpoint that wasn't added
  2567. * with xhci_add_endpoint()
  2568. */
  2569. if (!ep->hcpriv)
  2570. return;
  2571. ep_index = xhci_get_endpoint_index(&ep->desc);
  2572. virt_ep = &xhci->devs[udev->slot_id]->eps[ep_index];
  2573. if (!virt_ep->stopped_td) {
  2574. xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
  2575. "Endpoint 0x%x not halted, refusing to reset.",
  2576. ep->desc.bEndpointAddress);
  2577. return;
  2578. }
  2579. if (usb_endpoint_xfer_control(&ep->desc)) {
  2580. xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
  2581. "Control endpoint stall already handled.");
  2582. return;
  2583. }
  2584. xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
  2585. "Queueing reset endpoint command");
  2586. spin_lock_irqsave(&xhci->lock, flags);
  2587. ret = xhci_queue_reset_ep(xhci, udev->slot_id, ep_index);
  2588. /*
  2589. * Can't change the ring dequeue pointer until it's transitioned to the
  2590. * stopped state, which is only upon a successful reset endpoint
  2591. * command. Better hope that last command worked!
  2592. */
  2593. if (!ret) {
  2594. xhci_cleanup_stalled_ring(xhci, udev, ep_index);
  2595. kfree(virt_ep->stopped_td);
  2596. xhci_ring_cmd_db(xhci);
  2597. }
  2598. virt_ep->stopped_td = NULL;
  2599. virt_ep->stopped_trb = NULL;
  2600. virt_ep->stopped_stream = 0;
  2601. spin_unlock_irqrestore(&xhci->lock, flags);
  2602. if (ret)
  2603. xhci_warn(xhci, "FIXME allocate a new ring segment\n");
  2604. }
  2605. static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
  2606. struct usb_device *udev, struct usb_host_endpoint *ep,
  2607. unsigned int slot_id)
  2608. {
  2609. int ret;
  2610. unsigned int ep_index;
  2611. unsigned int ep_state;
  2612. if (!ep)
  2613. return -EINVAL;
  2614. ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
  2615. if (ret <= 0)
  2616. return -EINVAL;
  2617. if (ep->ss_ep_comp.bmAttributes == 0) {
  2618. xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
  2619. " descriptor for ep 0x%x does not support streams\n",
  2620. ep->desc.bEndpointAddress);
  2621. return -EINVAL;
  2622. }
  2623. ep_index = xhci_get_endpoint_index(&ep->desc);
  2624. ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
  2625. if (ep_state & EP_HAS_STREAMS ||
  2626. ep_state & EP_GETTING_STREAMS) {
  2627. xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
  2628. "already has streams set up.\n",
  2629. ep->desc.bEndpointAddress);
  2630. xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
  2631. "dynamic stream context array reallocation.\n");
  2632. return -EINVAL;
  2633. }
  2634. if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
  2635. xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
  2636. "endpoint 0x%x; URBs are pending.\n",
  2637. ep->desc.bEndpointAddress);
  2638. return -EINVAL;
  2639. }
  2640. return 0;
  2641. }
  2642. static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
  2643. unsigned int *num_streams, unsigned int *num_stream_ctxs)
  2644. {
  2645. unsigned int max_streams;
  2646. /* The stream context array size must be a power of two */
  2647. *num_stream_ctxs = roundup_pow_of_two(*num_streams);
  2648. /*
  2649. * Find out how many primary stream array entries the host controller
  2650. * supports. Later we may use secondary stream arrays (similar to 2nd
  2651. * level page entries), but that's an optional feature for xHCI host
  2652. * controllers. xHCs must support at least 4 stream IDs.
  2653. */
  2654. max_streams = HCC_MAX_PSA(xhci->hcc_params);
  2655. if (*num_stream_ctxs > max_streams) {
  2656. xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
  2657. max_streams);
  2658. *num_stream_ctxs = max_streams;
  2659. *num_streams = max_streams;
  2660. }
  2661. }
  2662. /* Returns an error code if one of the endpoint already has streams.
  2663. * This does not change any data structures, it only checks and gathers
  2664. * information.
  2665. */
  2666. static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
  2667. struct usb_device *udev,
  2668. struct usb_host_endpoint **eps, unsigned int num_eps,
  2669. unsigned int *num_streams, u32 *changed_ep_bitmask)
  2670. {
  2671. unsigned int max_streams;
  2672. unsigned int endpoint_flag;
  2673. int i;
  2674. int ret;
  2675. for (i = 0; i < num_eps; i++) {
  2676. ret = xhci_check_streams_endpoint(xhci, udev,
  2677. eps[i], udev->slot_id);
  2678. if (ret < 0)
  2679. return ret;
  2680. max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
  2681. if (max_streams < (*num_streams - 1)) {
  2682. xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
  2683. eps[i]->desc.bEndpointAddress,
  2684. max_streams);
  2685. *num_streams = max_streams+1;
  2686. }
  2687. endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
  2688. if (*changed_ep_bitmask & endpoint_flag)
  2689. return -EINVAL;
  2690. *changed_ep_bitmask |= endpoint_flag;
  2691. }
  2692. return 0;
  2693. }
  2694. static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
  2695. struct usb_device *udev,
  2696. struct usb_host_endpoint **eps, unsigned int num_eps)
  2697. {
  2698. u32 changed_ep_bitmask = 0;
  2699. unsigned int slot_id;
  2700. unsigned int ep_index;
  2701. unsigned int ep_state;
  2702. int i;
  2703. slot_id = udev->slot_id;
  2704. if (!xhci->devs[slot_id])
  2705. return 0;
  2706. for (i = 0; i < num_eps; i++) {
  2707. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  2708. ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
  2709. /* Are streams already being freed for the endpoint? */
  2710. if (ep_state & EP_GETTING_NO_STREAMS) {
  2711. xhci_warn(xhci, "WARN Can't disable streams for "
  2712. "endpoint 0x%x, "
  2713. "streams are being disabled already\n",
  2714. eps[i]->desc.bEndpointAddress);
  2715. return 0;
  2716. }
  2717. /* Are there actually any streams to free? */
  2718. if (!(ep_state & EP_HAS_STREAMS) &&
  2719. !(ep_state & EP_GETTING_STREAMS)) {
  2720. xhci_warn(xhci, "WARN Can't disable streams for "
  2721. "endpoint 0x%x, "
  2722. "streams are already disabled!\n",
  2723. eps[i]->desc.bEndpointAddress);
  2724. xhci_warn(xhci, "WARN xhci_free_streams() called "
  2725. "with non-streams endpoint\n");
  2726. return 0;
  2727. }
  2728. changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
  2729. }
  2730. return changed_ep_bitmask;
  2731. }
  2732. /*
  2733. * The USB device drivers use this function (though the HCD interface in USB
  2734. * core) to prepare a set of bulk endpoints to use streams. Streams are used to
  2735. * coordinate mass storage command queueing across multiple endpoints (basically
  2736. * a stream ID == a task ID).
  2737. *
  2738. * Setting up streams involves allocating the same size stream context array
  2739. * for each endpoint and issuing a configure endpoint command for all endpoints.
  2740. *
  2741. * Don't allow the call to succeed if one endpoint only supports one stream
  2742. * (which means it doesn't support streams at all).
  2743. *
  2744. * Drivers may get less stream IDs than they asked for, if the host controller
  2745. * hardware or endpoints claim they can't support the number of requested
  2746. * stream IDs.
  2747. */
  2748. int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
  2749. struct usb_host_endpoint **eps, unsigned int num_eps,
  2750. unsigned int num_streams, gfp_t mem_flags)
  2751. {
  2752. int i, ret;
  2753. struct xhci_hcd *xhci;
  2754. struct xhci_virt_device *vdev;
  2755. struct xhci_command *config_cmd;
  2756. struct xhci_input_control_ctx *ctrl_ctx;
  2757. unsigned int ep_index;
  2758. unsigned int num_stream_ctxs;
  2759. unsigned long flags;
  2760. u32 changed_ep_bitmask = 0;
  2761. if (!eps)
  2762. return -EINVAL;
  2763. /* Add one to the number of streams requested to account for
  2764. * stream 0 that is reserved for xHCI usage.
  2765. */
  2766. num_streams += 1;
  2767. xhci = hcd_to_xhci(hcd);
  2768. xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
  2769. num_streams);
  2770. config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
  2771. if (!config_cmd) {
  2772. xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
  2773. return -ENOMEM;
  2774. }
  2775. ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx);
  2776. if (!ctrl_ctx) {
  2777. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  2778. __func__);
  2779. xhci_free_command(xhci, config_cmd);
  2780. return -ENOMEM;
  2781. }
  2782. /* Check to make sure all endpoints are not already configured for
  2783. * streams. While we're at it, find the maximum number of streams that
  2784. * all the endpoints will support and check for duplicate endpoints.
  2785. */
  2786. spin_lock_irqsave(&xhci->lock, flags);
  2787. ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
  2788. num_eps, &num_streams, &changed_ep_bitmask);
  2789. if (ret < 0) {
  2790. xhci_free_command(xhci, config_cmd);
  2791. spin_unlock_irqrestore(&xhci->lock, flags);
  2792. return ret;
  2793. }
  2794. if (num_streams <= 1) {
  2795. xhci_warn(xhci, "WARN: endpoints can't handle "
  2796. "more than one stream.\n");
  2797. xhci_free_command(xhci, config_cmd);
  2798. spin_unlock_irqrestore(&xhci->lock, flags);
  2799. return -EINVAL;
  2800. }
  2801. vdev = xhci->devs[udev->slot_id];
  2802. /* Mark each endpoint as being in transition, so
  2803. * xhci_urb_enqueue() will reject all URBs.
  2804. */
  2805. for (i = 0; i < num_eps; i++) {
  2806. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  2807. vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
  2808. }
  2809. spin_unlock_irqrestore(&xhci->lock, flags);
  2810. /* Setup internal data structures and allocate HW data structures for
  2811. * streams (but don't install the HW structures in the input context
  2812. * until we're sure all memory allocation succeeded).
  2813. */
  2814. xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
  2815. xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
  2816. num_stream_ctxs, num_streams);
  2817. for (i = 0; i < num_eps; i++) {
  2818. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  2819. vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
  2820. num_stream_ctxs,
  2821. num_streams, mem_flags);
  2822. if (!vdev->eps[ep_index].stream_info)
  2823. goto cleanup;
  2824. /* Set maxPstreams in endpoint context and update deq ptr to
  2825. * point to stream context array. FIXME
  2826. */
  2827. }
  2828. /* Set up the input context for a configure endpoint command. */
  2829. for (i = 0; i < num_eps; i++) {
  2830. struct xhci_ep_ctx *ep_ctx;
  2831. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  2832. ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
  2833. xhci_endpoint_copy(xhci, config_cmd->in_ctx,
  2834. vdev->out_ctx, ep_index);
  2835. xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
  2836. vdev->eps[ep_index].stream_info);
  2837. }
  2838. /* Tell the HW to drop its old copy of the endpoint context info
  2839. * and add the updated copy from the input context.
  2840. */
  2841. xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
  2842. vdev->out_ctx, ctrl_ctx,
  2843. changed_ep_bitmask, changed_ep_bitmask);
  2844. /* Issue and wait for the configure endpoint command */
  2845. ret = xhci_configure_endpoint(xhci, udev, config_cmd,
  2846. false, false);
  2847. /* xHC rejected the configure endpoint command for some reason, so we
  2848. * leave the old ring intact and free our internal streams data
  2849. * structure.
  2850. */
  2851. if (ret < 0)
  2852. goto cleanup;
  2853. spin_lock_irqsave(&xhci->lock, flags);
  2854. for (i = 0; i < num_eps; i++) {
  2855. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  2856. vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
  2857. xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
  2858. udev->slot_id, ep_index);
  2859. vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
  2860. }
  2861. xhci_free_command(xhci, config_cmd);
  2862. spin_unlock_irqrestore(&xhci->lock, flags);
  2863. /* Subtract 1 for stream 0, which drivers can't use */
  2864. return num_streams - 1;
  2865. cleanup:
  2866. /* If it didn't work, free the streams! */
  2867. for (i = 0; i < num_eps; i++) {
  2868. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  2869. xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
  2870. vdev->eps[ep_index].stream_info = NULL;
  2871. /* FIXME Unset maxPstreams in endpoint context and
  2872. * update deq ptr to point to normal string ring.
  2873. */
  2874. vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
  2875. vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
  2876. xhci_endpoint_zero(xhci, vdev, eps[i]);
  2877. }
  2878. xhci_free_command(xhci, config_cmd);
  2879. return -ENOMEM;
  2880. }
  2881. /* Transition the endpoint from using streams to being a "normal" endpoint
  2882. * without streams.
  2883. *
  2884. * Modify the endpoint context state, submit a configure endpoint command,
  2885. * and free all endpoint rings for streams if that completes successfully.
  2886. */
  2887. int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
  2888. struct usb_host_endpoint **eps, unsigned int num_eps,
  2889. gfp_t mem_flags)
  2890. {
  2891. int i, ret;
  2892. struct xhci_hcd *xhci;
  2893. struct xhci_virt_device *vdev;
  2894. struct xhci_command *command;
  2895. struct xhci_input_control_ctx *ctrl_ctx;
  2896. unsigned int ep_index;
  2897. unsigned long flags;
  2898. u32 changed_ep_bitmask;
  2899. xhci = hcd_to_xhci(hcd);
  2900. vdev = xhci->devs[udev->slot_id];
  2901. /* Set up a configure endpoint command to remove the streams rings */
  2902. spin_lock_irqsave(&xhci->lock, flags);
  2903. changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
  2904. udev, eps, num_eps);
  2905. if (changed_ep_bitmask == 0) {
  2906. spin_unlock_irqrestore(&xhci->lock, flags);
  2907. return -EINVAL;
  2908. }
  2909. /* Use the xhci_command structure from the first endpoint. We may have
  2910. * allocated too many, but the driver may call xhci_free_streams() for
  2911. * each endpoint it grouped into one call to xhci_alloc_streams().
  2912. */
  2913. ep_index = xhci_get_endpoint_index(&eps[0]->desc);
  2914. command = vdev->eps[ep_index].stream_info->free_streams_command;
  2915. ctrl_ctx = xhci_get_input_control_ctx(xhci, command->in_ctx);
  2916. if (!ctrl_ctx) {
  2917. spin_unlock_irqrestore(&xhci->lock, flags);
  2918. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  2919. __func__);
  2920. return -EINVAL;
  2921. }
  2922. for (i = 0; i < num_eps; i++) {
  2923. struct xhci_ep_ctx *ep_ctx;
  2924. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  2925. ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
  2926. xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
  2927. EP_GETTING_NO_STREAMS;
  2928. xhci_endpoint_copy(xhci, command->in_ctx,
  2929. vdev->out_ctx, ep_index);
  2930. xhci_setup_no_streams_ep_input_ctx(xhci, ep_ctx,
  2931. &vdev->eps[ep_index]);
  2932. }
  2933. xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
  2934. vdev->out_ctx, ctrl_ctx,
  2935. changed_ep_bitmask, changed_ep_bitmask);
  2936. spin_unlock_irqrestore(&xhci->lock, flags);
  2937. /* Issue and wait for the configure endpoint command,
  2938. * which must succeed.
  2939. */
  2940. ret = xhci_configure_endpoint(xhci, udev, command,
  2941. false, true);
  2942. /* xHC rejected the configure endpoint command for some reason, so we
  2943. * leave the streams rings intact.
  2944. */
  2945. if (ret < 0)
  2946. return ret;
  2947. spin_lock_irqsave(&xhci->lock, flags);
  2948. for (i = 0; i < num_eps; i++) {
  2949. ep_index = xhci_get_endpoint_index(&eps[i]->desc);
  2950. xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
  2951. vdev->eps[ep_index].stream_info = NULL;
  2952. /* FIXME Unset maxPstreams in endpoint context and
  2953. * update deq ptr to point to normal string ring.
  2954. */
  2955. vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
  2956. vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
  2957. }
  2958. spin_unlock_irqrestore(&xhci->lock, flags);
  2959. return 0;
  2960. }
  2961. /*
  2962. * Deletes endpoint resources for endpoints that were active before a Reset
  2963. * Device command, or a Disable Slot command. The Reset Device command leaves
  2964. * the control endpoint intact, whereas the Disable Slot command deletes it.
  2965. *
  2966. * Must be called with xhci->lock held.
  2967. */
  2968. void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
  2969. struct xhci_virt_device *virt_dev, bool drop_control_ep)
  2970. {
  2971. int i;
  2972. unsigned int num_dropped_eps = 0;
  2973. unsigned int drop_flags = 0;
  2974. for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
  2975. if (virt_dev->eps[i].ring) {
  2976. drop_flags |= 1 << i;
  2977. num_dropped_eps++;
  2978. }
  2979. }
  2980. xhci->num_active_eps -= num_dropped_eps;
  2981. if (num_dropped_eps)
  2982. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  2983. "Dropped %u ep ctxs, flags = 0x%x, "
  2984. "%u now active.",
  2985. num_dropped_eps, drop_flags,
  2986. xhci->num_active_eps);
  2987. }
  2988. /*
  2989. * This submits a Reset Device Command, which will set the device state to 0,
  2990. * set the device address to 0, and disable all the endpoints except the default
  2991. * control endpoint. The USB core should come back and call
  2992. * xhci_address_device(), and then re-set up the configuration. If this is
  2993. * called because of a usb_reset_and_verify_device(), then the old alternate
  2994. * settings will be re-installed through the normal bandwidth allocation
  2995. * functions.
  2996. *
  2997. * Wait for the Reset Device command to finish. Remove all structures
  2998. * associated with the endpoints that were disabled. Clear the input device
  2999. * structure? Cache the rings? Reset the control endpoint 0 max packet size?
  3000. *
  3001. * If the virt_dev to be reset does not exist or does not match the udev,
  3002. * it means the device is lost, possibly due to the xHC restore error and
  3003. * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
  3004. * re-allocate the device.
  3005. */
  3006. int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
  3007. {
  3008. int ret, i;
  3009. unsigned long flags;
  3010. struct xhci_hcd *xhci;
  3011. unsigned int slot_id;
  3012. struct xhci_virt_device *virt_dev;
  3013. struct xhci_command *reset_device_cmd;
  3014. int timeleft;
  3015. int last_freed_endpoint;
  3016. struct xhci_slot_ctx *slot_ctx;
  3017. int old_active_eps = 0;
  3018. ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
  3019. if (ret <= 0)
  3020. return ret;
  3021. xhci = hcd_to_xhci(hcd);
  3022. slot_id = udev->slot_id;
  3023. virt_dev = xhci->devs[slot_id];
  3024. if (!virt_dev) {
  3025. xhci_dbg(xhci, "The device to be reset with slot ID %u does "
  3026. "not exist. Re-allocate the device\n", slot_id);
  3027. ret = xhci_alloc_dev(hcd, udev);
  3028. if (ret == 1)
  3029. return 0;
  3030. else
  3031. return -EINVAL;
  3032. }
  3033. if (virt_dev->udev != udev) {
  3034. /* If the virt_dev and the udev does not match, this virt_dev
  3035. * may belong to another udev.
  3036. * Re-allocate the device.
  3037. */
  3038. xhci_dbg(xhci, "The device to be reset with slot ID %u does "
  3039. "not match the udev. Re-allocate the device\n",
  3040. slot_id);
  3041. ret = xhci_alloc_dev(hcd, udev);
  3042. if (ret == 1)
  3043. return 0;
  3044. else
  3045. return -EINVAL;
  3046. }
  3047. /* If device is not setup, there is no point in resetting it */
  3048. slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
  3049. if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
  3050. SLOT_STATE_DISABLED)
  3051. return 0;
  3052. xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
  3053. /* Allocate the command structure that holds the struct completion.
  3054. * Assume we're in process context, since the normal device reset
  3055. * process has to wait for the device anyway. Storage devices are
  3056. * reset as part of error handling, so use GFP_NOIO instead of
  3057. * GFP_KERNEL.
  3058. */
  3059. reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
  3060. if (!reset_device_cmd) {
  3061. xhci_dbg(xhci, "Couldn't allocate command structure.\n");
  3062. return -ENOMEM;
  3063. }
  3064. /* Attempt to submit the Reset Device command to the command ring */
  3065. spin_lock_irqsave(&xhci->lock, flags);
  3066. reset_device_cmd->command_trb = xhci->cmd_ring->enqueue;
  3067. /* Enqueue pointer can be left pointing to the link TRB,
  3068. * we must handle that
  3069. */
  3070. if (TRB_TYPE_LINK_LE32(reset_device_cmd->command_trb->link.control))
  3071. reset_device_cmd->command_trb =
  3072. xhci->cmd_ring->enq_seg->next->trbs;
  3073. list_add_tail(&reset_device_cmd->cmd_list, &virt_dev->cmd_list);
  3074. ret = xhci_queue_reset_device(xhci, slot_id);
  3075. if (ret) {
  3076. xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
  3077. list_del(&reset_device_cmd->cmd_list);
  3078. spin_unlock_irqrestore(&xhci->lock, flags);
  3079. goto command_cleanup;
  3080. }
  3081. xhci_ring_cmd_db(xhci);
  3082. spin_unlock_irqrestore(&xhci->lock, flags);
  3083. /* Wait for the Reset Device command to finish */
  3084. timeleft = wait_for_completion_interruptible_timeout(
  3085. reset_device_cmd->completion,
  3086. USB_CTRL_SET_TIMEOUT);
  3087. if (timeleft <= 0) {
  3088. xhci_warn(xhci, "%s while waiting for reset device command\n",
  3089. timeleft == 0 ? "Timeout" : "Signal");
  3090. spin_lock_irqsave(&xhci->lock, flags);
  3091. /* The timeout might have raced with the event ring handler, so
  3092. * only delete from the list if the item isn't poisoned.
  3093. */
  3094. if (reset_device_cmd->cmd_list.next != LIST_POISON1)
  3095. list_del(&reset_device_cmd->cmd_list);
  3096. spin_unlock_irqrestore(&xhci->lock, flags);
  3097. ret = -ETIME;
  3098. goto command_cleanup;
  3099. }
  3100. /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
  3101. * unless we tried to reset a slot ID that wasn't enabled,
  3102. * or the device wasn't in the addressed or configured state.
  3103. */
  3104. ret = reset_device_cmd->status;
  3105. switch (ret) {
  3106. case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
  3107. case COMP_CTX_STATE: /* 0.96 completion code for same thing */
  3108. xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
  3109. slot_id,
  3110. xhci_get_slot_state(xhci, virt_dev->out_ctx));
  3111. xhci_dbg(xhci, "Not freeing device rings.\n");
  3112. /* Don't treat this as an error. May change my mind later. */
  3113. ret = 0;
  3114. goto command_cleanup;
  3115. case COMP_SUCCESS:
  3116. xhci_dbg(xhci, "Successful reset device command.\n");
  3117. break;
  3118. default:
  3119. if (xhci_is_vendor_info_code(xhci, ret))
  3120. break;
  3121. xhci_warn(xhci, "Unknown completion code %u for "
  3122. "reset device command.\n", ret);
  3123. ret = -EINVAL;
  3124. goto command_cleanup;
  3125. }
  3126. /* Free up host controller endpoint resources */
  3127. if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
  3128. spin_lock_irqsave(&xhci->lock, flags);
  3129. /* Don't delete the default control endpoint resources */
  3130. xhci_free_device_endpoint_resources(xhci, virt_dev, false);
  3131. spin_unlock_irqrestore(&xhci->lock, flags);
  3132. }
  3133. /* Everything but endpoint 0 is disabled, so free or cache the rings. */
  3134. last_freed_endpoint = 1;
  3135. for (i = 1; i < 31; ++i) {
  3136. struct xhci_virt_ep *ep = &virt_dev->eps[i];
  3137. if (ep->ep_state & EP_HAS_STREAMS) {
  3138. xhci_free_stream_info(xhci, ep->stream_info);
  3139. ep->stream_info = NULL;
  3140. ep->ep_state &= ~EP_HAS_STREAMS;
  3141. }
  3142. if (ep->ring) {
  3143. xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
  3144. last_freed_endpoint = i;
  3145. }
  3146. if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
  3147. xhci_drop_ep_from_interval_table(xhci,
  3148. &virt_dev->eps[i].bw_info,
  3149. virt_dev->bw_table,
  3150. udev,
  3151. &virt_dev->eps[i],
  3152. virt_dev->tt_info);
  3153. xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
  3154. }
  3155. /* If necessary, update the number of active TTs on this root port */
  3156. xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
  3157. xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
  3158. xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
  3159. ret = 0;
  3160. command_cleanup:
  3161. xhci_free_command(xhci, reset_device_cmd);
  3162. return ret;
  3163. }
  3164. /*
  3165. * At this point, the struct usb_device is about to go away, the device has
  3166. * disconnected, and all traffic has been stopped and the endpoints have been
  3167. * disabled. Free any HC data structures associated with that device.
  3168. */
  3169. void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
  3170. {
  3171. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  3172. struct xhci_virt_device *virt_dev;
  3173. unsigned long flags;
  3174. u32 state;
  3175. int i, ret;
  3176. #ifndef CONFIG_USB_DEFAULT_PERSIST
  3177. /*
  3178. * We called pm_runtime_get_noresume when the device was attached.
  3179. * Decrement the counter here to allow controller to runtime suspend
  3180. * if no devices remain.
  3181. */
  3182. if (xhci->quirks & XHCI_RESET_ON_RESUME)
  3183. pm_runtime_put_noidle(hcd->self.controller);
  3184. #endif
  3185. ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
  3186. /* If the host is halted due to driver unload, we still need to free the
  3187. * device.
  3188. */
  3189. if (ret <= 0 && ret != -ENODEV)
  3190. return;
  3191. virt_dev = xhci->devs[udev->slot_id];
  3192. /* Stop any wayward timer functions (which may grab the lock) */
  3193. for (i = 0; i < 31; ++i) {
  3194. virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
  3195. del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
  3196. }
  3197. if (udev->usb2_hw_lpm_enabled) {
  3198. xhci_set_usb2_hardware_lpm(hcd, udev, 0);
  3199. udev->usb2_hw_lpm_enabled = 0;
  3200. }
  3201. spin_lock_irqsave(&xhci->lock, flags);
  3202. /* Don't disable the slot if the host controller is dead. */
  3203. state = xhci_readl(xhci, &xhci->op_regs->status);
  3204. if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
  3205. (xhci->xhc_state & XHCI_STATE_HALTED)) {
  3206. xhci_free_virt_device(xhci, udev->slot_id);
  3207. spin_unlock_irqrestore(&xhci->lock, flags);
  3208. return;
  3209. }
  3210. if (xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) {
  3211. spin_unlock_irqrestore(&xhci->lock, flags);
  3212. xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
  3213. return;
  3214. }
  3215. xhci_ring_cmd_db(xhci);
  3216. spin_unlock_irqrestore(&xhci->lock, flags);
  3217. /*
  3218. * Event command completion handler will free any data structures
  3219. * associated with the slot. XXX Can free sleep?
  3220. */
  3221. }
  3222. /*
  3223. * Checks if we have enough host controller resources for the default control
  3224. * endpoint.
  3225. *
  3226. * Must be called with xhci->lock held.
  3227. */
  3228. static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
  3229. {
  3230. if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
  3231. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  3232. "Not enough ep ctxs: "
  3233. "%u active, need to add 1, limit is %u.",
  3234. xhci->num_active_eps, xhci->limit_active_eps);
  3235. return -ENOMEM;
  3236. }
  3237. xhci->num_active_eps += 1;
  3238. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  3239. "Adding 1 ep ctx, %u now active.",
  3240. xhci->num_active_eps);
  3241. return 0;
  3242. }
  3243. /*
  3244. * Returns 0 if the xHC ran out of device slots, the Enable Slot command
  3245. * timed out, or allocating memory failed. Returns 1 on success.
  3246. */
  3247. int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
  3248. {
  3249. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  3250. unsigned long flags;
  3251. int timeleft;
  3252. int ret;
  3253. union xhci_trb *cmd_trb;
  3254. spin_lock_irqsave(&xhci->lock, flags);
  3255. cmd_trb = xhci->cmd_ring->dequeue;
  3256. ret = xhci_queue_slot_control(xhci, TRB_ENABLE_SLOT, 0);
  3257. if (ret) {
  3258. spin_unlock_irqrestore(&xhci->lock, flags);
  3259. xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
  3260. return 0;
  3261. }
  3262. xhci_ring_cmd_db(xhci);
  3263. spin_unlock_irqrestore(&xhci->lock, flags);
  3264. /* XXX: how much time for xHC slot assignment? */
  3265. timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
  3266. XHCI_CMD_DEFAULT_TIMEOUT);
  3267. if (timeleft <= 0) {
  3268. xhci_warn(xhci, "%s while waiting for a slot\n",
  3269. timeleft == 0 ? "Timeout" : "Signal");
  3270. /* cancel the enable slot request */
  3271. return xhci_cancel_cmd(xhci, NULL, cmd_trb);
  3272. }
  3273. if (!xhci->slot_id) {
  3274. xhci_err(xhci, "Error while assigning device slot ID\n");
  3275. return 0;
  3276. }
  3277. if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
  3278. spin_lock_irqsave(&xhci->lock, flags);
  3279. ret = xhci_reserve_host_control_ep_resources(xhci);
  3280. if (ret) {
  3281. spin_unlock_irqrestore(&xhci->lock, flags);
  3282. xhci_warn(xhci, "Not enough host resources, "
  3283. "active endpoint contexts = %u\n",
  3284. xhci->num_active_eps);
  3285. goto disable_slot;
  3286. }
  3287. spin_unlock_irqrestore(&xhci->lock, flags);
  3288. }
  3289. /* Use GFP_NOIO, since this function can be called from
  3290. * xhci_discover_or_reset_device(), which may be called as part of
  3291. * mass storage driver error handling.
  3292. */
  3293. if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_NOIO)) {
  3294. xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
  3295. goto disable_slot;
  3296. }
  3297. udev->slot_id = xhci->slot_id;
  3298. #ifndef CONFIG_USB_DEFAULT_PERSIST
  3299. /*
  3300. * If resetting upon resume, we can't put the controller into runtime
  3301. * suspend if there is a device attached.
  3302. */
  3303. if (xhci->quirks & XHCI_RESET_ON_RESUME)
  3304. pm_runtime_get_noresume(hcd->self.controller);
  3305. #endif
  3306. /* Is this a LS or FS device under a HS hub? */
  3307. /* Hub or peripherial? */
  3308. return 1;
  3309. disable_slot:
  3310. /* Disable slot, if we can do it without mem alloc */
  3311. spin_lock_irqsave(&xhci->lock, flags);
  3312. if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id))
  3313. xhci_ring_cmd_db(xhci);
  3314. spin_unlock_irqrestore(&xhci->lock, flags);
  3315. return 0;
  3316. }
  3317. /*
  3318. * Issue an Address Device command (which will issue a SetAddress request to
  3319. * the device).
  3320. * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so
  3321. * we should only issue and wait on one address command at the same time.
  3322. *
  3323. * We add one to the device address issued by the hardware because the USB core
  3324. * uses address 1 for the root hubs (even though they're not really devices).
  3325. */
  3326. int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
  3327. {
  3328. unsigned long flags;
  3329. int timeleft;
  3330. struct xhci_virt_device *virt_dev;
  3331. int ret = 0;
  3332. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  3333. struct xhci_slot_ctx *slot_ctx;
  3334. struct xhci_input_control_ctx *ctrl_ctx;
  3335. u64 temp_64;
  3336. union xhci_trb *cmd_trb;
  3337. if (!udev->slot_id) {
  3338. xhci_dbg_trace(xhci, trace_xhci_dbg_address,
  3339. "Bad Slot ID %d", udev->slot_id);
  3340. return -EINVAL;
  3341. }
  3342. virt_dev = xhci->devs[udev->slot_id];
  3343. if (WARN_ON(!virt_dev)) {
  3344. /*
  3345. * In plug/unplug torture test with an NEC controller,
  3346. * a zero-dereference was observed once due to virt_dev = 0.
  3347. * Print useful debug rather than crash if it is observed again!
  3348. */
  3349. xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
  3350. udev->slot_id);
  3351. return -EINVAL;
  3352. }
  3353. slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
  3354. ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
  3355. if (!ctrl_ctx) {
  3356. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  3357. __func__);
  3358. return -EINVAL;
  3359. }
  3360. /*
  3361. * If this is the first Set Address since device plug-in or
  3362. * virt_device realloaction after a resume with an xHCI power loss,
  3363. * then set up the slot context.
  3364. */
  3365. if (!slot_ctx->dev_info)
  3366. xhci_setup_addressable_virt_dev(xhci, udev);
  3367. /* Otherwise, update the control endpoint ring enqueue pointer. */
  3368. else
  3369. xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
  3370. ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
  3371. ctrl_ctx->drop_flags = 0;
  3372. xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
  3373. xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
  3374. trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
  3375. slot_ctx->dev_info >> 27);
  3376. spin_lock_irqsave(&xhci->lock, flags);
  3377. cmd_trb = xhci->cmd_ring->dequeue;
  3378. ret = xhci_queue_address_device(xhci, virt_dev->in_ctx->dma,
  3379. udev->slot_id);
  3380. if (ret) {
  3381. spin_unlock_irqrestore(&xhci->lock, flags);
  3382. xhci_dbg_trace(xhci, trace_xhci_dbg_address,
  3383. "FIXME: allocate a command ring segment");
  3384. return ret;
  3385. }
  3386. xhci_ring_cmd_db(xhci);
  3387. spin_unlock_irqrestore(&xhci->lock, flags);
  3388. /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
  3389. timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
  3390. XHCI_CMD_DEFAULT_TIMEOUT);
  3391. /* FIXME: From section 4.3.4: "Software shall be responsible for timing
  3392. * the SetAddress() "recovery interval" required by USB and aborting the
  3393. * command on a timeout.
  3394. */
  3395. if (timeleft <= 0) {
  3396. xhci_warn(xhci, "%s while waiting for address device command\n",
  3397. timeleft == 0 ? "Timeout" : "Signal");
  3398. /* cancel the address device command */
  3399. ret = xhci_cancel_cmd(xhci, NULL, cmd_trb);
  3400. if (ret < 0)
  3401. return ret;
  3402. return -ETIME;
  3403. }
  3404. switch (virt_dev->cmd_status) {
  3405. case COMP_CTX_STATE:
  3406. case COMP_EBADSLT:
  3407. xhci_err(xhci, "Setup ERROR: address device command for slot %d.\n",
  3408. udev->slot_id);
  3409. ret = -EINVAL;
  3410. break;
  3411. case COMP_TX_ERR:
  3412. dev_warn(&udev->dev, "Device not responding to set address.\n");
  3413. ret = -EPROTO;
  3414. break;
  3415. case COMP_DEV_ERR:
  3416. dev_warn(&udev->dev, "ERROR: Incompatible device for address "
  3417. "device command.\n");
  3418. ret = -ENODEV;
  3419. break;
  3420. case COMP_SUCCESS:
  3421. xhci_dbg_trace(xhci, trace_xhci_dbg_address,
  3422. "Successful Address Device command");
  3423. break;
  3424. default:
  3425. xhci_err(xhci, "ERROR: unexpected command completion "
  3426. "code 0x%x.\n", virt_dev->cmd_status);
  3427. xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
  3428. xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
  3429. trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
  3430. ret = -EINVAL;
  3431. break;
  3432. }
  3433. if (ret) {
  3434. return ret;
  3435. }
  3436. temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
  3437. xhci_dbg_trace(xhci, trace_xhci_dbg_address,
  3438. "Op regs DCBAA ptr = %#016llx", temp_64);
  3439. xhci_dbg_trace(xhci, trace_xhci_dbg_address,
  3440. "Slot ID %d dcbaa entry @%p = %#016llx",
  3441. udev->slot_id,
  3442. &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
  3443. (unsigned long long)
  3444. le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
  3445. xhci_dbg_trace(xhci, trace_xhci_dbg_address,
  3446. "Output Context DMA address = %#08llx",
  3447. (unsigned long long)virt_dev->out_ctx->dma);
  3448. xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
  3449. xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
  3450. trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
  3451. slot_ctx->dev_info >> 27);
  3452. xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
  3453. xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
  3454. /*
  3455. * USB core uses address 1 for the roothubs, so we add one to the
  3456. * address given back to us by the HC.
  3457. */
  3458. slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
  3459. trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
  3460. slot_ctx->dev_info >> 27);
  3461. /* Use kernel assigned address for devices; store xHC assigned
  3462. * address locally. */
  3463. virt_dev->address = (le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK)
  3464. + 1;
  3465. /* Zero the input context control for later use */
  3466. ctrl_ctx->add_flags = 0;
  3467. ctrl_ctx->drop_flags = 0;
  3468. xhci_dbg_trace(xhci, trace_xhci_dbg_address,
  3469. "Internal device address = %d", virt_dev->address);
  3470. return 0;
  3471. }
  3472. /*
  3473. * Transfer the port index into real index in the HW port status
  3474. * registers. Caculate offset between the port's PORTSC register
  3475. * and port status base. Divide the number of per port register
  3476. * to get the real index. The raw port number bases 1.
  3477. */
  3478. int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
  3479. {
  3480. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  3481. __le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
  3482. __le32 __iomem *addr;
  3483. int raw_port;
  3484. if (hcd->speed != HCD_USB3)
  3485. addr = xhci->usb2_ports[port1 - 1];
  3486. else
  3487. addr = xhci->usb3_ports[port1 - 1];
  3488. raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
  3489. return raw_port;
  3490. }
  3491. /*
  3492. * Issue an Evaluate Context command to change the Maximum Exit Latency in the
  3493. * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
  3494. */
  3495. static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
  3496. struct usb_device *udev, u16 max_exit_latency)
  3497. {
  3498. struct xhci_virt_device *virt_dev;
  3499. struct xhci_command *command;
  3500. struct xhci_input_control_ctx *ctrl_ctx;
  3501. struct xhci_slot_ctx *slot_ctx;
  3502. unsigned long flags;
  3503. int ret;
  3504. spin_lock_irqsave(&xhci->lock, flags);
  3505. if (max_exit_latency == xhci->devs[udev->slot_id]->current_mel) {
  3506. spin_unlock_irqrestore(&xhci->lock, flags);
  3507. return 0;
  3508. }
  3509. /* Attempt to issue an Evaluate Context command to change the MEL. */
  3510. virt_dev = xhci->devs[udev->slot_id];
  3511. command = xhci->lpm_command;
  3512. ctrl_ctx = xhci_get_input_control_ctx(xhci, command->in_ctx);
  3513. if (!ctrl_ctx) {
  3514. spin_unlock_irqrestore(&xhci->lock, flags);
  3515. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  3516. __func__);
  3517. return -ENOMEM;
  3518. }
  3519. xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
  3520. spin_unlock_irqrestore(&xhci->lock, flags);
  3521. ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
  3522. slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
  3523. slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
  3524. slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
  3525. xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
  3526. "Set up evaluate context for LPM MEL change.");
  3527. xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id);
  3528. xhci_dbg_ctx(xhci, command->in_ctx, 0);
  3529. /* Issue and wait for the evaluate context command. */
  3530. ret = xhci_configure_endpoint(xhci, udev, command,
  3531. true, true);
  3532. xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id);
  3533. xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0);
  3534. if (!ret) {
  3535. spin_lock_irqsave(&xhci->lock, flags);
  3536. virt_dev->current_mel = max_exit_latency;
  3537. spin_unlock_irqrestore(&xhci->lock, flags);
  3538. }
  3539. return ret;
  3540. }
  3541. #ifdef CONFIG_PM_RUNTIME
  3542. /* BESL to HIRD Encoding array for USB2 LPM */
  3543. static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
  3544. 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
  3545. /* Calculate HIRD/BESL for USB2 PORTPMSC*/
  3546. static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
  3547. struct usb_device *udev)
  3548. {
  3549. int u2del, besl, besl_host;
  3550. int besl_device = 0;
  3551. u32 field;
  3552. u2del = HCS_U2_LATENCY(xhci->hcs_params3);
  3553. field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
  3554. if (field & USB_BESL_SUPPORT) {
  3555. for (besl_host = 0; besl_host < 16; besl_host++) {
  3556. if (xhci_besl_encoding[besl_host] >= u2del)
  3557. break;
  3558. }
  3559. /* Use baseline BESL value as default */
  3560. if (field & USB_BESL_BASELINE_VALID)
  3561. besl_device = USB_GET_BESL_BASELINE(field);
  3562. else if (field & USB_BESL_DEEP_VALID)
  3563. besl_device = USB_GET_BESL_DEEP(field);
  3564. } else {
  3565. if (u2del <= 50)
  3566. besl_host = 0;
  3567. else
  3568. besl_host = (u2del - 51) / 75 + 1;
  3569. }
  3570. besl = besl_host + besl_device;
  3571. if (besl > 15)
  3572. besl = 15;
  3573. return besl;
  3574. }
  3575. /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
  3576. static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
  3577. {
  3578. u32 field;
  3579. int l1;
  3580. int besld = 0;
  3581. int hirdm = 0;
  3582. field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
  3583. /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
  3584. l1 = udev->l1_params.timeout / 256;
  3585. /* device has preferred BESLD */
  3586. if (field & USB_BESL_DEEP_VALID) {
  3587. besld = USB_GET_BESL_DEEP(field);
  3588. hirdm = 1;
  3589. }
  3590. return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
  3591. }
  3592. static int xhci_usb2_software_lpm_test(struct usb_hcd *hcd,
  3593. struct usb_device *udev)
  3594. {
  3595. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  3596. struct dev_info *dev_info;
  3597. __le32 __iomem **port_array;
  3598. __le32 __iomem *addr, *pm_addr;
  3599. u32 temp, dev_id;
  3600. unsigned int port_num;
  3601. unsigned long flags;
  3602. int hird;
  3603. int ret;
  3604. if (hcd->speed == HCD_USB3 || !xhci->sw_lpm_support ||
  3605. !udev->lpm_capable)
  3606. return -EINVAL;
  3607. /* we only support lpm for non-hub device connected to root hub yet */
  3608. if (!udev->parent || udev->parent->parent ||
  3609. udev->descriptor.bDeviceClass == USB_CLASS_HUB)
  3610. return -EINVAL;
  3611. spin_lock_irqsave(&xhci->lock, flags);
  3612. /* Look for devices in lpm_failed_devs list */
  3613. dev_id = le16_to_cpu(udev->descriptor.idVendor) << 16 |
  3614. le16_to_cpu(udev->descriptor.idProduct);
  3615. list_for_each_entry(dev_info, &xhci->lpm_failed_devs, list) {
  3616. if (dev_info->dev_id == dev_id) {
  3617. ret = -EINVAL;
  3618. goto finish;
  3619. }
  3620. }
  3621. port_array = xhci->usb2_ports;
  3622. port_num = udev->portnum - 1;
  3623. if (port_num > HCS_MAX_PORTS(xhci->hcs_params1)) {
  3624. xhci_dbg(xhci, "invalid port number %d\n", udev->portnum);
  3625. ret = -EINVAL;
  3626. goto finish;
  3627. }
  3628. /*
  3629. * Test USB 2.0 software LPM.
  3630. * FIXME: some xHCI 1.0 hosts may implement a new register to set up
  3631. * hardware-controlled USB 2.0 LPM. See section 5.4.11 and 4.23.5.1.1.1
  3632. * in the June 2011 errata release.
  3633. */
  3634. xhci_dbg(xhci, "test port %d software LPM\n", port_num);
  3635. /*
  3636. * Set L1 Device Slot and HIRD/BESL.
  3637. * Check device's USB 2.0 extension descriptor to determine whether
  3638. * HIRD or BESL shoule be used. See USB2.0 LPM errata.
  3639. */
  3640. pm_addr = port_array[port_num] + PORTPMSC;
  3641. hird = xhci_calculate_hird_besl(xhci, udev);
  3642. temp = PORT_L1DS(udev->slot_id) | PORT_HIRD(hird);
  3643. xhci_writel(xhci, temp, pm_addr);
  3644. /* Set port link state to U2(L1) */
  3645. addr = port_array[port_num];
  3646. xhci_set_link_state(xhci, port_array, port_num, XDEV_U2);
  3647. /* wait for ACK */
  3648. spin_unlock_irqrestore(&xhci->lock, flags);
  3649. msleep(10);
  3650. spin_lock_irqsave(&xhci->lock, flags);
  3651. /* Check L1 Status */
  3652. ret = xhci_handshake(xhci, pm_addr,
  3653. PORT_L1S_MASK, PORT_L1S_SUCCESS, 125);
  3654. if (ret != -ETIMEDOUT) {
  3655. /* enter L1 successfully */
  3656. temp = xhci_readl(xhci, addr);
  3657. xhci_dbg(xhci, "port %d entered L1 state, port status 0x%x\n",
  3658. port_num, temp);
  3659. ret = 0;
  3660. } else {
  3661. temp = xhci_readl(xhci, pm_addr);
  3662. xhci_dbg(xhci, "port %d software lpm failed, L1 status %d\n",
  3663. port_num, temp & PORT_L1S_MASK);
  3664. ret = -EINVAL;
  3665. }
  3666. /* Resume the port */
  3667. xhci_set_link_state(xhci, port_array, port_num, XDEV_U0);
  3668. spin_unlock_irqrestore(&xhci->lock, flags);
  3669. msleep(10);
  3670. spin_lock_irqsave(&xhci->lock, flags);
  3671. /* Clear PLC */
  3672. xhci_test_and_clear_bit(xhci, port_array, port_num, PORT_PLC);
  3673. /* Check PORTSC to make sure the device is in the right state */
  3674. if (!ret) {
  3675. temp = xhci_readl(xhci, addr);
  3676. xhci_dbg(xhci, "resumed port %d status 0x%x\n", port_num, temp);
  3677. if (!(temp & PORT_CONNECT) || !(temp & PORT_PE) ||
  3678. (temp & PORT_PLS_MASK) != XDEV_U0) {
  3679. xhci_dbg(xhci, "port L1 resume fail\n");
  3680. ret = -EINVAL;
  3681. }
  3682. }
  3683. if (ret) {
  3684. /* Insert dev to lpm_failed_devs list */
  3685. xhci_warn(xhci, "device LPM test failed, may disconnect and "
  3686. "re-enumerate\n");
  3687. dev_info = kzalloc(sizeof(struct dev_info), GFP_ATOMIC);
  3688. if (!dev_info) {
  3689. ret = -ENOMEM;
  3690. goto finish;
  3691. }
  3692. dev_info->dev_id = dev_id;
  3693. INIT_LIST_HEAD(&dev_info->list);
  3694. list_add(&dev_info->list, &xhci->lpm_failed_devs);
  3695. } else {
  3696. xhci_ring_device(xhci, udev->slot_id);
  3697. }
  3698. finish:
  3699. spin_unlock_irqrestore(&xhci->lock, flags);
  3700. return ret;
  3701. }
  3702. int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
  3703. struct usb_device *udev, int enable)
  3704. {
  3705. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  3706. __le32 __iomem **port_array;
  3707. __le32 __iomem *pm_addr, *hlpm_addr;
  3708. u32 pm_val, hlpm_val, field;
  3709. unsigned int port_num;
  3710. unsigned long flags;
  3711. int hird, exit_latency;
  3712. int ret;
  3713. if (hcd->speed == HCD_USB3 || !xhci->hw_lpm_support ||
  3714. !udev->lpm_capable)
  3715. return -EPERM;
  3716. if (!udev->parent || udev->parent->parent ||
  3717. udev->descriptor.bDeviceClass == USB_CLASS_HUB)
  3718. return -EPERM;
  3719. if (udev->usb2_hw_lpm_capable != 1)
  3720. return -EPERM;
  3721. spin_lock_irqsave(&xhci->lock, flags);
  3722. port_array = xhci->usb2_ports;
  3723. port_num = udev->portnum - 1;
  3724. pm_addr = port_array[port_num] + PORTPMSC;
  3725. pm_val = xhci_readl(xhci, pm_addr);
  3726. hlpm_addr = port_array[port_num] + PORTHLPMC;
  3727. field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
  3728. xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
  3729. enable ? "enable" : "disable", port_num);
  3730. if (enable) {
  3731. /* Host supports BESL timeout instead of HIRD */
  3732. if (udev->usb2_hw_lpm_besl_capable) {
  3733. /* if device doesn't have a preferred BESL value use a
  3734. * default one which works with mixed HIRD and BESL
  3735. * systems. See XHCI_DEFAULT_BESL definition in xhci.h
  3736. */
  3737. if ((field & USB_BESL_SUPPORT) &&
  3738. (field & USB_BESL_BASELINE_VALID))
  3739. hird = USB_GET_BESL_BASELINE(field);
  3740. else
  3741. hird = udev->l1_params.besl;
  3742. exit_latency = xhci_besl_encoding[hird];
  3743. spin_unlock_irqrestore(&xhci->lock, flags);
  3744. /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
  3745. * input context for link powermanagement evaluate
  3746. * context commands. It is protected by hcd->bandwidth
  3747. * mutex and is shared by all devices. We need to set
  3748. * the max ext latency in USB 2 BESL LPM as well, so
  3749. * use the same mutex and xhci_change_max_exit_latency()
  3750. */
  3751. mutex_lock(hcd->bandwidth_mutex);
  3752. ret = xhci_change_max_exit_latency(xhci, udev,
  3753. exit_latency);
  3754. mutex_unlock(hcd->bandwidth_mutex);
  3755. if (ret < 0)
  3756. return ret;
  3757. spin_lock_irqsave(&xhci->lock, flags);
  3758. hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
  3759. xhci_writel(xhci, hlpm_val, hlpm_addr);
  3760. /* flush write */
  3761. xhci_readl(xhci, hlpm_addr);
  3762. } else {
  3763. hird = xhci_calculate_hird_besl(xhci, udev);
  3764. }
  3765. pm_val &= ~PORT_HIRD_MASK;
  3766. pm_val |= PORT_HIRD(hird) | PORT_RWE;
  3767. xhci_writel(xhci, pm_val, pm_addr);
  3768. pm_val = xhci_readl(xhci, pm_addr);
  3769. pm_val |= PORT_HLE;
  3770. xhci_writel(xhci, pm_val, pm_addr);
  3771. /* flush write */
  3772. xhci_readl(xhci, pm_addr);
  3773. } else {
  3774. pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK);
  3775. xhci_writel(xhci, pm_val, pm_addr);
  3776. /* flush write */
  3777. xhci_readl(xhci, pm_addr);
  3778. if (udev->usb2_hw_lpm_besl_capable) {
  3779. spin_unlock_irqrestore(&xhci->lock, flags);
  3780. mutex_lock(hcd->bandwidth_mutex);
  3781. xhci_change_max_exit_latency(xhci, udev, 0);
  3782. mutex_unlock(hcd->bandwidth_mutex);
  3783. return 0;
  3784. }
  3785. }
  3786. spin_unlock_irqrestore(&xhci->lock, flags);
  3787. return 0;
  3788. }
  3789. /* check if a usb2 port supports a given extened capability protocol
  3790. * only USB2 ports extended protocol capability values are cached.
  3791. * Return 1 if capability is supported
  3792. */
  3793. static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
  3794. unsigned capability)
  3795. {
  3796. u32 port_offset, port_count;
  3797. int i;
  3798. for (i = 0; i < xhci->num_ext_caps; i++) {
  3799. if (xhci->ext_caps[i] & capability) {
  3800. /* port offsets starts at 1 */
  3801. port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
  3802. port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
  3803. if (port >= port_offset &&
  3804. port < port_offset + port_count)
  3805. return 1;
  3806. }
  3807. }
  3808. return 0;
  3809. }
  3810. int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
  3811. {
  3812. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  3813. int ret;
  3814. int portnum = udev->portnum - 1;
  3815. ret = xhci_usb2_software_lpm_test(hcd, udev);
  3816. if (!ret) {
  3817. xhci_dbg(xhci, "software LPM test succeed\n");
  3818. if (xhci->hw_lpm_support == 1 &&
  3819. xhci_check_usb2_port_capability(xhci, portnum, XHCI_HLC)) {
  3820. udev->usb2_hw_lpm_capable = 1;
  3821. udev->l1_params.timeout = XHCI_L1_TIMEOUT;
  3822. udev->l1_params.besl = XHCI_DEFAULT_BESL;
  3823. if (xhci_check_usb2_port_capability(xhci, portnum,
  3824. XHCI_BLC))
  3825. udev->usb2_hw_lpm_besl_capable = 1;
  3826. ret = xhci_set_usb2_hardware_lpm(hcd, udev, 1);
  3827. if (!ret)
  3828. udev->usb2_hw_lpm_enabled = 1;
  3829. }
  3830. }
  3831. return 0;
  3832. }
  3833. #else
  3834. int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
  3835. struct usb_device *udev, int enable)
  3836. {
  3837. return 0;
  3838. }
  3839. int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
  3840. {
  3841. return 0;
  3842. }
  3843. #endif /* CONFIG_PM_RUNTIME */
  3844. /*---------------------- USB 3.0 Link PM functions ------------------------*/
  3845. #ifdef CONFIG_PM
  3846. /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
  3847. static unsigned long long xhci_service_interval_to_ns(
  3848. struct usb_endpoint_descriptor *desc)
  3849. {
  3850. return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
  3851. }
  3852. static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
  3853. enum usb3_link_state state)
  3854. {
  3855. unsigned long long sel;
  3856. unsigned long long pel;
  3857. unsigned int max_sel_pel;
  3858. char *state_name;
  3859. switch (state) {
  3860. case USB3_LPM_U1:
  3861. /* Convert SEL and PEL stored in nanoseconds to microseconds */
  3862. sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
  3863. pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
  3864. max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
  3865. state_name = "U1";
  3866. break;
  3867. case USB3_LPM_U2:
  3868. sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
  3869. pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
  3870. max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
  3871. state_name = "U2";
  3872. break;
  3873. default:
  3874. dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
  3875. __func__);
  3876. return USB3_LPM_DISABLED;
  3877. }
  3878. if (sel <= max_sel_pel && pel <= max_sel_pel)
  3879. return USB3_LPM_DEVICE_INITIATED;
  3880. if (sel > max_sel_pel)
  3881. dev_dbg(&udev->dev, "Device-initiated %s disabled "
  3882. "due to long SEL %llu ms\n",
  3883. state_name, sel);
  3884. else
  3885. dev_dbg(&udev->dev, "Device-initiated %s disabled "
  3886. "due to long PEL %llu ms\n",
  3887. state_name, pel);
  3888. return USB3_LPM_DISABLED;
  3889. }
  3890. /* Returns the hub-encoded U1 timeout value.
  3891. * The U1 timeout should be the maximum of the following values:
  3892. * - For control endpoints, U1 system exit latency (SEL) * 3
  3893. * - For bulk endpoints, U1 SEL * 5
  3894. * - For interrupt endpoints:
  3895. * - Notification EPs, U1 SEL * 3
  3896. * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
  3897. * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
  3898. */
  3899. static u16 xhci_calculate_intel_u1_timeout(struct usb_device *udev,
  3900. struct usb_endpoint_descriptor *desc)
  3901. {
  3902. unsigned long long timeout_ns;
  3903. int ep_type;
  3904. int intr_type;
  3905. ep_type = usb_endpoint_type(desc);
  3906. switch (ep_type) {
  3907. case USB_ENDPOINT_XFER_CONTROL:
  3908. timeout_ns = udev->u1_params.sel * 3;
  3909. break;
  3910. case USB_ENDPOINT_XFER_BULK:
  3911. timeout_ns = udev->u1_params.sel * 5;
  3912. break;
  3913. case USB_ENDPOINT_XFER_INT:
  3914. intr_type = usb_endpoint_interrupt_type(desc);
  3915. if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
  3916. timeout_ns = udev->u1_params.sel * 3;
  3917. break;
  3918. }
  3919. /* Otherwise the calculation is the same as isoc eps */
  3920. case USB_ENDPOINT_XFER_ISOC:
  3921. timeout_ns = xhci_service_interval_to_ns(desc);
  3922. timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
  3923. if (timeout_ns < udev->u1_params.sel * 2)
  3924. timeout_ns = udev->u1_params.sel * 2;
  3925. break;
  3926. default:
  3927. return 0;
  3928. }
  3929. /* The U1 timeout is encoded in 1us intervals. */
  3930. timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
  3931. /* Don't return a timeout of zero, because that's USB3_LPM_DISABLED. */
  3932. if (timeout_ns == USB3_LPM_DISABLED)
  3933. timeout_ns++;
  3934. /* If the necessary timeout value is bigger than what we can set in the
  3935. * USB 3.0 hub, we have to disable hub-initiated U1.
  3936. */
  3937. if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
  3938. return timeout_ns;
  3939. dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
  3940. "due to long timeout %llu ms\n", timeout_ns);
  3941. return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
  3942. }
  3943. /* Returns the hub-encoded U2 timeout value.
  3944. * The U2 timeout should be the maximum of:
  3945. * - 10 ms (to avoid the bandwidth impact on the scheduler)
  3946. * - largest bInterval of any active periodic endpoint (to avoid going
  3947. * into lower power link states between intervals).
  3948. * - the U2 Exit Latency of the device
  3949. */
  3950. static u16 xhci_calculate_intel_u2_timeout(struct usb_device *udev,
  3951. struct usb_endpoint_descriptor *desc)
  3952. {
  3953. unsigned long long timeout_ns;
  3954. unsigned long long u2_del_ns;
  3955. timeout_ns = 10 * 1000 * 1000;
  3956. if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
  3957. (xhci_service_interval_to_ns(desc) > timeout_ns))
  3958. timeout_ns = xhci_service_interval_to_ns(desc);
  3959. u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
  3960. if (u2_del_ns > timeout_ns)
  3961. timeout_ns = u2_del_ns;
  3962. /* The U2 timeout is encoded in 256us intervals */
  3963. timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
  3964. /* If the necessary timeout value is bigger than what we can set in the
  3965. * USB 3.0 hub, we have to disable hub-initiated U2.
  3966. */
  3967. if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
  3968. return timeout_ns;
  3969. dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
  3970. "due to long timeout %llu ms\n", timeout_ns);
  3971. return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
  3972. }
  3973. static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
  3974. struct usb_device *udev,
  3975. struct usb_endpoint_descriptor *desc,
  3976. enum usb3_link_state state,
  3977. u16 *timeout)
  3978. {
  3979. if (state == USB3_LPM_U1) {
  3980. if (xhci->quirks & XHCI_INTEL_HOST)
  3981. return xhci_calculate_intel_u1_timeout(udev, desc);
  3982. } else {
  3983. if (xhci->quirks & XHCI_INTEL_HOST)
  3984. return xhci_calculate_intel_u2_timeout(udev, desc);
  3985. }
  3986. return USB3_LPM_DISABLED;
  3987. }
  3988. static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
  3989. struct usb_device *udev,
  3990. struct usb_endpoint_descriptor *desc,
  3991. enum usb3_link_state state,
  3992. u16 *timeout)
  3993. {
  3994. u16 alt_timeout;
  3995. alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
  3996. desc, state, timeout);
  3997. /* If we found we can't enable hub-initiated LPM, or
  3998. * the U1 or U2 exit latency was too high to allow
  3999. * device-initiated LPM as well, just stop searching.
  4000. */
  4001. if (alt_timeout == USB3_LPM_DISABLED ||
  4002. alt_timeout == USB3_LPM_DEVICE_INITIATED) {
  4003. *timeout = alt_timeout;
  4004. return -E2BIG;
  4005. }
  4006. if (alt_timeout > *timeout)
  4007. *timeout = alt_timeout;
  4008. return 0;
  4009. }
  4010. static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
  4011. struct usb_device *udev,
  4012. struct usb_host_interface *alt,
  4013. enum usb3_link_state state,
  4014. u16 *timeout)
  4015. {
  4016. int j;
  4017. for (j = 0; j < alt->desc.bNumEndpoints; j++) {
  4018. if (xhci_update_timeout_for_endpoint(xhci, udev,
  4019. &alt->endpoint[j].desc, state, timeout))
  4020. return -E2BIG;
  4021. continue;
  4022. }
  4023. return 0;
  4024. }
  4025. static int xhci_check_intel_tier_policy(struct usb_device *udev,
  4026. enum usb3_link_state state)
  4027. {
  4028. struct usb_device *parent;
  4029. unsigned int num_hubs;
  4030. if (state == USB3_LPM_U2)
  4031. return 0;
  4032. /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
  4033. for (parent = udev->parent, num_hubs = 0; parent->parent;
  4034. parent = parent->parent)
  4035. num_hubs++;
  4036. if (num_hubs < 2)
  4037. return 0;
  4038. dev_dbg(&udev->dev, "Disabling U1 link state for device"
  4039. " below second-tier hub.\n");
  4040. dev_dbg(&udev->dev, "Plug device into first-tier hub "
  4041. "to decrease power consumption.\n");
  4042. return -E2BIG;
  4043. }
  4044. static int xhci_check_tier_policy(struct xhci_hcd *xhci,
  4045. struct usb_device *udev,
  4046. enum usb3_link_state state)
  4047. {
  4048. if (xhci->quirks & XHCI_INTEL_HOST)
  4049. return xhci_check_intel_tier_policy(udev, state);
  4050. return -EINVAL;
  4051. }
  4052. /* Returns the U1 or U2 timeout that should be enabled.
  4053. * If the tier check or timeout setting functions return with a non-zero exit
  4054. * code, that means the timeout value has been finalized and we shouldn't look
  4055. * at any more endpoints.
  4056. */
  4057. static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
  4058. struct usb_device *udev, enum usb3_link_state state)
  4059. {
  4060. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  4061. struct usb_host_config *config;
  4062. char *state_name;
  4063. int i;
  4064. u16 timeout = USB3_LPM_DISABLED;
  4065. if (state == USB3_LPM_U1)
  4066. state_name = "U1";
  4067. else if (state == USB3_LPM_U2)
  4068. state_name = "U2";
  4069. else {
  4070. dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
  4071. state);
  4072. return timeout;
  4073. }
  4074. if (xhci_check_tier_policy(xhci, udev, state) < 0)
  4075. return timeout;
  4076. /* Gather some information about the currently installed configuration
  4077. * and alternate interface settings.
  4078. */
  4079. if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
  4080. state, &timeout))
  4081. return timeout;
  4082. config = udev->actconfig;
  4083. if (!config)
  4084. return timeout;
  4085. for (i = 0; i < USB_MAXINTERFACES; i++) {
  4086. struct usb_driver *driver;
  4087. struct usb_interface *intf = config->interface[i];
  4088. if (!intf)
  4089. continue;
  4090. /* Check if any currently bound drivers want hub-initiated LPM
  4091. * disabled.
  4092. */
  4093. if (intf->dev.driver) {
  4094. driver = to_usb_driver(intf->dev.driver);
  4095. if (driver && driver->disable_hub_initiated_lpm) {
  4096. dev_dbg(&udev->dev, "Hub-initiated %s disabled "
  4097. "at request of driver %s\n",
  4098. state_name, driver->name);
  4099. return xhci_get_timeout_no_hub_lpm(udev, state);
  4100. }
  4101. }
  4102. /* Not sure how this could happen... */
  4103. if (!intf->cur_altsetting)
  4104. continue;
  4105. if (xhci_update_timeout_for_interface(xhci, udev,
  4106. intf->cur_altsetting,
  4107. state, &timeout))
  4108. return timeout;
  4109. }
  4110. return timeout;
  4111. }
  4112. static int calculate_max_exit_latency(struct usb_device *udev,
  4113. enum usb3_link_state state_changed,
  4114. u16 hub_encoded_timeout)
  4115. {
  4116. unsigned long long u1_mel_us = 0;
  4117. unsigned long long u2_mel_us = 0;
  4118. unsigned long long mel_us = 0;
  4119. bool disabling_u1;
  4120. bool disabling_u2;
  4121. bool enabling_u1;
  4122. bool enabling_u2;
  4123. disabling_u1 = (state_changed == USB3_LPM_U1 &&
  4124. hub_encoded_timeout == USB3_LPM_DISABLED);
  4125. disabling_u2 = (state_changed == USB3_LPM_U2 &&
  4126. hub_encoded_timeout == USB3_LPM_DISABLED);
  4127. enabling_u1 = (state_changed == USB3_LPM_U1 &&
  4128. hub_encoded_timeout != USB3_LPM_DISABLED);
  4129. enabling_u2 = (state_changed == USB3_LPM_U2 &&
  4130. hub_encoded_timeout != USB3_LPM_DISABLED);
  4131. /* If U1 was already enabled and we're not disabling it,
  4132. * or we're going to enable U1, account for the U1 max exit latency.
  4133. */
  4134. if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
  4135. enabling_u1)
  4136. u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
  4137. if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
  4138. enabling_u2)
  4139. u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
  4140. if (u1_mel_us > u2_mel_us)
  4141. mel_us = u1_mel_us;
  4142. else
  4143. mel_us = u2_mel_us;
  4144. /* xHCI host controller max exit latency field is only 16 bits wide. */
  4145. if (mel_us > MAX_EXIT) {
  4146. dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
  4147. "is too big.\n", mel_us);
  4148. return -E2BIG;
  4149. }
  4150. return mel_us;
  4151. }
  4152. /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
  4153. int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
  4154. struct usb_device *udev, enum usb3_link_state state)
  4155. {
  4156. struct xhci_hcd *xhci;
  4157. u16 hub_encoded_timeout;
  4158. int mel;
  4159. int ret;
  4160. xhci = hcd_to_xhci(hcd);
  4161. /* The LPM timeout values are pretty host-controller specific, so don't
  4162. * enable hub-initiated timeouts unless the vendor has provided
  4163. * information about their timeout algorithm.
  4164. */
  4165. if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
  4166. !xhci->devs[udev->slot_id])
  4167. return USB3_LPM_DISABLED;
  4168. hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
  4169. mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
  4170. if (mel < 0) {
  4171. /* Max Exit Latency is too big, disable LPM. */
  4172. hub_encoded_timeout = USB3_LPM_DISABLED;
  4173. mel = 0;
  4174. }
  4175. ret = xhci_change_max_exit_latency(xhci, udev, mel);
  4176. if (ret)
  4177. return ret;
  4178. return hub_encoded_timeout;
  4179. }
  4180. int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
  4181. struct usb_device *udev, enum usb3_link_state state)
  4182. {
  4183. struct xhci_hcd *xhci;
  4184. u16 mel;
  4185. int ret;
  4186. xhci = hcd_to_xhci(hcd);
  4187. if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
  4188. !xhci->devs[udev->slot_id])
  4189. return 0;
  4190. mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
  4191. ret = xhci_change_max_exit_latency(xhci, udev, mel);
  4192. if (ret)
  4193. return ret;
  4194. return 0;
  4195. }
  4196. #else /* CONFIG_PM */
  4197. int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
  4198. struct usb_device *udev, enum usb3_link_state state)
  4199. {
  4200. return USB3_LPM_DISABLED;
  4201. }
  4202. int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
  4203. struct usb_device *udev, enum usb3_link_state state)
  4204. {
  4205. return 0;
  4206. }
  4207. #endif /* CONFIG_PM */
  4208. /*-------------------------------------------------------------------------*/
  4209. /* Once a hub descriptor is fetched for a device, we need to update the xHC's
  4210. * internal data structures for the device.
  4211. */
  4212. int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
  4213. struct usb_tt *tt, gfp_t mem_flags)
  4214. {
  4215. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  4216. struct xhci_virt_device *vdev;
  4217. struct xhci_command *config_cmd;
  4218. struct xhci_input_control_ctx *ctrl_ctx;
  4219. struct xhci_slot_ctx *slot_ctx;
  4220. unsigned long flags;
  4221. unsigned think_time;
  4222. int ret;
  4223. /* Ignore root hubs */
  4224. if (!hdev->parent)
  4225. return 0;
  4226. vdev = xhci->devs[hdev->slot_id];
  4227. if (!vdev) {
  4228. xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
  4229. return -EINVAL;
  4230. }
  4231. config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
  4232. if (!config_cmd) {
  4233. xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
  4234. return -ENOMEM;
  4235. }
  4236. ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx);
  4237. if (!ctrl_ctx) {
  4238. xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
  4239. __func__);
  4240. xhci_free_command(xhci, config_cmd);
  4241. return -ENOMEM;
  4242. }
  4243. spin_lock_irqsave(&xhci->lock, flags);
  4244. if (hdev->speed == USB_SPEED_HIGH &&
  4245. xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
  4246. xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
  4247. xhci_free_command(xhci, config_cmd);
  4248. spin_unlock_irqrestore(&xhci->lock, flags);
  4249. return -ENOMEM;
  4250. }
  4251. xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
  4252. ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
  4253. slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
  4254. slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
  4255. if (tt->multi)
  4256. slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
  4257. if (xhci->hci_version > 0x95) {
  4258. xhci_dbg(xhci, "xHCI version %x needs hub "
  4259. "TT think time and number of ports\n",
  4260. (unsigned int) xhci->hci_version);
  4261. slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
  4262. /* Set TT think time - convert from ns to FS bit times.
  4263. * 0 = 8 FS bit times, 1 = 16 FS bit times,
  4264. * 2 = 24 FS bit times, 3 = 32 FS bit times.
  4265. *
  4266. * xHCI 1.0: this field shall be 0 if the device is not a
  4267. * High-spped hub.
  4268. */
  4269. think_time = tt->think_time;
  4270. if (think_time != 0)
  4271. think_time = (think_time / 666) - 1;
  4272. if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
  4273. slot_ctx->tt_info |=
  4274. cpu_to_le32(TT_THINK_TIME(think_time));
  4275. } else {
  4276. xhci_dbg(xhci, "xHCI version %x doesn't need hub "
  4277. "TT think time or number of ports\n",
  4278. (unsigned int) xhci->hci_version);
  4279. }
  4280. slot_ctx->dev_state = 0;
  4281. spin_unlock_irqrestore(&xhci->lock, flags);
  4282. xhci_dbg(xhci, "Set up %s for hub device.\n",
  4283. (xhci->hci_version > 0x95) ?
  4284. "configure endpoint" : "evaluate context");
  4285. xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
  4286. xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
  4287. /* Issue and wait for the configure endpoint or
  4288. * evaluate context command.
  4289. */
  4290. if (xhci->hci_version > 0x95)
  4291. ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
  4292. false, false);
  4293. else
  4294. ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
  4295. true, false);
  4296. xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
  4297. xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
  4298. xhci_free_command(xhci, config_cmd);
  4299. return ret;
  4300. }
  4301. int xhci_get_frame(struct usb_hcd *hcd)
  4302. {
  4303. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  4304. /* EHCI mods by the periodic size. Why? */
  4305. return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3;
  4306. }
  4307. int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
  4308. {
  4309. struct xhci_hcd *xhci;
  4310. struct device *dev = hcd->self.controller;
  4311. int retval;
  4312. /* Accept arbitrarily long scatter-gather lists */
  4313. hcd->self.sg_tablesize = ~0;
  4314. /* support to build packet from discontinuous buffers */
  4315. hcd->self.no_sg_constraint = 1;
  4316. /* XHCI controllers don't stop the ep queue on short packets :| */
  4317. hcd->self.no_stop_on_short = 1;
  4318. if (usb_hcd_is_primary_hcd(hcd)) {
  4319. xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
  4320. if (!xhci)
  4321. return -ENOMEM;
  4322. *((struct xhci_hcd **) hcd->hcd_priv) = xhci;
  4323. xhci->main_hcd = hcd;
  4324. /* Mark the first roothub as being USB 2.0.
  4325. * The xHCI driver will register the USB 3.0 roothub.
  4326. */
  4327. hcd->speed = HCD_USB2;
  4328. hcd->self.root_hub->speed = USB_SPEED_HIGH;
  4329. /*
  4330. * USB 2.0 roothub under xHCI has an integrated TT,
  4331. * (rate matching hub) as opposed to having an OHCI/UHCI
  4332. * companion controller.
  4333. */
  4334. hcd->has_tt = 1;
  4335. } else {
  4336. /* xHCI private pointer was set in xhci_pci_probe for the second
  4337. * registered roothub.
  4338. */
  4339. return 0;
  4340. }
  4341. xhci->cap_regs = hcd->regs;
  4342. xhci->op_regs = hcd->regs +
  4343. HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));
  4344. xhci->run_regs = hcd->regs +
  4345. (xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
  4346. /* Cache read-only capability registers */
  4347. xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
  4348. xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
  4349. xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
  4350. xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
  4351. xhci->hci_version = HC_VERSION(xhci->hcc_params);
  4352. xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
  4353. xhci_print_registers(xhci);
  4354. get_quirks(dev, xhci);
  4355. /* In xhci controllers which follow xhci 1.0 spec gives a spurious
  4356. * success event after a short transfer. This quirk will ignore such
  4357. * spurious event.
  4358. */
  4359. if (xhci->hci_version > 0x96)
  4360. xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
  4361. /* Make sure the HC is halted. */
  4362. retval = xhci_halt(xhci);
  4363. if (retval)
  4364. goto error;
  4365. xhci_dbg(xhci, "Resetting HCD\n");
  4366. /* Reset the internal HC memory state and registers. */
  4367. retval = xhci_reset(xhci);
  4368. if (retval)
  4369. goto error;
  4370. xhci_dbg(xhci, "Reset complete\n");
  4371. /* Set dma_mask and coherent_dma_mask to 64-bits,
  4372. * if xHC supports 64-bit addressing */
  4373. if (HCC_64BIT_ADDR(xhci->hcc_params) &&
  4374. !dma_set_mask(dev, DMA_BIT_MASK(64))) {
  4375. xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
  4376. dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
  4377. }
  4378. xhci_dbg(xhci, "Calling HCD init\n");
  4379. /* Initialize HCD and host controller data structures. */
  4380. retval = xhci_init(hcd);
  4381. if (retval)
  4382. goto error;
  4383. xhci_dbg(xhci, "Called HCD init\n");
  4384. return 0;
  4385. error:
  4386. kfree(xhci);
  4387. return retval;
  4388. }
  4389. MODULE_DESCRIPTION(DRIVER_DESC);
  4390. MODULE_AUTHOR(DRIVER_AUTHOR);
  4391. MODULE_LICENSE("GPL");
  4392. static int __init xhci_hcd_init(void)
  4393. {
  4394. int retval;
  4395. retval = xhci_register_pci();
  4396. if (retval < 0) {
  4397. pr_debug("Problem registering PCI driver.\n");
  4398. return retval;
  4399. }
  4400. retval = xhci_register_plat();
  4401. if (retval < 0) {
  4402. pr_debug("Problem registering platform driver.\n");
  4403. goto unreg_pci;
  4404. }
  4405. /*
  4406. * Check the compiler generated sizes of structures that must be laid
  4407. * out in specific ways for hardware access.
  4408. */
  4409. BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
  4410. BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
  4411. BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
  4412. /* xhci_device_control has eight fields, and also
  4413. * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
  4414. */
  4415. BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
  4416. BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
  4417. BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
  4418. BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 7*32/8);
  4419. BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
  4420. /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
  4421. BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
  4422. return 0;
  4423. unreg_pci:
  4424. xhci_unregister_pci();
  4425. return retval;
  4426. }
  4427. module_init(xhci_hcd_init);
  4428. static void __exit xhci_hcd_cleanup(void)
  4429. {
  4430. xhci_unregister_pci();
  4431. xhci_unregister_plat();
  4432. }
  4433. module_exit(xhci_hcd_cleanup);