xhci-hub.c 36 KB

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  1. /*
  2. * xHCI host controller driver
  3. *
  4. * Copyright (C) 2008 Intel Corp.
  5. *
  6. * Author: Sarah Sharp
  7. * Some code borrowed from the Linux EHCI driver.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/gfp.h>
  23. #include <asm/unaligned.h>
  24. #include "xhci.h"
  25. #include "xhci-trace.h"
  26. #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  27. #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  28. PORT_RC | PORT_PLC | PORT_PE)
  29. /* USB 3.0 BOS descriptor and a capability descriptor, combined */
  30. static u8 usb_bos_descriptor [] = {
  31. USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
  32. USB_DT_BOS, /* __u8 bDescriptorType */
  33. 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
  34. 0x1, /* __u8 bNumDeviceCaps */
  35. /* First device capability */
  36. USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
  37. USB_DT_DEVICE_CAPABILITY, /* Device Capability */
  38. USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
  39. 0x00, /* bmAttributes, LTM off by default */
  40. USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
  41. 0x03, /* bFunctionalitySupport,
  42. USB 3.0 speed only */
  43. 0x00, /* bU1DevExitLat, set later. */
  44. 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */
  45. };
  46. static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
  47. struct usb_hub_descriptor *desc, int ports)
  48. {
  49. u16 temp;
  50. desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
  51. desc->bHubContrCurrent = 0;
  52. desc->bNbrPorts = ports;
  53. temp = 0;
  54. /* Bits 1:0 - support per-port power switching, or power always on */
  55. if (HCC_PPC(xhci->hcc_params))
  56. temp |= HUB_CHAR_INDV_PORT_LPSM;
  57. else
  58. temp |= HUB_CHAR_NO_LPSM;
  59. /* Bit 2 - root hubs are not part of a compound device */
  60. /* Bits 4:3 - individual port over current protection */
  61. temp |= HUB_CHAR_INDV_PORT_OCPM;
  62. /* Bits 6:5 - no TTs in root ports */
  63. /* Bit 7 - no port indicators */
  64. desc->wHubCharacteristics = cpu_to_le16(temp);
  65. }
  66. /* Fill in the USB 2.0 roothub descriptor */
  67. static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  68. struct usb_hub_descriptor *desc)
  69. {
  70. int ports;
  71. u16 temp;
  72. __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
  73. u32 portsc;
  74. unsigned int i;
  75. ports = xhci->num_usb2_ports;
  76. xhci_common_hub_descriptor(xhci, desc, ports);
  77. desc->bDescriptorType = USB_DT_HUB;
  78. temp = 1 + (ports / 8);
  79. desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
  80. /* The Device Removable bits are reported on a byte granularity.
  81. * If the port doesn't exist within that byte, the bit is set to 0.
  82. */
  83. memset(port_removable, 0, sizeof(port_removable));
  84. for (i = 0; i < ports; i++) {
  85. portsc = xhci_readl(xhci, xhci->usb2_ports[i]);
  86. /* If a device is removable, PORTSC reports a 0, same as in the
  87. * hub descriptor DeviceRemovable bits.
  88. */
  89. if (portsc & PORT_DEV_REMOVE)
  90. /* This math is hairy because bit 0 of DeviceRemovable
  91. * is reserved, and bit 1 is for port 1, etc.
  92. */
  93. port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
  94. }
  95. /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
  96. * ports on it. The USB 2.0 specification says that there are two
  97. * variable length fields at the end of the hub descriptor:
  98. * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
  99. * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
  100. * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
  101. * 0xFF, so we initialize the both arrays (DeviceRemovable and
  102. * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
  103. * set of ports that actually exist.
  104. */
  105. memset(desc->u.hs.DeviceRemovable, 0xff,
  106. sizeof(desc->u.hs.DeviceRemovable));
  107. memset(desc->u.hs.PortPwrCtrlMask, 0xff,
  108. sizeof(desc->u.hs.PortPwrCtrlMask));
  109. for (i = 0; i < (ports + 1 + 7) / 8; i++)
  110. memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
  111. sizeof(__u8));
  112. }
  113. /* Fill in the USB 3.0 roothub descriptor */
  114. static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  115. struct usb_hub_descriptor *desc)
  116. {
  117. int ports;
  118. u16 port_removable;
  119. u32 portsc;
  120. unsigned int i;
  121. ports = xhci->num_usb3_ports;
  122. xhci_common_hub_descriptor(xhci, desc, ports);
  123. desc->bDescriptorType = USB_DT_SS_HUB;
  124. desc->bDescLength = USB_DT_SS_HUB_SIZE;
  125. /* header decode latency should be zero for roothubs,
  126. * see section 4.23.5.2.
  127. */
  128. desc->u.ss.bHubHdrDecLat = 0;
  129. desc->u.ss.wHubDelay = 0;
  130. port_removable = 0;
  131. /* bit 0 is reserved, bit 1 is for port 1, etc. */
  132. for (i = 0; i < ports; i++) {
  133. portsc = xhci_readl(xhci, xhci->usb3_ports[i]);
  134. if (portsc & PORT_DEV_REMOVE)
  135. port_removable |= 1 << (i + 1);
  136. }
  137. desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
  138. }
  139. static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  140. struct usb_hub_descriptor *desc)
  141. {
  142. if (hcd->speed == HCD_USB3)
  143. xhci_usb3_hub_descriptor(hcd, xhci, desc);
  144. else
  145. xhci_usb2_hub_descriptor(hcd, xhci, desc);
  146. }
  147. static unsigned int xhci_port_speed(unsigned int port_status)
  148. {
  149. if (DEV_LOWSPEED(port_status))
  150. return USB_PORT_STAT_LOW_SPEED;
  151. if (DEV_HIGHSPEED(port_status))
  152. return USB_PORT_STAT_HIGH_SPEED;
  153. /*
  154. * FIXME: Yes, we should check for full speed, but the core uses that as
  155. * a default in portspeed() in usb/core/hub.c (which is the only place
  156. * USB_PORT_STAT_*_SPEED is used).
  157. */
  158. return 0;
  159. }
  160. /*
  161. * These bits are Read Only (RO) and should be saved and written to the
  162. * registers: 0, 3, 10:13, 30
  163. * connect status, over-current status, port speed, and device removable.
  164. * connect status and port speed are also sticky - meaning they're in
  165. * the AUX well and they aren't changed by a hot, warm, or cold reset.
  166. */
  167. #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
  168. /*
  169. * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
  170. * bits 5:8, 9, 14:15, 25:27
  171. * link state, port power, port indicator state, "wake on" enable state
  172. */
  173. #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
  174. /*
  175. * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
  176. * bit 4 (port reset)
  177. */
  178. #define XHCI_PORT_RW1S ((1<<4))
  179. /*
  180. * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
  181. * bits 1, 17, 18, 19, 20, 21, 22, 23
  182. * port enable/disable, and
  183. * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
  184. * over-current, reset, link state, and L1 change
  185. */
  186. #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
  187. /*
  188. * Bit 16 is RW, and writing a '1' to it causes the link state control to be
  189. * latched in
  190. */
  191. #define XHCI_PORT_RW ((1<<16))
  192. /*
  193. * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
  194. * bits 2, 24, 28:31
  195. */
  196. #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
  197. /*
  198. * Given a port state, this function returns a value that would result in the
  199. * port being in the same state, if the value was written to the port status
  200. * control register.
  201. * Save Read Only (RO) bits and save read/write bits where
  202. * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
  203. * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
  204. */
  205. u32 xhci_port_state_to_neutral(u32 state)
  206. {
  207. /* Save read-only status and port state */
  208. return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
  209. }
  210. /*
  211. * find slot id based on port number.
  212. * @port: The one-based port number from one of the two split roothubs.
  213. */
  214. int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  215. u16 port)
  216. {
  217. int slot_id;
  218. int i;
  219. enum usb_device_speed speed;
  220. slot_id = 0;
  221. for (i = 0; i < MAX_HC_SLOTS; i++) {
  222. if (!xhci->devs[i])
  223. continue;
  224. speed = xhci->devs[i]->udev->speed;
  225. if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
  226. && xhci->devs[i]->fake_port == port) {
  227. slot_id = i;
  228. break;
  229. }
  230. }
  231. return slot_id;
  232. }
  233. /*
  234. * Stop device
  235. * It issues stop endpoint command for EP 0 to 30. And wait the last command
  236. * to complete.
  237. * suspend will set to 1, if suspend bit need to set in command.
  238. */
  239. static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
  240. {
  241. struct xhci_virt_device *virt_dev;
  242. struct xhci_command *cmd;
  243. unsigned long flags;
  244. int timeleft;
  245. int ret;
  246. int i;
  247. ret = 0;
  248. virt_dev = xhci->devs[slot_id];
  249. cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
  250. if (!cmd) {
  251. xhci_dbg(xhci, "Couldn't allocate command structure.\n");
  252. return -ENOMEM;
  253. }
  254. spin_lock_irqsave(&xhci->lock, flags);
  255. for (i = LAST_EP_INDEX; i > 0; i--) {
  256. if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue)
  257. xhci_queue_stop_endpoint(xhci, slot_id, i, suspend);
  258. }
  259. cmd->command_trb = xhci->cmd_ring->enqueue;
  260. list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list);
  261. xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend);
  262. xhci_ring_cmd_db(xhci);
  263. spin_unlock_irqrestore(&xhci->lock, flags);
  264. /* Wait for last stop endpoint command to finish */
  265. timeleft = wait_for_completion_interruptible_timeout(
  266. cmd->completion,
  267. USB_CTRL_SET_TIMEOUT);
  268. if (timeleft <= 0) {
  269. xhci_warn(xhci, "%s while waiting for stop endpoint command\n",
  270. timeleft == 0 ? "Timeout" : "Signal");
  271. spin_lock_irqsave(&xhci->lock, flags);
  272. /* The timeout might have raced with the event ring handler, so
  273. * only delete from the list if the item isn't poisoned.
  274. */
  275. if (cmd->cmd_list.next != LIST_POISON1)
  276. list_del(&cmd->cmd_list);
  277. spin_unlock_irqrestore(&xhci->lock, flags);
  278. ret = -ETIME;
  279. goto command_cleanup;
  280. }
  281. command_cleanup:
  282. xhci_free_command(xhci, cmd);
  283. return ret;
  284. }
  285. /*
  286. * Ring device, it rings the all doorbells unconditionally.
  287. */
  288. void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
  289. {
  290. int i;
  291. for (i = 0; i < LAST_EP_INDEX + 1; i++)
  292. if (xhci->devs[slot_id]->eps[i].ring &&
  293. xhci->devs[slot_id]->eps[i].ring->dequeue)
  294. xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
  295. return;
  296. }
  297. static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  298. u16 wIndex, __le32 __iomem *addr, u32 port_status)
  299. {
  300. /* Don't allow the USB core to disable SuperSpeed ports. */
  301. if (hcd->speed == HCD_USB3) {
  302. xhci_dbg(xhci, "Ignoring request to disable "
  303. "SuperSpeed port.\n");
  304. return;
  305. }
  306. /* Write 1 to disable the port */
  307. xhci_writel(xhci, port_status | PORT_PE, addr);
  308. port_status = xhci_readl(xhci, addr);
  309. xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
  310. wIndex, port_status);
  311. }
  312. static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
  313. u16 wIndex, __le32 __iomem *addr, u32 port_status)
  314. {
  315. char *port_change_bit;
  316. u32 status;
  317. switch (wValue) {
  318. case USB_PORT_FEAT_C_RESET:
  319. status = PORT_RC;
  320. port_change_bit = "reset";
  321. break;
  322. case USB_PORT_FEAT_C_BH_PORT_RESET:
  323. status = PORT_WRC;
  324. port_change_bit = "warm(BH) reset";
  325. break;
  326. case USB_PORT_FEAT_C_CONNECTION:
  327. status = PORT_CSC;
  328. port_change_bit = "connect";
  329. break;
  330. case USB_PORT_FEAT_C_OVER_CURRENT:
  331. status = PORT_OCC;
  332. port_change_bit = "over-current";
  333. break;
  334. case USB_PORT_FEAT_C_ENABLE:
  335. status = PORT_PEC;
  336. port_change_bit = "enable/disable";
  337. break;
  338. case USB_PORT_FEAT_C_SUSPEND:
  339. status = PORT_PLC;
  340. port_change_bit = "suspend/resume";
  341. break;
  342. case USB_PORT_FEAT_C_PORT_LINK_STATE:
  343. status = PORT_PLC;
  344. port_change_bit = "link state";
  345. break;
  346. default:
  347. /* Should never happen */
  348. return;
  349. }
  350. /* Change bits are all write 1 to clear */
  351. xhci_writel(xhci, port_status | status, addr);
  352. port_status = xhci_readl(xhci, addr);
  353. xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
  354. port_change_bit, wIndex, port_status);
  355. }
  356. static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
  357. {
  358. int max_ports;
  359. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  360. if (hcd->speed == HCD_USB3) {
  361. max_ports = xhci->num_usb3_ports;
  362. *port_array = xhci->usb3_ports;
  363. } else {
  364. max_ports = xhci->num_usb2_ports;
  365. *port_array = xhci->usb2_ports;
  366. }
  367. return max_ports;
  368. }
  369. void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
  370. int port_id, u32 link_state)
  371. {
  372. u32 temp;
  373. temp = xhci_readl(xhci, port_array[port_id]);
  374. temp = xhci_port_state_to_neutral(temp);
  375. temp &= ~PORT_PLS_MASK;
  376. temp |= PORT_LINK_STROBE | link_state;
  377. xhci_writel(xhci, temp, port_array[port_id]);
  378. }
  379. static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
  380. __le32 __iomem **port_array, int port_id, u16 wake_mask)
  381. {
  382. u32 temp;
  383. temp = xhci_readl(xhci, port_array[port_id]);
  384. temp = xhci_port_state_to_neutral(temp);
  385. if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
  386. temp |= PORT_WKCONN_E;
  387. else
  388. temp &= ~PORT_WKCONN_E;
  389. if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
  390. temp |= PORT_WKDISC_E;
  391. else
  392. temp &= ~PORT_WKDISC_E;
  393. if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
  394. temp |= PORT_WKOC_E;
  395. else
  396. temp &= ~PORT_WKOC_E;
  397. xhci_writel(xhci, temp, port_array[port_id]);
  398. }
  399. /* Test and clear port RWC bit */
  400. void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
  401. int port_id, u32 port_bit)
  402. {
  403. u32 temp;
  404. temp = xhci_readl(xhci, port_array[port_id]);
  405. if (temp & port_bit) {
  406. temp = xhci_port_state_to_neutral(temp);
  407. temp |= port_bit;
  408. xhci_writel(xhci, temp, port_array[port_id]);
  409. }
  410. }
  411. /* Updates Link Status for USB 2.1 port */
  412. static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
  413. {
  414. if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
  415. *status |= USB_PORT_STAT_L1;
  416. }
  417. /* Updates Link Status for super Speed port */
  418. static void xhci_hub_report_usb3_link_state(u32 *status, u32 status_reg)
  419. {
  420. u32 pls = status_reg & PORT_PLS_MASK;
  421. /* resume state is a xHCI internal state.
  422. * Do not report it to usb core.
  423. */
  424. if (pls == XDEV_RESUME)
  425. return;
  426. /* When the CAS bit is set then warm reset
  427. * should be performed on port
  428. */
  429. if (status_reg & PORT_CAS) {
  430. /* The CAS bit can be set while the port is
  431. * in any link state.
  432. * Only roothubs have CAS bit, so we
  433. * pretend to be in compliance mode
  434. * unless we're already in compliance
  435. * or the inactive state.
  436. */
  437. if (pls != USB_SS_PORT_LS_COMP_MOD &&
  438. pls != USB_SS_PORT_LS_SS_INACTIVE) {
  439. pls = USB_SS_PORT_LS_COMP_MOD;
  440. }
  441. /* Return also connection bit -
  442. * hub state machine resets port
  443. * when this bit is set.
  444. */
  445. pls |= USB_PORT_STAT_CONNECTION;
  446. } else {
  447. /*
  448. * If CAS bit isn't set but the Port is already at
  449. * Compliance Mode, fake a connection so the USB core
  450. * notices the Compliance state and resets the port.
  451. * This resolves an issue generated by the SN65LVPE502CP
  452. * in which sometimes the port enters compliance mode
  453. * caused by a delay on the host-device negotiation.
  454. */
  455. if (pls == USB_SS_PORT_LS_COMP_MOD)
  456. pls |= USB_PORT_STAT_CONNECTION;
  457. }
  458. /* update status field */
  459. *status |= pls;
  460. }
  461. /*
  462. * Function for Compliance Mode Quirk.
  463. *
  464. * This Function verifies if all xhc USB3 ports have entered U0, if so,
  465. * the compliance mode timer is deleted. A port won't enter
  466. * compliance mode if it has previously entered U0.
  467. */
  468. void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, u16 wIndex)
  469. {
  470. u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
  471. bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
  472. if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
  473. return;
  474. if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
  475. xhci->port_status_u0 |= 1 << wIndex;
  476. if (xhci->port_status_u0 == all_ports_seen_u0) {
  477. del_timer_sync(&xhci->comp_mode_recovery_timer);
  478. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  479. "All USB3 ports have entered U0 already!");
  480. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  481. "Compliance Mode Recovery Timer Deleted.");
  482. }
  483. }
  484. }
  485. /*
  486. * Converts a raw xHCI port status into the format that external USB 2.0 or USB
  487. * 3.0 hubs use.
  488. *
  489. * Possible side effects:
  490. * - Mark a port as being done with device resume,
  491. * and ring the endpoint doorbells.
  492. * - Stop the Synopsys redriver Compliance Mode polling.
  493. */
  494. static u32 xhci_get_port_status(struct usb_hcd *hcd,
  495. struct xhci_bus_state *bus_state,
  496. __le32 __iomem **port_array,
  497. u16 wIndex, u32 raw_port_status)
  498. {
  499. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  500. u32 status = 0;
  501. int slot_id;
  502. /* wPortChange bits */
  503. if (raw_port_status & PORT_CSC)
  504. status |= USB_PORT_STAT_C_CONNECTION << 16;
  505. if (raw_port_status & PORT_PEC)
  506. status |= USB_PORT_STAT_C_ENABLE << 16;
  507. if ((raw_port_status & PORT_OCC))
  508. status |= USB_PORT_STAT_C_OVERCURRENT << 16;
  509. if ((raw_port_status & PORT_RC))
  510. status |= USB_PORT_STAT_C_RESET << 16;
  511. /* USB3.0 only */
  512. if (hcd->speed == HCD_USB3) {
  513. if ((raw_port_status & PORT_PLC))
  514. status |= USB_PORT_STAT_C_LINK_STATE << 16;
  515. if ((raw_port_status & PORT_WRC))
  516. status |= USB_PORT_STAT_C_BH_RESET << 16;
  517. }
  518. if (hcd->speed != HCD_USB3) {
  519. if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
  520. && (raw_port_status & PORT_POWER))
  521. status |= USB_PORT_STAT_SUSPEND;
  522. }
  523. if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
  524. !DEV_SUPERSPEED(raw_port_status)) {
  525. if ((raw_port_status & PORT_RESET) ||
  526. !(raw_port_status & PORT_PE))
  527. return 0xffffffff;
  528. if (time_after_eq(jiffies,
  529. bus_state->resume_done[wIndex])) {
  530. xhci_dbg(xhci, "Resume USB2 port %d\n",
  531. wIndex + 1);
  532. bus_state->resume_done[wIndex] = 0;
  533. clear_bit(wIndex, &bus_state->resuming_ports);
  534. xhci_set_link_state(xhci, port_array, wIndex,
  535. XDEV_U0);
  536. xhci_dbg(xhci, "set port %d resume\n",
  537. wIndex + 1);
  538. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  539. wIndex + 1);
  540. if (!slot_id) {
  541. xhci_dbg(xhci, "slot_id is zero\n");
  542. return 0xffffffff;
  543. }
  544. xhci_ring_device(xhci, slot_id);
  545. bus_state->port_c_suspend |= 1 << wIndex;
  546. bus_state->suspended_ports &= ~(1 << wIndex);
  547. } else {
  548. /*
  549. * The resume has been signaling for less than
  550. * 20ms. Report the port status as SUSPEND,
  551. * let the usbcore check port status again
  552. * and clear resume signaling later.
  553. */
  554. status |= USB_PORT_STAT_SUSPEND;
  555. }
  556. }
  557. if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0
  558. && (raw_port_status & PORT_POWER)
  559. && (bus_state->suspended_ports & (1 << wIndex))) {
  560. bus_state->suspended_ports &= ~(1 << wIndex);
  561. if (hcd->speed != HCD_USB3)
  562. bus_state->port_c_suspend |= 1 << wIndex;
  563. }
  564. if (raw_port_status & PORT_CONNECT) {
  565. status |= USB_PORT_STAT_CONNECTION;
  566. status |= xhci_port_speed(raw_port_status);
  567. }
  568. if (raw_port_status & PORT_PE)
  569. status |= USB_PORT_STAT_ENABLE;
  570. if (raw_port_status & PORT_OC)
  571. status |= USB_PORT_STAT_OVERCURRENT;
  572. if (raw_port_status & PORT_RESET)
  573. status |= USB_PORT_STAT_RESET;
  574. if (raw_port_status & PORT_POWER) {
  575. if (hcd->speed == HCD_USB3)
  576. status |= USB_SS_PORT_STAT_POWER;
  577. else
  578. status |= USB_PORT_STAT_POWER;
  579. }
  580. /* Update Port Link State */
  581. if (hcd->speed == HCD_USB3) {
  582. xhci_hub_report_usb3_link_state(&status, raw_port_status);
  583. /*
  584. * Verify if all USB3 Ports Have entered U0 already.
  585. * Delete Compliance Mode Timer if so.
  586. */
  587. xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
  588. } else {
  589. xhci_hub_report_usb2_link_state(&status, raw_port_status);
  590. }
  591. if (bus_state->port_c_suspend & (1 << wIndex))
  592. status |= 1 << USB_PORT_FEAT_C_SUSPEND;
  593. return status;
  594. }
  595. int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
  596. u16 wIndex, char *buf, u16 wLength)
  597. {
  598. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  599. int max_ports;
  600. unsigned long flags;
  601. u32 temp, status;
  602. int retval = 0;
  603. __le32 __iomem **port_array;
  604. int slot_id;
  605. struct xhci_bus_state *bus_state;
  606. u16 link_state = 0;
  607. u16 wake_mask = 0;
  608. u16 timeout = 0;
  609. max_ports = xhci_get_ports(hcd, &port_array);
  610. bus_state = &xhci->bus_state[hcd_index(hcd)];
  611. spin_lock_irqsave(&xhci->lock, flags);
  612. switch (typeReq) {
  613. case GetHubStatus:
  614. /* No power source, over-current reported per port */
  615. memset(buf, 0, 4);
  616. break;
  617. case GetHubDescriptor:
  618. /* Check to make sure userspace is asking for the USB 3.0 hub
  619. * descriptor for the USB 3.0 roothub. If not, we stall the
  620. * endpoint, like external hubs do.
  621. */
  622. if (hcd->speed == HCD_USB3 &&
  623. (wLength < USB_DT_SS_HUB_SIZE ||
  624. wValue != (USB_DT_SS_HUB << 8))) {
  625. xhci_dbg(xhci, "Wrong hub descriptor type for "
  626. "USB 3.0 roothub.\n");
  627. goto error;
  628. }
  629. xhci_hub_descriptor(hcd, xhci,
  630. (struct usb_hub_descriptor *) buf);
  631. break;
  632. case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
  633. if ((wValue & 0xff00) != (USB_DT_BOS << 8))
  634. goto error;
  635. if (hcd->speed != HCD_USB3)
  636. goto error;
  637. /* Set the U1 and U2 exit latencies. */
  638. memcpy(buf, &usb_bos_descriptor,
  639. USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE);
  640. temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
  641. buf[12] = HCS_U1_LATENCY(temp);
  642. put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
  643. /* Indicate whether the host has LTM support. */
  644. temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
  645. if (HCC_LTC(temp))
  646. buf[8] |= USB_LTM_SUPPORT;
  647. spin_unlock_irqrestore(&xhci->lock, flags);
  648. return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  649. case GetPortStatus:
  650. if (!wIndex || wIndex > max_ports)
  651. goto error;
  652. wIndex--;
  653. temp = xhci_readl(xhci, port_array[wIndex]);
  654. if (temp == 0xffffffff) {
  655. retval = -ENODEV;
  656. break;
  657. }
  658. status = xhci_get_port_status(hcd, bus_state, port_array,
  659. wIndex, temp);
  660. if (status == 0xffffffff)
  661. goto error;
  662. xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n",
  663. wIndex, temp);
  664. xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
  665. put_unaligned(cpu_to_le32(status), (__le32 *) buf);
  666. break;
  667. case SetPortFeature:
  668. if (wValue == USB_PORT_FEAT_LINK_STATE)
  669. link_state = (wIndex & 0xff00) >> 3;
  670. if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
  671. wake_mask = wIndex & 0xff00;
  672. /* The MSB of wIndex is the U1/U2 timeout */
  673. timeout = (wIndex & 0xff00) >> 8;
  674. wIndex &= 0xff;
  675. if (!wIndex || wIndex > max_ports)
  676. goto error;
  677. wIndex--;
  678. temp = xhci_readl(xhci, port_array[wIndex]);
  679. if (temp == 0xffffffff) {
  680. retval = -ENODEV;
  681. break;
  682. }
  683. temp = xhci_port_state_to_neutral(temp);
  684. /* FIXME: What new port features do we need to support? */
  685. switch (wValue) {
  686. case USB_PORT_FEAT_SUSPEND:
  687. temp = xhci_readl(xhci, port_array[wIndex]);
  688. if ((temp & PORT_PLS_MASK) != XDEV_U0) {
  689. /* Resume the port to U0 first */
  690. xhci_set_link_state(xhci, port_array, wIndex,
  691. XDEV_U0);
  692. spin_unlock_irqrestore(&xhci->lock, flags);
  693. msleep(10);
  694. spin_lock_irqsave(&xhci->lock, flags);
  695. }
  696. /* In spec software should not attempt to suspend
  697. * a port unless the port reports that it is in the
  698. * enabled (PED = ‘1’,PLS < ‘3’) state.
  699. */
  700. temp = xhci_readl(xhci, port_array[wIndex]);
  701. if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
  702. || (temp & PORT_PLS_MASK) >= XDEV_U3) {
  703. xhci_warn(xhci, "USB core suspending device "
  704. "not in U0/U1/U2.\n");
  705. goto error;
  706. }
  707. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  708. wIndex + 1);
  709. if (!slot_id) {
  710. xhci_warn(xhci, "slot_id is zero\n");
  711. goto error;
  712. }
  713. /* unlock to execute stop endpoint commands */
  714. spin_unlock_irqrestore(&xhci->lock, flags);
  715. xhci_stop_device(xhci, slot_id, 1);
  716. spin_lock_irqsave(&xhci->lock, flags);
  717. xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
  718. spin_unlock_irqrestore(&xhci->lock, flags);
  719. msleep(10); /* wait device to enter */
  720. spin_lock_irqsave(&xhci->lock, flags);
  721. temp = xhci_readl(xhci, port_array[wIndex]);
  722. bus_state->suspended_ports |= 1 << wIndex;
  723. break;
  724. case USB_PORT_FEAT_LINK_STATE:
  725. temp = xhci_readl(xhci, port_array[wIndex]);
  726. /* Disable port */
  727. if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
  728. xhci_dbg(xhci, "Disable port %d\n", wIndex);
  729. temp = xhci_port_state_to_neutral(temp);
  730. /*
  731. * Clear all change bits, so that we get a new
  732. * connection event.
  733. */
  734. temp |= PORT_CSC | PORT_PEC | PORT_WRC |
  735. PORT_OCC | PORT_RC | PORT_PLC |
  736. PORT_CEC;
  737. xhci_writel(xhci, temp | PORT_PE,
  738. port_array[wIndex]);
  739. temp = xhci_readl(xhci, port_array[wIndex]);
  740. break;
  741. }
  742. /* Put link in RxDetect (enable port) */
  743. if (link_state == USB_SS_PORT_LS_RX_DETECT) {
  744. xhci_dbg(xhci, "Enable port %d\n", wIndex);
  745. xhci_set_link_state(xhci, port_array, wIndex,
  746. link_state);
  747. temp = xhci_readl(xhci, port_array[wIndex]);
  748. break;
  749. }
  750. /* Software should not attempt to set
  751. * port link state above '3' (U3) and the port
  752. * must be enabled.
  753. */
  754. if ((temp & PORT_PE) == 0 ||
  755. (link_state > USB_SS_PORT_LS_U3)) {
  756. xhci_warn(xhci, "Cannot set link state.\n");
  757. goto error;
  758. }
  759. if (link_state == USB_SS_PORT_LS_U3) {
  760. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  761. wIndex + 1);
  762. if (slot_id) {
  763. /* unlock to execute stop endpoint
  764. * commands */
  765. spin_unlock_irqrestore(&xhci->lock,
  766. flags);
  767. xhci_stop_device(xhci, slot_id, 1);
  768. spin_lock_irqsave(&xhci->lock, flags);
  769. }
  770. }
  771. xhci_set_link_state(xhci, port_array, wIndex,
  772. link_state);
  773. spin_unlock_irqrestore(&xhci->lock, flags);
  774. msleep(20); /* wait device to enter */
  775. spin_lock_irqsave(&xhci->lock, flags);
  776. temp = xhci_readl(xhci, port_array[wIndex]);
  777. if (link_state == USB_SS_PORT_LS_U3)
  778. bus_state->suspended_ports |= 1 << wIndex;
  779. break;
  780. case USB_PORT_FEAT_POWER:
  781. /*
  782. * Turn on ports, even if there isn't per-port switching.
  783. * HC will report connect events even before this is set.
  784. * However, khubd will ignore the roothub events until
  785. * the roothub is registered.
  786. */
  787. xhci_writel(xhci, temp | PORT_POWER,
  788. port_array[wIndex]);
  789. temp = xhci_readl(xhci, port_array[wIndex]);
  790. xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
  791. spin_unlock_irqrestore(&xhci->lock, flags);
  792. temp = usb_acpi_power_manageable(hcd->self.root_hub,
  793. wIndex);
  794. if (temp)
  795. usb_acpi_set_power_state(hcd->self.root_hub,
  796. wIndex, true);
  797. spin_lock_irqsave(&xhci->lock, flags);
  798. break;
  799. case USB_PORT_FEAT_RESET:
  800. temp = (temp | PORT_RESET);
  801. xhci_writel(xhci, temp, port_array[wIndex]);
  802. temp = xhci_readl(xhci, port_array[wIndex]);
  803. xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
  804. break;
  805. case USB_PORT_FEAT_REMOTE_WAKE_MASK:
  806. xhci_set_remote_wake_mask(xhci, port_array,
  807. wIndex, wake_mask);
  808. temp = xhci_readl(xhci, port_array[wIndex]);
  809. xhci_dbg(xhci, "set port remote wake mask, "
  810. "actual port %d status = 0x%x\n",
  811. wIndex, temp);
  812. break;
  813. case USB_PORT_FEAT_BH_PORT_RESET:
  814. temp |= PORT_WR;
  815. xhci_writel(xhci, temp, port_array[wIndex]);
  816. temp = xhci_readl(xhci, port_array[wIndex]);
  817. break;
  818. case USB_PORT_FEAT_U1_TIMEOUT:
  819. if (hcd->speed != HCD_USB3)
  820. goto error;
  821. temp = xhci_readl(xhci, port_array[wIndex] + PORTPMSC);
  822. temp &= ~PORT_U1_TIMEOUT_MASK;
  823. temp |= PORT_U1_TIMEOUT(timeout);
  824. xhci_writel(xhci, temp, port_array[wIndex] + PORTPMSC);
  825. break;
  826. case USB_PORT_FEAT_U2_TIMEOUT:
  827. if (hcd->speed != HCD_USB3)
  828. goto error;
  829. temp = xhci_readl(xhci, port_array[wIndex] + PORTPMSC);
  830. temp &= ~PORT_U2_TIMEOUT_MASK;
  831. temp |= PORT_U2_TIMEOUT(timeout);
  832. xhci_writel(xhci, temp, port_array[wIndex] + PORTPMSC);
  833. break;
  834. default:
  835. goto error;
  836. }
  837. /* unblock any posted writes */
  838. temp = xhci_readl(xhci, port_array[wIndex]);
  839. break;
  840. case ClearPortFeature:
  841. if (!wIndex || wIndex > max_ports)
  842. goto error;
  843. wIndex--;
  844. temp = xhci_readl(xhci, port_array[wIndex]);
  845. if (temp == 0xffffffff) {
  846. retval = -ENODEV;
  847. break;
  848. }
  849. /* FIXME: What new port features do we need to support? */
  850. temp = xhci_port_state_to_neutral(temp);
  851. switch (wValue) {
  852. case USB_PORT_FEAT_SUSPEND:
  853. temp = xhci_readl(xhci, port_array[wIndex]);
  854. xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
  855. xhci_dbg(xhci, "PORTSC %04x\n", temp);
  856. if (temp & PORT_RESET)
  857. goto error;
  858. if ((temp & PORT_PLS_MASK) == XDEV_U3) {
  859. if ((temp & PORT_PE) == 0)
  860. goto error;
  861. xhci_set_link_state(xhci, port_array, wIndex,
  862. XDEV_RESUME);
  863. spin_unlock_irqrestore(&xhci->lock, flags);
  864. msleep(20);
  865. spin_lock_irqsave(&xhci->lock, flags);
  866. xhci_set_link_state(xhci, port_array, wIndex,
  867. XDEV_U0);
  868. }
  869. bus_state->port_c_suspend |= 1 << wIndex;
  870. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  871. wIndex + 1);
  872. if (!slot_id) {
  873. xhci_dbg(xhci, "slot_id is zero\n");
  874. goto error;
  875. }
  876. xhci_ring_device(xhci, slot_id);
  877. break;
  878. case USB_PORT_FEAT_C_SUSPEND:
  879. bus_state->port_c_suspend &= ~(1 << wIndex);
  880. case USB_PORT_FEAT_C_RESET:
  881. case USB_PORT_FEAT_C_BH_PORT_RESET:
  882. case USB_PORT_FEAT_C_CONNECTION:
  883. case USB_PORT_FEAT_C_OVER_CURRENT:
  884. case USB_PORT_FEAT_C_ENABLE:
  885. case USB_PORT_FEAT_C_PORT_LINK_STATE:
  886. xhci_clear_port_change_bit(xhci, wValue, wIndex,
  887. port_array[wIndex], temp);
  888. break;
  889. case USB_PORT_FEAT_ENABLE:
  890. xhci_disable_port(hcd, xhci, wIndex,
  891. port_array[wIndex], temp);
  892. break;
  893. case USB_PORT_FEAT_POWER:
  894. xhci_writel(xhci, temp & ~PORT_POWER,
  895. port_array[wIndex]);
  896. spin_unlock_irqrestore(&xhci->lock, flags);
  897. temp = usb_acpi_power_manageable(hcd->self.root_hub,
  898. wIndex);
  899. if (temp)
  900. usb_acpi_set_power_state(hcd->self.root_hub,
  901. wIndex, false);
  902. spin_lock_irqsave(&xhci->lock, flags);
  903. break;
  904. default:
  905. goto error;
  906. }
  907. break;
  908. default:
  909. error:
  910. /* "stall" on error */
  911. retval = -EPIPE;
  912. }
  913. spin_unlock_irqrestore(&xhci->lock, flags);
  914. return retval;
  915. }
  916. /*
  917. * Returns 0 if the status hasn't changed, or the number of bytes in buf.
  918. * Ports are 0-indexed from the HCD point of view,
  919. * and 1-indexed from the USB core pointer of view.
  920. *
  921. * Note that the status change bits will be cleared as soon as a port status
  922. * change event is generated, so we use the saved status from that event.
  923. */
  924. int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
  925. {
  926. unsigned long flags;
  927. u32 temp, status;
  928. u32 mask;
  929. int i, retval;
  930. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  931. int max_ports;
  932. __le32 __iomem **port_array;
  933. struct xhci_bus_state *bus_state;
  934. bool reset_change = false;
  935. max_ports = xhci_get_ports(hcd, &port_array);
  936. bus_state = &xhci->bus_state[hcd_index(hcd)];
  937. /* Initial status is no changes */
  938. retval = (max_ports + 8) / 8;
  939. memset(buf, 0, retval);
  940. /*
  941. * Inform the usbcore about resume-in-progress by returning
  942. * a non-zero value even if there are no status changes.
  943. */
  944. status = bus_state->resuming_ports;
  945. mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC;
  946. spin_lock_irqsave(&xhci->lock, flags);
  947. /* For each port, did anything change? If so, set that bit in buf. */
  948. for (i = 0; i < max_ports; i++) {
  949. temp = xhci_readl(xhci, port_array[i]);
  950. if (temp == 0xffffffff) {
  951. retval = -ENODEV;
  952. break;
  953. }
  954. if ((temp & mask) != 0 ||
  955. (bus_state->port_c_suspend & 1 << i) ||
  956. (bus_state->resume_done[i] && time_after_eq(
  957. jiffies, bus_state->resume_done[i]))) {
  958. buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
  959. status = 1;
  960. }
  961. if ((temp & PORT_RC))
  962. reset_change = true;
  963. }
  964. if (!status && !reset_change) {
  965. xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
  966. clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
  967. }
  968. spin_unlock_irqrestore(&xhci->lock, flags);
  969. return status ? retval : 0;
  970. }
  971. #ifdef CONFIG_PM
  972. int xhci_bus_suspend(struct usb_hcd *hcd)
  973. {
  974. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  975. int max_ports, port_index;
  976. __le32 __iomem **port_array;
  977. struct xhci_bus_state *bus_state;
  978. unsigned long flags;
  979. max_ports = xhci_get_ports(hcd, &port_array);
  980. bus_state = &xhci->bus_state[hcd_index(hcd)];
  981. spin_lock_irqsave(&xhci->lock, flags);
  982. if (hcd->self.root_hub->do_remote_wakeup) {
  983. if (bus_state->resuming_ports) {
  984. spin_unlock_irqrestore(&xhci->lock, flags);
  985. xhci_dbg(xhci, "suspend failed because "
  986. "a port is resuming\n");
  987. return -EBUSY;
  988. }
  989. }
  990. port_index = max_ports;
  991. bus_state->bus_suspended = 0;
  992. while (port_index--) {
  993. /* suspend the port if the port is not suspended */
  994. u32 t1, t2;
  995. int slot_id;
  996. t1 = xhci_readl(xhci, port_array[port_index]);
  997. t2 = xhci_port_state_to_neutral(t1);
  998. if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
  999. xhci_dbg(xhci, "port %d not suspended\n", port_index);
  1000. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  1001. port_index + 1);
  1002. if (slot_id) {
  1003. spin_unlock_irqrestore(&xhci->lock, flags);
  1004. xhci_stop_device(xhci, slot_id, 1);
  1005. spin_lock_irqsave(&xhci->lock, flags);
  1006. }
  1007. t2 &= ~PORT_PLS_MASK;
  1008. t2 |= PORT_LINK_STROBE | XDEV_U3;
  1009. set_bit(port_index, &bus_state->bus_suspended);
  1010. }
  1011. /* USB core sets remote wake mask for USB 3.0 hubs,
  1012. * including the USB 3.0 roothub, but only if CONFIG_PM_RUNTIME
  1013. * is enabled, so also enable remote wake here.
  1014. */
  1015. if (hcd->self.root_hub->do_remote_wakeup) {
  1016. if (t1 & PORT_CONNECT) {
  1017. t2 |= PORT_WKOC_E | PORT_WKDISC_E;
  1018. t2 &= ~PORT_WKCONN_E;
  1019. } else {
  1020. t2 |= PORT_WKOC_E | PORT_WKCONN_E;
  1021. t2 &= ~PORT_WKDISC_E;
  1022. }
  1023. } else
  1024. t2 &= ~PORT_WAKE_BITS;
  1025. t1 = xhci_port_state_to_neutral(t1);
  1026. if (t1 != t2)
  1027. xhci_writel(xhci, t2, port_array[port_index]);
  1028. if (hcd->speed != HCD_USB3) {
  1029. /* enable remote wake up for USB 2.0 */
  1030. __le32 __iomem *addr;
  1031. u32 tmp;
  1032. /* Get the port power control register address. */
  1033. addr = port_array[port_index] + PORTPMSC;
  1034. tmp = xhci_readl(xhci, addr);
  1035. tmp |= PORT_RWE;
  1036. xhci_writel(xhci, tmp, addr);
  1037. }
  1038. }
  1039. hcd->state = HC_STATE_SUSPENDED;
  1040. bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
  1041. spin_unlock_irqrestore(&xhci->lock, flags);
  1042. return 0;
  1043. }
  1044. int xhci_bus_resume(struct usb_hcd *hcd)
  1045. {
  1046. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  1047. int max_ports, port_index;
  1048. __le32 __iomem **port_array;
  1049. struct xhci_bus_state *bus_state;
  1050. u32 temp;
  1051. unsigned long flags;
  1052. max_ports = xhci_get_ports(hcd, &port_array);
  1053. bus_state = &xhci->bus_state[hcd_index(hcd)];
  1054. if (time_before(jiffies, bus_state->next_statechange))
  1055. msleep(5);
  1056. spin_lock_irqsave(&xhci->lock, flags);
  1057. if (!HCD_HW_ACCESSIBLE(hcd)) {
  1058. spin_unlock_irqrestore(&xhci->lock, flags);
  1059. return -ESHUTDOWN;
  1060. }
  1061. /* delay the irqs */
  1062. temp = xhci_readl(xhci, &xhci->op_regs->command);
  1063. temp &= ~CMD_EIE;
  1064. xhci_writel(xhci, temp, &xhci->op_regs->command);
  1065. port_index = max_ports;
  1066. while (port_index--) {
  1067. /* Check whether need resume ports. If needed
  1068. resume port and disable remote wakeup */
  1069. u32 temp;
  1070. int slot_id;
  1071. temp = xhci_readl(xhci, port_array[port_index]);
  1072. if (DEV_SUPERSPEED(temp))
  1073. temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
  1074. else
  1075. temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
  1076. if (test_bit(port_index, &bus_state->bus_suspended) &&
  1077. (temp & PORT_PLS_MASK)) {
  1078. if (DEV_SUPERSPEED(temp)) {
  1079. xhci_set_link_state(xhci, port_array,
  1080. port_index, XDEV_U0);
  1081. } else {
  1082. xhci_set_link_state(xhci, port_array,
  1083. port_index, XDEV_RESUME);
  1084. spin_unlock_irqrestore(&xhci->lock, flags);
  1085. msleep(20);
  1086. spin_lock_irqsave(&xhci->lock, flags);
  1087. xhci_set_link_state(xhci, port_array,
  1088. port_index, XDEV_U0);
  1089. }
  1090. /* wait for the port to enter U0 and report port link
  1091. * state change.
  1092. */
  1093. spin_unlock_irqrestore(&xhci->lock, flags);
  1094. msleep(20);
  1095. spin_lock_irqsave(&xhci->lock, flags);
  1096. /* Clear PLC */
  1097. xhci_test_and_clear_bit(xhci, port_array, port_index,
  1098. PORT_PLC);
  1099. slot_id = xhci_find_slot_id_by_port(hcd,
  1100. xhci, port_index + 1);
  1101. if (slot_id)
  1102. xhci_ring_device(xhci, slot_id);
  1103. } else
  1104. xhci_writel(xhci, temp, port_array[port_index]);
  1105. if (hcd->speed != HCD_USB3) {
  1106. /* disable remote wake up for USB 2.0 */
  1107. __le32 __iomem *addr;
  1108. u32 tmp;
  1109. /* Add one to the port status register address to get
  1110. * the port power control register address.
  1111. */
  1112. addr = port_array[port_index] + PORTPMSC;
  1113. tmp = xhci_readl(xhci, addr);
  1114. tmp &= ~PORT_RWE;
  1115. xhci_writel(xhci, tmp, addr);
  1116. }
  1117. }
  1118. (void) xhci_readl(xhci, &xhci->op_regs->command);
  1119. bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
  1120. /* re-enable irqs */
  1121. temp = xhci_readl(xhci, &xhci->op_regs->command);
  1122. temp |= CMD_EIE;
  1123. xhci_writel(xhci, temp, &xhci->op_regs->command);
  1124. temp = xhci_readl(xhci, &xhci->op_regs->command);
  1125. spin_unlock_irqrestore(&xhci->lock, flags);
  1126. return 0;
  1127. }
  1128. #endif /* CONFIG_PM */