ehci-tegra.c 14 KB

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  1. /*
  2. * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
  3. *
  4. * Copyright (C) 2010 Google, Inc.
  5. * Copyright (C) 2009 - 2013 NVIDIA Corporation
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. */
  18. #include <linux/clk.h>
  19. #include <linux/clk/tegra.h>
  20. #include <linux/dma-mapping.h>
  21. #include <linux/err.h>
  22. #include <linux/gpio.h>
  23. #include <linux/io.h>
  24. #include <linux/irq.h>
  25. #include <linux/module.h>
  26. #include <linux/of.h>
  27. #include <linux/of_device.h>
  28. #include <linux/of_gpio.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/pm_runtime.h>
  31. #include <linux/slab.h>
  32. #include <linux/usb/ehci_def.h>
  33. #include <linux/usb/tegra_usb_phy.h>
  34. #include <linux/usb.h>
  35. #include <linux/usb/hcd.h>
  36. #include <linux/usb/otg.h>
  37. #include "ehci.h"
  38. #define TEGRA_USB_BASE 0xC5000000
  39. #define TEGRA_USB2_BASE 0xC5004000
  40. #define TEGRA_USB3_BASE 0xC5008000
  41. #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
  42. #define TEGRA_USB_DMA_ALIGN 32
  43. #define DRIVER_DESC "Tegra EHCI driver"
  44. #define DRV_NAME "tegra-ehci"
  45. static struct hc_driver __read_mostly tegra_ehci_hc_driver;
  46. struct tegra_ehci_soc_config {
  47. bool has_hostpc;
  48. };
  49. static int (*orig_hub_control)(struct usb_hcd *hcd,
  50. u16 typeReq, u16 wValue, u16 wIndex,
  51. char *buf, u16 wLength);
  52. struct tegra_ehci_hcd {
  53. struct tegra_usb_phy *phy;
  54. struct clk *clk;
  55. int port_resuming;
  56. bool needs_double_reset;
  57. enum tegra_usb_phy_port_speed port_speed;
  58. };
  59. static int tegra_ehci_internal_port_reset(
  60. struct ehci_hcd *ehci,
  61. u32 __iomem *portsc_reg
  62. )
  63. {
  64. u32 temp;
  65. unsigned long flags;
  66. int retval = 0;
  67. int i, tries;
  68. u32 saved_usbintr;
  69. spin_lock_irqsave(&ehci->lock, flags);
  70. saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
  71. /* disable USB interrupt */
  72. ehci_writel(ehci, 0, &ehci->regs->intr_enable);
  73. spin_unlock_irqrestore(&ehci->lock, flags);
  74. /*
  75. * Here we have to do Port Reset at most twice for
  76. * Port Enable bit to be set.
  77. */
  78. for (i = 0; i < 2; i++) {
  79. temp = ehci_readl(ehci, portsc_reg);
  80. temp |= PORT_RESET;
  81. ehci_writel(ehci, temp, portsc_reg);
  82. mdelay(10);
  83. temp &= ~PORT_RESET;
  84. ehci_writel(ehci, temp, portsc_reg);
  85. mdelay(1);
  86. tries = 100;
  87. do {
  88. mdelay(1);
  89. /*
  90. * Up to this point, Port Enable bit is
  91. * expected to be set after 2 ms waiting.
  92. * USB1 usually takes extra 45 ms, for safety,
  93. * we take 100 ms as timeout.
  94. */
  95. temp = ehci_readl(ehci, portsc_reg);
  96. } while (!(temp & PORT_PE) && tries--);
  97. if (temp & PORT_PE)
  98. break;
  99. }
  100. if (i == 2)
  101. retval = -ETIMEDOUT;
  102. /*
  103. * Clear Connect Status Change bit if it's set.
  104. * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
  105. */
  106. if (temp & PORT_CSC)
  107. ehci_writel(ehci, PORT_CSC, portsc_reg);
  108. /*
  109. * Write to clear any interrupt status bits that might be set
  110. * during port reset.
  111. */
  112. temp = ehci_readl(ehci, &ehci->regs->status);
  113. ehci_writel(ehci, temp, &ehci->regs->status);
  114. /* restore original interrupt enable bits */
  115. ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
  116. return retval;
  117. }
  118. static int tegra_ehci_hub_control(
  119. struct usb_hcd *hcd,
  120. u16 typeReq,
  121. u16 wValue,
  122. u16 wIndex,
  123. char *buf,
  124. u16 wLength
  125. )
  126. {
  127. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  128. struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd *)ehci->priv;
  129. u32 __iomem *status_reg;
  130. u32 temp;
  131. unsigned long flags;
  132. int retval = 0;
  133. status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
  134. spin_lock_irqsave(&ehci->lock, flags);
  135. if (typeReq == GetPortStatus) {
  136. temp = ehci_readl(ehci, status_reg);
  137. if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
  138. /* Resume completed, re-enable disconnect detection */
  139. tegra->port_resuming = 0;
  140. tegra_usb_phy_postresume(hcd->phy);
  141. }
  142. }
  143. else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
  144. temp = ehci_readl(ehci, status_reg);
  145. if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
  146. retval = -EPIPE;
  147. goto done;
  148. }
  149. temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
  150. temp |= PORT_WKDISC_E | PORT_WKOC_E;
  151. ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
  152. /*
  153. * If a transaction is in progress, there may be a delay in
  154. * suspending the port. Poll until the port is suspended.
  155. */
  156. if (ehci_handshake(ehci, status_reg, PORT_SUSPEND,
  157. PORT_SUSPEND, 5000))
  158. pr_err("%s: timeout waiting for SUSPEND\n", __func__);
  159. set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
  160. goto done;
  161. }
  162. /* For USB1 port we need to issue Port Reset twice internally */
  163. if (tegra->needs_double_reset &&
  164. (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
  165. spin_unlock_irqrestore(&ehci->lock, flags);
  166. return tegra_ehci_internal_port_reset(ehci, status_reg);
  167. }
  168. /*
  169. * Tegra host controller will time the resume operation to clear the bit
  170. * when the port control state switches to HS or FS Idle. This behavior
  171. * is different from EHCI where the host controller driver is required
  172. * to set this bit to a zero after the resume duration is timed in the
  173. * driver.
  174. */
  175. else if (typeReq == ClearPortFeature &&
  176. wValue == USB_PORT_FEAT_SUSPEND) {
  177. temp = ehci_readl(ehci, status_reg);
  178. if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
  179. retval = -EPIPE;
  180. goto done;
  181. }
  182. if (!(temp & PORT_SUSPEND))
  183. goto done;
  184. /* Disable disconnect detection during port resume */
  185. tegra_usb_phy_preresume(hcd->phy);
  186. ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
  187. temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
  188. /* start resume signalling */
  189. ehci_writel(ehci, temp | PORT_RESUME, status_reg);
  190. set_bit(wIndex-1, &ehci->resuming_ports);
  191. spin_unlock_irqrestore(&ehci->lock, flags);
  192. msleep(20);
  193. spin_lock_irqsave(&ehci->lock, flags);
  194. /* Poll until the controller clears RESUME and SUSPEND */
  195. if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
  196. pr_err("%s: timeout waiting for RESUME\n", __func__);
  197. if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
  198. pr_err("%s: timeout waiting for SUSPEND\n", __func__);
  199. ehci->reset_done[wIndex-1] = 0;
  200. clear_bit(wIndex-1, &ehci->resuming_ports);
  201. tegra->port_resuming = 1;
  202. goto done;
  203. }
  204. spin_unlock_irqrestore(&ehci->lock, flags);
  205. /* Handle the hub control events here */
  206. return orig_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
  207. done:
  208. spin_unlock_irqrestore(&ehci->lock, flags);
  209. return retval;
  210. }
  211. struct dma_aligned_buffer {
  212. void *kmalloc_ptr;
  213. void *old_xfer_buffer;
  214. u8 data[0];
  215. };
  216. static void free_dma_aligned_buffer(struct urb *urb)
  217. {
  218. struct dma_aligned_buffer *temp;
  219. if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
  220. return;
  221. temp = container_of(urb->transfer_buffer,
  222. struct dma_aligned_buffer, data);
  223. if (usb_urb_dir_in(urb))
  224. memcpy(temp->old_xfer_buffer, temp->data,
  225. urb->transfer_buffer_length);
  226. urb->transfer_buffer = temp->old_xfer_buffer;
  227. kfree(temp->kmalloc_ptr);
  228. urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
  229. }
  230. static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
  231. {
  232. struct dma_aligned_buffer *temp, *kmalloc_ptr;
  233. size_t kmalloc_size;
  234. if (urb->num_sgs || urb->sg ||
  235. urb->transfer_buffer_length == 0 ||
  236. !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
  237. return 0;
  238. /* Allocate a buffer with enough padding for alignment */
  239. kmalloc_size = urb->transfer_buffer_length +
  240. sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
  241. kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
  242. if (!kmalloc_ptr)
  243. return -ENOMEM;
  244. /* Position our struct dma_aligned_buffer such that data is aligned */
  245. temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
  246. temp->kmalloc_ptr = kmalloc_ptr;
  247. temp->old_xfer_buffer = urb->transfer_buffer;
  248. if (usb_urb_dir_out(urb))
  249. memcpy(temp->data, urb->transfer_buffer,
  250. urb->transfer_buffer_length);
  251. urb->transfer_buffer = temp->data;
  252. urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
  253. return 0;
  254. }
  255. static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
  256. gfp_t mem_flags)
  257. {
  258. int ret;
  259. ret = alloc_dma_aligned_buffer(urb, mem_flags);
  260. if (ret)
  261. return ret;
  262. ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
  263. if (ret)
  264. free_dma_aligned_buffer(urb);
  265. return ret;
  266. }
  267. static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
  268. {
  269. usb_hcd_unmap_urb_for_dma(hcd, urb);
  270. free_dma_aligned_buffer(urb);
  271. }
  272. static const struct tegra_ehci_soc_config tegra30_soc_config = {
  273. .has_hostpc = true,
  274. };
  275. static const struct tegra_ehci_soc_config tegra20_soc_config = {
  276. .has_hostpc = false,
  277. };
  278. static struct of_device_id tegra_ehci_of_match[] = {
  279. { .compatible = "nvidia,tegra30-ehci", .data = &tegra30_soc_config },
  280. { .compatible = "nvidia,tegra20-ehci", .data = &tegra20_soc_config },
  281. { },
  282. };
  283. static int tegra_ehci_probe(struct platform_device *pdev)
  284. {
  285. const struct of_device_id *match;
  286. const struct tegra_ehci_soc_config *soc_config;
  287. struct resource *res;
  288. struct usb_hcd *hcd;
  289. struct ehci_hcd *ehci;
  290. struct tegra_ehci_hcd *tegra;
  291. int err = 0;
  292. int irq;
  293. struct usb_phy *u_phy;
  294. match = of_match_device(tegra_ehci_of_match, &pdev->dev);
  295. if (!match) {
  296. dev_err(&pdev->dev, "Error: No device match found\n");
  297. return -ENODEV;
  298. }
  299. soc_config = match->data;
  300. /* Right now device-tree probed devices don't get dma_mask set.
  301. * Since shared usb code relies on it, set it here for now.
  302. * Once we have dma capability bindings this can go away.
  303. */
  304. if (!pdev->dev.dma_mask)
  305. pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
  306. if (!pdev->dev.coherent_dma_mask)
  307. pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
  308. hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
  309. dev_name(&pdev->dev));
  310. if (!hcd) {
  311. dev_err(&pdev->dev, "Unable to create HCD\n");
  312. return -ENOMEM;
  313. }
  314. platform_set_drvdata(pdev, hcd);
  315. ehci = hcd_to_ehci(hcd);
  316. tegra = (struct tegra_ehci_hcd *)ehci->priv;
  317. hcd->has_tt = 1;
  318. tegra->clk = devm_clk_get(&pdev->dev, NULL);
  319. if (IS_ERR(tegra->clk)) {
  320. dev_err(&pdev->dev, "Can't get ehci clock\n");
  321. err = PTR_ERR(tegra->clk);
  322. goto cleanup_hcd_create;
  323. }
  324. err = clk_prepare_enable(tegra->clk);
  325. if (err)
  326. goto cleanup_clk_get;
  327. tegra_periph_reset_assert(tegra->clk);
  328. udelay(1);
  329. tegra_periph_reset_deassert(tegra->clk);
  330. u_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
  331. if (IS_ERR(u_phy)) {
  332. err = PTR_ERR(u_phy);
  333. goto cleanup_clk_en;
  334. }
  335. hcd->phy = u_phy;
  336. tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node,
  337. "nvidia,needs-double-reset");
  338. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  339. if (!res) {
  340. dev_err(&pdev->dev, "Failed to get I/O memory\n");
  341. err = -ENXIO;
  342. goto cleanup_clk_en;
  343. }
  344. hcd->rsrc_start = res->start;
  345. hcd->rsrc_len = resource_size(res);
  346. hcd->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
  347. if (!hcd->regs) {
  348. dev_err(&pdev->dev, "Failed to remap I/O memory\n");
  349. err = -ENOMEM;
  350. goto cleanup_clk_en;
  351. }
  352. ehci->caps = hcd->regs + 0x100;
  353. ehci->has_hostpc = soc_config->has_hostpc;
  354. err = usb_phy_init(hcd->phy);
  355. if (err) {
  356. dev_err(&pdev->dev, "Failed to initialize phy\n");
  357. goto cleanup_clk_en;
  358. }
  359. u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
  360. GFP_KERNEL);
  361. if (!u_phy->otg) {
  362. dev_err(&pdev->dev, "Failed to alloc memory for otg\n");
  363. err = -ENOMEM;
  364. goto cleanup_phy;
  365. }
  366. u_phy->otg->host = hcd_to_bus(hcd);
  367. err = usb_phy_set_suspend(hcd->phy, 0);
  368. if (err) {
  369. dev_err(&pdev->dev, "Failed to power on the phy\n");
  370. goto cleanup_phy;
  371. }
  372. irq = platform_get_irq(pdev, 0);
  373. if (!irq) {
  374. dev_err(&pdev->dev, "Failed to get IRQ\n");
  375. err = -ENODEV;
  376. goto cleanup_phy;
  377. }
  378. otg_set_host(u_phy->otg, &hcd->self);
  379. err = usb_add_hcd(hcd, irq, IRQF_SHARED);
  380. if (err) {
  381. dev_err(&pdev->dev, "Failed to add USB HCD\n");
  382. goto cleanup_otg_set_host;
  383. }
  384. return err;
  385. cleanup_otg_set_host:
  386. otg_set_host(u_phy->otg, NULL);
  387. cleanup_phy:
  388. usb_phy_shutdown(hcd->phy);
  389. cleanup_clk_en:
  390. clk_disable_unprepare(tegra->clk);
  391. cleanup_clk_get:
  392. clk_put(tegra->clk);
  393. cleanup_hcd_create:
  394. usb_put_hcd(hcd);
  395. return err;
  396. }
  397. static int tegra_ehci_remove(struct platform_device *pdev)
  398. {
  399. struct usb_hcd *hcd = platform_get_drvdata(pdev);
  400. struct tegra_ehci_hcd *tegra =
  401. (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
  402. otg_set_host(hcd->phy->otg, NULL);
  403. usb_phy_shutdown(hcd->phy);
  404. usb_remove_hcd(hcd);
  405. usb_put_hcd(hcd);
  406. clk_disable_unprepare(tegra->clk);
  407. return 0;
  408. }
  409. static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
  410. {
  411. struct usb_hcd *hcd = platform_get_drvdata(pdev);
  412. if (hcd->driver->shutdown)
  413. hcd->driver->shutdown(hcd);
  414. }
  415. static struct platform_driver tegra_ehci_driver = {
  416. .probe = tegra_ehci_probe,
  417. .remove = tegra_ehci_remove,
  418. .shutdown = tegra_ehci_hcd_shutdown,
  419. .driver = {
  420. .name = DRV_NAME,
  421. .of_match_table = tegra_ehci_of_match,
  422. }
  423. };
  424. static const struct ehci_driver_overrides tegra_overrides __initconst = {
  425. .extra_priv_size = sizeof(struct tegra_ehci_hcd),
  426. };
  427. static int __init ehci_tegra_init(void)
  428. {
  429. if (usb_disabled())
  430. return -ENODEV;
  431. pr_info(DRV_NAME ": " DRIVER_DESC "\n");
  432. ehci_init_driver(&tegra_ehci_hc_driver, &tegra_overrides);
  433. /*
  434. * The Tegra HW has some unusual quirks, which require Tegra-specific
  435. * workarounds. We override certain hc_driver functions here to
  436. * achieve that. We explicitly do not enhance ehci_driver_overrides to
  437. * allow this more easily, since this is an unusual case, and we don't
  438. * want to encourage others to override these functions by making it
  439. * too easy.
  440. */
  441. orig_hub_control = tegra_ehci_hc_driver.hub_control;
  442. tegra_ehci_hc_driver.map_urb_for_dma = tegra_ehci_map_urb_for_dma;
  443. tegra_ehci_hc_driver.unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma;
  444. tegra_ehci_hc_driver.hub_control = tegra_ehci_hub_control;
  445. return platform_driver_register(&tegra_ehci_driver);
  446. }
  447. module_init(ehci_tegra_init);
  448. static void __exit ehci_tegra_cleanup(void)
  449. {
  450. platform_driver_unregister(&tegra_ehci_driver);
  451. }
  452. module_exit(ehci_tegra_cleanup);
  453. MODULE_DESCRIPTION(DRIVER_DESC);
  454. MODULE_LICENSE("GPL");
  455. MODULE_ALIAS("platform:" DRV_NAME);
  456. MODULE_DEVICE_TABLE(of, tegra_ehci_of_match);