8250_dma.c 5.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232
  1. /*
  2. * 8250_dma.c - DMA Engine API support for 8250.c
  3. *
  4. * Copyright (C) 2013 Intel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. */
  11. #include <linux/tty.h>
  12. #include <linux/tty_flip.h>
  13. #include <linux/serial_reg.h>
  14. #include <linux/dma-mapping.h>
  15. #include "8250.h"
  16. static void __dma_tx_complete(void *param)
  17. {
  18. struct uart_8250_port *p = param;
  19. struct uart_8250_dma *dma = p->dma;
  20. struct circ_buf *xmit = &p->port.state->xmit;
  21. dma->tx_running = 0;
  22. dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
  23. UART_XMIT_SIZE, DMA_TO_DEVICE);
  24. xmit->tail += dma->tx_size;
  25. xmit->tail &= UART_XMIT_SIZE - 1;
  26. p->port.icount.tx += dma->tx_size;
  27. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  28. uart_write_wakeup(&p->port);
  29. if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port))
  30. serial8250_tx_dma(p);
  31. }
  32. static void __dma_rx_complete(void *param)
  33. {
  34. struct uart_8250_port *p = param;
  35. struct uart_8250_dma *dma = p->dma;
  36. struct tty_port *tty_port = &p->port.state->port;
  37. struct dma_tx_state state;
  38. int count;
  39. dma_sync_single_for_cpu(dma->rxchan->device->dev, dma->rx_addr,
  40. dma->rx_size, DMA_FROM_DEVICE);
  41. dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
  42. dmaengine_terminate_all(dma->rxchan);
  43. count = dma->rx_size - state.residue;
  44. tty_insert_flip_string(tty_port, dma->rx_buf, count);
  45. p->port.icount.rx += count;
  46. tty_flip_buffer_push(tty_port);
  47. }
  48. int serial8250_tx_dma(struct uart_8250_port *p)
  49. {
  50. struct uart_8250_dma *dma = p->dma;
  51. struct circ_buf *xmit = &p->port.state->xmit;
  52. struct dma_async_tx_descriptor *desc;
  53. if (uart_tx_stopped(&p->port) || dma->tx_running ||
  54. uart_circ_empty(xmit))
  55. return 0;
  56. dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
  57. desc = dmaengine_prep_slave_single(dma->txchan,
  58. dma->tx_addr + xmit->tail,
  59. dma->tx_size, DMA_MEM_TO_DEV,
  60. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  61. if (!desc)
  62. return -EBUSY;
  63. dma->tx_running = 1;
  64. desc->callback = __dma_tx_complete;
  65. desc->callback_param = p;
  66. dma->tx_cookie = dmaengine_submit(desc);
  67. dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
  68. UART_XMIT_SIZE, DMA_TO_DEVICE);
  69. dma_async_issue_pending(dma->txchan);
  70. return 0;
  71. }
  72. EXPORT_SYMBOL_GPL(serial8250_tx_dma);
  73. int serial8250_rx_dma(struct uart_8250_port *p, unsigned int iir)
  74. {
  75. struct uart_8250_dma *dma = p->dma;
  76. struct dma_async_tx_descriptor *desc;
  77. struct dma_tx_state state;
  78. int dma_status;
  79. dma_status = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
  80. switch (iir & 0x3f) {
  81. case UART_IIR_RLSI:
  82. /* 8250_core handles errors and break interrupts */
  83. return -EIO;
  84. case UART_IIR_RX_TIMEOUT:
  85. /*
  86. * If RCVR FIFO trigger level was not reached, complete the
  87. * transfer and let 8250_core copy the remaining data.
  88. */
  89. if (dma_status == DMA_IN_PROGRESS) {
  90. dmaengine_pause(dma->rxchan);
  91. __dma_rx_complete(p);
  92. }
  93. return -ETIMEDOUT;
  94. default:
  95. break;
  96. }
  97. if (dma_status)
  98. return 0;
  99. desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
  100. dma->rx_size, DMA_DEV_TO_MEM,
  101. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  102. if (!desc)
  103. return -EBUSY;
  104. desc->callback = __dma_rx_complete;
  105. desc->callback_param = p;
  106. dma->rx_cookie = dmaengine_submit(desc);
  107. dma_sync_single_for_device(dma->rxchan->device->dev, dma->rx_addr,
  108. dma->rx_size, DMA_FROM_DEVICE);
  109. dma_async_issue_pending(dma->rxchan);
  110. return 0;
  111. }
  112. EXPORT_SYMBOL_GPL(serial8250_rx_dma);
  113. int serial8250_request_dma(struct uart_8250_port *p)
  114. {
  115. struct uart_8250_dma *dma = p->dma;
  116. dma_cap_mask_t mask;
  117. /* Default slave configuration parameters */
  118. dma->rxconf.direction = DMA_DEV_TO_MEM;
  119. dma->rxconf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  120. dma->rxconf.src_addr = p->port.mapbase + UART_RX;
  121. dma->txconf.direction = DMA_MEM_TO_DEV;
  122. dma->txconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
  123. dma->txconf.dst_addr = p->port.mapbase + UART_TX;
  124. dma_cap_zero(mask);
  125. dma_cap_set(DMA_SLAVE, mask);
  126. /* Get a channel for RX */
  127. dma->rxchan = dma_request_slave_channel_compat(mask,
  128. dma->fn, dma->rx_param,
  129. p->port.dev, "rx");
  130. if (!dma->rxchan)
  131. return -ENODEV;
  132. dmaengine_slave_config(dma->rxchan, &dma->rxconf);
  133. /* Get a channel for TX */
  134. dma->txchan = dma_request_slave_channel_compat(mask,
  135. dma->fn, dma->tx_param,
  136. p->port.dev, "tx");
  137. if (!dma->txchan) {
  138. dma_release_channel(dma->rxchan);
  139. return -ENODEV;
  140. }
  141. dmaengine_slave_config(dma->txchan, &dma->txconf);
  142. /* RX buffer */
  143. if (!dma->rx_size)
  144. dma->rx_size = PAGE_SIZE;
  145. dma->rx_buf = dma_alloc_coherent(dma->rxchan->device->dev, dma->rx_size,
  146. &dma->rx_addr, GFP_KERNEL);
  147. if (!dma->rx_buf) {
  148. dma_release_channel(dma->rxchan);
  149. dma_release_channel(dma->txchan);
  150. return -ENOMEM;
  151. }
  152. /* TX buffer */
  153. dma->tx_addr = dma_map_single(dma->txchan->device->dev,
  154. p->port.state->xmit.buf,
  155. UART_XMIT_SIZE,
  156. DMA_TO_DEVICE);
  157. dev_dbg_ratelimited(p->port.dev, "got both dma channels\n");
  158. return 0;
  159. }
  160. EXPORT_SYMBOL_GPL(serial8250_request_dma);
  161. void serial8250_release_dma(struct uart_8250_port *p)
  162. {
  163. struct uart_8250_dma *dma = p->dma;
  164. if (!dma)
  165. return;
  166. /* Release RX resources */
  167. dmaengine_terminate_all(dma->rxchan);
  168. dma_free_coherent(dma->rxchan->device->dev, dma->rx_size, dma->rx_buf,
  169. dma->rx_addr);
  170. dma_release_channel(dma->rxchan);
  171. dma->rxchan = NULL;
  172. /* Release TX resources */
  173. dmaengine_terminate_all(dma->txchan);
  174. dma_unmap_single(dma->txchan->device->dev, dma->tx_addr,
  175. UART_XMIT_SIZE, DMA_TO_DEVICE);
  176. dma_release_channel(dma->txchan);
  177. dma->txchan = NULL;
  178. dma->tx_running = 0;
  179. dev_dbg_ratelimited(p->port.dev, "dma channels released\n");
  180. }
  181. EXPORT_SYMBOL_GPL(serial8250_release_dma);