8250.h 4.5 KB

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  1. /*
  2. * Driver for 8250/16550-type serial ports
  3. *
  4. * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  5. *
  6. * Copyright (C) 2001 Russell King.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/serial_8250.h>
  14. #include <linux/dmaengine.h>
  15. struct uart_8250_dma {
  16. dma_filter_fn fn;
  17. void *rx_param;
  18. void *tx_param;
  19. int rx_chan_id;
  20. int tx_chan_id;
  21. struct dma_slave_config rxconf;
  22. struct dma_slave_config txconf;
  23. struct dma_chan *rxchan;
  24. struct dma_chan *txchan;
  25. dma_addr_t rx_addr;
  26. dma_addr_t tx_addr;
  27. dma_cookie_t rx_cookie;
  28. dma_cookie_t tx_cookie;
  29. void *rx_buf;
  30. size_t rx_size;
  31. size_t tx_size;
  32. unsigned char tx_running:1;
  33. };
  34. struct old_serial_port {
  35. unsigned int uart;
  36. unsigned int baud_base;
  37. unsigned int port;
  38. unsigned int irq;
  39. unsigned int flags;
  40. unsigned char hub6;
  41. unsigned char io_type;
  42. unsigned char *iomem_base;
  43. unsigned short iomem_reg_shift;
  44. unsigned long irqflags;
  45. };
  46. struct serial8250_config {
  47. const char *name;
  48. unsigned short fifo_size;
  49. unsigned short tx_loadsz;
  50. unsigned char fcr;
  51. unsigned int flags;
  52. };
  53. #define UART_CAP_FIFO (1 << 8) /* UART has FIFO */
  54. #define UART_CAP_EFR (1 << 9) /* UART has EFR */
  55. #define UART_CAP_SLEEP (1 << 10) /* UART has IER sleep */
  56. #define UART_CAP_AFE (1 << 11) /* MCR-based hw flow control */
  57. #define UART_CAP_UUE (1 << 12) /* UART needs IER bit 6 set (Xscale) */
  58. #define UART_CAP_RTOIE (1 << 13) /* UART needs IER bit 4 set (Xscale, Tegra) */
  59. #define UART_CAP_HFIFO (1 << 14) /* UART has a "hidden" FIFO */
  60. #define UART_BUG_QUOT (1 << 0) /* UART has buggy quot LSB */
  61. #define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */
  62. #define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */
  63. #define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */
  64. #define UART_BUG_PARITY (1 << 4) /* UART mishandles parity if FIFO enabled */
  65. #define PROBE_RSA (1 << 0)
  66. #define PROBE_ANY (~0)
  67. #define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
  68. #ifdef CONFIG_SERIAL_8250_SHARE_IRQ
  69. #define SERIAL8250_SHARE_IRQS 1
  70. #else
  71. #define SERIAL8250_SHARE_IRQS 0
  72. #endif
  73. static inline int serial_in(struct uart_8250_port *up, int offset)
  74. {
  75. return up->port.serial_in(&up->port, offset);
  76. }
  77. static inline void serial_out(struct uart_8250_port *up, int offset, int value)
  78. {
  79. up->port.serial_out(&up->port, offset, value);
  80. }
  81. void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p);
  82. static inline int serial_dl_read(struct uart_8250_port *up)
  83. {
  84. return up->dl_read(up);
  85. }
  86. static inline void serial_dl_write(struct uart_8250_port *up, int value)
  87. {
  88. up->dl_write(up, value);
  89. }
  90. #if defined(__alpha__) && !defined(CONFIG_PCI)
  91. /*
  92. * Digital did something really horribly wrong with the OUT1 and OUT2
  93. * lines on at least some ALPHA's. The failure mode is that if either
  94. * is cleared, the machine locks up with endless interrupts.
  95. */
  96. #define ALPHA_KLUDGE_MCR (UART_MCR_OUT2 | UART_MCR_OUT1)
  97. #else
  98. #define ALPHA_KLUDGE_MCR 0
  99. #endif
  100. #ifdef CONFIG_SERIAL_8250_PNP
  101. int serial8250_pnp_init(void);
  102. void serial8250_pnp_exit(void);
  103. #else
  104. static inline int serial8250_pnp_init(void) { return 0; }
  105. static inline void serial8250_pnp_exit(void) { }
  106. #endif
  107. #ifdef CONFIG_ARCH_OMAP1
  108. static inline int is_omap1_8250(struct uart_8250_port *pt)
  109. {
  110. int res;
  111. switch (pt->port.mapbase) {
  112. case OMAP1_UART1_BASE:
  113. case OMAP1_UART2_BASE:
  114. case OMAP1_UART3_BASE:
  115. res = 1;
  116. break;
  117. default:
  118. res = 0;
  119. break;
  120. }
  121. return res;
  122. }
  123. static inline int is_omap1510_8250(struct uart_8250_port *pt)
  124. {
  125. if (!cpu_is_omap1510())
  126. return 0;
  127. return is_omap1_8250(pt);
  128. }
  129. #else
  130. static inline int is_omap1_8250(struct uart_8250_port *pt)
  131. {
  132. return 0;
  133. }
  134. static inline int is_omap1510_8250(struct uart_8250_port *pt)
  135. {
  136. return 0;
  137. }
  138. #endif
  139. #ifdef CONFIG_SERIAL_8250_DMA
  140. extern int serial8250_tx_dma(struct uart_8250_port *);
  141. extern int serial8250_rx_dma(struct uart_8250_port *, unsigned int iir);
  142. extern int serial8250_request_dma(struct uart_8250_port *);
  143. extern void serial8250_release_dma(struct uart_8250_port *);
  144. #else
  145. static inline int serial8250_tx_dma(struct uart_8250_port *p)
  146. {
  147. return -1;
  148. }
  149. static inline int serial8250_rx_dma(struct uart_8250_port *p, unsigned int iir)
  150. {
  151. return -1;
  152. }
  153. static inline int serial8250_request_dma(struct uart_8250_port *p)
  154. {
  155. return -1;
  156. }
  157. static inline void serial8250_release_dma(struct uart_8250_port *p) { }
  158. #endif