ql4_mbx.c 66 KB

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  1. /*
  2. * QLogic iSCSI HBA Driver
  3. * Copyright (c) 2003-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qla4xxx for copyright and licensing details.
  6. */
  7. #include <linux/ctype.h>
  8. #include "ql4_def.h"
  9. #include "ql4_glbl.h"
  10. #include "ql4_dbg.h"
  11. #include "ql4_inline.h"
  12. #include "ql4_version.h"
  13. void qla4xxx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
  14. int in_count)
  15. {
  16. int i;
  17. /* Load all mailbox registers, except mailbox 0. */
  18. for (i = 1; i < in_count; i++)
  19. writel(mbx_cmd[i], &ha->reg->mailbox[i]);
  20. /* Wakeup firmware */
  21. writel(mbx_cmd[0], &ha->reg->mailbox[0]);
  22. readl(&ha->reg->mailbox[0]);
  23. writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
  24. readl(&ha->reg->ctrl_status);
  25. }
  26. void qla4xxx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
  27. {
  28. int intr_status;
  29. intr_status = readl(&ha->reg->ctrl_status);
  30. if (intr_status & INTR_PENDING) {
  31. /*
  32. * Service the interrupt.
  33. * The ISR will save the mailbox status registers
  34. * to a temporary storage location in the adapter structure.
  35. */
  36. ha->mbox_status_count = out_count;
  37. ha->isp_ops->interrupt_service_routine(ha, intr_status);
  38. }
  39. }
  40. /**
  41. * qla4xxx_is_intr_poll_mode – Are we allowed to poll for interrupts?
  42. * @ha: Pointer to host adapter structure.
  43. * @ret: 1=polling mode, 0=non-polling mode
  44. **/
  45. static int qla4xxx_is_intr_poll_mode(struct scsi_qla_host *ha)
  46. {
  47. int rval = 1;
  48. if (is_qla8032(ha) || is_qla8042(ha)) {
  49. if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
  50. test_bit(AF_83XX_MBOX_INTR_ON, &ha->flags))
  51. rval = 0;
  52. } else {
  53. if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
  54. test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
  55. test_bit(AF_ONLINE, &ha->flags) &&
  56. !test_bit(AF_HA_REMOVAL, &ha->flags))
  57. rval = 0;
  58. }
  59. return rval;
  60. }
  61. /**
  62. * qla4xxx_mailbox_command - issues mailbox commands
  63. * @ha: Pointer to host adapter structure.
  64. * @inCount: number of mailbox registers to load.
  65. * @outCount: number of mailbox registers to return.
  66. * @mbx_cmd: data pointer for mailbox in registers.
  67. * @mbx_sts: data pointer for mailbox out registers.
  68. *
  69. * This routine issue mailbox commands and waits for completion.
  70. * If outCount is 0, this routine completes successfully WITHOUT waiting
  71. * for the mailbox command to complete.
  72. **/
  73. int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
  74. uint8_t outCount, uint32_t *mbx_cmd,
  75. uint32_t *mbx_sts)
  76. {
  77. int status = QLA_ERROR;
  78. uint8_t i;
  79. u_long wait_count;
  80. unsigned long flags = 0;
  81. uint32_t dev_state;
  82. /* Make sure that pointers are valid */
  83. if (!mbx_cmd || !mbx_sts) {
  84. DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
  85. "pointer\n", ha->host_no, __func__));
  86. return status;
  87. }
  88. if (is_qla40XX(ha)) {
  89. if (test_bit(AF_HA_REMOVAL, &ha->flags)) {
  90. DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: "
  91. "prematurely completing mbx cmd as "
  92. "adapter removal detected\n",
  93. ha->host_no, __func__));
  94. return status;
  95. }
  96. }
  97. if ((is_aer_supported(ha)) &&
  98. (test_bit(AF_PCI_CHANNEL_IO_PERM_FAILURE, &ha->flags))) {
  99. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Perm failure on EEH, "
  100. "timeout MBX Exiting.\n", ha->host_no, __func__));
  101. return status;
  102. }
  103. /* Mailbox code active */
  104. wait_count = MBOX_TOV * 100;
  105. while (wait_count--) {
  106. mutex_lock(&ha->mbox_sem);
  107. if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  108. set_bit(AF_MBOX_COMMAND, &ha->flags);
  109. mutex_unlock(&ha->mbox_sem);
  110. break;
  111. }
  112. mutex_unlock(&ha->mbox_sem);
  113. if (!wait_count) {
  114. DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
  115. ha->host_no, __func__));
  116. return status;
  117. }
  118. msleep(10);
  119. }
  120. if (is_qla80XX(ha)) {
  121. if (test_bit(AF_FW_RECOVERY, &ha->flags)) {
  122. DEBUG2(ql4_printk(KERN_WARNING, ha,
  123. "scsi%ld: %s: prematurely completing mbx cmd as firmware recovery detected\n",
  124. ha->host_no, __func__));
  125. goto mbox_exit;
  126. }
  127. /* Do not send any mbx cmd if h/w is in failed state*/
  128. ha->isp_ops->idc_lock(ha);
  129. dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
  130. ha->isp_ops->idc_unlock(ha);
  131. if (dev_state == QLA8XXX_DEV_FAILED) {
  132. ql4_printk(KERN_WARNING, ha,
  133. "scsi%ld: %s: H/W is in failed state, do not send any mailbox commands\n",
  134. ha->host_no, __func__);
  135. goto mbox_exit;
  136. }
  137. }
  138. spin_lock_irqsave(&ha->hardware_lock, flags);
  139. ha->mbox_status_count = outCount;
  140. for (i = 0; i < outCount; i++)
  141. ha->mbox_status[i] = 0;
  142. /* Queue the mailbox command to the firmware */
  143. ha->isp_ops->queue_mailbox_command(ha, mbx_cmd, inCount);
  144. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  145. /* Wait for completion */
  146. /*
  147. * If we don't want status, don't wait for the mailbox command to
  148. * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
  149. * you must poll the inbound Interrupt Mask for completion.
  150. */
  151. if (outCount == 0) {
  152. status = QLA_SUCCESS;
  153. goto mbox_exit;
  154. }
  155. /*
  156. * Wait for completion: Poll or completion queue
  157. */
  158. if (qla4xxx_is_intr_poll_mode(ha)) {
  159. /* Poll for command to complete */
  160. wait_count = jiffies + MBOX_TOV * HZ;
  161. while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
  162. if (time_after_eq(jiffies, wait_count))
  163. break;
  164. /*
  165. * Service the interrupt.
  166. * The ISR will save the mailbox status registers
  167. * to a temporary storage location in the adapter
  168. * structure.
  169. */
  170. spin_lock_irqsave(&ha->hardware_lock, flags);
  171. ha->isp_ops->process_mailbox_interrupt(ha, outCount);
  172. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  173. msleep(10);
  174. }
  175. } else {
  176. /* Do not poll for completion. Use completion queue */
  177. set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  178. wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
  179. clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  180. }
  181. /* Check for mailbox timeout. */
  182. if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
  183. if (is_qla80XX(ha) &&
  184. test_bit(AF_FW_RECOVERY, &ha->flags)) {
  185. DEBUG2(ql4_printk(KERN_INFO, ha,
  186. "scsi%ld: %s: prematurely completing mbx cmd as "
  187. "firmware recovery detected\n",
  188. ha->host_no, __func__));
  189. goto mbox_exit;
  190. }
  191. DEBUG2(printk("scsi%ld: Mailbox Cmd 0x%08X timed out ...,"
  192. " Scheduling Adapter Reset\n", ha->host_no,
  193. mbx_cmd[0]));
  194. ha->mailbox_timeout_count++;
  195. mbx_sts[0] = (-1);
  196. set_bit(DPC_RESET_HA, &ha->dpc_flags);
  197. if (is_qla8022(ha)) {
  198. ql4_printk(KERN_INFO, ha,
  199. "disabling pause transmit on port 0 & 1.\n");
  200. qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
  201. CRB_NIU_XG_PAUSE_CTL_P0 |
  202. CRB_NIU_XG_PAUSE_CTL_P1);
  203. } else if (is_qla8032(ha) || is_qla8042(ha)) {
  204. ql4_printk(KERN_INFO, ha, " %s: disabling pause transmit on port 0 & 1.\n",
  205. __func__);
  206. qla4_83xx_disable_pause(ha);
  207. }
  208. goto mbox_exit;
  209. }
  210. /*
  211. * Copy the mailbox out registers to the caller's mailbox in/out
  212. * structure.
  213. */
  214. spin_lock_irqsave(&ha->hardware_lock, flags);
  215. for (i = 0; i < outCount; i++)
  216. mbx_sts[i] = ha->mbox_status[i];
  217. /* Set return status and error flags (if applicable). */
  218. switch (ha->mbox_status[0]) {
  219. case MBOX_STS_COMMAND_COMPLETE:
  220. status = QLA_SUCCESS;
  221. break;
  222. case MBOX_STS_INTERMEDIATE_COMPLETION:
  223. status = QLA_SUCCESS;
  224. break;
  225. case MBOX_STS_BUSY:
  226. DEBUG2( printk("scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
  227. ha->host_no, __func__, mbx_cmd[0]));
  228. ha->mailbox_timeout_count++;
  229. break;
  230. default:
  231. DEBUG2(printk("scsi%ld: %s: **** FAILED, cmd = %08X, "
  232. "sts = %08X ****\n", ha->host_no, __func__,
  233. mbx_cmd[0], mbx_sts[0]));
  234. break;
  235. }
  236. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  237. mbox_exit:
  238. mutex_lock(&ha->mbox_sem);
  239. clear_bit(AF_MBOX_COMMAND, &ha->flags);
  240. mutex_unlock(&ha->mbox_sem);
  241. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  242. return status;
  243. }
  244. /**
  245. * qla4xxx_get_minidump_template - Get the firmware template
  246. * @ha: Pointer to host adapter structure.
  247. * @phys_addr: dma address for template
  248. *
  249. * Obtain the minidump template from firmware during initialization
  250. * as it may not be available when minidump is desired.
  251. **/
  252. int qla4xxx_get_minidump_template(struct scsi_qla_host *ha,
  253. dma_addr_t phys_addr)
  254. {
  255. uint32_t mbox_cmd[MBOX_REG_COUNT];
  256. uint32_t mbox_sts[MBOX_REG_COUNT];
  257. int status;
  258. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  259. memset(&mbox_sts, 0, sizeof(mbox_sts));
  260. mbox_cmd[0] = MBOX_CMD_MINIDUMP;
  261. mbox_cmd[1] = MINIDUMP_GET_TMPLT_SUBCOMMAND;
  262. mbox_cmd[2] = LSDW(phys_addr);
  263. mbox_cmd[3] = MSDW(phys_addr);
  264. mbox_cmd[4] = ha->fw_dump_tmplt_size;
  265. mbox_cmd[5] = 0;
  266. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
  267. &mbox_sts[0]);
  268. if (status != QLA_SUCCESS) {
  269. DEBUG2(ql4_printk(KERN_INFO, ha,
  270. "scsi%ld: %s: Cmd = %08X, mbx[0] = 0x%04x, mbx[1] = 0x%04x\n",
  271. ha->host_no, __func__, mbox_cmd[0],
  272. mbox_sts[0], mbox_sts[1]));
  273. }
  274. return status;
  275. }
  276. /**
  277. * qla4xxx_req_template_size - Get minidump template size from firmware.
  278. * @ha: Pointer to host adapter structure.
  279. **/
  280. int qla4xxx_req_template_size(struct scsi_qla_host *ha)
  281. {
  282. uint32_t mbox_cmd[MBOX_REG_COUNT];
  283. uint32_t mbox_sts[MBOX_REG_COUNT];
  284. int status;
  285. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  286. memset(&mbox_sts, 0, sizeof(mbox_sts));
  287. mbox_cmd[0] = MBOX_CMD_MINIDUMP;
  288. mbox_cmd[1] = MINIDUMP_GET_SIZE_SUBCOMMAND;
  289. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 8, &mbox_cmd[0],
  290. &mbox_sts[0]);
  291. if (status == QLA_SUCCESS) {
  292. ha->fw_dump_tmplt_size = mbox_sts[1];
  293. DEBUG2(ql4_printk(KERN_INFO, ha,
  294. "%s: sts[0]=0x%04x, template size=0x%04x, size_cm_02=0x%04x, size_cm_04=0x%04x, size_cm_08=0x%04x, size_cm_10=0x%04x, size_cm_FF=0x%04x, version=0x%04x\n",
  295. __func__, mbox_sts[0], mbox_sts[1],
  296. mbox_sts[2], mbox_sts[3], mbox_sts[4],
  297. mbox_sts[5], mbox_sts[6], mbox_sts[7]));
  298. if (ha->fw_dump_tmplt_size == 0)
  299. status = QLA_ERROR;
  300. } else {
  301. ql4_printk(KERN_WARNING, ha,
  302. "%s: Error sts[0]=0x%04x, mbx[1]=0x%04x\n",
  303. __func__, mbox_sts[0], mbox_sts[1]);
  304. status = QLA_ERROR;
  305. }
  306. return status;
  307. }
  308. void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha)
  309. {
  310. set_bit(AF_FW_RECOVERY, &ha->flags);
  311. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n",
  312. ha->host_no, __func__);
  313. if (test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  314. if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) {
  315. complete(&ha->mbx_intr_comp);
  316. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  317. "recovery, doing premature completion of "
  318. "mbx cmd\n", ha->host_no, __func__);
  319. } else {
  320. set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  321. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  322. "recovery, doing premature completion of "
  323. "polling mbx cmd\n", ha->host_no, __func__);
  324. }
  325. }
  326. }
  327. static uint8_t
  328. qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  329. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  330. {
  331. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  332. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  333. if (is_qla8022(ha))
  334. qla4_82xx_wr_32(ha, ha->nx_db_wr_ptr, 0);
  335. mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
  336. mbox_cmd[1] = 0;
  337. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  338. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  339. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  340. mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
  341. if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
  342. QLA_SUCCESS) {
  343. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  344. "MBOX_CMD_INITIALIZE_FIRMWARE"
  345. " failed w/ status %04X\n",
  346. ha->host_no, __func__, mbox_sts[0]));
  347. return QLA_ERROR;
  348. }
  349. return QLA_SUCCESS;
  350. }
  351. uint8_t
  352. qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  353. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  354. {
  355. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  356. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  357. mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
  358. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  359. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  360. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  361. if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
  362. QLA_SUCCESS) {
  363. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  364. "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
  365. " failed w/ status %04X\n",
  366. ha->host_no, __func__, mbox_sts[0]));
  367. return QLA_ERROR;
  368. }
  369. return QLA_SUCCESS;
  370. }
  371. static void
  372. qla4xxx_update_local_ip(struct scsi_qla_host *ha,
  373. struct addr_ctrl_blk *init_fw_cb)
  374. {
  375. ha->ip_config.tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
  376. ha->ip_config.ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
  377. ha->ip_config.ipv4_addr_state =
  378. le16_to_cpu(init_fw_cb->ipv4_addr_state);
  379. ha->ip_config.eth_mtu_size =
  380. le16_to_cpu(init_fw_cb->eth_mtu_size);
  381. ha->ip_config.ipv4_port = le16_to_cpu(init_fw_cb->ipv4_port);
  382. if (ha->acb_version == ACB_SUPPORTED) {
  383. ha->ip_config.ipv6_options = le16_to_cpu(init_fw_cb->ipv6_opts);
  384. ha->ip_config.ipv6_addl_options =
  385. le16_to_cpu(init_fw_cb->ipv6_addtl_opts);
  386. }
  387. /* Save IPv4 Address Info */
  388. memcpy(ha->ip_config.ip_address, init_fw_cb->ipv4_addr,
  389. min(sizeof(ha->ip_config.ip_address),
  390. sizeof(init_fw_cb->ipv4_addr)));
  391. memcpy(ha->ip_config.subnet_mask, init_fw_cb->ipv4_subnet,
  392. min(sizeof(ha->ip_config.subnet_mask),
  393. sizeof(init_fw_cb->ipv4_subnet)));
  394. memcpy(ha->ip_config.gateway, init_fw_cb->ipv4_gw_addr,
  395. min(sizeof(ha->ip_config.gateway),
  396. sizeof(init_fw_cb->ipv4_gw_addr)));
  397. ha->ip_config.ipv4_vlan_tag = be16_to_cpu(init_fw_cb->ipv4_vlan_tag);
  398. if (is_ipv6_enabled(ha)) {
  399. /* Save IPv6 Address */
  400. ha->ip_config.ipv6_link_local_state =
  401. le16_to_cpu(init_fw_cb->ipv6_lnk_lcl_addr_state);
  402. ha->ip_config.ipv6_addr0_state =
  403. le16_to_cpu(init_fw_cb->ipv6_addr0_state);
  404. ha->ip_config.ipv6_addr1_state =
  405. le16_to_cpu(init_fw_cb->ipv6_addr1_state);
  406. ha->ip_config.ipv6_default_router_state =
  407. le16_to_cpu(init_fw_cb->ipv6_dflt_rtr_state);
  408. ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
  409. ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
  410. memcpy(&ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[8],
  411. init_fw_cb->ipv6_if_id,
  412. min(sizeof(ha->ip_config.ipv6_link_local_addr)/2,
  413. sizeof(init_fw_cb->ipv6_if_id)));
  414. memcpy(&ha->ip_config.ipv6_addr0, init_fw_cb->ipv6_addr0,
  415. min(sizeof(ha->ip_config.ipv6_addr0),
  416. sizeof(init_fw_cb->ipv6_addr0)));
  417. memcpy(&ha->ip_config.ipv6_addr1, init_fw_cb->ipv6_addr1,
  418. min(sizeof(ha->ip_config.ipv6_addr1),
  419. sizeof(init_fw_cb->ipv6_addr1)));
  420. memcpy(&ha->ip_config.ipv6_default_router_addr,
  421. init_fw_cb->ipv6_dflt_rtr_addr,
  422. min(sizeof(ha->ip_config.ipv6_default_router_addr),
  423. sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
  424. ha->ip_config.ipv6_vlan_tag =
  425. be16_to_cpu(init_fw_cb->ipv6_vlan_tag);
  426. ha->ip_config.ipv6_port = le16_to_cpu(init_fw_cb->ipv6_port);
  427. }
  428. }
  429. uint8_t
  430. qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
  431. uint32_t *mbox_cmd,
  432. uint32_t *mbox_sts,
  433. struct addr_ctrl_blk *init_fw_cb,
  434. dma_addr_t init_fw_cb_dma)
  435. {
  436. if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
  437. != QLA_SUCCESS) {
  438. DEBUG2(printk(KERN_WARNING
  439. "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  440. ha->host_no, __func__));
  441. return QLA_ERROR;
  442. }
  443. DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
  444. /* Save some info in adapter structure. */
  445. ha->acb_version = init_fw_cb->acb_version;
  446. ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
  447. ha->heartbeat_interval = init_fw_cb->hb_interval;
  448. memcpy(ha->name_string, init_fw_cb->iscsi_name,
  449. min(sizeof(ha->name_string),
  450. sizeof(init_fw_cb->iscsi_name)));
  451. ha->def_timeout = le16_to_cpu(init_fw_cb->def_timeout);
  452. /*memcpy(ha->alias, init_fw_cb->Alias,
  453. min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
  454. qla4xxx_update_local_ip(ha, init_fw_cb);
  455. return QLA_SUCCESS;
  456. }
  457. /**
  458. * qla4xxx_initialize_fw_cb - initializes firmware control block.
  459. * @ha: Pointer to host adapter structure.
  460. **/
  461. int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
  462. {
  463. struct addr_ctrl_blk *init_fw_cb;
  464. dma_addr_t init_fw_cb_dma;
  465. uint32_t mbox_cmd[MBOX_REG_COUNT];
  466. uint32_t mbox_sts[MBOX_REG_COUNT];
  467. int status = QLA_ERROR;
  468. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  469. sizeof(struct addr_ctrl_blk),
  470. &init_fw_cb_dma, GFP_KERNEL);
  471. if (init_fw_cb == NULL) {
  472. DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
  473. ha->host_no, __func__));
  474. goto exit_init_fw_cb_no_free;
  475. }
  476. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  477. /* Get Initialize Firmware Control Block. */
  478. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  479. memset(&mbox_sts, 0, sizeof(mbox_sts));
  480. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  481. QLA_SUCCESS) {
  482. dma_free_coherent(&ha->pdev->dev,
  483. sizeof(struct addr_ctrl_blk),
  484. init_fw_cb, init_fw_cb_dma);
  485. goto exit_init_fw_cb;
  486. }
  487. /* Initialize request and response queues. */
  488. qla4xxx_init_rings(ha);
  489. /* Fill in the request and response queue information. */
  490. init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
  491. init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
  492. init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
  493. init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
  494. init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
  495. init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
  496. init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
  497. init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
  498. init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
  499. init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
  500. /* Set up required options. */
  501. init_fw_cb->fw_options |=
  502. __constant_cpu_to_le16(FWOPT_SESSION_MODE |
  503. FWOPT_INITIATOR_MODE);
  504. if (is_qla80XX(ha))
  505. init_fw_cb->fw_options |=
  506. __constant_cpu_to_le16(FWOPT_ENABLE_CRBDB);
  507. init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
  508. init_fw_cb->add_fw_options = 0;
  509. init_fw_cb->add_fw_options |=
  510. __constant_cpu_to_le16(ADFWOPT_SERIALIZE_TASK_MGMT);
  511. init_fw_cb->add_fw_options |=
  512. __constant_cpu_to_le16(ADFWOPT_AUTOCONN_DISABLE);
  513. if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
  514. != QLA_SUCCESS) {
  515. DEBUG2(printk(KERN_WARNING
  516. "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
  517. ha->host_no, __func__));
  518. goto exit_init_fw_cb;
  519. }
  520. if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
  521. init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
  522. DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
  523. ha->host_no, __func__));
  524. goto exit_init_fw_cb;
  525. }
  526. status = QLA_SUCCESS;
  527. exit_init_fw_cb:
  528. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  529. init_fw_cb, init_fw_cb_dma);
  530. exit_init_fw_cb_no_free:
  531. return status;
  532. }
  533. /**
  534. * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
  535. * @ha: Pointer to host adapter structure.
  536. **/
  537. int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
  538. {
  539. struct addr_ctrl_blk *init_fw_cb;
  540. dma_addr_t init_fw_cb_dma;
  541. uint32_t mbox_cmd[MBOX_REG_COUNT];
  542. uint32_t mbox_sts[MBOX_REG_COUNT];
  543. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  544. sizeof(struct addr_ctrl_blk),
  545. &init_fw_cb_dma, GFP_KERNEL);
  546. if (init_fw_cb == NULL) {
  547. printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
  548. __func__);
  549. return QLA_ERROR;
  550. }
  551. /* Get Initialize Firmware Control Block. */
  552. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  553. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  554. QLA_SUCCESS) {
  555. DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  556. ha->host_no, __func__));
  557. dma_free_coherent(&ha->pdev->dev,
  558. sizeof(struct addr_ctrl_blk),
  559. init_fw_cb, init_fw_cb_dma);
  560. return QLA_ERROR;
  561. }
  562. /* Save IP Address. */
  563. qla4xxx_update_local_ip(ha, init_fw_cb);
  564. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  565. init_fw_cb, init_fw_cb_dma);
  566. return QLA_SUCCESS;
  567. }
  568. /**
  569. * qla4xxx_get_firmware_state - gets firmware state of HBA
  570. * @ha: Pointer to host adapter structure.
  571. **/
  572. int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
  573. {
  574. uint32_t mbox_cmd[MBOX_REG_COUNT];
  575. uint32_t mbox_sts[MBOX_REG_COUNT];
  576. /* Get firmware version */
  577. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  578. memset(&mbox_sts, 0, sizeof(mbox_sts));
  579. mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
  580. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
  581. QLA_SUCCESS) {
  582. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
  583. "status %04X\n", ha->host_no, __func__,
  584. mbox_sts[0]));
  585. return QLA_ERROR;
  586. }
  587. ha->firmware_state = mbox_sts[1];
  588. ha->board_id = mbox_sts[2];
  589. ha->addl_fw_state = mbox_sts[3];
  590. DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
  591. ha->host_no, __func__, ha->firmware_state);)
  592. return QLA_SUCCESS;
  593. }
  594. /**
  595. * qla4xxx_get_firmware_status - retrieves firmware status
  596. * @ha: Pointer to host adapter structure.
  597. **/
  598. int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
  599. {
  600. uint32_t mbox_cmd[MBOX_REG_COUNT];
  601. uint32_t mbox_sts[MBOX_REG_COUNT];
  602. /* Get firmware version */
  603. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  604. memset(&mbox_sts, 0, sizeof(mbox_sts));
  605. mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
  606. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  607. QLA_SUCCESS) {
  608. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
  609. "status %04X\n", ha->host_no, __func__,
  610. mbox_sts[0]));
  611. return QLA_ERROR;
  612. }
  613. /* High-water mark of IOCBs */
  614. ha->iocb_hiwat = mbox_sts[2];
  615. DEBUG2(ql4_printk(KERN_INFO, ha,
  616. "%s: firmware IOCBs available = %d\n", __func__,
  617. ha->iocb_hiwat));
  618. if (ha->iocb_hiwat > IOCB_HIWAT_CUSHION)
  619. ha->iocb_hiwat -= IOCB_HIWAT_CUSHION;
  620. /* Ideally, we should not enter this code, as the # of firmware
  621. * IOCBs is hard-coded in the firmware. We set a default
  622. * iocb_hiwat here just in case */
  623. if (ha->iocb_hiwat == 0) {
  624. ha->iocb_hiwat = REQUEST_QUEUE_DEPTH / 4;
  625. DEBUG2(ql4_printk(KERN_WARNING, ha,
  626. "%s: Setting IOCB's to = %d\n", __func__,
  627. ha->iocb_hiwat));
  628. }
  629. return QLA_SUCCESS;
  630. }
  631. /**
  632. * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
  633. * @ha: Pointer to host adapter structure.
  634. * @fw_ddb_index: Firmware's device database index
  635. * @fw_ddb_entry: Pointer to firmware's device database entry structure
  636. * @num_valid_ddb_entries: Pointer to number of valid ddb entries
  637. * @next_ddb_index: Pointer to next valid device database index
  638. * @fw_ddb_device_state: Pointer to device state
  639. **/
  640. int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
  641. uint16_t fw_ddb_index,
  642. struct dev_db_entry *fw_ddb_entry,
  643. dma_addr_t fw_ddb_entry_dma,
  644. uint32_t *num_valid_ddb_entries,
  645. uint32_t *next_ddb_index,
  646. uint32_t *fw_ddb_device_state,
  647. uint32_t *conn_err_detail,
  648. uint16_t *tcp_source_port_num,
  649. uint16_t *connection_id)
  650. {
  651. int status = QLA_ERROR;
  652. uint16_t options;
  653. uint32_t mbox_cmd[MBOX_REG_COUNT];
  654. uint32_t mbox_sts[MBOX_REG_COUNT];
  655. /* Make sure the device index is valid */
  656. if (fw_ddb_index >= MAX_DDB_ENTRIES) {
  657. DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
  658. ha->host_no, __func__, fw_ddb_index));
  659. goto exit_get_fwddb;
  660. }
  661. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  662. memset(&mbox_sts, 0, sizeof(mbox_sts));
  663. if (fw_ddb_entry)
  664. memset(fw_ddb_entry, 0, sizeof(struct dev_db_entry));
  665. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
  666. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  667. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  668. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  669. mbox_cmd[4] = sizeof(struct dev_db_entry);
  670. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
  671. QLA_ERROR) {
  672. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
  673. " with status 0x%04X\n", ha->host_no, __func__,
  674. mbox_sts[0]));
  675. goto exit_get_fwddb;
  676. }
  677. if (fw_ddb_index != mbox_sts[1]) {
  678. DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
  679. ha->host_no, __func__, fw_ddb_index,
  680. mbox_sts[1]));
  681. goto exit_get_fwddb;
  682. }
  683. if (fw_ddb_entry) {
  684. options = le16_to_cpu(fw_ddb_entry->options);
  685. if (options & DDB_OPT_IPV6_DEVICE) {
  686. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  687. "Next %d State %04x ConnErr %08x %pI6 "
  688. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  689. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  690. mbox_sts[4], mbox_sts[5],
  691. fw_ddb_entry->ip_addr,
  692. le16_to_cpu(fw_ddb_entry->port),
  693. fw_ddb_entry->iscsi_name);
  694. } else {
  695. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  696. "Next %d State %04x ConnErr %08x %pI4 "
  697. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  698. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  699. mbox_sts[4], mbox_sts[5],
  700. fw_ddb_entry->ip_addr,
  701. le16_to_cpu(fw_ddb_entry->port),
  702. fw_ddb_entry->iscsi_name);
  703. }
  704. }
  705. if (num_valid_ddb_entries)
  706. *num_valid_ddb_entries = mbox_sts[2];
  707. if (next_ddb_index)
  708. *next_ddb_index = mbox_sts[3];
  709. if (fw_ddb_device_state)
  710. *fw_ddb_device_state = mbox_sts[4];
  711. /*
  712. * RA: This mailbox has been changed to pass connection error and
  713. * details. Its true for ISP4010 as per Version E - Not sure when it
  714. * was changed. Get the time2wait from the fw_dd_entry field :
  715. * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
  716. * struct.
  717. */
  718. if (conn_err_detail)
  719. *conn_err_detail = mbox_sts[5];
  720. if (tcp_source_port_num)
  721. *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
  722. if (connection_id)
  723. *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
  724. status = QLA_SUCCESS;
  725. exit_get_fwddb:
  726. return status;
  727. }
  728. int qla4xxx_conn_open(struct scsi_qla_host *ha, uint16_t fw_ddb_index)
  729. {
  730. uint32_t mbox_cmd[MBOX_REG_COUNT];
  731. uint32_t mbox_sts[MBOX_REG_COUNT];
  732. int status;
  733. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  734. memset(&mbox_sts, 0, sizeof(mbox_sts));
  735. mbox_cmd[0] = MBOX_CMD_CONN_OPEN;
  736. mbox_cmd[1] = fw_ddb_index;
  737. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
  738. &mbox_sts[0]);
  739. DEBUG2(ql4_printk(KERN_INFO, ha,
  740. "%s: status = %d mbx0 = 0x%x mbx1 = 0x%x\n",
  741. __func__, status, mbox_sts[0], mbox_sts[1]));
  742. return status;
  743. }
  744. /**
  745. * qla4xxx_set_fwddb_entry - sets a ddb entry.
  746. * @ha: Pointer to host adapter structure.
  747. * @fw_ddb_index: Firmware's device database index
  748. * @fw_ddb_entry_dma: dma address of ddb entry
  749. * @mbx_sts: mailbox 0 to be returned or NULL
  750. *
  751. * This routine initializes or updates the adapter's device database
  752. * entry for the specified device.
  753. **/
  754. int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
  755. dma_addr_t fw_ddb_entry_dma, uint32_t *mbx_sts)
  756. {
  757. uint32_t mbox_cmd[MBOX_REG_COUNT];
  758. uint32_t mbox_sts[MBOX_REG_COUNT];
  759. int status;
  760. /* Do not wait for completion. The firmware will send us an
  761. * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
  762. */
  763. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  764. memset(&mbox_sts, 0, sizeof(mbox_sts));
  765. mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
  766. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  767. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  768. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  769. mbox_cmd[4] = sizeof(struct dev_db_entry);
  770. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  771. &mbox_sts[0]);
  772. if (mbx_sts)
  773. *mbx_sts = mbox_sts[0];
  774. DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
  775. ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
  776. return status;
  777. }
  778. int qla4xxx_session_logout_ddb(struct scsi_qla_host *ha,
  779. struct ddb_entry *ddb_entry, int options)
  780. {
  781. int status;
  782. uint32_t mbox_cmd[MBOX_REG_COUNT];
  783. uint32_t mbox_sts[MBOX_REG_COUNT];
  784. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  785. memset(&mbox_sts, 0, sizeof(mbox_sts));
  786. mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
  787. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  788. mbox_cmd[3] = options;
  789. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
  790. &mbox_sts[0]);
  791. if (status != QLA_SUCCESS) {
  792. DEBUG2(ql4_printk(KERN_INFO, ha,
  793. "%s: MBOX_CMD_CONN_CLOSE_SESS_LOGOUT "
  794. "failed sts %04X %04X", __func__,
  795. mbox_sts[0], mbox_sts[1]));
  796. }
  797. return status;
  798. }
  799. /**
  800. * qla4xxx_get_crash_record - retrieves crash record.
  801. * @ha: Pointer to host adapter structure.
  802. *
  803. * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
  804. **/
  805. void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
  806. {
  807. uint32_t mbox_cmd[MBOX_REG_COUNT];
  808. uint32_t mbox_sts[MBOX_REG_COUNT];
  809. struct crash_record *crash_record = NULL;
  810. dma_addr_t crash_record_dma = 0;
  811. uint32_t crash_record_size = 0;
  812. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  813. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  814. /* Get size of crash record. */
  815. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  816. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  817. QLA_SUCCESS) {
  818. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
  819. ha->host_no, __func__));
  820. goto exit_get_crash_record;
  821. }
  822. crash_record_size = mbox_sts[4];
  823. if (crash_record_size == 0) {
  824. DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
  825. ha->host_no, __func__));
  826. goto exit_get_crash_record;
  827. }
  828. /* Alloc Memory for Crash Record. */
  829. crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
  830. &crash_record_dma, GFP_KERNEL);
  831. if (crash_record == NULL)
  832. goto exit_get_crash_record;
  833. /* Get Crash Record. */
  834. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  835. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  836. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  837. mbox_cmd[2] = LSDW(crash_record_dma);
  838. mbox_cmd[3] = MSDW(crash_record_dma);
  839. mbox_cmd[4] = crash_record_size;
  840. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  841. QLA_SUCCESS)
  842. goto exit_get_crash_record;
  843. /* Dump Crash Record. */
  844. exit_get_crash_record:
  845. if (crash_record)
  846. dma_free_coherent(&ha->pdev->dev, crash_record_size,
  847. crash_record, crash_record_dma);
  848. }
  849. /**
  850. * qla4xxx_get_conn_event_log - retrieves connection event log
  851. * @ha: Pointer to host adapter structure.
  852. **/
  853. void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
  854. {
  855. uint32_t mbox_cmd[MBOX_REG_COUNT];
  856. uint32_t mbox_sts[MBOX_REG_COUNT];
  857. struct conn_event_log_entry *event_log = NULL;
  858. dma_addr_t event_log_dma = 0;
  859. uint32_t event_log_size = 0;
  860. uint32_t num_valid_entries;
  861. uint32_t oldest_entry = 0;
  862. uint32_t max_event_log_entries;
  863. uint8_t i;
  864. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  865. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  866. /* Get size of crash record. */
  867. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  868. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  869. QLA_SUCCESS)
  870. goto exit_get_event_log;
  871. event_log_size = mbox_sts[4];
  872. if (event_log_size == 0)
  873. goto exit_get_event_log;
  874. /* Alloc Memory for Crash Record. */
  875. event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
  876. &event_log_dma, GFP_KERNEL);
  877. if (event_log == NULL)
  878. goto exit_get_event_log;
  879. /* Get Crash Record. */
  880. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  881. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  882. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  883. mbox_cmd[2] = LSDW(event_log_dma);
  884. mbox_cmd[3] = MSDW(event_log_dma);
  885. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  886. QLA_SUCCESS) {
  887. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
  888. "log!\n", ha->host_no, __func__));
  889. goto exit_get_event_log;
  890. }
  891. /* Dump Event Log. */
  892. num_valid_entries = mbox_sts[1];
  893. max_event_log_entries = event_log_size /
  894. sizeof(struct conn_event_log_entry);
  895. if (num_valid_entries > max_event_log_entries)
  896. oldest_entry = num_valid_entries % max_event_log_entries;
  897. DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
  898. ha->host_no, num_valid_entries));
  899. if (ql4xextended_error_logging == 3) {
  900. if (oldest_entry == 0) {
  901. /* Circular Buffer has not wrapped around */
  902. for (i=0; i < num_valid_entries; i++) {
  903. qla4xxx_dump_buffer((uint8_t *)event_log+
  904. (i*sizeof(*event_log)),
  905. sizeof(*event_log));
  906. }
  907. }
  908. else {
  909. /* Circular Buffer has wrapped around -
  910. * display accordingly*/
  911. for (i=oldest_entry; i < max_event_log_entries; i++) {
  912. qla4xxx_dump_buffer((uint8_t *)event_log+
  913. (i*sizeof(*event_log)),
  914. sizeof(*event_log));
  915. }
  916. for (i=0; i < oldest_entry; i++) {
  917. qla4xxx_dump_buffer((uint8_t *)event_log+
  918. (i*sizeof(*event_log)),
  919. sizeof(*event_log));
  920. }
  921. }
  922. }
  923. exit_get_event_log:
  924. if (event_log)
  925. dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
  926. event_log_dma);
  927. }
  928. /**
  929. * qla4xxx_abort_task - issues Abort Task
  930. * @ha: Pointer to host adapter structure.
  931. * @srb: Pointer to srb entry
  932. *
  933. * This routine performs a LUN RESET on the specified target/lun.
  934. * The caller must ensure that the ddb_entry and lun_entry pointers
  935. * are valid before calling this routine.
  936. **/
  937. int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
  938. {
  939. uint32_t mbox_cmd[MBOX_REG_COUNT];
  940. uint32_t mbox_sts[MBOX_REG_COUNT];
  941. struct scsi_cmnd *cmd = srb->cmd;
  942. int status = QLA_SUCCESS;
  943. unsigned long flags = 0;
  944. uint32_t index;
  945. /*
  946. * Send abort task command to ISP, so that the ISP will return
  947. * request with ABORT status
  948. */
  949. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  950. memset(&mbox_sts, 0, sizeof(mbox_sts));
  951. spin_lock_irqsave(&ha->hardware_lock, flags);
  952. index = (unsigned long)(unsigned char *)cmd->host_scribble;
  953. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  954. /* Firmware already posted completion on response queue */
  955. if (index == MAX_SRBS)
  956. return status;
  957. mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
  958. mbox_cmd[1] = srb->ddb->fw_ddb_index;
  959. mbox_cmd[2] = index;
  960. /* Immediate Command Enable */
  961. mbox_cmd[5] = 0x01;
  962. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  963. &mbox_sts[0]);
  964. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
  965. status = QLA_ERROR;
  966. DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%d: abort task FAILED: "
  967. "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
  968. ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
  969. mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
  970. }
  971. return status;
  972. }
  973. /**
  974. * qla4xxx_reset_lun - issues LUN Reset
  975. * @ha: Pointer to host adapter structure.
  976. * @ddb_entry: Pointer to device database entry
  977. * @lun: lun number
  978. *
  979. * This routine performs a LUN RESET on the specified target/lun.
  980. * The caller must ensure that the ddb_entry and lun_entry pointers
  981. * are valid before calling this routine.
  982. **/
  983. int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
  984. int lun)
  985. {
  986. uint32_t mbox_cmd[MBOX_REG_COUNT];
  987. uint32_t mbox_sts[MBOX_REG_COUNT];
  988. uint32_t scsi_lun[2];
  989. int status = QLA_SUCCESS;
  990. DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no,
  991. ddb_entry->fw_ddb_index, lun));
  992. /*
  993. * Send lun reset command to ISP, so that the ISP will return all
  994. * outstanding requests with RESET status
  995. */
  996. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  997. memset(&mbox_sts, 0, sizeof(mbox_sts));
  998. int_to_scsilun(lun, (struct scsi_lun *) scsi_lun);
  999. mbox_cmd[0] = MBOX_CMD_LUN_RESET;
  1000. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  1001. /* FW expects LUN bytes 0-3 in Incoming Mailbox 2
  1002. * (LUN byte 0 is LSByte, byte 3 is MSByte) */
  1003. mbox_cmd[2] = cpu_to_le32(scsi_lun[0]);
  1004. /* FW expects LUN bytes 4-7 in Incoming Mailbox 3
  1005. * (LUN byte 4 is LSByte, byte 7 is MSByte) */
  1006. mbox_cmd[3] = cpu_to_le32(scsi_lun[1]);
  1007. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  1008. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
  1009. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  1010. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  1011. status = QLA_ERROR;
  1012. return status;
  1013. }
  1014. /**
  1015. * qla4xxx_reset_target - issues target Reset
  1016. * @ha: Pointer to host adapter structure.
  1017. * @db_entry: Pointer to device database entry
  1018. * @un_entry: Pointer to lun entry structure
  1019. *
  1020. * This routine performs a TARGET RESET on the specified target.
  1021. * The caller must ensure that the ddb_entry pointers
  1022. * are valid before calling this routine.
  1023. **/
  1024. int qla4xxx_reset_target(struct scsi_qla_host *ha,
  1025. struct ddb_entry *ddb_entry)
  1026. {
  1027. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1028. uint32_t mbox_sts[MBOX_REG_COUNT];
  1029. int status = QLA_SUCCESS;
  1030. DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
  1031. ddb_entry->fw_ddb_index));
  1032. /*
  1033. * Send target reset command to ISP, so that the ISP will return all
  1034. * outstanding requests with RESET status
  1035. */
  1036. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1037. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1038. mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
  1039. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  1040. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  1041. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1042. &mbox_sts[0]);
  1043. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  1044. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  1045. status = QLA_ERROR;
  1046. return status;
  1047. }
  1048. int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
  1049. uint32_t offset, uint32_t len)
  1050. {
  1051. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1052. uint32_t mbox_sts[MBOX_REG_COUNT];
  1053. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1054. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1055. mbox_cmd[0] = MBOX_CMD_READ_FLASH;
  1056. mbox_cmd[1] = LSDW(dma_addr);
  1057. mbox_cmd[2] = MSDW(dma_addr);
  1058. mbox_cmd[3] = offset;
  1059. mbox_cmd[4] = len;
  1060. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
  1061. QLA_SUCCESS) {
  1062. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
  1063. "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
  1064. __func__, mbox_sts[0], mbox_sts[1], offset, len));
  1065. return QLA_ERROR;
  1066. }
  1067. return QLA_SUCCESS;
  1068. }
  1069. /**
  1070. * qla4xxx_about_firmware - gets FW, iscsi draft and boot loader version
  1071. * @ha: Pointer to host adapter structure.
  1072. *
  1073. * Retrieves the FW version, iSCSI draft version & bootloader version of HBA.
  1074. * Mailboxes 2 & 3 may hold an address for data. Make sure that we write 0 to
  1075. * those mailboxes, if unused.
  1076. **/
  1077. int qla4xxx_about_firmware(struct scsi_qla_host *ha)
  1078. {
  1079. struct about_fw_info *about_fw = NULL;
  1080. dma_addr_t about_fw_dma;
  1081. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1082. uint32_t mbox_sts[MBOX_REG_COUNT];
  1083. int status = QLA_ERROR;
  1084. about_fw = dma_alloc_coherent(&ha->pdev->dev,
  1085. sizeof(struct about_fw_info),
  1086. &about_fw_dma, GFP_KERNEL);
  1087. if (!about_fw) {
  1088. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: Unable to alloc memory "
  1089. "for about_fw\n", __func__));
  1090. return status;
  1091. }
  1092. memset(about_fw, 0, sizeof(struct about_fw_info));
  1093. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1094. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1095. mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
  1096. mbox_cmd[2] = LSDW(about_fw_dma);
  1097. mbox_cmd[3] = MSDW(about_fw_dma);
  1098. mbox_cmd[4] = sizeof(struct about_fw_info);
  1099. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
  1100. &mbox_cmd[0], &mbox_sts[0]);
  1101. if (status != QLA_SUCCESS) {
  1102. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_ABOUT_FW "
  1103. "failed w/ status %04X\n", __func__,
  1104. mbox_sts[0]));
  1105. goto exit_about_fw;
  1106. }
  1107. /* Save version information. */
  1108. ha->fw_info.fw_major = le16_to_cpu(about_fw->fw_major);
  1109. ha->fw_info.fw_minor = le16_to_cpu(about_fw->fw_minor);
  1110. ha->fw_info.fw_patch = le16_to_cpu(about_fw->fw_patch);
  1111. ha->fw_info.fw_build = le16_to_cpu(about_fw->fw_build);
  1112. memcpy(ha->fw_info.fw_build_date, about_fw->fw_build_date,
  1113. sizeof(about_fw->fw_build_date));
  1114. memcpy(ha->fw_info.fw_build_time, about_fw->fw_build_time,
  1115. sizeof(about_fw->fw_build_time));
  1116. strcpy((char *)ha->fw_info.fw_build_user,
  1117. skip_spaces((char *)about_fw->fw_build_user));
  1118. ha->fw_info.fw_load_source = le16_to_cpu(about_fw->fw_load_source);
  1119. ha->fw_info.iscsi_major = le16_to_cpu(about_fw->iscsi_major);
  1120. ha->fw_info.iscsi_minor = le16_to_cpu(about_fw->iscsi_minor);
  1121. ha->fw_info.bootload_major = le16_to_cpu(about_fw->bootload_major);
  1122. ha->fw_info.bootload_minor = le16_to_cpu(about_fw->bootload_minor);
  1123. ha->fw_info.bootload_patch = le16_to_cpu(about_fw->bootload_patch);
  1124. ha->fw_info.bootload_build = le16_to_cpu(about_fw->bootload_build);
  1125. strcpy((char *)ha->fw_info.extended_timestamp,
  1126. skip_spaces((char *)about_fw->extended_timestamp));
  1127. ha->fw_uptime_secs = le32_to_cpu(mbox_sts[5]);
  1128. ha->fw_uptime_msecs = le32_to_cpu(mbox_sts[6]);
  1129. status = QLA_SUCCESS;
  1130. exit_about_fw:
  1131. dma_free_coherent(&ha->pdev->dev, sizeof(struct about_fw_info),
  1132. about_fw, about_fw_dma);
  1133. return status;
  1134. }
  1135. int qla4xxx_get_default_ddb(struct scsi_qla_host *ha, uint32_t options,
  1136. dma_addr_t dma_addr)
  1137. {
  1138. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1139. uint32_t mbox_sts[MBOX_REG_COUNT];
  1140. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1141. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1142. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
  1143. mbox_cmd[1] = options;
  1144. mbox_cmd[2] = LSDW(dma_addr);
  1145. mbox_cmd[3] = MSDW(dma_addr);
  1146. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
  1147. QLA_SUCCESS) {
  1148. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  1149. ha->host_no, __func__, mbox_sts[0]));
  1150. return QLA_ERROR;
  1151. }
  1152. return QLA_SUCCESS;
  1153. }
  1154. int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index,
  1155. uint32_t *mbx_sts)
  1156. {
  1157. int status;
  1158. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1159. uint32_t mbox_sts[MBOX_REG_COUNT];
  1160. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1161. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1162. mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
  1163. mbox_cmd[1] = ddb_index;
  1164. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1165. &mbox_sts[0]);
  1166. if (status != QLA_SUCCESS) {
  1167. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
  1168. __func__, mbox_sts[0]));
  1169. }
  1170. *mbx_sts = mbox_sts[0];
  1171. return status;
  1172. }
  1173. int qla4xxx_clear_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index)
  1174. {
  1175. int status;
  1176. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1177. uint32_t mbox_sts[MBOX_REG_COUNT];
  1178. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1179. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1180. mbox_cmd[0] = MBOX_CMD_CLEAR_DATABASE_ENTRY;
  1181. mbox_cmd[1] = ddb_index;
  1182. status = qla4xxx_mailbox_command(ha, 2, 1, &mbox_cmd[0],
  1183. &mbox_sts[0]);
  1184. if (status != QLA_SUCCESS) {
  1185. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
  1186. __func__, mbox_sts[0]));
  1187. }
  1188. return status;
  1189. }
  1190. int qla4xxx_set_flash(struct scsi_qla_host *ha, dma_addr_t dma_addr,
  1191. uint32_t offset, uint32_t length, uint32_t options)
  1192. {
  1193. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1194. uint32_t mbox_sts[MBOX_REG_COUNT];
  1195. int status = QLA_SUCCESS;
  1196. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1197. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1198. mbox_cmd[0] = MBOX_CMD_WRITE_FLASH;
  1199. mbox_cmd[1] = LSDW(dma_addr);
  1200. mbox_cmd[2] = MSDW(dma_addr);
  1201. mbox_cmd[3] = offset;
  1202. mbox_cmd[4] = length;
  1203. mbox_cmd[5] = options;
  1204. status = qla4xxx_mailbox_command(ha, 6, 2, &mbox_cmd[0], &mbox_sts[0]);
  1205. if (status != QLA_SUCCESS) {
  1206. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_WRITE_FLASH "
  1207. "failed w/ status %04X, mbx1 %04X\n",
  1208. __func__, mbox_sts[0], mbox_sts[1]));
  1209. }
  1210. return status;
  1211. }
  1212. int qla4xxx_bootdb_by_index(struct scsi_qla_host *ha,
  1213. struct dev_db_entry *fw_ddb_entry,
  1214. dma_addr_t fw_ddb_entry_dma, uint16_t ddb_index)
  1215. {
  1216. uint32_t dev_db_start_offset = FLASH_OFFSET_DB_INFO;
  1217. uint32_t dev_db_end_offset;
  1218. int status = QLA_ERROR;
  1219. memset(fw_ddb_entry, 0, sizeof(*fw_ddb_entry));
  1220. dev_db_start_offset += (ddb_index * sizeof(*fw_ddb_entry));
  1221. dev_db_end_offset = FLASH_OFFSET_DB_END;
  1222. if (dev_db_start_offset > dev_db_end_offset) {
  1223. DEBUG2(ql4_printk(KERN_ERR, ha,
  1224. "%s:Invalid DDB index %d", __func__,
  1225. ddb_index));
  1226. goto exit_bootdb_failed;
  1227. }
  1228. if (qla4xxx_get_flash(ha, fw_ddb_entry_dma, dev_db_start_offset,
  1229. sizeof(*fw_ddb_entry)) != QLA_SUCCESS) {
  1230. ql4_printk(KERN_ERR, ha, "scsi%ld: %s: Get Flash"
  1231. "failed\n", ha->host_no, __func__);
  1232. goto exit_bootdb_failed;
  1233. }
  1234. if (fw_ddb_entry->cookie == DDB_VALID_COOKIE)
  1235. status = QLA_SUCCESS;
  1236. exit_bootdb_failed:
  1237. return status;
  1238. }
  1239. int qla4xxx_flashdb_by_index(struct scsi_qla_host *ha,
  1240. struct dev_db_entry *fw_ddb_entry,
  1241. dma_addr_t fw_ddb_entry_dma, uint16_t ddb_index)
  1242. {
  1243. uint32_t dev_db_start_offset;
  1244. uint32_t dev_db_end_offset;
  1245. int status = QLA_ERROR;
  1246. memset(fw_ddb_entry, 0, sizeof(*fw_ddb_entry));
  1247. if (is_qla40XX(ha)) {
  1248. dev_db_start_offset = FLASH_OFFSET_DB_INFO;
  1249. dev_db_end_offset = FLASH_OFFSET_DB_END;
  1250. } else {
  1251. dev_db_start_offset = FLASH_RAW_ACCESS_ADDR +
  1252. (ha->hw.flt_region_ddb << 2);
  1253. /* flt_ddb_size is DDB table size for both ports
  1254. * so divide it by 2 to calculate the offset for second port
  1255. */
  1256. if (ha->port_num == 1)
  1257. dev_db_start_offset += (ha->hw.flt_ddb_size / 2);
  1258. dev_db_end_offset = dev_db_start_offset +
  1259. (ha->hw.flt_ddb_size / 2);
  1260. }
  1261. dev_db_start_offset += (ddb_index * sizeof(*fw_ddb_entry));
  1262. if (dev_db_start_offset > dev_db_end_offset) {
  1263. DEBUG2(ql4_printk(KERN_ERR, ha,
  1264. "%s:Invalid DDB index %d", __func__,
  1265. ddb_index));
  1266. goto exit_fdb_failed;
  1267. }
  1268. if (qla4xxx_get_flash(ha, fw_ddb_entry_dma, dev_db_start_offset,
  1269. sizeof(*fw_ddb_entry)) != QLA_SUCCESS) {
  1270. ql4_printk(KERN_ERR, ha, "scsi%ld: %s: Get Flash failed\n",
  1271. ha->host_no, __func__);
  1272. goto exit_fdb_failed;
  1273. }
  1274. if (fw_ddb_entry->cookie == DDB_VALID_COOKIE)
  1275. status = QLA_SUCCESS;
  1276. exit_fdb_failed:
  1277. return status;
  1278. }
  1279. int qla4xxx_get_chap(struct scsi_qla_host *ha, char *username, char *password,
  1280. uint16_t idx)
  1281. {
  1282. int ret = 0;
  1283. int rval = QLA_ERROR;
  1284. uint32_t offset = 0, chap_size;
  1285. struct ql4_chap_table *chap_table;
  1286. dma_addr_t chap_dma;
  1287. chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
  1288. if (chap_table == NULL)
  1289. return -ENOMEM;
  1290. chap_size = sizeof(struct ql4_chap_table);
  1291. memset(chap_table, 0, chap_size);
  1292. if (is_qla40XX(ha))
  1293. offset = FLASH_CHAP_OFFSET | (idx * chap_size);
  1294. else {
  1295. offset = FLASH_RAW_ACCESS_ADDR + (ha->hw.flt_region_chap << 2);
  1296. /* flt_chap_size is CHAP table size for both ports
  1297. * so divide it by 2 to calculate the offset for second port
  1298. */
  1299. if (ha->port_num == 1)
  1300. offset += (ha->hw.flt_chap_size / 2);
  1301. offset += (idx * chap_size);
  1302. }
  1303. rval = qla4xxx_get_flash(ha, chap_dma, offset, chap_size);
  1304. if (rval != QLA_SUCCESS) {
  1305. ret = -EINVAL;
  1306. goto exit_get_chap;
  1307. }
  1308. DEBUG2(ql4_printk(KERN_INFO, ha, "Chap Cookie: x%x\n",
  1309. __le16_to_cpu(chap_table->cookie)));
  1310. if (__le16_to_cpu(chap_table->cookie) != CHAP_VALID_COOKIE) {
  1311. ql4_printk(KERN_ERR, ha, "No valid chap entry found\n");
  1312. goto exit_get_chap;
  1313. }
  1314. strncpy(password, chap_table->secret, QL4_CHAP_MAX_SECRET_LEN);
  1315. strncpy(username, chap_table->name, QL4_CHAP_MAX_NAME_LEN);
  1316. chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
  1317. exit_get_chap:
  1318. dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
  1319. return ret;
  1320. }
  1321. static int qla4xxx_set_chap(struct scsi_qla_host *ha, char *username,
  1322. char *password, uint16_t idx, int bidi)
  1323. {
  1324. int ret = 0;
  1325. int rval = QLA_ERROR;
  1326. uint32_t offset = 0;
  1327. struct ql4_chap_table *chap_table;
  1328. dma_addr_t chap_dma;
  1329. chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
  1330. if (chap_table == NULL) {
  1331. ret = -ENOMEM;
  1332. goto exit_set_chap;
  1333. }
  1334. memset(chap_table, 0, sizeof(struct ql4_chap_table));
  1335. if (bidi)
  1336. chap_table->flags |= BIT_6; /* peer */
  1337. else
  1338. chap_table->flags |= BIT_7; /* local */
  1339. chap_table->secret_len = strlen(password);
  1340. strncpy(chap_table->secret, password, MAX_CHAP_SECRET_LEN);
  1341. strncpy(chap_table->name, username, MAX_CHAP_NAME_LEN);
  1342. chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
  1343. offset = FLASH_CHAP_OFFSET | (idx * sizeof(struct ql4_chap_table));
  1344. rval = qla4xxx_set_flash(ha, chap_dma, offset,
  1345. sizeof(struct ql4_chap_table),
  1346. FLASH_OPT_RMW_COMMIT);
  1347. if (rval == QLA_SUCCESS && ha->chap_list) {
  1348. /* Update ha chap_list cache */
  1349. memcpy((struct ql4_chap_table *)ha->chap_list + idx,
  1350. chap_table, sizeof(struct ql4_chap_table));
  1351. }
  1352. dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
  1353. if (rval != QLA_SUCCESS)
  1354. ret = -EINVAL;
  1355. exit_set_chap:
  1356. return ret;
  1357. }
  1358. int qla4xxx_get_uni_chap_at_index(struct scsi_qla_host *ha, char *username,
  1359. char *password, uint16_t chap_index)
  1360. {
  1361. int rval = QLA_ERROR;
  1362. struct ql4_chap_table *chap_table = NULL;
  1363. int max_chap_entries;
  1364. if (!ha->chap_list) {
  1365. ql4_printk(KERN_ERR, ha, "Do not have CHAP table cache\n");
  1366. rval = QLA_ERROR;
  1367. goto exit_uni_chap;
  1368. }
  1369. if (!username || !password) {
  1370. ql4_printk(KERN_ERR, ha, "No memory for username & secret\n");
  1371. rval = QLA_ERROR;
  1372. goto exit_uni_chap;
  1373. }
  1374. if (is_qla80XX(ha))
  1375. max_chap_entries = (ha->hw.flt_chap_size / 2) /
  1376. sizeof(struct ql4_chap_table);
  1377. else
  1378. max_chap_entries = MAX_CHAP_ENTRIES_40XX;
  1379. if (chap_index > max_chap_entries) {
  1380. ql4_printk(KERN_ERR, ha, "Invalid Chap index\n");
  1381. rval = QLA_ERROR;
  1382. goto exit_uni_chap;
  1383. }
  1384. mutex_lock(&ha->chap_sem);
  1385. chap_table = (struct ql4_chap_table *)ha->chap_list + chap_index;
  1386. if (chap_table->cookie != __constant_cpu_to_le16(CHAP_VALID_COOKIE)) {
  1387. rval = QLA_ERROR;
  1388. goto exit_unlock_uni_chap;
  1389. }
  1390. if (!(chap_table->flags & BIT_6)) {
  1391. ql4_printk(KERN_ERR, ha, "Unidirectional entry not set\n");
  1392. rval = QLA_ERROR;
  1393. goto exit_unlock_uni_chap;
  1394. }
  1395. strncpy(password, chap_table->secret, MAX_CHAP_SECRET_LEN);
  1396. strncpy(username, chap_table->name, MAX_CHAP_NAME_LEN);
  1397. rval = QLA_SUCCESS;
  1398. exit_unlock_uni_chap:
  1399. mutex_unlock(&ha->chap_sem);
  1400. exit_uni_chap:
  1401. return rval;
  1402. }
  1403. /**
  1404. * qla4xxx_get_chap_index - Get chap index given username and secret
  1405. * @ha: pointer to adapter structure
  1406. * @username: CHAP username to be searched
  1407. * @password: CHAP password to be searched
  1408. * @bidi: Is this a BIDI CHAP
  1409. * @chap_index: CHAP index to be returned
  1410. *
  1411. * Match the username and password in the chap_list, return the index if a
  1412. * match is found. If a match is not found then add the entry in FLASH and
  1413. * return the index at which entry is written in the FLASH.
  1414. **/
  1415. int qla4xxx_get_chap_index(struct scsi_qla_host *ha, char *username,
  1416. char *password, int bidi, uint16_t *chap_index)
  1417. {
  1418. int i, rval;
  1419. int free_index = -1;
  1420. int found_index = 0;
  1421. int max_chap_entries = 0;
  1422. struct ql4_chap_table *chap_table;
  1423. if (is_qla80XX(ha))
  1424. max_chap_entries = (ha->hw.flt_chap_size / 2) /
  1425. sizeof(struct ql4_chap_table);
  1426. else
  1427. max_chap_entries = MAX_CHAP_ENTRIES_40XX;
  1428. if (!ha->chap_list) {
  1429. ql4_printk(KERN_ERR, ha, "Do not have CHAP table cache\n");
  1430. return QLA_ERROR;
  1431. }
  1432. if (!username || !password) {
  1433. ql4_printk(KERN_ERR, ha, "Do not have username and psw\n");
  1434. return QLA_ERROR;
  1435. }
  1436. mutex_lock(&ha->chap_sem);
  1437. for (i = 0; i < max_chap_entries; i++) {
  1438. chap_table = (struct ql4_chap_table *)ha->chap_list + i;
  1439. if (chap_table->cookie !=
  1440. __constant_cpu_to_le16(CHAP_VALID_COOKIE)) {
  1441. if (i > MAX_RESRV_CHAP_IDX && free_index == -1)
  1442. free_index = i;
  1443. continue;
  1444. }
  1445. if (bidi) {
  1446. if (chap_table->flags & BIT_7)
  1447. continue;
  1448. } else {
  1449. if (chap_table->flags & BIT_6)
  1450. continue;
  1451. }
  1452. if (!strncmp(chap_table->secret, password,
  1453. MAX_CHAP_SECRET_LEN) &&
  1454. !strncmp(chap_table->name, username,
  1455. MAX_CHAP_NAME_LEN)) {
  1456. *chap_index = i;
  1457. found_index = 1;
  1458. break;
  1459. }
  1460. }
  1461. /* If chap entry is not present and a free index is available then
  1462. * write the entry in flash
  1463. */
  1464. if (!found_index && free_index != -1) {
  1465. rval = qla4xxx_set_chap(ha, username, password,
  1466. free_index, bidi);
  1467. if (!rval) {
  1468. *chap_index = free_index;
  1469. found_index = 1;
  1470. }
  1471. }
  1472. mutex_unlock(&ha->chap_sem);
  1473. if (found_index)
  1474. return QLA_SUCCESS;
  1475. return QLA_ERROR;
  1476. }
  1477. int qla4xxx_conn_close_sess_logout(struct scsi_qla_host *ha,
  1478. uint16_t fw_ddb_index,
  1479. uint16_t connection_id,
  1480. uint16_t option)
  1481. {
  1482. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1483. uint32_t mbox_sts[MBOX_REG_COUNT];
  1484. int status = QLA_SUCCESS;
  1485. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1486. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1487. mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
  1488. mbox_cmd[1] = fw_ddb_index;
  1489. mbox_cmd[2] = connection_id;
  1490. mbox_cmd[3] = option;
  1491. status = qla4xxx_mailbox_command(ha, 4, 2, &mbox_cmd[0], &mbox_sts[0]);
  1492. if (status != QLA_SUCCESS) {
  1493. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_CONN_CLOSE "
  1494. "option %04x failed w/ status %04X %04X\n",
  1495. __func__, option, mbox_sts[0], mbox_sts[1]));
  1496. }
  1497. return status;
  1498. }
  1499. /**
  1500. * qla4_84xx_extend_idc_tmo - Extend IDC Timeout.
  1501. * @ha: Pointer to host adapter structure.
  1502. * @ext_tmo: idc timeout value
  1503. *
  1504. * Requests firmware to extend the idc timeout value.
  1505. **/
  1506. static int qla4_84xx_extend_idc_tmo(struct scsi_qla_host *ha, uint32_t ext_tmo)
  1507. {
  1508. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1509. uint32_t mbox_sts[MBOX_REG_COUNT];
  1510. int status;
  1511. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1512. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1513. ext_tmo &= 0xf;
  1514. mbox_cmd[0] = MBOX_CMD_IDC_TIME_EXTEND;
  1515. mbox_cmd[1] = ((ha->idc_info.request_desc & 0xfffff0ff) |
  1516. (ext_tmo << 8)); /* new timeout */
  1517. mbox_cmd[2] = ha->idc_info.info1;
  1518. mbox_cmd[3] = ha->idc_info.info2;
  1519. mbox_cmd[4] = ha->idc_info.info3;
  1520. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
  1521. mbox_cmd, mbox_sts);
  1522. if (status != QLA_SUCCESS) {
  1523. DEBUG2(ql4_printk(KERN_INFO, ha,
  1524. "scsi%ld: %s: failed status %04X\n",
  1525. ha->host_no, __func__, mbox_sts[0]));
  1526. return QLA_ERROR;
  1527. } else {
  1528. ql4_printk(KERN_INFO, ha, "%s: IDC timeout extended by %d secs\n",
  1529. __func__, ext_tmo);
  1530. }
  1531. return QLA_SUCCESS;
  1532. }
  1533. int qla4xxx_disable_acb(struct scsi_qla_host *ha)
  1534. {
  1535. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1536. uint32_t mbox_sts[MBOX_REG_COUNT];
  1537. int status = QLA_SUCCESS;
  1538. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1539. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1540. mbox_cmd[0] = MBOX_CMD_DISABLE_ACB;
  1541. status = qla4xxx_mailbox_command(ha, 8, 5, &mbox_cmd[0], &mbox_sts[0]);
  1542. if (status != QLA_SUCCESS) {
  1543. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_DISABLE_ACB "
  1544. "failed w/ status %04X %04X %04X", __func__,
  1545. mbox_sts[0], mbox_sts[1], mbox_sts[2]));
  1546. } else {
  1547. if (is_qla8042(ha) &&
  1548. (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE)) {
  1549. /*
  1550. * Disable ACB mailbox command takes time to complete
  1551. * based on the total number of targets connected.
  1552. * For 512 targets, it took approximately 5 secs to
  1553. * complete. Setting the timeout value to 8, with the 3
  1554. * secs buffer.
  1555. */
  1556. qla4_84xx_extend_idc_tmo(ha, IDC_EXTEND_TOV);
  1557. if (!wait_for_completion_timeout(&ha->disable_acb_comp,
  1558. IDC_EXTEND_TOV * HZ)) {
  1559. ql4_printk(KERN_WARNING, ha, "%s: Disable ACB Completion not received\n",
  1560. __func__);
  1561. }
  1562. }
  1563. }
  1564. return status;
  1565. }
  1566. int qla4xxx_get_acb(struct scsi_qla_host *ha, dma_addr_t acb_dma,
  1567. uint32_t acb_type, uint32_t len)
  1568. {
  1569. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1570. uint32_t mbox_sts[MBOX_REG_COUNT];
  1571. int status = QLA_SUCCESS;
  1572. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1573. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1574. mbox_cmd[0] = MBOX_CMD_GET_ACB;
  1575. mbox_cmd[1] = acb_type;
  1576. mbox_cmd[2] = LSDW(acb_dma);
  1577. mbox_cmd[3] = MSDW(acb_dma);
  1578. mbox_cmd[4] = len;
  1579. status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
  1580. if (status != QLA_SUCCESS) {
  1581. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_GET_ACB "
  1582. "failed w/ status %04X\n", __func__,
  1583. mbox_sts[0]));
  1584. }
  1585. return status;
  1586. }
  1587. int qla4xxx_set_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  1588. uint32_t *mbox_sts, dma_addr_t acb_dma)
  1589. {
  1590. int status = QLA_SUCCESS;
  1591. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  1592. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  1593. mbox_cmd[0] = MBOX_CMD_SET_ACB;
  1594. mbox_cmd[1] = 0; /* Primary ACB */
  1595. mbox_cmd[2] = LSDW(acb_dma);
  1596. mbox_cmd[3] = MSDW(acb_dma);
  1597. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  1598. status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
  1599. if (status != QLA_SUCCESS) {
  1600. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_SET_ACB "
  1601. "failed w/ status %04X\n", __func__,
  1602. mbox_sts[0]));
  1603. }
  1604. return status;
  1605. }
  1606. int qla4xxx_set_param_ddbentry(struct scsi_qla_host *ha,
  1607. struct ddb_entry *ddb_entry,
  1608. struct iscsi_cls_conn *cls_conn,
  1609. uint32_t *mbx_sts)
  1610. {
  1611. struct dev_db_entry *fw_ddb_entry;
  1612. struct iscsi_conn *conn;
  1613. struct iscsi_session *sess;
  1614. struct qla_conn *qla_conn;
  1615. struct sockaddr *dst_addr;
  1616. dma_addr_t fw_ddb_entry_dma;
  1617. int status = QLA_SUCCESS;
  1618. int rval = 0;
  1619. struct sockaddr_in *addr;
  1620. struct sockaddr_in6 *addr6;
  1621. char *ip;
  1622. uint16_t iscsi_opts = 0;
  1623. uint32_t options = 0;
  1624. uint16_t idx, *ptid;
  1625. fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1626. &fw_ddb_entry_dma, GFP_KERNEL);
  1627. if (!fw_ddb_entry) {
  1628. DEBUG2(ql4_printk(KERN_ERR, ha,
  1629. "%s: Unable to allocate dma buffer.\n",
  1630. __func__));
  1631. rval = -ENOMEM;
  1632. goto exit_set_param_no_free;
  1633. }
  1634. conn = cls_conn->dd_data;
  1635. qla_conn = conn->dd_data;
  1636. sess = conn->session;
  1637. dst_addr = (struct sockaddr *)&qla_conn->qla_ep->dst_addr;
  1638. if (dst_addr->sa_family == AF_INET6)
  1639. options |= IPV6_DEFAULT_DDB_ENTRY;
  1640. status = qla4xxx_get_default_ddb(ha, options, fw_ddb_entry_dma);
  1641. if (status == QLA_ERROR) {
  1642. rval = -EINVAL;
  1643. goto exit_set_param;
  1644. }
  1645. ptid = (uint16_t *)&fw_ddb_entry->isid[1];
  1646. *ptid = cpu_to_le16((uint16_t)ddb_entry->sess->target_id);
  1647. DEBUG2(ql4_printk(KERN_INFO, ha, "ISID [%02x%02x%02x%02x%02x%02x]\n",
  1648. fw_ddb_entry->isid[5], fw_ddb_entry->isid[4],
  1649. fw_ddb_entry->isid[3], fw_ddb_entry->isid[2],
  1650. fw_ddb_entry->isid[1], fw_ddb_entry->isid[0]));
  1651. iscsi_opts = le16_to_cpu(fw_ddb_entry->iscsi_options);
  1652. memset(fw_ddb_entry->iscsi_alias, 0, sizeof(fw_ddb_entry->iscsi_alias));
  1653. memset(fw_ddb_entry->iscsi_name, 0, sizeof(fw_ddb_entry->iscsi_name));
  1654. if (sess->targetname != NULL) {
  1655. memcpy(fw_ddb_entry->iscsi_name, sess->targetname,
  1656. min(strlen(sess->targetname),
  1657. sizeof(fw_ddb_entry->iscsi_name)));
  1658. }
  1659. memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
  1660. memset(fw_ddb_entry->tgt_addr, 0, sizeof(fw_ddb_entry->tgt_addr));
  1661. fw_ddb_entry->options = DDB_OPT_TARGET | DDB_OPT_AUTO_SENDTGTS_DISABLE;
  1662. if (dst_addr->sa_family == AF_INET) {
  1663. addr = (struct sockaddr_in *)dst_addr;
  1664. ip = (char *)&addr->sin_addr;
  1665. memcpy(fw_ddb_entry->ip_addr, ip, IP_ADDR_LEN);
  1666. fw_ddb_entry->port = cpu_to_le16(ntohs(addr->sin_port));
  1667. DEBUG2(ql4_printk(KERN_INFO, ha,
  1668. "%s: Destination Address [%pI4]: index [%d]\n",
  1669. __func__, fw_ddb_entry->ip_addr,
  1670. ddb_entry->fw_ddb_index));
  1671. } else if (dst_addr->sa_family == AF_INET6) {
  1672. addr6 = (struct sockaddr_in6 *)dst_addr;
  1673. ip = (char *)&addr6->sin6_addr;
  1674. memcpy(fw_ddb_entry->ip_addr, ip, IPv6_ADDR_LEN);
  1675. fw_ddb_entry->port = cpu_to_le16(ntohs(addr6->sin6_port));
  1676. fw_ddb_entry->options |= DDB_OPT_IPV6_DEVICE;
  1677. DEBUG2(ql4_printk(KERN_INFO, ha,
  1678. "%s: Destination Address [%pI6]: index [%d]\n",
  1679. __func__, fw_ddb_entry->ip_addr,
  1680. ddb_entry->fw_ddb_index));
  1681. } else {
  1682. ql4_printk(KERN_ERR, ha,
  1683. "%s: Failed to get IP Address\n",
  1684. __func__);
  1685. rval = -EINVAL;
  1686. goto exit_set_param;
  1687. }
  1688. /* CHAP */
  1689. if (sess->username != NULL && sess->password != NULL) {
  1690. if (strlen(sess->username) && strlen(sess->password)) {
  1691. iscsi_opts |= BIT_7;
  1692. rval = qla4xxx_get_chap_index(ha, sess->username,
  1693. sess->password,
  1694. LOCAL_CHAP, &idx);
  1695. if (rval)
  1696. goto exit_set_param;
  1697. fw_ddb_entry->chap_tbl_idx = cpu_to_le16(idx);
  1698. }
  1699. }
  1700. if (sess->username_in != NULL && sess->password_in != NULL) {
  1701. /* Check if BIDI CHAP */
  1702. if (strlen(sess->username_in) && strlen(sess->password_in)) {
  1703. iscsi_opts |= BIT_4;
  1704. rval = qla4xxx_get_chap_index(ha, sess->username_in,
  1705. sess->password_in,
  1706. BIDI_CHAP, &idx);
  1707. if (rval)
  1708. goto exit_set_param;
  1709. }
  1710. }
  1711. if (sess->initial_r2t_en)
  1712. iscsi_opts |= BIT_10;
  1713. if (sess->imm_data_en)
  1714. iscsi_opts |= BIT_11;
  1715. fw_ddb_entry->iscsi_options = cpu_to_le16(iscsi_opts);
  1716. if (conn->max_recv_dlength)
  1717. fw_ddb_entry->iscsi_max_rcv_data_seg_len =
  1718. __constant_cpu_to_le16((conn->max_recv_dlength / BYTE_UNITS));
  1719. if (sess->max_r2t)
  1720. fw_ddb_entry->iscsi_max_outsnd_r2t = cpu_to_le16(sess->max_r2t);
  1721. if (sess->first_burst)
  1722. fw_ddb_entry->iscsi_first_burst_len =
  1723. __constant_cpu_to_le16((sess->first_burst / BYTE_UNITS));
  1724. if (sess->max_burst)
  1725. fw_ddb_entry->iscsi_max_burst_len =
  1726. __constant_cpu_to_le16((sess->max_burst / BYTE_UNITS));
  1727. if (sess->time2wait)
  1728. fw_ddb_entry->iscsi_def_time2wait =
  1729. cpu_to_le16(sess->time2wait);
  1730. if (sess->time2retain)
  1731. fw_ddb_entry->iscsi_def_time2retain =
  1732. cpu_to_le16(sess->time2retain);
  1733. status = qla4xxx_set_ddb_entry(ha, ddb_entry->fw_ddb_index,
  1734. fw_ddb_entry_dma, mbx_sts);
  1735. if (status != QLA_SUCCESS)
  1736. rval = -EINVAL;
  1737. exit_set_param:
  1738. dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1739. fw_ddb_entry, fw_ddb_entry_dma);
  1740. exit_set_param_no_free:
  1741. return rval;
  1742. }
  1743. int qla4xxx_get_mgmt_data(struct scsi_qla_host *ha, uint16_t fw_ddb_index,
  1744. uint16_t stats_size, dma_addr_t stats_dma)
  1745. {
  1746. int status = QLA_SUCCESS;
  1747. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1748. uint32_t mbox_sts[MBOX_REG_COUNT];
  1749. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  1750. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  1751. mbox_cmd[0] = MBOX_CMD_GET_MANAGEMENT_DATA;
  1752. mbox_cmd[1] = fw_ddb_index;
  1753. mbox_cmd[2] = LSDW(stats_dma);
  1754. mbox_cmd[3] = MSDW(stats_dma);
  1755. mbox_cmd[4] = stats_size;
  1756. status = qla4xxx_mailbox_command(ha, 5, 1, &mbox_cmd[0], &mbox_sts[0]);
  1757. if (status != QLA_SUCCESS) {
  1758. DEBUG2(ql4_printk(KERN_WARNING, ha,
  1759. "%s: MBOX_CMD_GET_MANAGEMENT_DATA "
  1760. "failed w/ status %04X\n", __func__,
  1761. mbox_sts[0]));
  1762. }
  1763. return status;
  1764. }
  1765. int qla4xxx_get_ip_state(struct scsi_qla_host *ha, uint32_t acb_idx,
  1766. uint32_t ip_idx, uint32_t *sts)
  1767. {
  1768. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1769. uint32_t mbox_sts[MBOX_REG_COUNT];
  1770. int status = QLA_SUCCESS;
  1771. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1772. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1773. mbox_cmd[0] = MBOX_CMD_GET_IP_ADDR_STATE;
  1774. mbox_cmd[1] = acb_idx;
  1775. mbox_cmd[2] = ip_idx;
  1776. status = qla4xxx_mailbox_command(ha, 3, 8, &mbox_cmd[0], &mbox_sts[0]);
  1777. if (status != QLA_SUCCESS) {
  1778. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: "
  1779. "MBOX_CMD_GET_IP_ADDR_STATE failed w/ "
  1780. "status %04X\n", __func__, mbox_sts[0]));
  1781. }
  1782. memcpy(sts, mbox_sts, sizeof(mbox_sts));
  1783. return status;
  1784. }
  1785. int qla4xxx_get_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
  1786. uint32_t offset, uint32_t size)
  1787. {
  1788. int status = QLA_SUCCESS;
  1789. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1790. uint32_t mbox_sts[MBOX_REG_COUNT];
  1791. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1792. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1793. mbox_cmd[0] = MBOX_CMD_GET_NVRAM;
  1794. mbox_cmd[1] = LSDW(nvram_dma);
  1795. mbox_cmd[2] = MSDW(nvram_dma);
  1796. mbox_cmd[3] = offset;
  1797. mbox_cmd[4] = size;
  1798. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1799. &mbox_sts[0]);
  1800. if (status != QLA_SUCCESS) {
  1801. DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
  1802. "status %04X\n", ha->host_no, __func__,
  1803. mbox_sts[0]));
  1804. }
  1805. return status;
  1806. }
  1807. int qla4xxx_set_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
  1808. uint32_t offset, uint32_t size)
  1809. {
  1810. int status = QLA_SUCCESS;
  1811. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1812. uint32_t mbox_sts[MBOX_REG_COUNT];
  1813. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1814. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1815. mbox_cmd[0] = MBOX_CMD_SET_NVRAM;
  1816. mbox_cmd[1] = LSDW(nvram_dma);
  1817. mbox_cmd[2] = MSDW(nvram_dma);
  1818. mbox_cmd[3] = offset;
  1819. mbox_cmd[4] = size;
  1820. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1821. &mbox_sts[0]);
  1822. if (status != QLA_SUCCESS) {
  1823. DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
  1824. "status %04X\n", ha->host_no, __func__,
  1825. mbox_sts[0]));
  1826. }
  1827. return status;
  1828. }
  1829. int qla4xxx_restore_factory_defaults(struct scsi_qla_host *ha,
  1830. uint32_t region, uint32_t field0,
  1831. uint32_t field1)
  1832. {
  1833. int status = QLA_SUCCESS;
  1834. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1835. uint32_t mbox_sts[MBOX_REG_COUNT];
  1836. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1837. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1838. mbox_cmd[0] = MBOX_CMD_RESTORE_FACTORY_DEFAULTS;
  1839. mbox_cmd[3] = region;
  1840. mbox_cmd[4] = field0;
  1841. mbox_cmd[5] = field1;
  1842. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0],
  1843. &mbox_sts[0]);
  1844. if (status != QLA_SUCCESS) {
  1845. DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
  1846. "status %04X\n", ha->host_no, __func__,
  1847. mbox_sts[0]));
  1848. }
  1849. return status;
  1850. }
  1851. /**
  1852. * qla4_8xxx_set_param - set driver version in firmware.
  1853. * @ha: Pointer to host adapter structure.
  1854. * @param: Parameter to set i.e driver version
  1855. **/
  1856. int qla4_8xxx_set_param(struct scsi_qla_host *ha, int param)
  1857. {
  1858. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1859. uint32_t mbox_sts[MBOX_REG_COUNT];
  1860. uint32_t status;
  1861. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1862. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1863. mbox_cmd[0] = MBOX_CMD_SET_PARAM;
  1864. if (param == SET_DRVR_VERSION) {
  1865. mbox_cmd[1] = SET_DRVR_VERSION;
  1866. strncpy((char *)&mbox_cmd[2], QLA4XXX_DRIVER_VERSION,
  1867. MAX_DRVR_VER_LEN);
  1868. } else {
  1869. ql4_printk(KERN_ERR, ha, "%s: invalid parameter 0x%x\n",
  1870. __func__, param);
  1871. status = QLA_ERROR;
  1872. goto exit_set_param;
  1873. }
  1874. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, mbox_cmd,
  1875. mbox_sts);
  1876. if (status == QLA_ERROR)
  1877. ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
  1878. __func__, mbox_sts[0]);
  1879. exit_set_param:
  1880. return status;
  1881. }
  1882. /**
  1883. * qla4_83xx_post_idc_ack - post IDC ACK
  1884. * @ha: Pointer to host adapter structure.
  1885. *
  1886. * Posts IDC ACK for IDC Request Notification AEN.
  1887. **/
  1888. int qla4_83xx_post_idc_ack(struct scsi_qla_host *ha)
  1889. {
  1890. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1891. uint32_t mbox_sts[MBOX_REG_COUNT];
  1892. int status;
  1893. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1894. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1895. mbox_cmd[0] = MBOX_CMD_IDC_ACK;
  1896. mbox_cmd[1] = ha->idc_info.request_desc;
  1897. mbox_cmd[2] = ha->idc_info.info1;
  1898. mbox_cmd[3] = ha->idc_info.info2;
  1899. mbox_cmd[4] = ha->idc_info.info3;
  1900. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
  1901. mbox_cmd, mbox_sts);
  1902. if (status == QLA_ERROR)
  1903. ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", __func__,
  1904. mbox_sts[0]);
  1905. else
  1906. ql4_printk(KERN_INFO, ha, "%s: IDC ACK posted\n", __func__);
  1907. return status;
  1908. }
  1909. int qla4_84xx_config_acb(struct scsi_qla_host *ha, int acb_config)
  1910. {
  1911. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1912. uint32_t mbox_sts[MBOX_REG_COUNT];
  1913. struct addr_ctrl_blk *acb = NULL;
  1914. uint32_t acb_len = sizeof(struct addr_ctrl_blk);
  1915. int rval = QLA_SUCCESS;
  1916. dma_addr_t acb_dma;
  1917. acb = dma_alloc_coherent(&ha->pdev->dev,
  1918. sizeof(struct addr_ctrl_blk),
  1919. &acb_dma, GFP_KERNEL);
  1920. if (!acb) {
  1921. ql4_printk(KERN_ERR, ha, "%s: Unable to alloc acb\n", __func__);
  1922. rval = QLA_ERROR;
  1923. goto exit_config_acb;
  1924. }
  1925. memset(acb, 0, acb_len);
  1926. switch (acb_config) {
  1927. case ACB_CONFIG_DISABLE:
  1928. rval = qla4xxx_get_acb(ha, acb_dma, 0, acb_len);
  1929. if (rval != QLA_SUCCESS)
  1930. goto exit_free_acb;
  1931. rval = qla4xxx_disable_acb(ha);
  1932. if (rval != QLA_SUCCESS)
  1933. goto exit_free_acb;
  1934. if (!ha->saved_acb)
  1935. ha->saved_acb = kzalloc(acb_len, GFP_KERNEL);
  1936. if (!ha->saved_acb) {
  1937. ql4_printk(KERN_ERR, ha, "%s: Unable to alloc acb\n",
  1938. __func__);
  1939. rval = QLA_ERROR;
  1940. goto exit_config_acb;
  1941. }
  1942. memcpy(ha->saved_acb, acb, acb_len);
  1943. break;
  1944. case ACB_CONFIG_SET:
  1945. if (!ha->saved_acb) {
  1946. ql4_printk(KERN_ERR, ha, "%s: Can't set ACB, Saved ACB not available\n",
  1947. __func__);
  1948. rval = QLA_ERROR;
  1949. goto exit_free_acb;
  1950. }
  1951. memcpy(acb, ha->saved_acb, acb_len);
  1952. kfree(ha->saved_acb);
  1953. ha->saved_acb = NULL;
  1954. rval = qla4xxx_set_acb(ha, &mbox_cmd[0], &mbox_sts[0], acb_dma);
  1955. if (rval != QLA_SUCCESS)
  1956. goto exit_free_acb;
  1957. break;
  1958. default:
  1959. ql4_printk(KERN_ERR, ha, "%s: Invalid ACB Configuration\n",
  1960. __func__);
  1961. }
  1962. exit_free_acb:
  1963. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk), acb,
  1964. acb_dma);
  1965. exit_config_acb:
  1966. DEBUG2(ql4_printk(KERN_INFO, ha,
  1967. "%s %s\n", __func__,
  1968. rval == QLA_SUCCESS ? "SUCCEEDED" : "FAILED"));
  1969. return rval;
  1970. }