be_main.c 145 KB

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  1. /**
  2. * Copyright (C) 2005 - 2013 Emulex
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
  11. *
  12. * Contact Information:
  13. * linux-drivers@emulex.com
  14. *
  15. * Emulex
  16. * 3333 Susan Street
  17. * Costa Mesa, CA 92626
  18. */
  19. #include <linux/reboot.h>
  20. #include <linux/delay.h>
  21. #include <linux/slab.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/blkdev.h>
  24. #include <linux/pci.h>
  25. #include <linux/string.h>
  26. #include <linux/kernel.h>
  27. #include <linux/semaphore.h>
  28. #include <linux/iscsi_boot_sysfs.h>
  29. #include <linux/module.h>
  30. #include <linux/bsg-lib.h>
  31. #include <scsi/libiscsi.h>
  32. #include <scsi/scsi_bsg_iscsi.h>
  33. #include <scsi/scsi_netlink.h>
  34. #include <scsi/scsi_transport_iscsi.h>
  35. #include <scsi/scsi_transport.h>
  36. #include <scsi/scsi_cmnd.h>
  37. #include <scsi/scsi_device.h>
  38. #include <scsi/scsi_host.h>
  39. #include <scsi/scsi.h>
  40. #include "be_main.h"
  41. #include "be_iscsi.h"
  42. #include "be_mgmt.h"
  43. #include "be_cmds.h"
  44. static unsigned int be_iopoll_budget = 10;
  45. static unsigned int be_max_phys_size = 64;
  46. static unsigned int enable_msix = 1;
  47. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  48. MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
  49. MODULE_VERSION(BUILD_STR);
  50. MODULE_AUTHOR("Emulex Corporation");
  51. MODULE_LICENSE("GPL");
  52. module_param(be_iopoll_budget, int, 0);
  53. module_param(enable_msix, int, 0);
  54. module_param(be_max_phys_size, uint, S_IRUGO);
  55. MODULE_PARM_DESC(be_max_phys_size,
  56. "Maximum Size (In Kilobytes) of physically contiguous "
  57. "memory that can be allocated. Range is 16 - 128");
  58. #define beiscsi_disp_param(_name)\
  59. ssize_t \
  60. beiscsi_##_name##_disp(struct device *dev,\
  61. struct device_attribute *attrib, char *buf) \
  62. { \
  63. struct Scsi_Host *shost = class_to_shost(dev);\
  64. struct beiscsi_hba *phba = iscsi_host_priv(shost); \
  65. uint32_t param_val = 0; \
  66. param_val = phba->attr_##_name;\
  67. return snprintf(buf, PAGE_SIZE, "%d\n",\
  68. phba->attr_##_name);\
  69. }
  70. #define beiscsi_change_param(_name, _minval, _maxval, _defaval)\
  71. int \
  72. beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\
  73. {\
  74. if (val >= _minval && val <= _maxval) {\
  75. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  76. "BA_%d : beiscsi_"#_name" updated "\
  77. "from 0x%x ==> 0x%x\n",\
  78. phba->attr_##_name, val); \
  79. phba->attr_##_name = val;\
  80. return 0;\
  81. } \
  82. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \
  83. "BA_%d beiscsi_"#_name" attribute "\
  84. "cannot be updated to 0x%x, "\
  85. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  86. return -EINVAL;\
  87. }
  88. #define beiscsi_store_param(_name) \
  89. ssize_t \
  90. beiscsi_##_name##_store(struct device *dev,\
  91. struct device_attribute *attr, const char *buf,\
  92. size_t count) \
  93. { \
  94. struct Scsi_Host *shost = class_to_shost(dev);\
  95. struct beiscsi_hba *phba = iscsi_host_priv(shost);\
  96. uint32_t param_val = 0;\
  97. if (!isdigit(buf[0]))\
  98. return -EINVAL;\
  99. if (sscanf(buf, "%i", &param_val) != 1)\
  100. return -EINVAL;\
  101. if (beiscsi_##_name##_change(phba, param_val) == 0) \
  102. return strlen(buf);\
  103. else \
  104. return -EINVAL;\
  105. }
  106. #define beiscsi_init_param(_name, _minval, _maxval, _defval) \
  107. int \
  108. beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \
  109. { \
  110. if (val >= _minval && val <= _maxval) {\
  111. phba->attr_##_name = val;\
  112. return 0;\
  113. } \
  114. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  115. "BA_%d beiscsi_"#_name" attribute " \
  116. "cannot be updated to 0x%x, "\
  117. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  118. phba->attr_##_name = _defval;\
  119. return -EINVAL;\
  120. }
  121. #define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \
  122. static uint beiscsi_##_name = _defval;\
  123. module_param(beiscsi_##_name, uint, S_IRUGO);\
  124. MODULE_PARM_DESC(beiscsi_##_name, _descp);\
  125. beiscsi_disp_param(_name)\
  126. beiscsi_change_param(_name, _minval, _maxval, _defval)\
  127. beiscsi_store_param(_name)\
  128. beiscsi_init_param(_name, _minval, _maxval, _defval)\
  129. DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\
  130. beiscsi_##_name##_disp, beiscsi_##_name##_store)
  131. /*
  132. * When new log level added update the
  133. * the MAX allowed value for log_enable
  134. */
  135. BEISCSI_RW_ATTR(log_enable, 0x00,
  136. 0xFF, 0x00, "Enable logging Bit Mask\n"
  137. "\t\t\t\tInitialization Events : 0x01\n"
  138. "\t\t\t\tMailbox Events : 0x02\n"
  139. "\t\t\t\tMiscellaneous Events : 0x04\n"
  140. "\t\t\t\tError Handling : 0x08\n"
  141. "\t\t\t\tIO Path Events : 0x10\n"
  142. "\t\t\t\tConfiguration Path : 0x20\n");
  143. DEVICE_ATTR(beiscsi_drvr_ver, S_IRUGO, beiscsi_drvr_ver_disp, NULL);
  144. DEVICE_ATTR(beiscsi_adapter_family, S_IRUGO, beiscsi_adap_family_disp, NULL);
  145. DEVICE_ATTR(beiscsi_fw_ver, S_IRUGO, beiscsi_fw_ver_disp, NULL);
  146. DEVICE_ATTR(beiscsi_active_cid_count, S_IRUGO, beiscsi_active_cid_disp, NULL);
  147. struct device_attribute *beiscsi_attrs[] = {
  148. &dev_attr_beiscsi_log_enable,
  149. &dev_attr_beiscsi_drvr_ver,
  150. &dev_attr_beiscsi_adapter_family,
  151. &dev_attr_beiscsi_fw_ver,
  152. &dev_attr_beiscsi_active_cid_count,
  153. NULL,
  154. };
  155. static char const *cqe_desc[] = {
  156. "RESERVED_DESC",
  157. "SOL_CMD_COMPLETE",
  158. "SOL_CMD_KILLED_DATA_DIGEST_ERR",
  159. "CXN_KILLED_PDU_SIZE_EXCEEDS_DSL",
  160. "CXN_KILLED_BURST_LEN_MISMATCH",
  161. "CXN_KILLED_AHS_RCVD",
  162. "CXN_KILLED_HDR_DIGEST_ERR",
  163. "CXN_KILLED_UNKNOWN_HDR",
  164. "CXN_KILLED_STALE_ITT_TTT_RCVD",
  165. "CXN_KILLED_INVALID_ITT_TTT_RCVD",
  166. "CXN_KILLED_RST_RCVD",
  167. "CXN_KILLED_TIMED_OUT",
  168. "CXN_KILLED_RST_SENT",
  169. "CXN_KILLED_FIN_RCVD",
  170. "CXN_KILLED_BAD_UNSOL_PDU_RCVD",
  171. "CXN_KILLED_BAD_WRB_INDEX_ERROR",
  172. "CXN_KILLED_OVER_RUN_RESIDUAL",
  173. "CXN_KILLED_UNDER_RUN_RESIDUAL",
  174. "CMD_KILLED_INVALID_STATSN_RCVD",
  175. "CMD_KILLED_INVALID_R2T_RCVD",
  176. "CMD_CXN_KILLED_LUN_INVALID",
  177. "CMD_CXN_KILLED_ICD_INVALID",
  178. "CMD_CXN_KILLED_ITT_INVALID",
  179. "CMD_CXN_KILLED_SEQ_OUTOFORDER",
  180. "CMD_CXN_KILLED_INVALID_DATASN_RCVD",
  181. "CXN_INVALIDATE_NOTIFY",
  182. "CXN_INVALIDATE_INDEX_NOTIFY",
  183. "CMD_INVALIDATED_NOTIFY",
  184. "UNSOL_HDR_NOTIFY",
  185. "UNSOL_DATA_NOTIFY",
  186. "UNSOL_DATA_DIGEST_ERROR_NOTIFY",
  187. "DRIVERMSG_NOTIFY",
  188. "CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN",
  189. "SOL_CMD_KILLED_DIF_ERR",
  190. "CXN_KILLED_SYN_RCVD",
  191. "CXN_KILLED_IMM_DATA_RCVD"
  192. };
  193. static int beiscsi_slave_configure(struct scsi_device *sdev)
  194. {
  195. blk_queue_max_segment_size(sdev->request_queue, 65536);
  196. return 0;
  197. }
  198. static int beiscsi_eh_abort(struct scsi_cmnd *sc)
  199. {
  200. struct iscsi_cls_session *cls_session;
  201. struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr;
  202. struct beiscsi_io_task *aborted_io_task;
  203. struct iscsi_conn *conn;
  204. struct beiscsi_conn *beiscsi_conn;
  205. struct beiscsi_hba *phba;
  206. struct iscsi_session *session;
  207. struct invalidate_command_table *inv_tbl;
  208. struct be_dma_mem nonemb_cmd;
  209. unsigned int cid, tag, num_invalidate;
  210. cls_session = starget_to_session(scsi_target(sc->device));
  211. session = cls_session->dd_data;
  212. spin_lock_bh(&session->lock);
  213. if (!aborted_task || !aborted_task->sc) {
  214. /* we raced */
  215. spin_unlock_bh(&session->lock);
  216. return SUCCESS;
  217. }
  218. aborted_io_task = aborted_task->dd_data;
  219. if (!aborted_io_task->scsi_cmnd) {
  220. /* raced or invalid command */
  221. spin_unlock_bh(&session->lock);
  222. return SUCCESS;
  223. }
  224. spin_unlock_bh(&session->lock);
  225. conn = aborted_task->conn;
  226. beiscsi_conn = conn->dd_data;
  227. phba = beiscsi_conn->phba;
  228. /* invalidate iocb */
  229. cid = beiscsi_conn->beiscsi_conn_cid;
  230. inv_tbl = phba->inv_tbl;
  231. memset(inv_tbl, 0x0, sizeof(*inv_tbl));
  232. inv_tbl->cid = cid;
  233. inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index;
  234. num_invalidate = 1;
  235. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  236. sizeof(struct invalidate_commands_params_in),
  237. &nonemb_cmd.dma);
  238. if (nonemb_cmd.va == NULL) {
  239. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  240. "BM_%d : Failed to allocate memory for"
  241. "mgmt_invalidate_icds\n");
  242. return FAILED;
  243. }
  244. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  245. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  246. cid, &nonemb_cmd);
  247. if (!tag) {
  248. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  249. "BM_%d : mgmt_invalidate_icds could not be"
  250. "submitted\n");
  251. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  252. nonemb_cmd.va, nonemb_cmd.dma);
  253. return FAILED;
  254. }
  255. beiscsi_mccq_compl(phba, tag, NULL, nonemb_cmd.va);
  256. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  257. nonemb_cmd.va, nonemb_cmd.dma);
  258. return iscsi_eh_abort(sc);
  259. }
  260. static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
  261. {
  262. struct iscsi_task *abrt_task;
  263. struct beiscsi_io_task *abrt_io_task;
  264. struct iscsi_conn *conn;
  265. struct beiscsi_conn *beiscsi_conn;
  266. struct beiscsi_hba *phba;
  267. struct iscsi_session *session;
  268. struct iscsi_cls_session *cls_session;
  269. struct invalidate_command_table *inv_tbl;
  270. struct be_dma_mem nonemb_cmd;
  271. unsigned int cid, tag, i, num_invalidate;
  272. /* invalidate iocbs */
  273. cls_session = starget_to_session(scsi_target(sc->device));
  274. session = cls_session->dd_data;
  275. spin_lock_bh(&session->lock);
  276. if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) {
  277. spin_unlock_bh(&session->lock);
  278. return FAILED;
  279. }
  280. conn = session->leadconn;
  281. beiscsi_conn = conn->dd_data;
  282. phba = beiscsi_conn->phba;
  283. cid = beiscsi_conn->beiscsi_conn_cid;
  284. inv_tbl = phba->inv_tbl;
  285. memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN);
  286. num_invalidate = 0;
  287. for (i = 0; i < conn->session->cmds_max; i++) {
  288. abrt_task = conn->session->cmds[i];
  289. abrt_io_task = abrt_task->dd_data;
  290. if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE)
  291. continue;
  292. if (abrt_task->sc->device->lun != abrt_task->sc->device->lun)
  293. continue;
  294. inv_tbl->cid = cid;
  295. inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index;
  296. num_invalidate++;
  297. inv_tbl++;
  298. }
  299. spin_unlock_bh(&session->lock);
  300. inv_tbl = phba->inv_tbl;
  301. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  302. sizeof(struct invalidate_commands_params_in),
  303. &nonemb_cmd.dma);
  304. if (nonemb_cmd.va == NULL) {
  305. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  306. "BM_%d : Failed to allocate memory for"
  307. "mgmt_invalidate_icds\n");
  308. return FAILED;
  309. }
  310. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  311. memset(nonemb_cmd.va, 0, nonemb_cmd.size);
  312. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  313. cid, &nonemb_cmd);
  314. if (!tag) {
  315. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  316. "BM_%d : mgmt_invalidate_icds could not be"
  317. " submitted\n");
  318. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  319. nonemb_cmd.va, nonemb_cmd.dma);
  320. return FAILED;
  321. }
  322. beiscsi_mccq_compl(phba, tag, NULL, nonemb_cmd.va);
  323. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  324. nonemb_cmd.va, nonemb_cmd.dma);
  325. return iscsi_eh_device_reset(sc);
  326. }
  327. static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
  328. {
  329. struct beiscsi_hba *phba = data;
  330. struct mgmt_session_info *boot_sess = &phba->boot_sess;
  331. struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
  332. char *str = buf;
  333. int rc;
  334. switch (type) {
  335. case ISCSI_BOOT_TGT_NAME:
  336. rc = sprintf(buf, "%.*s\n",
  337. (int)strlen(boot_sess->target_name),
  338. (char *)&boot_sess->target_name);
  339. break;
  340. case ISCSI_BOOT_TGT_IP_ADDR:
  341. if (boot_conn->dest_ipaddr.ip_type == 0x1)
  342. rc = sprintf(buf, "%pI4\n",
  343. (char *)&boot_conn->dest_ipaddr.addr);
  344. else
  345. rc = sprintf(str, "%pI6\n",
  346. (char *)&boot_conn->dest_ipaddr.addr);
  347. break;
  348. case ISCSI_BOOT_TGT_PORT:
  349. rc = sprintf(str, "%d\n", boot_conn->dest_port);
  350. break;
  351. case ISCSI_BOOT_TGT_CHAP_NAME:
  352. rc = sprintf(str, "%.*s\n",
  353. boot_conn->negotiated_login_options.auth_data.chap.
  354. target_chap_name_length,
  355. (char *)&boot_conn->negotiated_login_options.
  356. auth_data.chap.target_chap_name);
  357. break;
  358. case ISCSI_BOOT_TGT_CHAP_SECRET:
  359. rc = sprintf(str, "%.*s\n",
  360. boot_conn->negotiated_login_options.auth_data.chap.
  361. target_secret_length,
  362. (char *)&boot_conn->negotiated_login_options.
  363. auth_data.chap.target_secret);
  364. break;
  365. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  366. rc = sprintf(str, "%.*s\n",
  367. boot_conn->negotiated_login_options.auth_data.chap.
  368. intr_chap_name_length,
  369. (char *)&boot_conn->negotiated_login_options.
  370. auth_data.chap.intr_chap_name);
  371. break;
  372. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  373. rc = sprintf(str, "%.*s\n",
  374. boot_conn->negotiated_login_options.auth_data.chap.
  375. intr_secret_length,
  376. (char *)&boot_conn->negotiated_login_options.
  377. auth_data.chap.intr_secret);
  378. break;
  379. case ISCSI_BOOT_TGT_FLAGS:
  380. rc = sprintf(str, "2\n");
  381. break;
  382. case ISCSI_BOOT_TGT_NIC_ASSOC:
  383. rc = sprintf(str, "0\n");
  384. break;
  385. default:
  386. rc = -ENOSYS;
  387. break;
  388. }
  389. return rc;
  390. }
  391. static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
  392. {
  393. struct beiscsi_hba *phba = data;
  394. char *str = buf;
  395. int rc;
  396. switch (type) {
  397. case ISCSI_BOOT_INI_INITIATOR_NAME:
  398. rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname);
  399. break;
  400. default:
  401. rc = -ENOSYS;
  402. break;
  403. }
  404. return rc;
  405. }
  406. static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
  407. {
  408. struct beiscsi_hba *phba = data;
  409. char *str = buf;
  410. int rc;
  411. switch (type) {
  412. case ISCSI_BOOT_ETH_FLAGS:
  413. rc = sprintf(str, "2\n");
  414. break;
  415. case ISCSI_BOOT_ETH_INDEX:
  416. rc = sprintf(str, "0\n");
  417. break;
  418. case ISCSI_BOOT_ETH_MAC:
  419. rc = beiscsi_get_macaddr(str, phba);
  420. break;
  421. default:
  422. rc = -ENOSYS;
  423. break;
  424. }
  425. return rc;
  426. }
  427. static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
  428. {
  429. umode_t rc;
  430. switch (type) {
  431. case ISCSI_BOOT_TGT_NAME:
  432. case ISCSI_BOOT_TGT_IP_ADDR:
  433. case ISCSI_BOOT_TGT_PORT:
  434. case ISCSI_BOOT_TGT_CHAP_NAME:
  435. case ISCSI_BOOT_TGT_CHAP_SECRET:
  436. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  437. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  438. case ISCSI_BOOT_TGT_NIC_ASSOC:
  439. case ISCSI_BOOT_TGT_FLAGS:
  440. rc = S_IRUGO;
  441. break;
  442. default:
  443. rc = 0;
  444. break;
  445. }
  446. return rc;
  447. }
  448. static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
  449. {
  450. umode_t rc;
  451. switch (type) {
  452. case ISCSI_BOOT_INI_INITIATOR_NAME:
  453. rc = S_IRUGO;
  454. break;
  455. default:
  456. rc = 0;
  457. break;
  458. }
  459. return rc;
  460. }
  461. static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
  462. {
  463. umode_t rc;
  464. switch (type) {
  465. case ISCSI_BOOT_ETH_FLAGS:
  466. case ISCSI_BOOT_ETH_MAC:
  467. case ISCSI_BOOT_ETH_INDEX:
  468. rc = S_IRUGO;
  469. break;
  470. default:
  471. rc = 0;
  472. break;
  473. }
  474. return rc;
  475. }
  476. /*------------------- PCI Driver operations and data ----------------- */
  477. static DEFINE_PCI_DEVICE_TABLE(beiscsi_pci_id_table) = {
  478. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
  479. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
  480. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
  481. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
  482. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
  483. { PCI_DEVICE(ELX_VENDOR_ID, OC_SKH_ID1) },
  484. { 0 }
  485. };
  486. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  487. static struct scsi_host_template beiscsi_sht = {
  488. .module = THIS_MODULE,
  489. .name = "Emulex 10Gbe open-iscsi Initiator Driver",
  490. .proc_name = DRV_NAME,
  491. .queuecommand = iscsi_queuecommand,
  492. .change_queue_depth = iscsi_change_queue_depth,
  493. .slave_configure = beiscsi_slave_configure,
  494. .target_alloc = iscsi_target_alloc,
  495. .eh_abort_handler = beiscsi_eh_abort,
  496. .eh_device_reset_handler = beiscsi_eh_device_reset,
  497. .eh_target_reset_handler = iscsi_eh_session_reset,
  498. .shost_attrs = beiscsi_attrs,
  499. .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
  500. .can_queue = BE2_IO_DEPTH,
  501. .this_id = -1,
  502. .max_sectors = BEISCSI_MAX_SECTORS,
  503. .cmd_per_lun = BEISCSI_CMD_PER_LUN,
  504. .use_clustering = ENABLE_CLUSTERING,
  505. .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID,
  506. };
  507. static struct scsi_transport_template *beiscsi_scsi_transport;
  508. static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
  509. {
  510. struct beiscsi_hba *phba;
  511. struct Scsi_Host *shost;
  512. shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
  513. if (!shost) {
  514. dev_err(&pcidev->dev,
  515. "beiscsi_hba_alloc - iscsi_host_alloc failed\n");
  516. return NULL;
  517. }
  518. shost->dma_boundary = pcidev->dma_mask;
  519. shost->max_id = BE2_MAX_SESSIONS;
  520. shost->max_channel = 0;
  521. shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
  522. shost->max_lun = BEISCSI_NUM_MAX_LUN;
  523. shost->transportt = beiscsi_scsi_transport;
  524. phba = iscsi_host_priv(shost);
  525. memset(phba, 0, sizeof(*phba));
  526. phba->shost = shost;
  527. phba->pcidev = pci_dev_get(pcidev);
  528. pci_set_drvdata(pcidev, phba);
  529. phba->interface_handle = 0xFFFFFFFF;
  530. if (iscsi_host_add(shost, &phba->pcidev->dev))
  531. goto free_devices;
  532. return phba;
  533. free_devices:
  534. pci_dev_put(phba->pcidev);
  535. iscsi_host_free(phba->shost);
  536. return NULL;
  537. }
  538. static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
  539. {
  540. if (phba->csr_va) {
  541. iounmap(phba->csr_va);
  542. phba->csr_va = NULL;
  543. }
  544. if (phba->db_va) {
  545. iounmap(phba->db_va);
  546. phba->db_va = NULL;
  547. }
  548. if (phba->pci_va) {
  549. iounmap(phba->pci_va);
  550. phba->pci_va = NULL;
  551. }
  552. }
  553. static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
  554. struct pci_dev *pcidev)
  555. {
  556. u8 __iomem *addr;
  557. int pcicfg_reg;
  558. addr = ioremap_nocache(pci_resource_start(pcidev, 2),
  559. pci_resource_len(pcidev, 2));
  560. if (addr == NULL)
  561. return -ENOMEM;
  562. phba->ctrl.csr = addr;
  563. phba->csr_va = addr;
  564. phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
  565. addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
  566. if (addr == NULL)
  567. goto pci_map_err;
  568. phba->ctrl.db = addr;
  569. phba->db_va = addr;
  570. phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
  571. if (phba->generation == BE_GEN2)
  572. pcicfg_reg = 1;
  573. else
  574. pcicfg_reg = 0;
  575. addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
  576. pci_resource_len(pcidev, pcicfg_reg));
  577. if (addr == NULL)
  578. goto pci_map_err;
  579. phba->ctrl.pcicfg = addr;
  580. phba->pci_va = addr;
  581. phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
  582. return 0;
  583. pci_map_err:
  584. beiscsi_unmap_pci_function(phba);
  585. return -ENOMEM;
  586. }
  587. static int beiscsi_enable_pci(struct pci_dev *pcidev)
  588. {
  589. int ret;
  590. ret = pci_enable_device(pcidev);
  591. if (ret) {
  592. dev_err(&pcidev->dev,
  593. "beiscsi_enable_pci - enable device failed\n");
  594. return ret;
  595. }
  596. pci_set_master(pcidev);
  597. if (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64))) {
  598. ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
  599. if (ret) {
  600. dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
  601. pci_disable_device(pcidev);
  602. return ret;
  603. }
  604. }
  605. return 0;
  606. }
  607. static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
  608. {
  609. struct be_ctrl_info *ctrl = &phba->ctrl;
  610. struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
  611. struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
  612. int status = 0;
  613. ctrl->pdev = pdev;
  614. status = beiscsi_map_pci_bars(phba, pdev);
  615. if (status)
  616. return status;
  617. mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
  618. mbox_mem_alloc->va = pci_alloc_consistent(pdev,
  619. mbox_mem_alloc->size,
  620. &mbox_mem_alloc->dma);
  621. if (!mbox_mem_alloc->va) {
  622. beiscsi_unmap_pci_function(phba);
  623. return -ENOMEM;
  624. }
  625. mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
  626. mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
  627. mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
  628. memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
  629. spin_lock_init(&ctrl->mbox_lock);
  630. spin_lock_init(&phba->ctrl.mcc_lock);
  631. spin_lock_init(&phba->ctrl.mcc_cq_lock);
  632. return status;
  633. }
  634. static void beiscsi_get_params(struct beiscsi_hba *phba)
  635. {
  636. phba->params.ios_per_ctrl = (phba->fw_config.iscsi_icd_count
  637. - (phba->fw_config.iscsi_cid_count
  638. + BE2_TMFS
  639. + BE2_NOPOUT_REQ));
  640. phba->params.cxns_per_ctrl = phba->fw_config.iscsi_cid_count;
  641. phba->params.asyncpdus_per_ctrl = phba->fw_config.iscsi_cid_count;
  642. phba->params.icds_per_ctrl = phba->fw_config.iscsi_icd_count;
  643. phba->params.num_sge_per_io = BE2_SGE;
  644. phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
  645. phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
  646. phba->params.eq_timer = 64;
  647. phba->params.num_eq_entries =
  648. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  649. + BE2_TMFS) / 512) + 1) * 512;
  650. phba->params.num_eq_entries = (phba->params.num_eq_entries < 1024)
  651. ? 1024 : phba->params.num_eq_entries;
  652. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  653. "BM_%d : phba->params.num_eq_entries=%d\n",
  654. phba->params.num_eq_entries);
  655. phba->params.num_cq_entries =
  656. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  657. + BE2_TMFS) / 512) + 1) * 512;
  658. phba->params.wrbs_per_cxn = 256;
  659. }
  660. static void hwi_ring_eq_db(struct beiscsi_hba *phba,
  661. unsigned int id, unsigned int clr_interrupt,
  662. unsigned int num_processed,
  663. unsigned char rearm, unsigned char event)
  664. {
  665. u32 val = 0;
  666. val |= id & DB_EQ_RING_ID_MASK;
  667. if (rearm)
  668. val |= 1 << DB_EQ_REARM_SHIFT;
  669. if (clr_interrupt)
  670. val |= 1 << DB_EQ_CLR_SHIFT;
  671. if (event)
  672. val |= 1 << DB_EQ_EVNT_SHIFT;
  673. val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
  674. iowrite32(val, phba->db_va + DB_EQ_OFFSET);
  675. }
  676. /**
  677. * be_isr_mcc - The isr routine of the driver.
  678. * @irq: Not used
  679. * @dev_id: Pointer to host adapter structure
  680. */
  681. static irqreturn_t be_isr_mcc(int irq, void *dev_id)
  682. {
  683. struct beiscsi_hba *phba;
  684. struct be_eq_entry *eqe = NULL;
  685. struct be_queue_info *eq;
  686. struct be_queue_info *mcc;
  687. unsigned int num_eq_processed;
  688. struct be_eq_obj *pbe_eq;
  689. unsigned long flags;
  690. pbe_eq = dev_id;
  691. eq = &pbe_eq->q;
  692. phba = pbe_eq->phba;
  693. mcc = &phba->ctrl.mcc_obj.cq;
  694. eqe = queue_tail_node(eq);
  695. num_eq_processed = 0;
  696. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  697. & EQE_VALID_MASK) {
  698. if (((eqe->dw[offsetof(struct amap_eq_entry,
  699. resource_id) / 32] &
  700. EQE_RESID_MASK) >> 16) == mcc->id) {
  701. spin_lock_irqsave(&phba->isr_lock, flags);
  702. pbe_eq->todo_mcc_cq = true;
  703. spin_unlock_irqrestore(&phba->isr_lock, flags);
  704. }
  705. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  706. queue_tail_inc(eq);
  707. eqe = queue_tail_node(eq);
  708. num_eq_processed++;
  709. }
  710. if (pbe_eq->todo_mcc_cq)
  711. queue_work(phba->wq, &pbe_eq->work_cqs);
  712. if (num_eq_processed)
  713. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
  714. return IRQ_HANDLED;
  715. }
  716. /**
  717. * be_isr_msix - The isr routine of the driver.
  718. * @irq: Not used
  719. * @dev_id: Pointer to host adapter structure
  720. */
  721. static irqreturn_t be_isr_msix(int irq, void *dev_id)
  722. {
  723. struct beiscsi_hba *phba;
  724. struct be_eq_entry *eqe = NULL;
  725. struct be_queue_info *eq;
  726. struct be_queue_info *cq;
  727. unsigned int num_eq_processed;
  728. struct be_eq_obj *pbe_eq;
  729. unsigned long flags;
  730. pbe_eq = dev_id;
  731. eq = &pbe_eq->q;
  732. cq = pbe_eq->cq;
  733. eqe = queue_tail_node(eq);
  734. phba = pbe_eq->phba;
  735. num_eq_processed = 0;
  736. if (blk_iopoll_enabled) {
  737. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  738. & EQE_VALID_MASK) {
  739. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  740. blk_iopoll_sched(&pbe_eq->iopoll);
  741. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  742. queue_tail_inc(eq);
  743. eqe = queue_tail_node(eq);
  744. num_eq_processed++;
  745. }
  746. } else {
  747. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  748. & EQE_VALID_MASK) {
  749. spin_lock_irqsave(&phba->isr_lock, flags);
  750. pbe_eq->todo_cq = true;
  751. spin_unlock_irqrestore(&phba->isr_lock, flags);
  752. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  753. queue_tail_inc(eq);
  754. eqe = queue_tail_node(eq);
  755. num_eq_processed++;
  756. }
  757. if (pbe_eq->todo_cq)
  758. queue_work(phba->wq, &pbe_eq->work_cqs);
  759. }
  760. if (num_eq_processed)
  761. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1);
  762. return IRQ_HANDLED;
  763. }
  764. /**
  765. * be_isr - The isr routine of the driver.
  766. * @irq: Not used
  767. * @dev_id: Pointer to host adapter structure
  768. */
  769. static irqreturn_t be_isr(int irq, void *dev_id)
  770. {
  771. struct beiscsi_hba *phba;
  772. struct hwi_controller *phwi_ctrlr;
  773. struct hwi_context_memory *phwi_context;
  774. struct be_eq_entry *eqe = NULL;
  775. struct be_queue_info *eq;
  776. struct be_queue_info *cq;
  777. struct be_queue_info *mcc;
  778. unsigned long flags, index;
  779. unsigned int num_mcceq_processed, num_ioeq_processed;
  780. struct be_ctrl_info *ctrl;
  781. struct be_eq_obj *pbe_eq;
  782. int isr;
  783. phba = dev_id;
  784. ctrl = &phba->ctrl;
  785. isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
  786. (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
  787. if (!isr)
  788. return IRQ_NONE;
  789. phwi_ctrlr = phba->phwi_ctrlr;
  790. phwi_context = phwi_ctrlr->phwi_ctxt;
  791. pbe_eq = &phwi_context->be_eq[0];
  792. eq = &phwi_context->be_eq[0].q;
  793. mcc = &phba->ctrl.mcc_obj.cq;
  794. index = 0;
  795. eqe = queue_tail_node(eq);
  796. num_ioeq_processed = 0;
  797. num_mcceq_processed = 0;
  798. if (blk_iopoll_enabled) {
  799. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  800. & EQE_VALID_MASK) {
  801. if (((eqe->dw[offsetof(struct amap_eq_entry,
  802. resource_id) / 32] &
  803. EQE_RESID_MASK) >> 16) == mcc->id) {
  804. spin_lock_irqsave(&phba->isr_lock, flags);
  805. pbe_eq->todo_mcc_cq = true;
  806. spin_unlock_irqrestore(&phba->isr_lock, flags);
  807. num_mcceq_processed++;
  808. } else {
  809. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  810. blk_iopoll_sched(&pbe_eq->iopoll);
  811. num_ioeq_processed++;
  812. }
  813. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  814. queue_tail_inc(eq);
  815. eqe = queue_tail_node(eq);
  816. }
  817. if (num_ioeq_processed || num_mcceq_processed) {
  818. if (pbe_eq->todo_mcc_cq)
  819. queue_work(phba->wq, &pbe_eq->work_cqs);
  820. if ((num_mcceq_processed) && (!num_ioeq_processed))
  821. hwi_ring_eq_db(phba, eq->id, 0,
  822. (num_ioeq_processed +
  823. num_mcceq_processed) , 1, 1);
  824. else
  825. hwi_ring_eq_db(phba, eq->id, 0,
  826. (num_ioeq_processed +
  827. num_mcceq_processed), 0, 1);
  828. return IRQ_HANDLED;
  829. } else
  830. return IRQ_NONE;
  831. } else {
  832. cq = &phwi_context->be_cq[0];
  833. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  834. & EQE_VALID_MASK) {
  835. if (((eqe->dw[offsetof(struct amap_eq_entry,
  836. resource_id) / 32] &
  837. EQE_RESID_MASK) >> 16) != cq->id) {
  838. spin_lock_irqsave(&phba->isr_lock, flags);
  839. pbe_eq->todo_mcc_cq = true;
  840. spin_unlock_irqrestore(&phba->isr_lock, flags);
  841. } else {
  842. spin_lock_irqsave(&phba->isr_lock, flags);
  843. pbe_eq->todo_cq = true;
  844. spin_unlock_irqrestore(&phba->isr_lock, flags);
  845. }
  846. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  847. queue_tail_inc(eq);
  848. eqe = queue_tail_node(eq);
  849. num_ioeq_processed++;
  850. }
  851. if (pbe_eq->todo_cq || pbe_eq->todo_mcc_cq)
  852. queue_work(phba->wq, &pbe_eq->work_cqs);
  853. if (num_ioeq_processed) {
  854. hwi_ring_eq_db(phba, eq->id, 0,
  855. num_ioeq_processed, 1, 1);
  856. return IRQ_HANDLED;
  857. } else
  858. return IRQ_NONE;
  859. }
  860. }
  861. static int beiscsi_init_irqs(struct beiscsi_hba *phba)
  862. {
  863. struct pci_dev *pcidev = phba->pcidev;
  864. struct hwi_controller *phwi_ctrlr;
  865. struct hwi_context_memory *phwi_context;
  866. int ret, msix_vec, i, j;
  867. phwi_ctrlr = phba->phwi_ctrlr;
  868. phwi_context = phwi_ctrlr->phwi_ctxt;
  869. if (phba->msix_enabled) {
  870. for (i = 0; i < phba->num_cpus; i++) {
  871. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
  872. GFP_KERNEL);
  873. if (!phba->msi_name[i]) {
  874. ret = -ENOMEM;
  875. goto free_msix_irqs;
  876. }
  877. sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
  878. phba->shost->host_no, i);
  879. msix_vec = phba->msix_entries[i].vector;
  880. ret = request_irq(msix_vec, be_isr_msix, 0,
  881. phba->msi_name[i],
  882. &phwi_context->be_eq[i]);
  883. if (ret) {
  884. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  885. "BM_%d : beiscsi_init_irqs-Failed to"
  886. "register msix for i = %d\n",
  887. i);
  888. kfree(phba->msi_name[i]);
  889. goto free_msix_irqs;
  890. }
  891. }
  892. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
  893. if (!phba->msi_name[i]) {
  894. ret = -ENOMEM;
  895. goto free_msix_irqs;
  896. }
  897. sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
  898. phba->shost->host_no);
  899. msix_vec = phba->msix_entries[i].vector;
  900. ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
  901. &phwi_context->be_eq[i]);
  902. if (ret) {
  903. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT ,
  904. "BM_%d : beiscsi_init_irqs-"
  905. "Failed to register beiscsi_msix_mcc\n");
  906. kfree(phba->msi_name[i]);
  907. goto free_msix_irqs;
  908. }
  909. } else {
  910. ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
  911. "beiscsi", phba);
  912. if (ret) {
  913. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  914. "BM_%d : beiscsi_init_irqs-"
  915. "Failed to register irq\\n");
  916. return ret;
  917. }
  918. }
  919. return 0;
  920. free_msix_irqs:
  921. for (j = i - 1; j >= 0; j--) {
  922. kfree(phba->msi_name[j]);
  923. msix_vec = phba->msix_entries[j].vector;
  924. free_irq(msix_vec, &phwi_context->be_eq[j]);
  925. }
  926. return ret;
  927. }
  928. static void hwi_ring_cq_db(struct beiscsi_hba *phba,
  929. unsigned int id, unsigned int num_processed,
  930. unsigned char rearm, unsigned char event)
  931. {
  932. u32 val = 0;
  933. val |= id & DB_CQ_RING_ID_MASK;
  934. if (rearm)
  935. val |= 1 << DB_CQ_REARM_SHIFT;
  936. val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
  937. iowrite32(val, phba->db_va + DB_CQ_OFFSET);
  938. }
  939. static unsigned int
  940. beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn,
  941. struct beiscsi_hba *phba,
  942. struct pdu_base *ppdu,
  943. unsigned long pdu_len,
  944. void *pbuffer, unsigned long buf_len)
  945. {
  946. struct iscsi_conn *conn = beiscsi_conn->conn;
  947. struct iscsi_session *session = conn->session;
  948. struct iscsi_task *task;
  949. struct beiscsi_io_task *io_task;
  950. struct iscsi_hdr *login_hdr;
  951. switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] &
  952. PDUBASE_OPCODE_MASK) {
  953. case ISCSI_OP_NOOP_IN:
  954. pbuffer = NULL;
  955. buf_len = 0;
  956. break;
  957. case ISCSI_OP_ASYNC_EVENT:
  958. break;
  959. case ISCSI_OP_REJECT:
  960. WARN_ON(!pbuffer);
  961. WARN_ON(!(buf_len == 48));
  962. beiscsi_log(phba, KERN_ERR,
  963. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  964. "BM_%d : In ISCSI_OP_REJECT\n");
  965. break;
  966. case ISCSI_OP_LOGIN_RSP:
  967. case ISCSI_OP_TEXT_RSP:
  968. task = conn->login_task;
  969. io_task = task->dd_data;
  970. login_hdr = (struct iscsi_hdr *)ppdu;
  971. login_hdr->itt = io_task->libiscsi_itt;
  972. break;
  973. default:
  974. beiscsi_log(phba, KERN_WARNING,
  975. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  976. "BM_%d : Unrecognized opcode 0x%x in async msg\n",
  977. (ppdu->
  978. dw[offsetof(struct amap_pdu_base, opcode) / 32]
  979. & PDUBASE_OPCODE_MASK));
  980. return 1;
  981. }
  982. spin_lock_bh(&session->lock);
  983. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len);
  984. spin_unlock_bh(&session->lock);
  985. return 0;
  986. }
  987. static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
  988. {
  989. struct sgl_handle *psgl_handle;
  990. if (phba->io_sgl_hndl_avbl) {
  991. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  992. "BM_%d : In alloc_io_sgl_handle,"
  993. " io_sgl_alloc_index=%d\n",
  994. phba->io_sgl_alloc_index);
  995. psgl_handle = phba->io_sgl_hndl_base[phba->
  996. io_sgl_alloc_index];
  997. phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
  998. phba->io_sgl_hndl_avbl--;
  999. if (phba->io_sgl_alloc_index == (phba->params.
  1000. ios_per_ctrl - 1))
  1001. phba->io_sgl_alloc_index = 0;
  1002. else
  1003. phba->io_sgl_alloc_index++;
  1004. } else
  1005. psgl_handle = NULL;
  1006. return psgl_handle;
  1007. }
  1008. static void
  1009. free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1010. {
  1011. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1012. "BM_%d : In free_,io_sgl_free_index=%d\n",
  1013. phba->io_sgl_free_index);
  1014. if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
  1015. /*
  1016. * this can happen if clean_task is called on a task that
  1017. * failed in xmit_task or alloc_pdu.
  1018. */
  1019. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1020. "BM_%d : Double Free in IO SGL io_sgl_free_index=%d,"
  1021. "value there=%p\n", phba->io_sgl_free_index,
  1022. phba->io_sgl_hndl_base
  1023. [phba->io_sgl_free_index]);
  1024. return;
  1025. }
  1026. phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
  1027. phba->io_sgl_hndl_avbl++;
  1028. if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
  1029. phba->io_sgl_free_index = 0;
  1030. else
  1031. phba->io_sgl_free_index++;
  1032. }
  1033. /**
  1034. * alloc_wrb_handle - To allocate a wrb handle
  1035. * @phba: The hba pointer
  1036. * @cid: The cid to use for allocation
  1037. *
  1038. * This happens under session_lock until submission to chip
  1039. */
  1040. struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid)
  1041. {
  1042. struct hwi_wrb_context *pwrb_context;
  1043. struct hwi_controller *phwi_ctrlr;
  1044. struct wrb_handle *pwrb_handle, *pwrb_handle_tmp;
  1045. uint16_t cri_index = BE_GET_CRI_FROM_CID(cid);
  1046. phwi_ctrlr = phba->phwi_ctrlr;
  1047. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  1048. if (pwrb_context->wrb_handles_available >= 2) {
  1049. pwrb_handle = pwrb_context->pwrb_handle_base[
  1050. pwrb_context->alloc_index];
  1051. pwrb_context->wrb_handles_available--;
  1052. if (pwrb_context->alloc_index ==
  1053. (phba->params.wrbs_per_cxn - 1))
  1054. pwrb_context->alloc_index = 0;
  1055. else
  1056. pwrb_context->alloc_index++;
  1057. pwrb_handle_tmp = pwrb_context->pwrb_handle_base[
  1058. pwrb_context->alloc_index];
  1059. pwrb_handle->nxt_wrb_index = pwrb_handle_tmp->wrb_index;
  1060. } else
  1061. pwrb_handle = NULL;
  1062. return pwrb_handle;
  1063. }
  1064. /**
  1065. * free_wrb_handle - To free the wrb handle back to pool
  1066. * @phba: The hba pointer
  1067. * @pwrb_context: The context to free from
  1068. * @pwrb_handle: The wrb_handle to free
  1069. *
  1070. * This happens under session_lock until submission to chip
  1071. */
  1072. static void
  1073. free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
  1074. struct wrb_handle *pwrb_handle)
  1075. {
  1076. pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
  1077. pwrb_context->wrb_handles_available++;
  1078. if (pwrb_context->free_index == (phba->params.wrbs_per_cxn - 1))
  1079. pwrb_context->free_index = 0;
  1080. else
  1081. pwrb_context->free_index++;
  1082. beiscsi_log(phba, KERN_INFO,
  1083. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1084. "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x"
  1085. "wrb_handles_available=%d\n",
  1086. pwrb_handle, pwrb_context->free_index,
  1087. pwrb_context->wrb_handles_available);
  1088. }
  1089. static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
  1090. {
  1091. struct sgl_handle *psgl_handle;
  1092. if (phba->eh_sgl_hndl_avbl) {
  1093. psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
  1094. phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
  1095. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1096. "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n",
  1097. phba->eh_sgl_alloc_index,
  1098. phba->eh_sgl_alloc_index);
  1099. phba->eh_sgl_hndl_avbl--;
  1100. if (phba->eh_sgl_alloc_index ==
  1101. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
  1102. 1))
  1103. phba->eh_sgl_alloc_index = 0;
  1104. else
  1105. phba->eh_sgl_alloc_index++;
  1106. } else
  1107. psgl_handle = NULL;
  1108. return psgl_handle;
  1109. }
  1110. void
  1111. free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1112. {
  1113. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1114. "BM_%d : In free_mgmt_sgl_handle,"
  1115. "eh_sgl_free_index=%d\n",
  1116. phba->eh_sgl_free_index);
  1117. if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
  1118. /*
  1119. * this can happen if clean_task is called on a task that
  1120. * failed in xmit_task or alloc_pdu.
  1121. */
  1122. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG,
  1123. "BM_%d : Double Free in eh SGL ,"
  1124. "eh_sgl_free_index=%d\n",
  1125. phba->eh_sgl_free_index);
  1126. return;
  1127. }
  1128. phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
  1129. phba->eh_sgl_hndl_avbl++;
  1130. if (phba->eh_sgl_free_index ==
  1131. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
  1132. phba->eh_sgl_free_index = 0;
  1133. else
  1134. phba->eh_sgl_free_index++;
  1135. }
  1136. static void
  1137. be_complete_io(struct beiscsi_conn *beiscsi_conn,
  1138. struct iscsi_task *task,
  1139. struct common_sol_cqe *csol_cqe)
  1140. {
  1141. struct beiscsi_io_task *io_task = task->dd_data;
  1142. struct be_status_bhs *sts_bhs =
  1143. (struct be_status_bhs *)io_task->cmd_bhs;
  1144. struct iscsi_conn *conn = beiscsi_conn->conn;
  1145. unsigned char *sense;
  1146. u32 resid = 0, exp_cmdsn, max_cmdsn;
  1147. u8 rsp, status, flags;
  1148. exp_cmdsn = csol_cqe->exp_cmdsn;
  1149. max_cmdsn = (csol_cqe->exp_cmdsn +
  1150. csol_cqe->cmd_wnd - 1);
  1151. rsp = csol_cqe->i_resp;
  1152. status = csol_cqe->i_sts;
  1153. flags = csol_cqe->i_flags;
  1154. resid = csol_cqe->res_cnt;
  1155. if (!task->sc) {
  1156. if (io_task->scsi_cmnd)
  1157. scsi_dma_unmap(io_task->scsi_cmnd);
  1158. return;
  1159. }
  1160. task->sc->result = (DID_OK << 16) | status;
  1161. if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
  1162. task->sc->result = DID_ERROR << 16;
  1163. goto unmap;
  1164. }
  1165. /* bidi not initially supported */
  1166. if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
  1167. if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
  1168. task->sc->result = DID_ERROR << 16;
  1169. if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
  1170. scsi_set_resid(task->sc, resid);
  1171. if (!status && (scsi_bufflen(task->sc) - resid <
  1172. task->sc->underflow))
  1173. task->sc->result = DID_ERROR << 16;
  1174. }
  1175. }
  1176. if (status == SAM_STAT_CHECK_CONDITION) {
  1177. u16 sense_len;
  1178. unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
  1179. sense = sts_bhs->sense_info + sizeof(unsigned short);
  1180. sense_len = be16_to_cpu(*slen);
  1181. memcpy(task->sc->sense_buffer, sense,
  1182. min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
  1183. }
  1184. if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ)
  1185. conn->rxdata_octets += resid;
  1186. unmap:
  1187. scsi_dma_unmap(io_task->scsi_cmnd);
  1188. iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
  1189. }
  1190. static void
  1191. be_complete_logout(struct beiscsi_conn *beiscsi_conn,
  1192. struct iscsi_task *task,
  1193. struct common_sol_cqe *csol_cqe)
  1194. {
  1195. struct iscsi_logout_rsp *hdr;
  1196. struct beiscsi_io_task *io_task = task->dd_data;
  1197. struct iscsi_conn *conn = beiscsi_conn->conn;
  1198. hdr = (struct iscsi_logout_rsp *)task->hdr;
  1199. hdr->opcode = ISCSI_OP_LOGOUT_RSP;
  1200. hdr->t2wait = 5;
  1201. hdr->t2retain = 0;
  1202. hdr->flags = csol_cqe->i_flags;
  1203. hdr->response = csol_cqe->i_resp;
  1204. hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
  1205. hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
  1206. csol_cqe->cmd_wnd - 1);
  1207. hdr->dlength[0] = 0;
  1208. hdr->dlength[1] = 0;
  1209. hdr->dlength[2] = 0;
  1210. hdr->hlength = 0;
  1211. hdr->itt = io_task->libiscsi_itt;
  1212. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1213. }
  1214. static void
  1215. be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
  1216. struct iscsi_task *task,
  1217. struct common_sol_cqe *csol_cqe)
  1218. {
  1219. struct iscsi_tm_rsp *hdr;
  1220. struct iscsi_conn *conn = beiscsi_conn->conn;
  1221. struct beiscsi_io_task *io_task = task->dd_data;
  1222. hdr = (struct iscsi_tm_rsp *)task->hdr;
  1223. hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
  1224. hdr->flags = csol_cqe->i_flags;
  1225. hdr->response = csol_cqe->i_resp;
  1226. hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
  1227. hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
  1228. csol_cqe->cmd_wnd - 1);
  1229. hdr->itt = io_task->libiscsi_itt;
  1230. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1231. }
  1232. static void
  1233. hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
  1234. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1235. {
  1236. struct hwi_wrb_context *pwrb_context;
  1237. struct wrb_handle *pwrb_handle = NULL;
  1238. struct hwi_controller *phwi_ctrlr;
  1239. struct iscsi_task *task;
  1240. struct beiscsi_io_task *io_task;
  1241. uint16_t wrb_index, cid, cri_index;
  1242. phwi_ctrlr = phba->phwi_ctrlr;
  1243. if (is_chip_be2_be3r(phba)) {
  1244. wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
  1245. wrb_idx, psol);
  1246. cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
  1247. cid, psol);
  1248. } else {
  1249. wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
  1250. wrb_idx, psol);
  1251. cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
  1252. cid, psol);
  1253. }
  1254. cri_index = BE_GET_CRI_FROM_CID(cid);
  1255. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  1256. pwrb_handle = pwrb_context->pwrb_handle_basestd[wrb_index];
  1257. task = pwrb_handle->pio_handle;
  1258. io_task = task->dd_data;
  1259. memset(io_task->pwrb_handle->pwrb, 0, sizeof(struct iscsi_wrb));
  1260. iscsi_put_task(task);
  1261. }
  1262. static void
  1263. be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
  1264. struct iscsi_task *task,
  1265. struct common_sol_cqe *csol_cqe)
  1266. {
  1267. struct iscsi_nopin *hdr;
  1268. struct iscsi_conn *conn = beiscsi_conn->conn;
  1269. struct beiscsi_io_task *io_task = task->dd_data;
  1270. hdr = (struct iscsi_nopin *)task->hdr;
  1271. hdr->flags = csol_cqe->i_flags;
  1272. hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
  1273. hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
  1274. csol_cqe->cmd_wnd - 1);
  1275. hdr->opcode = ISCSI_OP_NOOP_IN;
  1276. hdr->itt = io_task->libiscsi_itt;
  1277. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1278. }
  1279. static void adapter_get_sol_cqe(struct beiscsi_hba *phba,
  1280. struct sol_cqe *psol,
  1281. struct common_sol_cqe *csol_cqe)
  1282. {
  1283. if (is_chip_be2_be3r(phba)) {
  1284. csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe,
  1285. i_exp_cmd_sn, psol);
  1286. csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe,
  1287. i_res_cnt, psol);
  1288. csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe,
  1289. i_cmd_wnd, psol);
  1290. csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe,
  1291. wrb_index, psol);
  1292. csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe,
  1293. cid, psol);
  1294. csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe,
  1295. hw_sts, psol);
  1296. csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe,
  1297. i_resp, psol);
  1298. csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe,
  1299. i_sts, psol);
  1300. csol_cqe->i_flags = AMAP_GET_BITS(struct amap_sol_cqe,
  1301. i_flags, psol);
  1302. } else {
  1303. csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1304. i_exp_cmd_sn, psol);
  1305. csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1306. i_res_cnt, psol);
  1307. csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1308. wrb_index, psol);
  1309. csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1310. cid, psol);
  1311. csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1312. hw_sts, psol);
  1313. csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1314. i_cmd_wnd, psol);
  1315. if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1316. cmd_cmpl, psol))
  1317. csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1318. i_sts, psol);
  1319. else
  1320. csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1321. i_sts, psol);
  1322. if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1323. u, psol))
  1324. csol_cqe->i_flags = ISCSI_FLAG_CMD_UNDERFLOW;
  1325. if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1326. o, psol))
  1327. csol_cqe->i_flags |= ISCSI_FLAG_CMD_OVERFLOW;
  1328. }
  1329. }
  1330. static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
  1331. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1332. {
  1333. struct hwi_wrb_context *pwrb_context;
  1334. struct wrb_handle *pwrb_handle;
  1335. struct iscsi_wrb *pwrb = NULL;
  1336. struct hwi_controller *phwi_ctrlr;
  1337. struct iscsi_task *task;
  1338. unsigned int type;
  1339. struct iscsi_conn *conn = beiscsi_conn->conn;
  1340. struct iscsi_session *session = conn->session;
  1341. struct common_sol_cqe csol_cqe = {0};
  1342. uint16_t cri_index = 0;
  1343. phwi_ctrlr = phba->phwi_ctrlr;
  1344. /* Copy the elements to a common structure */
  1345. adapter_get_sol_cqe(phba, psol, &csol_cqe);
  1346. cri_index = BE_GET_CRI_FROM_CID(csol_cqe.cid);
  1347. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  1348. pwrb_handle = pwrb_context->pwrb_handle_basestd[
  1349. csol_cqe.wrb_index];
  1350. task = pwrb_handle->pio_handle;
  1351. pwrb = pwrb_handle->pwrb;
  1352. type = ((struct beiscsi_io_task *)task->dd_data)->wrb_type;
  1353. spin_lock_bh(&session->lock);
  1354. switch (type) {
  1355. case HWH_TYPE_IO:
  1356. case HWH_TYPE_IO_RD:
  1357. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
  1358. ISCSI_OP_NOOP_OUT)
  1359. be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
  1360. else
  1361. be_complete_io(beiscsi_conn, task, &csol_cqe);
  1362. break;
  1363. case HWH_TYPE_LOGOUT:
  1364. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
  1365. be_complete_logout(beiscsi_conn, task, &csol_cqe);
  1366. else
  1367. be_complete_tmf(beiscsi_conn, task, &csol_cqe);
  1368. break;
  1369. case HWH_TYPE_LOGIN:
  1370. beiscsi_log(phba, KERN_ERR,
  1371. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1372. "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in"
  1373. " hwi_complete_cmd- Solicited path\n");
  1374. break;
  1375. case HWH_TYPE_NOP:
  1376. be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
  1377. break;
  1378. default:
  1379. beiscsi_log(phba, KERN_WARNING,
  1380. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1381. "BM_%d : In hwi_complete_cmd, unknown type = %d"
  1382. "wrb_index 0x%x CID 0x%x\n", type,
  1383. csol_cqe.wrb_index,
  1384. csol_cqe.cid);
  1385. break;
  1386. }
  1387. spin_unlock_bh(&session->lock);
  1388. }
  1389. static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context
  1390. *pasync_ctx, unsigned int is_header,
  1391. unsigned int host_write_ptr)
  1392. {
  1393. if (is_header)
  1394. return &pasync_ctx->async_entry[host_write_ptr].
  1395. header_busy_list;
  1396. else
  1397. return &pasync_ctx->async_entry[host_write_ptr].data_busy_list;
  1398. }
  1399. static struct async_pdu_handle *
  1400. hwi_get_async_handle(struct beiscsi_hba *phba,
  1401. struct beiscsi_conn *beiscsi_conn,
  1402. struct hwi_async_pdu_context *pasync_ctx,
  1403. struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index)
  1404. {
  1405. struct be_bus_address phys_addr;
  1406. struct list_head *pbusy_list;
  1407. struct async_pdu_handle *pasync_handle = NULL;
  1408. unsigned char is_header = 0;
  1409. unsigned int index, dpl;
  1410. if (is_chip_be2_be3r(phba)) {
  1411. dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
  1412. dpl, pdpdu_cqe);
  1413. index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
  1414. index, pdpdu_cqe);
  1415. } else {
  1416. dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
  1417. dpl, pdpdu_cqe);
  1418. index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
  1419. index, pdpdu_cqe);
  1420. }
  1421. phys_addr.u.a32.address_lo =
  1422. (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1423. db_addr_lo) / 32] - dpl);
  1424. phys_addr.u.a32.address_hi =
  1425. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1426. db_addr_hi) / 32];
  1427. phys_addr.u.a64.address =
  1428. *((unsigned long long *)(&phys_addr.u.a64.address));
  1429. switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32]
  1430. & PDUCQE_CODE_MASK) {
  1431. case UNSOL_HDR_NOTIFY:
  1432. is_header = 1;
  1433. pbusy_list = hwi_get_async_busy_list(pasync_ctx,
  1434. is_header, index);
  1435. break;
  1436. case UNSOL_DATA_NOTIFY:
  1437. pbusy_list = hwi_get_async_busy_list(pasync_ctx,
  1438. is_header, index);
  1439. break;
  1440. default:
  1441. pbusy_list = NULL;
  1442. beiscsi_log(phba, KERN_WARNING,
  1443. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1444. "BM_%d : Unexpected code=%d\n",
  1445. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1446. code) / 32] & PDUCQE_CODE_MASK);
  1447. return NULL;
  1448. }
  1449. WARN_ON(list_empty(pbusy_list));
  1450. list_for_each_entry(pasync_handle, pbusy_list, link) {
  1451. if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address)
  1452. break;
  1453. }
  1454. WARN_ON(!pasync_handle);
  1455. pasync_handle->cri =
  1456. BE_GET_CRI_FROM_CID(beiscsi_conn->beiscsi_conn_cid);
  1457. pasync_handle->is_header = is_header;
  1458. pasync_handle->buffer_len = dpl;
  1459. *pcq_index = index;
  1460. return pasync_handle;
  1461. }
  1462. static unsigned int
  1463. hwi_update_async_writables(struct beiscsi_hba *phba,
  1464. struct hwi_async_pdu_context *pasync_ctx,
  1465. unsigned int is_header, unsigned int cq_index)
  1466. {
  1467. struct list_head *pbusy_list;
  1468. struct async_pdu_handle *pasync_handle;
  1469. unsigned int num_entries, writables = 0;
  1470. unsigned int *pep_read_ptr, *pwritables;
  1471. num_entries = pasync_ctx->num_entries;
  1472. if (is_header) {
  1473. pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr;
  1474. pwritables = &pasync_ctx->async_header.writables;
  1475. } else {
  1476. pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr;
  1477. pwritables = &pasync_ctx->async_data.writables;
  1478. }
  1479. while ((*pep_read_ptr) != cq_index) {
  1480. (*pep_read_ptr)++;
  1481. *pep_read_ptr = (*pep_read_ptr) % num_entries;
  1482. pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header,
  1483. *pep_read_ptr);
  1484. if (writables == 0)
  1485. WARN_ON(list_empty(pbusy_list));
  1486. if (!list_empty(pbusy_list)) {
  1487. pasync_handle = list_entry(pbusy_list->next,
  1488. struct async_pdu_handle,
  1489. link);
  1490. WARN_ON(!pasync_handle);
  1491. pasync_handle->consumed = 1;
  1492. }
  1493. writables++;
  1494. }
  1495. if (!writables) {
  1496. beiscsi_log(phba, KERN_ERR,
  1497. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1498. "BM_%d : Duplicate notification received - index 0x%x!!\n",
  1499. cq_index);
  1500. WARN_ON(1);
  1501. }
  1502. *pwritables = *pwritables + writables;
  1503. return 0;
  1504. }
  1505. static void hwi_free_async_msg(struct beiscsi_hba *phba,
  1506. unsigned int cri)
  1507. {
  1508. struct hwi_controller *phwi_ctrlr;
  1509. struct hwi_async_pdu_context *pasync_ctx;
  1510. struct async_pdu_handle *pasync_handle, *tmp_handle;
  1511. struct list_head *plist;
  1512. phwi_ctrlr = phba->phwi_ctrlr;
  1513. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1514. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1515. list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
  1516. list_del(&pasync_handle->link);
  1517. if (pasync_handle->is_header) {
  1518. list_add_tail(&pasync_handle->link,
  1519. &pasync_ctx->async_header.free_list);
  1520. pasync_ctx->async_header.free_entries++;
  1521. } else {
  1522. list_add_tail(&pasync_handle->link,
  1523. &pasync_ctx->async_data.free_list);
  1524. pasync_ctx->async_data.free_entries++;
  1525. }
  1526. }
  1527. INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list);
  1528. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0;
  1529. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1530. }
  1531. static struct phys_addr *
  1532. hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx,
  1533. unsigned int is_header, unsigned int host_write_ptr)
  1534. {
  1535. struct phys_addr *pasync_sge = NULL;
  1536. if (is_header)
  1537. pasync_sge = pasync_ctx->async_header.ring_base;
  1538. else
  1539. pasync_sge = pasync_ctx->async_data.ring_base;
  1540. return pasync_sge + host_write_ptr;
  1541. }
  1542. static void hwi_post_async_buffers(struct beiscsi_hba *phba,
  1543. unsigned int is_header)
  1544. {
  1545. struct hwi_controller *phwi_ctrlr;
  1546. struct hwi_async_pdu_context *pasync_ctx;
  1547. struct async_pdu_handle *pasync_handle;
  1548. struct list_head *pfree_link, *pbusy_list;
  1549. struct phys_addr *pasync_sge;
  1550. unsigned int ring_id, num_entries;
  1551. unsigned int host_write_num;
  1552. unsigned int writables;
  1553. unsigned int i = 0;
  1554. u32 doorbell = 0;
  1555. phwi_ctrlr = phba->phwi_ctrlr;
  1556. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1557. num_entries = pasync_ctx->num_entries;
  1558. if (is_header) {
  1559. writables = min(pasync_ctx->async_header.writables,
  1560. pasync_ctx->async_header.free_entries);
  1561. pfree_link = pasync_ctx->async_header.free_list.next;
  1562. host_write_num = pasync_ctx->async_header.host_write_ptr;
  1563. ring_id = phwi_ctrlr->default_pdu_hdr.id;
  1564. } else {
  1565. writables = min(pasync_ctx->async_data.writables,
  1566. pasync_ctx->async_data.free_entries);
  1567. pfree_link = pasync_ctx->async_data.free_list.next;
  1568. host_write_num = pasync_ctx->async_data.host_write_ptr;
  1569. ring_id = phwi_ctrlr->default_pdu_data.id;
  1570. }
  1571. writables = (writables / 8) * 8;
  1572. if (writables) {
  1573. for (i = 0; i < writables; i++) {
  1574. pbusy_list =
  1575. hwi_get_async_busy_list(pasync_ctx, is_header,
  1576. host_write_num);
  1577. pasync_handle =
  1578. list_entry(pfree_link, struct async_pdu_handle,
  1579. link);
  1580. WARN_ON(!pasync_handle);
  1581. pasync_handle->consumed = 0;
  1582. pfree_link = pfree_link->next;
  1583. pasync_sge = hwi_get_ring_address(pasync_ctx,
  1584. is_header, host_write_num);
  1585. pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
  1586. pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
  1587. list_move(&pasync_handle->link, pbusy_list);
  1588. host_write_num++;
  1589. host_write_num = host_write_num % num_entries;
  1590. }
  1591. if (is_header) {
  1592. pasync_ctx->async_header.host_write_ptr =
  1593. host_write_num;
  1594. pasync_ctx->async_header.free_entries -= writables;
  1595. pasync_ctx->async_header.writables -= writables;
  1596. pasync_ctx->async_header.busy_entries += writables;
  1597. } else {
  1598. pasync_ctx->async_data.host_write_ptr = host_write_num;
  1599. pasync_ctx->async_data.free_entries -= writables;
  1600. pasync_ctx->async_data.writables -= writables;
  1601. pasync_ctx->async_data.busy_entries += writables;
  1602. }
  1603. doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
  1604. doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
  1605. doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
  1606. doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK)
  1607. << DB_DEF_PDU_CQPROC_SHIFT;
  1608. iowrite32(doorbell, phba->db_va + DB_RXULP0_OFFSET);
  1609. }
  1610. }
  1611. static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba,
  1612. struct beiscsi_conn *beiscsi_conn,
  1613. struct i_t_dpdu_cqe *pdpdu_cqe)
  1614. {
  1615. struct hwi_controller *phwi_ctrlr;
  1616. struct hwi_async_pdu_context *pasync_ctx;
  1617. struct async_pdu_handle *pasync_handle = NULL;
  1618. unsigned int cq_index = -1;
  1619. phwi_ctrlr = phba->phwi_ctrlr;
  1620. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1621. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1622. pdpdu_cqe, &cq_index);
  1623. BUG_ON(pasync_handle->is_header != 0);
  1624. if (pasync_handle->consumed == 0)
  1625. hwi_update_async_writables(phba, pasync_ctx,
  1626. pasync_handle->is_header, cq_index);
  1627. hwi_free_async_msg(phba, pasync_handle->cri);
  1628. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1629. }
  1630. static unsigned int
  1631. hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn,
  1632. struct beiscsi_hba *phba,
  1633. struct hwi_async_pdu_context *pasync_ctx, unsigned short cri)
  1634. {
  1635. struct list_head *plist;
  1636. struct async_pdu_handle *pasync_handle;
  1637. void *phdr = NULL;
  1638. unsigned int hdr_len = 0, buf_len = 0;
  1639. unsigned int status, index = 0, offset = 0;
  1640. void *pfirst_buffer = NULL;
  1641. unsigned int num_buf = 0;
  1642. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1643. list_for_each_entry(pasync_handle, plist, link) {
  1644. if (index == 0) {
  1645. phdr = pasync_handle->pbuffer;
  1646. hdr_len = pasync_handle->buffer_len;
  1647. } else {
  1648. buf_len = pasync_handle->buffer_len;
  1649. if (!num_buf) {
  1650. pfirst_buffer = pasync_handle->pbuffer;
  1651. num_buf++;
  1652. }
  1653. memcpy(pfirst_buffer + offset,
  1654. pasync_handle->pbuffer, buf_len);
  1655. offset += buf_len;
  1656. }
  1657. index++;
  1658. }
  1659. status = beiscsi_process_async_pdu(beiscsi_conn, phba,
  1660. phdr, hdr_len, pfirst_buffer,
  1661. offset);
  1662. hwi_free_async_msg(phba, cri);
  1663. return 0;
  1664. }
  1665. static unsigned int
  1666. hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn,
  1667. struct beiscsi_hba *phba,
  1668. struct async_pdu_handle *pasync_handle)
  1669. {
  1670. struct hwi_async_pdu_context *pasync_ctx;
  1671. struct hwi_controller *phwi_ctrlr;
  1672. unsigned int bytes_needed = 0, status = 0;
  1673. unsigned short cri = pasync_handle->cri;
  1674. struct pdu_base *ppdu;
  1675. phwi_ctrlr = phba->phwi_ctrlr;
  1676. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1677. list_del(&pasync_handle->link);
  1678. if (pasync_handle->is_header) {
  1679. pasync_ctx->async_header.busy_entries--;
  1680. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1681. hwi_free_async_msg(phba, cri);
  1682. BUG();
  1683. }
  1684. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1685. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1;
  1686. pasync_ctx->async_entry[cri].wait_queue.hdr_len =
  1687. (unsigned short)pasync_handle->buffer_len;
  1688. list_add_tail(&pasync_handle->link,
  1689. &pasync_ctx->async_entry[cri].wait_queue.list);
  1690. ppdu = pasync_handle->pbuffer;
  1691. bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base,
  1692. data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) &
  1693. 0xFFFF0000) | ((be16_to_cpu((ppdu->
  1694. dw[offsetof(struct amap_pdu_base, data_len_lo) / 32]
  1695. & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF));
  1696. if (status == 0) {
  1697. pasync_ctx->async_entry[cri].wait_queue.bytes_needed =
  1698. bytes_needed;
  1699. if (bytes_needed == 0)
  1700. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1701. pasync_ctx, cri);
  1702. }
  1703. } else {
  1704. pasync_ctx->async_data.busy_entries--;
  1705. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1706. list_add_tail(&pasync_handle->link,
  1707. &pasync_ctx->async_entry[cri].wait_queue.
  1708. list);
  1709. pasync_ctx->async_entry[cri].wait_queue.
  1710. bytes_received +=
  1711. (unsigned short)pasync_handle->buffer_len;
  1712. if (pasync_ctx->async_entry[cri].wait_queue.
  1713. bytes_received >=
  1714. pasync_ctx->async_entry[cri].wait_queue.
  1715. bytes_needed)
  1716. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1717. pasync_ctx, cri);
  1718. }
  1719. }
  1720. return status;
  1721. }
  1722. static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn,
  1723. struct beiscsi_hba *phba,
  1724. struct i_t_dpdu_cqe *pdpdu_cqe)
  1725. {
  1726. struct hwi_controller *phwi_ctrlr;
  1727. struct hwi_async_pdu_context *pasync_ctx;
  1728. struct async_pdu_handle *pasync_handle = NULL;
  1729. unsigned int cq_index = -1;
  1730. phwi_ctrlr = phba->phwi_ctrlr;
  1731. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1732. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1733. pdpdu_cqe, &cq_index);
  1734. if (pasync_handle->consumed == 0)
  1735. hwi_update_async_writables(phba, pasync_ctx,
  1736. pasync_handle->is_header, cq_index);
  1737. hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle);
  1738. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1739. }
  1740. static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
  1741. {
  1742. struct be_queue_info *mcc_cq;
  1743. struct be_mcc_compl *mcc_compl;
  1744. unsigned int num_processed = 0;
  1745. mcc_cq = &phba->ctrl.mcc_obj.cq;
  1746. mcc_compl = queue_tail_node(mcc_cq);
  1747. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1748. while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
  1749. if (num_processed >= 32) {
  1750. hwi_ring_cq_db(phba, mcc_cq->id,
  1751. num_processed, 0, 0);
  1752. num_processed = 0;
  1753. }
  1754. if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
  1755. /* Interpret flags as an async trailer */
  1756. if (is_link_state_evt(mcc_compl->flags))
  1757. /* Interpret compl as a async link evt */
  1758. beiscsi_async_link_state_process(phba,
  1759. (struct be_async_event_link_state *) mcc_compl);
  1760. else
  1761. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX,
  1762. "BM_%d : Unsupported Async Event, flags"
  1763. " = 0x%08x\n",
  1764. mcc_compl->flags);
  1765. } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
  1766. be_mcc_compl_process_isr(&phba->ctrl, mcc_compl);
  1767. atomic_dec(&phba->ctrl.mcc_obj.q.used);
  1768. }
  1769. mcc_compl->flags = 0;
  1770. queue_tail_inc(mcc_cq);
  1771. mcc_compl = queue_tail_node(mcc_cq);
  1772. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1773. num_processed++;
  1774. }
  1775. if (num_processed > 0)
  1776. hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1, 0);
  1777. }
  1778. /**
  1779. * beiscsi_process_cq()- Process the Completion Queue
  1780. * @pbe_eq: Event Q on which the Completion has come
  1781. *
  1782. * return
  1783. * Number of Completion Entries processed.
  1784. **/
  1785. static unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq)
  1786. {
  1787. struct be_queue_info *cq;
  1788. struct sol_cqe *sol;
  1789. struct dmsg_cqe *dmsg;
  1790. unsigned int num_processed = 0;
  1791. unsigned int tot_nump = 0;
  1792. unsigned short code = 0, cid = 0;
  1793. uint16_t cri_index = 0;
  1794. struct beiscsi_conn *beiscsi_conn;
  1795. struct beiscsi_endpoint *beiscsi_ep;
  1796. struct iscsi_endpoint *ep;
  1797. struct beiscsi_hba *phba;
  1798. cq = pbe_eq->cq;
  1799. sol = queue_tail_node(cq);
  1800. phba = pbe_eq->phba;
  1801. while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
  1802. CQE_VALID_MASK) {
  1803. be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
  1804. code = (sol->dw[offsetof(struct amap_sol_cqe, code) /
  1805. 32] & CQE_CODE_MASK);
  1806. /* Get the CID */
  1807. if (is_chip_be2_be3r(phba)) {
  1808. cid = AMAP_GET_BITS(struct amap_sol_cqe, cid, sol);
  1809. } else {
  1810. if ((code == DRIVERMSG_NOTIFY) ||
  1811. (code == UNSOL_HDR_NOTIFY) ||
  1812. (code == UNSOL_DATA_NOTIFY))
  1813. cid = AMAP_GET_BITS(
  1814. struct amap_i_t_dpdu_cqe_v2,
  1815. cid, sol);
  1816. else
  1817. cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1818. cid, sol);
  1819. }
  1820. cri_index = BE_GET_CRI_FROM_CID(cid);
  1821. ep = phba->ep_array[cri_index];
  1822. beiscsi_ep = ep->dd_data;
  1823. beiscsi_conn = beiscsi_ep->conn;
  1824. if (num_processed >= 32) {
  1825. hwi_ring_cq_db(phba, cq->id,
  1826. num_processed, 0, 0);
  1827. tot_nump += num_processed;
  1828. num_processed = 0;
  1829. }
  1830. switch (code) {
  1831. case SOL_CMD_COMPLETE:
  1832. hwi_complete_cmd(beiscsi_conn, phba, sol);
  1833. break;
  1834. case DRIVERMSG_NOTIFY:
  1835. beiscsi_log(phba, KERN_INFO,
  1836. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1837. "BM_%d : Received %s[%d] on CID : %d\n",
  1838. cqe_desc[code], code, cid);
  1839. dmsg = (struct dmsg_cqe *)sol;
  1840. hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
  1841. break;
  1842. case UNSOL_HDR_NOTIFY:
  1843. beiscsi_log(phba, KERN_INFO,
  1844. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1845. "BM_%d : Received %s[%d] on CID : %d\n",
  1846. cqe_desc[code], code, cid);
  1847. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1848. (struct i_t_dpdu_cqe *)sol);
  1849. break;
  1850. case UNSOL_DATA_NOTIFY:
  1851. beiscsi_log(phba, KERN_INFO,
  1852. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1853. "BM_%d : Received %s[%d] on CID : %d\n",
  1854. cqe_desc[code], code, cid);
  1855. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1856. (struct i_t_dpdu_cqe *)sol);
  1857. break;
  1858. case CXN_INVALIDATE_INDEX_NOTIFY:
  1859. case CMD_INVALIDATED_NOTIFY:
  1860. case CXN_INVALIDATE_NOTIFY:
  1861. beiscsi_log(phba, KERN_ERR,
  1862. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1863. "BM_%d : Ignoring %s[%d] on CID : %d\n",
  1864. cqe_desc[code], code, cid);
  1865. break;
  1866. case SOL_CMD_KILLED_DATA_DIGEST_ERR:
  1867. case CMD_KILLED_INVALID_STATSN_RCVD:
  1868. case CMD_KILLED_INVALID_R2T_RCVD:
  1869. case CMD_CXN_KILLED_LUN_INVALID:
  1870. case CMD_CXN_KILLED_ICD_INVALID:
  1871. case CMD_CXN_KILLED_ITT_INVALID:
  1872. case CMD_CXN_KILLED_SEQ_OUTOFORDER:
  1873. case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
  1874. beiscsi_log(phba, KERN_ERR,
  1875. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1876. "BM_%d : Cmd Notification %s[%d] on CID : %d\n",
  1877. cqe_desc[code], code, cid);
  1878. break;
  1879. case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
  1880. beiscsi_log(phba, KERN_ERR,
  1881. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1882. "BM_%d : Dropping %s[%d] on DPDU ring on CID : %d\n",
  1883. cqe_desc[code], code, cid);
  1884. hwi_flush_default_pdu_buffer(phba, beiscsi_conn,
  1885. (struct i_t_dpdu_cqe *) sol);
  1886. break;
  1887. case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
  1888. case CXN_KILLED_BURST_LEN_MISMATCH:
  1889. case CXN_KILLED_AHS_RCVD:
  1890. case CXN_KILLED_HDR_DIGEST_ERR:
  1891. case CXN_KILLED_UNKNOWN_HDR:
  1892. case CXN_KILLED_STALE_ITT_TTT_RCVD:
  1893. case CXN_KILLED_INVALID_ITT_TTT_RCVD:
  1894. case CXN_KILLED_TIMED_OUT:
  1895. case CXN_KILLED_FIN_RCVD:
  1896. case CXN_KILLED_RST_SENT:
  1897. case CXN_KILLED_RST_RCVD:
  1898. case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
  1899. case CXN_KILLED_BAD_WRB_INDEX_ERROR:
  1900. case CXN_KILLED_OVER_RUN_RESIDUAL:
  1901. case CXN_KILLED_UNDER_RUN_RESIDUAL:
  1902. case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
  1903. beiscsi_log(phba, KERN_ERR,
  1904. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1905. "BM_%d : Event %s[%d] received on CID : %d\n",
  1906. cqe_desc[code], code, cid);
  1907. if (beiscsi_conn)
  1908. iscsi_conn_failure(beiscsi_conn->conn,
  1909. ISCSI_ERR_CONN_FAILED);
  1910. break;
  1911. default:
  1912. beiscsi_log(phba, KERN_ERR,
  1913. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1914. "BM_%d : Invalid CQE Event Received Code : %d"
  1915. "CID 0x%x...\n",
  1916. code, cid);
  1917. break;
  1918. }
  1919. AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
  1920. queue_tail_inc(cq);
  1921. sol = queue_tail_node(cq);
  1922. num_processed++;
  1923. }
  1924. if (num_processed > 0) {
  1925. tot_nump += num_processed;
  1926. hwi_ring_cq_db(phba, cq->id, num_processed, 1, 0);
  1927. }
  1928. return tot_nump;
  1929. }
  1930. void beiscsi_process_all_cqs(struct work_struct *work)
  1931. {
  1932. unsigned long flags;
  1933. struct hwi_controller *phwi_ctrlr;
  1934. struct hwi_context_memory *phwi_context;
  1935. struct beiscsi_hba *phba;
  1936. struct be_eq_obj *pbe_eq =
  1937. container_of(work, struct be_eq_obj, work_cqs);
  1938. phba = pbe_eq->phba;
  1939. phwi_ctrlr = phba->phwi_ctrlr;
  1940. phwi_context = phwi_ctrlr->phwi_ctxt;
  1941. if (pbe_eq->todo_mcc_cq) {
  1942. spin_lock_irqsave(&phba->isr_lock, flags);
  1943. pbe_eq->todo_mcc_cq = false;
  1944. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1945. beiscsi_process_mcc_isr(phba);
  1946. }
  1947. if (pbe_eq->todo_cq) {
  1948. spin_lock_irqsave(&phba->isr_lock, flags);
  1949. pbe_eq->todo_cq = false;
  1950. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1951. beiscsi_process_cq(pbe_eq);
  1952. }
  1953. /* rearm EQ for further interrupts */
  1954. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1955. }
  1956. static int be_iopoll(struct blk_iopoll *iop, int budget)
  1957. {
  1958. unsigned int ret;
  1959. struct beiscsi_hba *phba;
  1960. struct be_eq_obj *pbe_eq;
  1961. pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
  1962. ret = beiscsi_process_cq(pbe_eq);
  1963. if (ret < budget) {
  1964. phba = pbe_eq->phba;
  1965. blk_iopoll_complete(iop);
  1966. beiscsi_log(phba, KERN_INFO,
  1967. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1968. "BM_%d : rearm pbe_eq->q.id =%d\n",
  1969. pbe_eq->q.id);
  1970. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1971. }
  1972. return ret;
  1973. }
  1974. static void
  1975. hwi_write_sgl_v2(struct iscsi_wrb *pwrb, struct scatterlist *sg,
  1976. unsigned int num_sg, struct beiscsi_io_task *io_task)
  1977. {
  1978. struct iscsi_sge *psgl;
  1979. unsigned int sg_len, index;
  1980. unsigned int sge_len = 0;
  1981. unsigned long long addr;
  1982. struct scatterlist *l_sg;
  1983. unsigned int offset;
  1984. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_lo, pwrb,
  1985. io_task->bhs_pa.u.a32.address_lo);
  1986. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_hi, pwrb,
  1987. io_task->bhs_pa.u.a32.address_hi);
  1988. l_sg = sg;
  1989. for (index = 0; (index < num_sg) && (index < 2); index++,
  1990. sg = sg_next(sg)) {
  1991. if (index == 0) {
  1992. sg_len = sg_dma_len(sg);
  1993. addr = (u64) sg_dma_address(sg);
  1994. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  1995. sge0_addr_lo, pwrb,
  1996. lower_32_bits(addr));
  1997. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  1998. sge0_addr_hi, pwrb,
  1999. upper_32_bits(addr));
  2000. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2001. sge0_len, pwrb,
  2002. sg_len);
  2003. sge_len = sg_len;
  2004. } else {
  2005. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_r2t_offset,
  2006. pwrb, sge_len);
  2007. sg_len = sg_dma_len(sg);
  2008. addr = (u64) sg_dma_address(sg);
  2009. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2010. sge1_addr_lo, pwrb,
  2011. lower_32_bits(addr));
  2012. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2013. sge1_addr_hi, pwrb,
  2014. upper_32_bits(addr));
  2015. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2016. sge1_len, pwrb,
  2017. sg_len);
  2018. }
  2019. }
  2020. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2021. memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
  2022. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
  2023. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2024. io_task->bhs_pa.u.a32.address_hi);
  2025. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2026. io_task->bhs_pa.u.a32.address_lo);
  2027. if (num_sg == 1) {
  2028. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
  2029. 1);
  2030. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
  2031. 0);
  2032. } else if (num_sg == 2) {
  2033. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
  2034. 0);
  2035. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
  2036. 1);
  2037. } else {
  2038. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
  2039. 0);
  2040. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
  2041. 0);
  2042. }
  2043. sg = l_sg;
  2044. psgl++;
  2045. psgl++;
  2046. offset = 0;
  2047. for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
  2048. sg_len = sg_dma_len(sg);
  2049. addr = (u64) sg_dma_address(sg);
  2050. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2051. lower_32_bits(addr));
  2052. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2053. upper_32_bits(addr));
  2054. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
  2055. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
  2056. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2057. offset += sg_len;
  2058. }
  2059. psgl--;
  2060. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2061. }
  2062. static void
  2063. hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
  2064. unsigned int num_sg, struct beiscsi_io_task *io_task)
  2065. {
  2066. struct iscsi_sge *psgl;
  2067. unsigned int sg_len, index;
  2068. unsigned int sge_len = 0;
  2069. unsigned long long addr;
  2070. struct scatterlist *l_sg;
  2071. unsigned int offset;
  2072. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  2073. io_task->bhs_pa.u.a32.address_lo);
  2074. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  2075. io_task->bhs_pa.u.a32.address_hi);
  2076. l_sg = sg;
  2077. for (index = 0; (index < num_sg) && (index < 2); index++,
  2078. sg = sg_next(sg)) {
  2079. if (index == 0) {
  2080. sg_len = sg_dma_len(sg);
  2081. addr = (u64) sg_dma_address(sg);
  2082. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  2083. ((u32)(addr & 0xFFFFFFFF)));
  2084. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  2085. ((u32)(addr >> 32)));
  2086. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  2087. sg_len);
  2088. sge_len = sg_len;
  2089. } else {
  2090. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
  2091. pwrb, sge_len);
  2092. sg_len = sg_dma_len(sg);
  2093. addr = (u64) sg_dma_address(sg);
  2094. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
  2095. ((u32)(addr & 0xFFFFFFFF)));
  2096. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
  2097. ((u32)(addr >> 32)));
  2098. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
  2099. sg_len);
  2100. }
  2101. }
  2102. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2103. memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
  2104. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
  2105. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2106. io_task->bhs_pa.u.a32.address_hi);
  2107. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2108. io_task->bhs_pa.u.a32.address_lo);
  2109. if (num_sg == 1) {
  2110. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  2111. 1);
  2112. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  2113. 0);
  2114. } else if (num_sg == 2) {
  2115. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  2116. 0);
  2117. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  2118. 1);
  2119. } else {
  2120. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  2121. 0);
  2122. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  2123. 0);
  2124. }
  2125. sg = l_sg;
  2126. psgl++;
  2127. psgl++;
  2128. offset = 0;
  2129. for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
  2130. sg_len = sg_dma_len(sg);
  2131. addr = (u64) sg_dma_address(sg);
  2132. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2133. (addr & 0xFFFFFFFF));
  2134. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2135. (addr >> 32));
  2136. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
  2137. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
  2138. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2139. offset += sg_len;
  2140. }
  2141. psgl--;
  2142. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2143. }
  2144. /**
  2145. * hwi_write_buffer()- Populate the WRB with task info
  2146. * @pwrb: ptr to the WRB entry
  2147. * @task: iscsi task which is to be executed
  2148. **/
  2149. static void hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
  2150. {
  2151. struct iscsi_sge *psgl;
  2152. struct beiscsi_io_task *io_task = task->dd_data;
  2153. struct beiscsi_conn *beiscsi_conn = io_task->conn;
  2154. struct beiscsi_hba *phba = beiscsi_conn->phba;
  2155. uint8_t dsp_value = 0;
  2156. io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
  2157. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  2158. io_task->bhs_pa.u.a32.address_lo);
  2159. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  2160. io_task->bhs_pa.u.a32.address_hi);
  2161. if (task->data) {
  2162. /* Check for the data_count */
  2163. dsp_value = (task->data_count) ? 1 : 0;
  2164. if (is_chip_be2_be3r(phba))
  2165. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp,
  2166. pwrb, dsp_value);
  2167. else
  2168. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp,
  2169. pwrb, dsp_value);
  2170. /* Map addr only if there is data_count */
  2171. if (dsp_value) {
  2172. io_task->mtask_addr = pci_map_single(phba->pcidev,
  2173. task->data,
  2174. task->data_count,
  2175. PCI_DMA_TODEVICE);
  2176. io_task->mtask_data_count = task->data_count;
  2177. } else
  2178. io_task->mtask_addr = 0;
  2179. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  2180. lower_32_bits(io_task->mtask_addr));
  2181. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  2182. upper_32_bits(io_task->mtask_addr));
  2183. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  2184. task->data_count);
  2185. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
  2186. } else {
  2187. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  2188. io_task->mtask_addr = 0;
  2189. }
  2190. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2191. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
  2192. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2193. io_task->bhs_pa.u.a32.address_hi);
  2194. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2195. io_task->bhs_pa.u.a32.address_lo);
  2196. if (task->data) {
  2197. psgl++;
  2198. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
  2199. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
  2200. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
  2201. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
  2202. AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
  2203. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2204. psgl++;
  2205. if (task->data) {
  2206. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2207. lower_32_bits(io_task->mtask_addr));
  2208. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2209. upper_32_bits(io_task->mtask_addr));
  2210. }
  2211. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
  2212. }
  2213. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2214. }
  2215. static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
  2216. {
  2217. unsigned int num_cq_pages, num_async_pdu_buf_pages;
  2218. unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
  2219. unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
  2220. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2221. sizeof(struct sol_cqe));
  2222. num_async_pdu_buf_pages =
  2223. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2224. phba->params.defpdu_hdr_sz);
  2225. num_async_pdu_buf_sgl_pages =
  2226. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2227. sizeof(struct phys_addr));
  2228. num_async_pdu_data_pages =
  2229. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2230. phba->params.defpdu_data_sz);
  2231. num_async_pdu_data_sgl_pages =
  2232. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2233. sizeof(struct phys_addr));
  2234. phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
  2235. phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
  2236. BE_ISCSI_PDU_HEADER_SIZE;
  2237. phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
  2238. sizeof(struct hwi_context_memory);
  2239. phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
  2240. * (phba->params.wrbs_per_cxn)
  2241. * phba->params.cxns_per_ctrl;
  2242. wrb_sz_per_cxn = sizeof(struct wrb_handle) *
  2243. (phba->params.wrbs_per_cxn);
  2244. phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
  2245. phba->params.cxns_per_ctrl);
  2246. phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
  2247. phba->params.icds_per_ctrl;
  2248. phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
  2249. phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
  2250. phba->mem_req[HWI_MEM_ASYNC_HEADER_BUF] =
  2251. num_async_pdu_buf_pages * PAGE_SIZE;
  2252. phba->mem_req[HWI_MEM_ASYNC_DATA_BUF] =
  2253. num_async_pdu_data_pages * PAGE_SIZE;
  2254. phba->mem_req[HWI_MEM_ASYNC_HEADER_RING] =
  2255. num_async_pdu_buf_sgl_pages * PAGE_SIZE;
  2256. phba->mem_req[HWI_MEM_ASYNC_DATA_RING] =
  2257. num_async_pdu_data_sgl_pages * PAGE_SIZE;
  2258. phba->mem_req[HWI_MEM_ASYNC_HEADER_HANDLE] =
  2259. phba->params.asyncpdus_per_ctrl *
  2260. sizeof(struct async_pdu_handle);
  2261. phba->mem_req[HWI_MEM_ASYNC_DATA_HANDLE] =
  2262. phba->params.asyncpdus_per_ctrl *
  2263. sizeof(struct async_pdu_handle);
  2264. phba->mem_req[HWI_MEM_ASYNC_PDU_CONTEXT] =
  2265. sizeof(struct hwi_async_pdu_context) +
  2266. (phba->params.cxns_per_ctrl * sizeof(struct hwi_async_entry));
  2267. }
  2268. static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
  2269. {
  2270. dma_addr_t bus_add;
  2271. struct hwi_controller *phwi_ctrlr;
  2272. struct be_mem_descriptor *mem_descr;
  2273. struct mem_array *mem_arr, *mem_arr_orig;
  2274. unsigned int i, j, alloc_size, curr_alloc_size;
  2275. phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
  2276. if (!phba->phwi_ctrlr)
  2277. return -ENOMEM;
  2278. /* Allocate memory for wrb_context */
  2279. phwi_ctrlr = phba->phwi_ctrlr;
  2280. phwi_ctrlr->wrb_context = kzalloc(sizeof(struct hwi_wrb_context) *
  2281. phba->params.cxns_per_ctrl,
  2282. GFP_KERNEL);
  2283. if (!phwi_ctrlr->wrb_context)
  2284. return -ENOMEM;
  2285. phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
  2286. GFP_KERNEL);
  2287. if (!phba->init_mem) {
  2288. kfree(phwi_ctrlr->wrb_context);
  2289. kfree(phba->phwi_ctrlr);
  2290. return -ENOMEM;
  2291. }
  2292. mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
  2293. GFP_KERNEL);
  2294. if (!mem_arr_orig) {
  2295. kfree(phba->init_mem);
  2296. kfree(phwi_ctrlr->wrb_context);
  2297. kfree(phba->phwi_ctrlr);
  2298. return -ENOMEM;
  2299. }
  2300. mem_descr = phba->init_mem;
  2301. for (i = 0; i < SE_MEM_MAX; i++) {
  2302. j = 0;
  2303. mem_arr = mem_arr_orig;
  2304. alloc_size = phba->mem_req[i];
  2305. memset(mem_arr, 0, sizeof(struct mem_array) *
  2306. BEISCSI_MAX_FRAGS_INIT);
  2307. curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
  2308. do {
  2309. mem_arr->virtual_address = pci_alloc_consistent(
  2310. phba->pcidev,
  2311. curr_alloc_size,
  2312. &bus_add);
  2313. if (!mem_arr->virtual_address) {
  2314. if (curr_alloc_size <= BE_MIN_MEM_SIZE)
  2315. goto free_mem;
  2316. if (curr_alloc_size -
  2317. rounddown_pow_of_two(curr_alloc_size))
  2318. curr_alloc_size = rounddown_pow_of_two
  2319. (curr_alloc_size);
  2320. else
  2321. curr_alloc_size = curr_alloc_size / 2;
  2322. } else {
  2323. mem_arr->bus_address.u.
  2324. a64.address = (__u64) bus_add;
  2325. mem_arr->size = curr_alloc_size;
  2326. alloc_size -= curr_alloc_size;
  2327. curr_alloc_size = min(be_max_phys_size *
  2328. 1024, alloc_size);
  2329. j++;
  2330. mem_arr++;
  2331. }
  2332. } while (alloc_size);
  2333. mem_descr->num_elements = j;
  2334. mem_descr->size_in_bytes = phba->mem_req[i];
  2335. mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
  2336. GFP_KERNEL);
  2337. if (!mem_descr->mem_array)
  2338. goto free_mem;
  2339. memcpy(mem_descr->mem_array, mem_arr_orig,
  2340. sizeof(struct mem_array) * j);
  2341. mem_descr++;
  2342. }
  2343. kfree(mem_arr_orig);
  2344. return 0;
  2345. free_mem:
  2346. mem_descr->num_elements = j;
  2347. while ((i) || (j)) {
  2348. for (j = mem_descr->num_elements; j > 0; j--) {
  2349. pci_free_consistent(phba->pcidev,
  2350. mem_descr->mem_array[j - 1].size,
  2351. mem_descr->mem_array[j - 1].
  2352. virtual_address,
  2353. (unsigned long)mem_descr->
  2354. mem_array[j - 1].
  2355. bus_address.u.a64.address);
  2356. }
  2357. if (i) {
  2358. i--;
  2359. kfree(mem_descr->mem_array);
  2360. mem_descr--;
  2361. }
  2362. }
  2363. kfree(mem_arr_orig);
  2364. kfree(phba->init_mem);
  2365. kfree(phba->phwi_ctrlr->wrb_context);
  2366. kfree(phba->phwi_ctrlr);
  2367. return -ENOMEM;
  2368. }
  2369. static int beiscsi_get_memory(struct beiscsi_hba *phba)
  2370. {
  2371. beiscsi_find_mem_req(phba);
  2372. return beiscsi_alloc_mem(phba);
  2373. }
  2374. static void iscsi_init_global_templates(struct beiscsi_hba *phba)
  2375. {
  2376. struct pdu_data_out *pdata_out;
  2377. struct pdu_nop_out *pnop_out;
  2378. struct be_mem_descriptor *mem_descr;
  2379. mem_descr = phba->init_mem;
  2380. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  2381. pdata_out =
  2382. (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
  2383. memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2384. AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
  2385. IIOC_SCSI_DATA);
  2386. pnop_out =
  2387. (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
  2388. virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
  2389. memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2390. AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
  2391. AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
  2392. AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
  2393. }
  2394. static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
  2395. {
  2396. struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
  2397. struct hwi_context_memory *phwi_ctxt;
  2398. struct wrb_handle *pwrb_handle = NULL;
  2399. struct hwi_controller *phwi_ctrlr;
  2400. struct hwi_wrb_context *pwrb_context;
  2401. struct iscsi_wrb *pwrb = NULL;
  2402. unsigned int num_cxn_wrbh = 0;
  2403. unsigned int num_cxn_wrb = 0, j, idx = 0, index;
  2404. mem_descr_wrbh = phba->init_mem;
  2405. mem_descr_wrbh += HWI_MEM_WRBH;
  2406. mem_descr_wrb = phba->init_mem;
  2407. mem_descr_wrb += HWI_MEM_WRB;
  2408. phwi_ctrlr = phba->phwi_ctrlr;
  2409. /* Allocate memory for WRBQ */
  2410. phwi_ctxt = phwi_ctrlr->phwi_ctxt;
  2411. phwi_ctxt->be_wrbq = kzalloc(sizeof(struct be_queue_info) *
  2412. phba->fw_config.iscsi_cid_count,
  2413. GFP_KERNEL);
  2414. if (!phwi_ctxt->be_wrbq) {
  2415. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2416. "BM_%d : WRBQ Mem Alloc Failed\n");
  2417. return -ENOMEM;
  2418. }
  2419. for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
  2420. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2421. pwrb_context->pwrb_handle_base =
  2422. kzalloc(sizeof(struct wrb_handle *) *
  2423. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2424. if (!pwrb_context->pwrb_handle_base) {
  2425. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2426. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2427. goto init_wrb_hndl_failed;
  2428. }
  2429. pwrb_context->pwrb_handle_basestd =
  2430. kzalloc(sizeof(struct wrb_handle *) *
  2431. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2432. if (!pwrb_context->pwrb_handle_basestd) {
  2433. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2434. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2435. goto init_wrb_hndl_failed;
  2436. }
  2437. if (!num_cxn_wrbh) {
  2438. pwrb_handle =
  2439. mem_descr_wrbh->mem_array[idx].virtual_address;
  2440. num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
  2441. ((sizeof(struct wrb_handle)) *
  2442. phba->params.wrbs_per_cxn));
  2443. idx++;
  2444. }
  2445. pwrb_context->alloc_index = 0;
  2446. pwrb_context->wrb_handles_available = 0;
  2447. pwrb_context->free_index = 0;
  2448. if (num_cxn_wrbh) {
  2449. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2450. pwrb_context->pwrb_handle_base[j] = pwrb_handle;
  2451. pwrb_context->pwrb_handle_basestd[j] =
  2452. pwrb_handle;
  2453. pwrb_context->wrb_handles_available++;
  2454. pwrb_handle->wrb_index = j;
  2455. pwrb_handle++;
  2456. }
  2457. num_cxn_wrbh--;
  2458. }
  2459. }
  2460. idx = 0;
  2461. for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
  2462. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2463. if (!num_cxn_wrb) {
  2464. pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
  2465. num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
  2466. ((sizeof(struct iscsi_wrb) *
  2467. phba->params.wrbs_per_cxn));
  2468. idx++;
  2469. }
  2470. if (num_cxn_wrb) {
  2471. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2472. pwrb_handle = pwrb_context->pwrb_handle_base[j];
  2473. pwrb_handle->pwrb = pwrb;
  2474. pwrb++;
  2475. }
  2476. num_cxn_wrb--;
  2477. }
  2478. }
  2479. return 0;
  2480. init_wrb_hndl_failed:
  2481. for (j = index; j > 0; j--) {
  2482. pwrb_context = &phwi_ctrlr->wrb_context[j];
  2483. kfree(pwrb_context->pwrb_handle_base);
  2484. kfree(pwrb_context->pwrb_handle_basestd);
  2485. }
  2486. return -ENOMEM;
  2487. }
  2488. static int hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
  2489. {
  2490. struct hwi_controller *phwi_ctrlr;
  2491. struct hba_parameters *p = &phba->params;
  2492. struct hwi_async_pdu_context *pasync_ctx;
  2493. struct async_pdu_handle *pasync_header_h, *pasync_data_h;
  2494. unsigned int index, idx, num_per_mem, num_async_data;
  2495. struct be_mem_descriptor *mem_descr;
  2496. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2497. mem_descr += HWI_MEM_ASYNC_PDU_CONTEXT;
  2498. phwi_ctrlr = phba->phwi_ctrlr;
  2499. phwi_ctrlr->phwi_ctxt->pasync_ctx = (struct hwi_async_pdu_context *)
  2500. mem_descr->mem_array[0].virtual_address;
  2501. pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx;
  2502. memset(pasync_ctx, 0, sizeof(*pasync_ctx));
  2503. pasync_ctx->async_entry = kzalloc(sizeof(struct hwi_async_entry) *
  2504. phba->fw_config.iscsi_cid_count,
  2505. GFP_KERNEL);
  2506. if (!pasync_ctx->async_entry) {
  2507. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2508. "BM_%d : hwi_init_async_pdu_ctx Mem Alloc Failed\n");
  2509. return -ENOMEM;
  2510. }
  2511. pasync_ctx->num_entries = p->asyncpdus_per_ctrl;
  2512. pasync_ctx->buffer_size = p->defpdu_hdr_sz;
  2513. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2514. mem_descr += HWI_MEM_ASYNC_HEADER_BUF;
  2515. if (mem_descr->mem_array[0].virtual_address) {
  2516. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2517. "BM_%d : hwi_init_async_pdu_ctx"
  2518. " HWI_MEM_ASYNC_HEADER_BUF va=%p\n",
  2519. mem_descr->mem_array[0].virtual_address);
  2520. } else
  2521. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2522. "BM_%d : No Virtual address\n");
  2523. pasync_ctx->async_header.va_base =
  2524. mem_descr->mem_array[0].virtual_address;
  2525. pasync_ctx->async_header.pa_base.u.a64.address =
  2526. mem_descr->mem_array[0].bus_address.u.a64.address;
  2527. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2528. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2529. if (mem_descr->mem_array[0].virtual_address) {
  2530. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2531. "BM_%d : hwi_init_async_pdu_ctx"
  2532. " HWI_MEM_ASYNC_HEADER_RING va=%p\n",
  2533. mem_descr->mem_array[0].virtual_address);
  2534. } else
  2535. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2536. "BM_%d : No Virtual address\n");
  2537. pasync_ctx->async_header.ring_base =
  2538. mem_descr->mem_array[0].virtual_address;
  2539. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2540. mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE;
  2541. if (mem_descr->mem_array[0].virtual_address) {
  2542. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2543. "BM_%d : hwi_init_async_pdu_ctx"
  2544. " HWI_MEM_ASYNC_HEADER_HANDLE va=%p\n",
  2545. mem_descr->mem_array[0].virtual_address);
  2546. } else
  2547. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2548. "BM_%d : No Virtual address\n");
  2549. pasync_ctx->async_header.handle_base =
  2550. mem_descr->mem_array[0].virtual_address;
  2551. pasync_ctx->async_header.writables = 0;
  2552. INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
  2553. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2554. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2555. if (mem_descr->mem_array[0].virtual_address) {
  2556. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2557. "BM_%d : hwi_init_async_pdu_ctx"
  2558. " HWI_MEM_ASYNC_DATA_RING va=%p\n",
  2559. mem_descr->mem_array[0].virtual_address);
  2560. } else
  2561. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2562. "BM_%d : No Virtual address\n");
  2563. pasync_ctx->async_data.ring_base =
  2564. mem_descr->mem_array[0].virtual_address;
  2565. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2566. mem_descr += HWI_MEM_ASYNC_DATA_HANDLE;
  2567. if (!mem_descr->mem_array[0].virtual_address)
  2568. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2569. "BM_%d : No Virtual address\n");
  2570. pasync_ctx->async_data.handle_base =
  2571. mem_descr->mem_array[0].virtual_address;
  2572. pasync_ctx->async_data.writables = 0;
  2573. INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
  2574. pasync_header_h =
  2575. (struct async_pdu_handle *)pasync_ctx->async_header.handle_base;
  2576. pasync_data_h =
  2577. (struct async_pdu_handle *)pasync_ctx->async_data.handle_base;
  2578. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2579. mem_descr += HWI_MEM_ASYNC_DATA_BUF;
  2580. if (mem_descr->mem_array[0].virtual_address) {
  2581. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2582. "BM_%d : hwi_init_async_pdu_ctx"
  2583. " HWI_MEM_ASYNC_DATA_BUF va=%p\n",
  2584. mem_descr->mem_array[0].virtual_address);
  2585. } else
  2586. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2587. "BM_%d : No Virtual address\n");
  2588. idx = 0;
  2589. pasync_ctx->async_data.va_base =
  2590. mem_descr->mem_array[idx].virtual_address;
  2591. pasync_ctx->async_data.pa_base.u.a64.address =
  2592. mem_descr->mem_array[idx].bus_address.u.a64.address;
  2593. num_async_data = ((mem_descr->mem_array[idx].size) /
  2594. phba->params.defpdu_data_sz);
  2595. num_per_mem = 0;
  2596. for (index = 0; index < p->asyncpdus_per_ctrl; index++) {
  2597. pasync_header_h->cri = -1;
  2598. pasync_header_h->index = (char)index;
  2599. INIT_LIST_HEAD(&pasync_header_h->link);
  2600. pasync_header_h->pbuffer =
  2601. (void *)((unsigned long)
  2602. (pasync_ctx->async_header.va_base) +
  2603. (p->defpdu_hdr_sz * index));
  2604. pasync_header_h->pa.u.a64.address =
  2605. pasync_ctx->async_header.pa_base.u.a64.address +
  2606. (p->defpdu_hdr_sz * index);
  2607. list_add_tail(&pasync_header_h->link,
  2608. &pasync_ctx->async_header.free_list);
  2609. pasync_header_h++;
  2610. pasync_ctx->async_header.free_entries++;
  2611. pasync_ctx->async_header.writables++;
  2612. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].wait_queue.list);
  2613. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
  2614. header_busy_list);
  2615. pasync_data_h->cri = -1;
  2616. pasync_data_h->index = (char)index;
  2617. INIT_LIST_HEAD(&pasync_data_h->link);
  2618. if (!num_async_data) {
  2619. num_per_mem = 0;
  2620. idx++;
  2621. pasync_ctx->async_data.va_base =
  2622. mem_descr->mem_array[idx].virtual_address;
  2623. pasync_ctx->async_data.pa_base.u.a64.address =
  2624. mem_descr->mem_array[idx].
  2625. bus_address.u.a64.address;
  2626. num_async_data = ((mem_descr->mem_array[idx].size) /
  2627. phba->params.defpdu_data_sz);
  2628. }
  2629. pasync_data_h->pbuffer =
  2630. (void *)((unsigned long)
  2631. (pasync_ctx->async_data.va_base) +
  2632. (p->defpdu_data_sz * num_per_mem));
  2633. pasync_data_h->pa.u.a64.address =
  2634. pasync_ctx->async_data.pa_base.u.a64.address +
  2635. (p->defpdu_data_sz * num_per_mem);
  2636. num_per_mem++;
  2637. num_async_data--;
  2638. list_add_tail(&pasync_data_h->link,
  2639. &pasync_ctx->async_data.free_list);
  2640. pasync_data_h++;
  2641. pasync_ctx->async_data.free_entries++;
  2642. pasync_ctx->async_data.writables++;
  2643. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].data_busy_list);
  2644. }
  2645. pasync_ctx->async_header.host_write_ptr = 0;
  2646. pasync_ctx->async_header.ep_read_ptr = -1;
  2647. pasync_ctx->async_data.host_write_ptr = 0;
  2648. pasync_ctx->async_data.ep_read_ptr = -1;
  2649. return 0;
  2650. }
  2651. static int
  2652. be_sgl_create_contiguous(void *virtual_address,
  2653. u64 physical_address, u32 length,
  2654. struct be_dma_mem *sgl)
  2655. {
  2656. WARN_ON(!virtual_address);
  2657. WARN_ON(!physical_address);
  2658. WARN_ON(!length > 0);
  2659. WARN_ON(!sgl);
  2660. sgl->va = virtual_address;
  2661. sgl->dma = (unsigned long)physical_address;
  2662. sgl->size = length;
  2663. return 0;
  2664. }
  2665. static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
  2666. {
  2667. memset(sgl, 0, sizeof(*sgl));
  2668. }
  2669. static void
  2670. hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
  2671. struct mem_array *pmem, struct be_dma_mem *sgl)
  2672. {
  2673. if (sgl->va)
  2674. be_sgl_destroy_contiguous(sgl);
  2675. be_sgl_create_contiguous(pmem->virtual_address,
  2676. pmem->bus_address.u.a64.address,
  2677. pmem->size, sgl);
  2678. }
  2679. static void
  2680. hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
  2681. struct mem_array *pmem, struct be_dma_mem *sgl)
  2682. {
  2683. if (sgl->va)
  2684. be_sgl_destroy_contiguous(sgl);
  2685. be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
  2686. pmem->bus_address.u.a64.address,
  2687. pmem->size, sgl);
  2688. }
  2689. static int be_fill_queue(struct be_queue_info *q,
  2690. u16 len, u16 entry_size, void *vaddress)
  2691. {
  2692. struct be_dma_mem *mem = &q->dma_mem;
  2693. memset(q, 0, sizeof(*q));
  2694. q->len = len;
  2695. q->entry_size = entry_size;
  2696. mem->size = len * entry_size;
  2697. mem->va = vaddress;
  2698. if (!mem->va)
  2699. return -ENOMEM;
  2700. memset(mem->va, 0, mem->size);
  2701. return 0;
  2702. }
  2703. static int beiscsi_create_eqs(struct beiscsi_hba *phba,
  2704. struct hwi_context_memory *phwi_context)
  2705. {
  2706. unsigned int i, num_eq_pages;
  2707. int ret = 0, eq_for_mcc;
  2708. struct be_queue_info *eq;
  2709. struct be_dma_mem *mem;
  2710. void *eq_vaddress;
  2711. dma_addr_t paddr;
  2712. num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
  2713. sizeof(struct be_eq_entry));
  2714. if (phba->msix_enabled)
  2715. eq_for_mcc = 1;
  2716. else
  2717. eq_for_mcc = 0;
  2718. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2719. eq = &phwi_context->be_eq[i].q;
  2720. mem = &eq->dma_mem;
  2721. phwi_context->be_eq[i].phba = phba;
  2722. eq_vaddress = pci_alloc_consistent(phba->pcidev,
  2723. num_eq_pages * PAGE_SIZE,
  2724. &paddr);
  2725. if (!eq_vaddress)
  2726. goto create_eq_error;
  2727. mem->va = eq_vaddress;
  2728. ret = be_fill_queue(eq, phba->params.num_eq_entries,
  2729. sizeof(struct be_eq_entry), eq_vaddress);
  2730. if (ret) {
  2731. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2732. "BM_%d : be_fill_queue Failed for EQ\n");
  2733. goto create_eq_error;
  2734. }
  2735. mem->dma = paddr;
  2736. ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
  2737. phwi_context->cur_eqd);
  2738. if (ret) {
  2739. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2740. "BM_%d : beiscsi_cmd_eq_create"
  2741. "Failed for EQ\n");
  2742. goto create_eq_error;
  2743. }
  2744. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2745. "BM_%d : eqid = %d\n",
  2746. phwi_context->be_eq[i].q.id);
  2747. }
  2748. return 0;
  2749. create_eq_error:
  2750. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2751. eq = &phwi_context->be_eq[i].q;
  2752. mem = &eq->dma_mem;
  2753. if (mem->va)
  2754. pci_free_consistent(phba->pcidev, num_eq_pages
  2755. * PAGE_SIZE,
  2756. mem->va, mem->dma);
  2757. }
  2758. return ret;
  2759. }
  2760. static int beiscsi_create_cqs(struct beiscsi_hba *phba,
  2761. struct hwi_context_memory *phwi_context)
  2762. {
  2763. unsigned int i, num_cq_pages;
  2764. int ret = 0;
  2765. struct be_queue_info *cq, *eq;
  2766. struct be_dma_mem *mem;
  2767. struct be_eq_obj *pbe_eq;
  2768. void *cq_vaddress;
  2769. dma_addr_t paddr;
  2770. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2771. sizeof(struct sol_cqe));
  2772. for (i = 0; i < phba->num_cpus; i++) {
  2773. cq = &phwi_context->be_cq[i];
  2774. eq = &phwi_context->be_eq[i].q;
  2775. pbe_eq = &phwi_context->be_eq[i];
  2776. pbe_eq->cq = cq;
  2777. pbe_eq->phba = phba;
  2778. mem = &cq->dma_mem;
  2779. cq_vaddress = pci_alloc_consistent(phba->pcidev,
  2780. num_cq_pages * PAGE_SIZE,
  2781. &paddr);
  2782. if (!cq_vaddress)
  2783. goto create_cq_error;
  2784. ret = be_fill_queue(cq, phba->params.num_cq_entries,
  2785. sizeof(struct sol_cqe), cq_vaddress);
  2786. if (ret) {
  2787. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2788. "BM_%d : be_fill_queue Failed "
  2789. "for ISCSI CQ\n");
  2790. goto create_cq_error;
  2791. }
  2792. mem->dma = paddr;
  2793. ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
  2794. false, 0);
  2795. if (ret) {
  2796. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2797. "BM_%d : beiscsi_cmd_eq_create"
  2798. "Failed for ISCSI CQ\n");
  2799. goto create_cq_error;
  2800. }
  2801. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2802. "BM_%d : iscsi cq_id is %d for eq_id %d\n"
  2803. "iSCSI CQ CREATED\n", cq->id, eq->id);
  2804. }
  2805. return 0;
  2806. create_cq_error:
  2807. for (i = 0; i < phba->num_cpus; i++) {
  2808. cq = &phwi_context->be_cq[i];
  2809. mem = &cq->dma_mem;
  2810. if (mem->va)
  2811. pci_free_consistent(phba->pcidev, num_cq_pages
  2812. * PAGE_SIZE,
  2813. mem->va, mem->dma);
  2814. }
  2815. return ret;
  2816. }
  2817. static int
  2818. beiscsi_create_def_hdr(struct beiscsi_hba *phba,
  2819. struct hwi_context_memory *phwi_context,
  2820. struct hwi_controller *phwi_ctrlr,
  2821. unsigned int def_pdu_ring_sz)
  2822. {
  2823. unsigned int idx;
  2824. int ret;
  2825. struct be_queue_info *dq, *cq;
  2826. struct be_dma_mem *mem;
  2827. struct be_mem_descriptor *mem_descr;
  2828. void *dq_vaddress;
  2829. idx = 0;
  2830. dq = &phwi_context->be_def_hdrq;
  2831. cq = &phwi_context->be_cq[0];
  2832. mem = &dq->dma_mem;
  2833. mem_descr = phba->init_mem;
  2834. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2835. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2836. ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
  2837. sizeof(struct phys_addr),
  2838. sizeof(struct phys_addr), dq_vaddress);
  2839. if (ret) {
  2840. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2841. "BM_%d : be_fill_queue Failed for DEF PDU HDR\n");
  2842. return ret;
  2843. }
  2844. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2845. bus_address.u.a64.address;
  2846. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
  2847. def_pdu_ring_sz,
  2848. phba->params.defpdu_hdr_sz);
  2849. if (ret) {
  2850. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2851. "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR\n");
  2852. return ret;
  2853. }
  2854. phwi_ctrlr->default_pdu_hdr.id = phwi_context->be_def_hdrq.id;
  2855. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2856. "BM_%d : iscsi def pdu id is %d\n",
  2857. phwi_context->be_def_hdrq.id);
  2858. hwi_post_async_buffers(phba, 1);
  2859. return 0;
  2860. }
  2861. static int
  2862. beiscsi_create_def_data(struct beiscsi_hba *phba,
  2863. struct hwi_context_memory *phwi_context,
  2864. struct hwi_controller *phwi_ctrlr,
  2865. unsigned int def_pdu_ring_sz)
  2866. {
  2867. unsigned int idx;
  2868. int ret;
  2869. struct be_queue_info *dataq, *cq;
  2870. struct be_dma_mem *mem;
  2871. struct be_mem_descriptor *mem_descr;
  2872. void *dq_vaddress;
  2873. idx = 0;
  2874. dataq = &phwi_context->be_def_dataq;
  2875. cq = &phwi_context->be_cq[0];
  2876. mem = &dataq->dma_mem;
  2877. mem_descr = phba->init_mem;
  2878. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2879. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2880. ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
  2881. sizeof(struct phys_addr),
  2882. sizeof(struct phys_addr), dq_vaddress);
  2883. if (ret) {
  2884. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2885. "BM_%d : be_fill_queue Failed for DEF PDU DATA\n");
  2886. return ret;
  2887. }
  2888. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2889. bus_address.u.a64.address;
  2890. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
  2891. def_pdu_ring_sz,
  2892. phba->params.defpdu_data_sz);
  2893. if (ret) {
  2894. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2895. "BM_%d be_cmd_create_default_pdu_queue"
  2896. " Failed for DEF PDU DATA\n");
  2897. return ret;
  2898. }
  2899. phwi_ctrlr->default_pdu_data.id = phwi_context->be_def_dataq.id;
  2900. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2901. "BM_%d : iscsi def data id is %d\n",
  2902. phwi_context->be_def_dataq.id);
  2903. hwi_post_async_buffers(phba, 0);
  2904. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2905. "BM_%d : DEFAULT PDU DATA RING CREATED\n");
  2906. return 0;
  2907. }
  2908. static int
  2909. beiscsi_post_pages(struct beiscsi_hba *phba)
  2910. {
  2911. struct be_mem_descriptor *mem_descr;
  2912. struct mem_array *pm_arr;
  2913. unsigned int page_offset, i;
  2914. struct be_dma_mem sgl;
  2915. int status;
  2916. mem_descr = phba->init_mem;
  2917. mem_descr += HWI_MEM_SGE;
  2918. pm_arr = mem_descr->mem_array;
  2919. page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
  2920. phba->fw_config.iscsi_icd_start) / PAGE_SIZE;
  2921. for (i = 0; i < mem_descr->num_elements; i++) {
  2922. hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
  2923. status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
  2924. page_offset,
  2925. (pm_arr->size / PAGE_SIZE));
  2926. page_offset += pm_arr->size / PAGE_SIZE;
  2927. if (status != 0) {
  2928. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2929. "BM_%d : post sgl failed.\n");
  2930. return status;
  2931. }
  2932. pm_arr++;
  2933. }
  2934. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2935. "BM_%d : POSTED PAGES\n");
  2936. return 0;
  2937. }
  2938. static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
  2939. {
  2940. struct be_dma_mem *mem = &q->dma_mem;
  2941. if (mem->va) {
  2942. pci_free_consistent(phba->pcidev, mem->size,
  2943. mem->va, mem->dma);
  2944. mem->va = NULL;
  2945. }
  2946. }
  2947. static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
  2948. u16 len, u16 entry_size)
  2949. {
  2950. struct be_dma_mem *mem = &q->dma_mem;
  2951. memset(q, 0, sizeof(*q));
  2952. q->len = len;
  2953. q->entry_size = entry_size;
  2954. mem->size = len * entry_size;
  2955. mem->va = pci_alloc_consistent(phba->pcidev, mem->size, &mem->dma);
  2956. if (!mem->va)
  2957. return -ENOMEM;
  2958. memset(mem->va, 0, mem->size);
  2959. return 0;
  2960. }
  2961. static int
  2962. beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
  2963. struct hwi_context_memory *phwi_context,
  2964. struct hwi_controller *phwi_ctrlr)
  2965. {
  2966. unsigned int wrb_mem_index, offset, size, num_wrb_rings;
  2967. u64 pa_addr_lo;
  2968. unsigned int idx, num, i;
  2969. struct mem_array *pwrb_arr;
  2970. void *wrb_vaddr;
  2971. struct be_dma_mem sgl;
  2972. struct be_mem_descriptor *mem_descr;
  2973. struct hwi_wrb_context *pwrb_context;
  2974. int status;
  2975. idx = 0;
  2976. mem_descr = phba->init_mem;
  2977. mem_descr += HWI_MEM_WRB;
  2978. pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
  2979. GFP_KERNEL);
  2980. if (!pwrb_arr) {
  2981. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2982. "BM_%d : Memory alloc failed in create wrb ring.\n");
  2983. return -ENOMEM;
  2984. }
  2985. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2986. pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
  2987. num_wrb_rings = mem_descr->mem_array[idx].size /
  2988. (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
  2989. for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
  2990. if (num_wrb_rings) {
  2991. pwrb_arr[num].virtual_address = wrb_vaddr;
  2992. pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
  2993. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2994. sizeof(struct iscsi_wrb);
  2995. wrb_vaddr += pwrb_arr[num].size;
  2996. pa_addr_lo += pwrb_arr[num].size;
  2997. num_wrb_rings--;
  2998. } else {
  2999. idx++;
  3000. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  3001. pa_addr_lo = mem_descr->mem_array[idx].\
  3002. bus_address.u.a64.address;
  3003. num_wrb_rings = mem_descr->mem_array[idx].size /
  3004. (phba->params.wrbs_per_cxn *
  3005. sizeof(struct iscsi_wrb));
  3006. pwrb_arr[num].virtual_address = wrb_vaddr;
  3007. pwrb_arr[num].bus_address.u.a64.address\
  3008. = pa_addr_lo;
  3009. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  3010. sizeof(struct iscsi_wrb);
  3011. wrb_vaddr += pwrb_arr[num].size;
  3012. pa_addr_lo += pwrb_arr[num].size;
  3013. num_wrb_rings--;
  3014. }
  3015. }
  3016. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3017. wrb_mem_index = 0;
  3018. offset = 0;
  3019. size = 0;
  3020. hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
  3021. status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
  3022. &phwi_context->be_wrbq[i]);
  3023. if (status != 0) {
  3024. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3025. "BM_%d : wrbq create failed.");
  3026. kfree(pwrb_arr);
  3027. return status;
  3028. }
  3029. pwrb_context = &phwi_ctrlr->wrb_context[i];
  3030. pwrb_context->cid = phwi_context->be_wrbq[i].id;
  3031. BE_SET_CID_TO_CRI(i, pwrb_context->cid);
  3032. }
  3033. kfree(pwrb_arr);
  3034. return 0;
  3035. }
  3036. static void free_wrb_handles(struct beiscsi_hba *phba)
  3037. {
  3038. unsigned int index;
  3039. struct hwi_controller *phwi_ctrlr;
  3040. struct hwi_wrb_context *pwrb_context;
  3041. phwi_ctrlr = phba->phwi_ctrlr;
  3042. for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
  3043. pwrb_context = &phwi_ctrlr->wrb_context[index];
  3044. kfree(pwrb_context->pwrb_handle_base);
  3045. kfree(pwrb_context->pwrb_handle_basestd);
  3046. }
  3047. }
  3048. static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
  3049. {
  3050. struct be_queue_info *q;
  3051. struct be_ctrl_info *ctrl = &phba->ctrl;
  3052. q = &phba->ctrl.mcc_obj.q;
  3053. if (q->created)
  3054. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
  3055. be_queue_free(phba, q);
  3056. q = &phba->ctrl.mcc_obj.cq;
  3057. if (q->created)
  3058. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  3059. be_queue_free(phba, q);
  3060. }
  3061. static void hwi_cleanup(struct beiscsi_hba *phba)
  3062. {
  3063. struct be_queue_info *q;
  3064. struct be_ctrl_info *ctrl = &phba->ctrl;
  3065. struct hwi_controller *phwi_ctrlr;
  3066. struct hwi_context_memory *phwi_context;
  3067. struct hwi_async_pdu_context *pasync_ctx;
  3068. int i, eq_num;
  3069. phwi_ctrlr = phba->phwi_ctrlr;
  3070. phwi_context = phwi_ctrlr->phwi_ctxt;
  3071. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3072. q = &phwi_context->be_wrbq[i];
  3073. if (q->created)
  3074. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
  3075. }
  3076. kfree(phwi_context->be_wrbq);
  3077. free_wrb_handles(phba);
  3078. q = &phwi_context->be_def_hdrq;
  3079. if (q->created)
  3080. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  3081. q = &phwi_context->be_def_dataq;
  3082. if (q->created)
  3083. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  3084. beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
  3085. for (i = 0; i < (phba->num_cpus); i++) {
  3086. q = &phwi_context->be_cq[i];
  3087. if (q->created)
  3088. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  3089. }
  3090. if (phba->msix_enabled)
  3091. eq_num = 1;
  3092. else
  3093. eq_num = 0;
  3094. for (i = 0; i < (phba->num_cpus + eq_num); i++) {
  3095. q = &phwi_context->be_eq[i].q;
  3096. if (q->created)
  3097. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
  3098. }
  3099. be_mcc_queues_destroy(phba);
  3100. pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx;
  3101. kfree(pasync_ctx->async_entry);
  3102. be_cmd_fw_uninit(ctrl);
  3103. }
  3104. static int be_mcc_queues_create(struct beiscsi_hba *phba,
  3105. struct hwi_context_memory *phwi_context)
  3106. {
  3107. struct be_queue_info *q, *cq;
  3108. struct be_ctrl_info *ctrl = &phba->ctrl;
  3109. /* Alloc MCC compl queue */
  3110. cq = &phba->ctrl.mcc_obj.cq;
  3111. if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
  3112. sizeof(struct be_mcc_compl)))
  3113. goto err;
  3114. /* Ask BE to create MCC compl queue; */
  3115. if (phba->msix_enabled) {
  3116. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
  3117. [phba->num_cpus].q, false, true, 0))
  3118. goto mcc_cq_free;
  3119. } else {
  3120. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
  3121. false, true, 0))
  3122. goto mcc_cq_free;
  3123. }
  3124. /* Alloc MCC queue */
  3125. q = &phba->ctrl.mcc_obj.q;
  3126. if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
  3127. goto mcc_cq_destroy;
  3128. /* Ask BE to create MCC queue */
  3129. if (beiscsi_cmd_mccq_create(phba, q, cq))
  3130. goto mcc_q_free;
  3131. return 0;
  3132. mcc_q_free:
  3133. be_queue_free(phba, q);
  3134. mcc_cq_destroy:
  3135. beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
  3136. mcc_cq_free:
  3137. be_queue_free(phba, cq);
  3138. err:
  3139. return -ENOMEM;
  3140. }
  3141. /**
  3142. * find_num_cpus()- Get the CPU online count
  3143. * @phba: ptr to priv structure
  3144. *
  3145. * CPU count is used for creating EQ.
  3146. **/
  3147. static void find_num_cpus(struct beiscsi_hba *phba)
  3148. {
  3149. int num_cpus = 0;
  3150. num_cpus = num_online_cpus();
  3151. switch (phba->generation) {
  3152. case BE_GEN2:
  3153. case BE_GEN3:
  3154. phba->num_cpus = (num_cpus > BEISCSI_MAX_NUM_CPUS) ?
  3155. BEISCSI_MAX_NUM_CPUS : num_cpus;
  3156. break;
  3157. case BE_GEN4:
  3158. phba->num_cpus = (num_cpus > OC_SKH_MAX_NUM_CPUS) ?
  3159. OC_SKH_MAX_NUM_CPUS : num_cpus;
  3160. break;
  3161. default:
  3162. phba->num_cpus = 1;
  3163. }
  3164. }
  3165. static int hwi_init_port(struct beiscsi_hba *phba)
  3166. {
  3167. struct hwi_controller *phwi_ctrlr;
  3168. struct hwi_context_memory *phwi_context;
  3169. unsigned int def_pdu_ring_sz;
  3170. struct be_ctrl_info *ctrl = &phba->ctrl;
  3171. int status;
  3172. def_pdu_ring_sz =
  3173. phba->params.asyncpdus_per_ctrl * sizeof(struct phys_addr);
  3174. phwi_ctrlr = phba->phwi_ctrlr;
  3175. phwi_context = phwi_ctrlr->phwi_ctxt;
  3176. phwi_context->max_eqd = 0;
  3177. phwi_context->min_eqd = 0;
  3178. phwi_context->cur_eqd = 64;
  3179. be_cmd_fw_initialize(&phba->ctrl);
  3180. status = beiscsi_create_eqs(phba, phwi_context);
  3181. if (status != 0) {
  3182. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3183. "BM_%d : EQ not created\n");
  3184. goto error;
  3185. }
  3186. status = be_mcc_queues_create(phba, phwi_context);
  3187. if (status != 0)
  3188. goto error;
  3189. status = mgmt_check_supported_fw(ctrl, phba);
  3190. if (status != 0) {
  3191. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3192. "BM_%d : Unsupported fw version\n");
  3193. goto error;
  3194. }
  3195. status = beiscsi_create_cqs(phba, phwi_context);
  3196. if (status != 0) {
  3197. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3198. "BM_%d : CQ not created\n");
  3199. goto error;
  3200. }
  3201. status = beiscsi_create_def_hdr(phba, phwi_context, phwi_ctrlr,
  3202. def_pdu_ring_sz);
  3203. if (status != 0) {
  3204. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3205. "BM_%d : Default Header not created\n");
  3206. goto error;
  3207. }
  3208. status = beiscsi_create_def_data(phba, phwi_context,
  3209. phwi_ctrlr, def_pdu_ring_sz);
  3210. if (status != 0) {
  3211. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3212. "BM_%d : Default Data not created\n");
  3213. goto error;
  3214. }
  3215. status = beiscsi_post_pages(phba);
  3216. if (status != 0) {
  3217. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3218. "BM_%d : Post SGL Pages Failed\n");
  3219. goto error;
  3220. }
  3221. status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
  3222. if (status != 0) {
  3223. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3224. "BM_%d : WRB Rings not created\n");
  3225. goto error;
  3226. }
  3227. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3228. "BM_%d : hwi_init_port success\n");
  3229. return 0;
  3230. error:
  3231. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3232. "BM_%d : hwi_init_port failed");
  3233. hwi_cleanup(phba);
  3234. return status;
  3235. }
  3236. static int hwi_init_controller(struct beiscsi_hba *phba)
  3237. {
  3238. struct hwi_controller *phwi_ctrlr;
  3239. phwi_ctrlr = phba->phwi_ctrlr;
  3240. if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
  3241. phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
  3242. init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
  3243. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3244. "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n",
  3245. phwi_ctrlr->phwi_ctxt);
  3246. } else {
  3247. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3248. "BM_%d : HWI_MEM_ADDN_CONTEXT is more "
  3249. "than one element.Failing to load\n");
  3250. return -ENOMEM;
  3251. }
  3252. iscsi_init_global_templates(phba);
  3253. if (beiscsi_init_wrb_handle(phba))
  3254. return -ENOMEM;
  3255. if (hwi_init_async_pdu_ctx(phba)) {
  3256. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3257. "BM_%d : hwi_init_async_pdu_ctx failed\n");
  3258. return -ENOMEM;
  3259. }
  3260. if (hwi_init_port(phba) != 0) {
  3261. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3262. "BM_%d : hwi_init_controller failed\n");
  3263. return -ENOMEM;
  3264. }
  3265. return 0;
  3266. }
  3267. static void beiscsi_free_mem(struct beiscsi_hba *phba)
  3268. {
  3269. struct be_mem_descriptor *mem_descr;
  3270. int i, j;
  3271. mem_descr = phba->init_mem;
  3272. i = 0;
  3273. j = 0;
  3274. for (i = 0; i < SE_MEM_MAX; i++) {
  3275. for (j = mem_descr->num_elements; j > 0; j--) {
  3276. pci_free_consistent(phba->pcidev,
  3277. mem_descr->mem_array[j - 1].size,
  3278. mem_descr->mem_array[j - 1].virtual_address,
  3279. (unsigned long)mem_descr->mem_array[j - 1].
  3280. bus_address.u.a64.address);
  3281. }
  3282. kfree(mem_descr->mem_array);
  3283. mem_descr++;
  3284. }
  3285. kfree(phba->init_mem);
  3286. kfree(phba->phwi_ctrlr->wrb_context);
  3287. kfree(phba->phwi_ctrlr);
  3288. }
  3289. static int beiscsi_init_controller(struct beiscsi_hba *phba)
  3290. {
  3291. int ret = -ENOMEM;
  3292. ret = beiscsi_get_memory(phba);
  3293. if (ret < 0) {
  3294. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3295. "BM_%d : beiscsi_dev_probe -"
  3296. "Failed in beiscsi_alloc_memory\n");
  3297. return ret;
  3298. }
  3299. ret = hwi_init_controller(phba);
  3300. if (ret)
  3301. goto free_init;
  3302. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3303. "BM_%d : Return success from beiscsi_init_controller");
  3304. return 0;
  3305. free_init:
  3306. beiscsi_free_mem(phba);
  3307. return ret;
  3308. }
  3309. static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
  3310. {
  3311. struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
  3312. struct sgl_handle *psgl_handle;
  3313. struct iscsi_sge *pfrag;
  3314. unsigned int arr_index, i, idx;
  3315. phba->io_sgl_hndl_avbl = 0;
  3316. phba->eh_sgl_hndl_avbl = 0;
  3317. mem_descr_sglh = phba->init_mem;
  3318. mem_descr_sglh += HWI_MEM_SGLH;
  3319. if (1 == mem_descr_sglh->num_elements) {
  3320. phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3321. phba->params.ios_per_ctrl,
  3322. GFP_KERNEL);
  3323. if (!phba->io_sgl_hndl_base) {
  3324. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3325. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3326. return -ENOMEM;
  3327. }
  3328. phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3329. (phba->params.icds_per_ctrl -
  3330. phba->params.ios_per_ctrl),
  3331. GFP_KERNEL);
  3332. if (!phba->eh_sgl_hndl_base) {
  3333. kfree(phba->io_sgl_hndl_base);
  3334. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3335. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3336. return -ENOMEM;
  3337. }
  3338. } else {
  3339. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3340. "BM_%d : HWI_MEM_SGLH is more than one element."
  3341. "Failing to load\n");
  3342. return -ENOMEM;
  3343. }
  3344. arr_index = 0;
  3345. idx = 0;
  3346. while (idx < mem_descr_sglh->num_elements) {
  3347. psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
  3348. for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
  3349. sizeof(struct sgl_handle)); i++) {
  3350. if (arr_index < phba->params.ios_per_ctrl) {
  3351. phba->io_sgl_hndl_base[arr_index] = psgl_handle;
  3352. phba->io_sgl_hndl_avbl++;
  3353. arr_index++;
  3354. } else {
  3355. phba->eh_sgl_hndl_base[arr_index -
  3356. phba->params.ios_per_ctrl] =
  3357. psgl_handle;
  3358. arr_index++;
  3359. phba->eh_sgl_hndl_avbl++;
  3360. }
  3361. psgl_handle++;
  3362. }
  3363. idx++;
  3364. }
  3365. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3366. "BM_%d : phba->io_sgl_hndl_avbl=%d"
  3367. "phba->eh_sgl_hndl_avbl=%d\n",
  3368. phba->io_sgl_hndl_avbl,
  3369. phba->eh_sgl_hndl_avbl);
  3370. mem_descr_sg = phba->init_mem;
  3371. mem_descr_sg += HWI_MEM_SGE;
  3372. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3373. "\n BM_%d : mem_descr_sg->num_elements=%d\n",
  3374. mem_descr_sg->num_elements);
  3375. arr_index = 0;
  3376. idx = 0;
  3377. while (idx < mem_descr_sg->num_elements) {
  3378. pfrag = mem_descr_sg->mem_array[idx].virtual_address;
  3379. for (i = 0;
  3380. i < (mem_descr_sg->mem_array[idx].size) /
  3381. (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
  3382. i++) {
  3383. if (arr_index < phba->params.ios_per_ctrl)
  3384. psgl_handle = phba->io_sgl_hndl_base[arr_index];
  3385. else
  3386. psgl_handle = phba->eh_sgl_hndl_base[arr_index -
  3387. phba->params.ios_per_ctrl];
  3388. psgl_handle->pfrag = pfrag;
  3389. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
  3390. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
  3391. pfrag += phba->params.num_sge_per_io;
  3392. psgl_handle->sgl_index =
  3393. phba->fw_config.iscsi_icd_start + arr_index++;
  3394. }
  3395. idx++;
  3396. }
  3397. phba->io_sgl_free_index = 0;
  3398. phba->io_sgl_alloc_index = 0;
  3399. phba->eh_sgl_free_index = 0;
  3400. phba->eh_sgl_alloc_index = 0;
  3401. return 0;
  3402. }
  3403. static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
  3404. {
  3405. int i;
  3406. phba->cid_array = kzalloc(sizeof(void *) * phba->params.cxns_per_ctrl,
  3407. GFP_KERNEL);
  3408. if (!phba->cid_array) {
  3409. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3410. "BM_%d : Failed to allocate memory in "
  3411. "hba_setup_cid_tbls\n");
  3412. return -ENOMEM;
  3413. }
  3414. phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
  3415. phba->params.cxns_per_ctrl, GFP_KERNEL);
  3416. if (!phba->ep_array) {
  3417. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3418. "BM_%d : Failed to allocate memory in "
  3419. "hba_setup_cid_tbls\n");
  3420. kfree(phba->cid_array);
  3421. phba->cid_array = NULL;
  3422. return -ENOMEM;
  3423. }
  3424. phba->conn_table = kzalloc(sizeof(struct beiscsi_conn *) *
  3425. phba->params.cxns_per_ctrl, GFP_KERNEL);
  3426. if (!phba->conn_table) {
  3427. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3428. "BM_%d : Failed to allocate memory in"
  3429. "hba_setup_cid_tbls\n");
  3430. kfree(phba->cid_array);
  3431. kfree(phba->ep_array);
  3432. phba->cid_array = NULL;
  3433. phba->ep_array = NULL;
  3434. return -ENOMEM;
  3435. }
  3436. for (i = 0; i < phba->params.cxns_per_ctrl; i++)
  3437. phba->cid_array[i] = phba->phwi_ctrlr->wrb_context[i].cid;
  3438. phba->avlbl_cids = phba->params.cxns_per_ctrl;
  3439. return 0;
  3440. }
  3441. static void hwi_enable_intr(struct beiscsi_hba *phba)
  3442. {
  3443. struct be_ctrl_info *ctrl = &phba->ctrl;
  3444. struct hwi_controller *phwi_ctrlr;
  3445. struct hwi_context_memory *phwi_context;
  3446. struct be_queue_info *eq;
  3447. u8 __iomem *addr;
  3448. u32 reg, i;
  3449. u32 enabled;
  3450. phwi_ctrlr = phba->phwi_ctrlr;
  3451. phwi_context = phwi_ctrlr->phwi_ctxt;
  3452. addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
  3453. PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
  3454. reg = ioread32(addr);
  3455. enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3456. if (!enabled) {
  3457. reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3458. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3459. "BM_%d : reg =x%08x addr=%p\n", reg, addr);
  3460. iowrite32(reg, addr);
  3461. }
  3462. if (!phba->msix_enabled) {
  3463. eq = &phwi_context->be_eq[0].q;
  3464. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3465. "BM_%d : eq->id=%d\n", eq->id);
  3466. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3467. } else {
  3468. for (i = 0; i <= phba->num_cpus; i++) {
  3469. eq = &phwi_context->be_eq[i].q;
  3470. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3471. "BM_%d : eq->id=%d\n", eq->id);
  3472. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3473. }
  3474. }
  3475. }
  3476. static void hwi_disable_intr(struct beiscsi_hba *phba)
  3477. {
  3478. struct be_ctrl_info *ctrl = &phba->ctrl;
  3479. u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
  3480. u32 reg = ioread32(addr);
  3481. u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3482. if (enabled) {
  3483. reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3484. iowrite32(reg, addr);
  3485. } else
  3486. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3487. "BM_%d : In hwi_disable_intr, Already Disabled\n");
  3488. }
  3489. /**
  3490. * beiscsi_get_boot_info()- Get the boot session info
  3491. * @phba: The device priv structure instance
  3492. *
  3493. * Get the boot target info and store in driver priv structure
  3494. *
  3495. * return values
  3496. * Success: 0
  3497. * Failure: Non-Zero Value
  3498. **/
  3499. static int beiscsi_get_boot_info(struct beiscsi_hba *phba)
  3500. {
  3501. struct be_cmd_get_session_resp *session_resp;
  3502. struct be_dma_mem nonemb_cmd;
  3503. unsigned int tag;
  3504. unsigned int s_handle;
  3505. int ret = -ENOMEM;
  3506. /* Get the session handle of the boot target */
  3507. ret = be_mgmt_get_boot_shandle(phba, &s_handle);
  3508. if (ret) {
  3509. beiscsi_log(phba, KERN_ERR,
  3510. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3511. "BM_%d : No boot session\n");
  3512. return ret;
  3513. }
  3514. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  3515. sizeof(*session_resp),
  3516. &nonemb_cmd.dma);
  3517. if (nonemb_cmd.va == NULL) {
  3518. beiscsi_log(phba, KERN_ERR,
  3519. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3520. "BM_%d : Failed to allocate memory for"
  3521. "beiscsi_get_session_info\n");
  3522. return -ENOMEM;
  3523. }
  3524. memset(nonemb_cmd.va, 0, sizeof(*session_resp));
  3525. tag = mgmt_get_session_info(phba, s_handle,
  3526. &nonemb_cmd);
  3527. if (!tag) {
  3528. beiscsi_log(phba, KERN_ERR,
  3529. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3530. "BM_%d : beiscsi_get_session_info"
  3531. " Failed\n");
  3532. goto boot_freemem;
  3533. }
  3534. ret = beiscsi_mccq_compl(phba, tag, NULL, nonemb_cmd.va);
  3535. if (ret) {
  3536. beiscsi_log(phba, KERN_ERR,
  3537. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3538. "BM_%d : beiscsi_get_session_info Failed");
  3539. goto boot_freemem;
  3540. }
  3541. session_resp = nonemb_cmd.va ;
  3542. memcpy(&phba->boot_sess, &session_resp->session_info,
  3543. sizeof(struct mgmt_session_info));
  3544. ret = 0;
  3545. boot_freemem:
  3546. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3547. nonemb_cmd.va, nonemb_cmd.dma);
  3548. return ret;
  3549. }
  3550. static void beiscsi_boot_release(void *data)
  3551. {
  3552. struct beiscsi_hba *phba = data;
  3553. scsi_host_put(phba->shost);
  3554. }
  3555. static int beiscsi_setup_boot_info(struct beiscsi_hba *phba)
  3556. {
  3557. struct iscsi_boot_kobj *boot_kobj;
  3558. /* get boot info using mgmt cmd */
  3559. if (beiscsi_get_boot_info(phba))
  3560. /* Try to see if we can carry on without this */
  3561. return 0;
  3562. phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
  3563. if (!phba->boot_kset)
  3564. return -ENOMEM;
  3565. /* get a ref because the show function will ref the phba */
  3566. if (!scsi_host_get(phba->shost))
  3567. goto free_kset;
  3568. boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba,
  3569. beiscsi_show_boot_tgt_info,
  3570. beiscsi_tgt_get_attr_visibility,
  3571. beiscsi_boot_release);
  3572. if (!boot_kobj)
  3573. goto put_shost;
  3574. if (!scsi_host_get(phba->shost))
  3575. goto free_kset;
  3576. boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba,
  3577. beiscsi_show_boot_ini_info,
  3578. beiscsi_ini_get_attr_visibility,
  3579. beiscsi_boot_release);
  3580. if (!boot_kobj)
  3581. goto put_shost;
  3582. if (!scsi_host_get(phba->shost))
  3583. goto free_kset;
  3584. boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba,
  3585. beiscsi_show_boot_eth_info,
  3586. beiscsi_eth_get_attr_visibility,
  3587. beiscsi_boot_release);
  3588. if (!boot_kobj)
  3589. goto put_shost;
  3590. return 0;
  3591. put_shost:
  3592. scsi_host_put(phba->shost);
  3593. free_kset:
  3594. iscsi_boot_destroy_kset(phba->boot_kset);
  3595. return -ENOMEM;
  3596. }
  3597. static int beiscsi_init_port(struct beiscsi_hba *phba)
  3598. {
  3599. int ret;
  3600. ret = beiscsi_init_controller(phba);
  3601. if (ret < 0) {
  3602. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3603. "BM_%d : beiscsi_dev_probe - Failed in"
  3604. "beiscsi_init_controller\n");
  3605. return ret;
  3606. }
  3607. ret = beiscsi_init_sgl_handle(phba);
  3608. if (ret < 0) {
  3609. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3610. "BM_%d : beiscsi_dev_probe - Failed in"
  3611. "beiscsi_init_sgl_handle\n");
  3612. goto do_cleanup_ctrlr;
  3613. }
  3614. if (hba_setup_cid_tbls(phba)) {
  3615. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3616. "BM_%d : Failed in hba_setup_cid_tbls\n");
  3617. kfree(phba->io_sgl_hndl_base);
  3618. kfree(phba->eh_sgl_hndl_base);
  3619. goto do_cleanup_ctrlr;
  3620. }
  3621. return ret;
  3622. do_cleanup_ctrlr:
  3623. hwi_cleanup(phba);
  3624. return ret;
  3625. }
  3626. static void hwi_purge_eq(struct beiscsi_hba *phba)
  3627. {
  3628. struct hwi_controller *phwi_ctrlr;
  3629. struct hwi_context_memory *phwi_context;
  3630. struct be_queue_info *eq;
  3631. struct be_eq_entry *eqe = NULL;
  3632. int i, eq_msix;
  3633. unsigned int num_processed;
  3634. phwi_ctrlr = phba->phwi_ctrlr;
  3635. phwi_context = phwi_ctrlr->phwi_ctxt;
  3636. if (phba->msix_enabled)
  3637. eq_msix = 1;
  3638. else
  3639. eq_msix = 0;
  3640. for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
  3641. eq = &phwi_context->be_eq[i].q;
  3642. eqe = queue_tail_node(eq);
  3643. num_processed = 0;
  3644. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  3645. & EQE_VALID_MASK) {
  3646. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  3647. queue_tail_inc(eq);
  3648. eqe = queue_tail_node(eq);
  3649. num_processed++;
  3650. }
  3651. if (num_processed)
  3652. hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
  3653. }
  3654. }
  3655. static void beiscsi_clean_port(struct beiscsi_hba *phba)
  3656. {
  3657. int mgmt_status;
  3658. mgmt_status = mgmt_epfw_cleanup(phba, CMD_CONNECTION_CHUTE_0);
  3659. if (mgmt_status)
  3660. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3661. "BM_%d : mgmt_epfw_cleanup FAILED\n");
  3662. hwi_purge_eq(phba);
  3663. hwi_cleanup(phba);
  3664. kfree(phba->io_sgl_hndl_base);
  3665. kfree(phba->eh_sgl_hndl_base);
  3666. kfree(phba->cid_array);
  3667. kfree(phba->ep_array);
  3668. kfree(phba->conn_table);
  3669. }
  3670. /**
  3671. * beiscsi_free_mgmt_task_handles()- Free driver CXN resources
  3672. * @beiscsi_conn: ptr to the conn to be cleaned up
  3673. * @task: ptr to iscsi_task resource to be freed.
  3674. *
  3675. * Free driver mgmt resources binded to CXN.
  3676. **/
  3677. void
  3678. beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
  3679. struct iscsi_task *task)
  3680. {
  3681. struct beiscsi_io_task *io_task;
  3682. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3683. struct hwi_wrb_context *pwrb_context;
  3684. struct hwi_controller *phwi_ctrlr;
  3685. uint16_t cri_index = BE_GET_CRI_FROM_CID(
  3686. beiscsi_conn->beiscsi_conn_cid);
  3687. phwi_ctrlr = phba->phwi_ctrlr;
  3688. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  3689. io_task = task->dd_data;
  3690. if (io_task->pwrb_handle) {
  3691. memset(io_task->pwrb_handle->pwrb, 0,
  3692. sizeof(struct iscsi_wrb));
  3693. free_wrb_handle(phba, pwrb_context,
  3694. io_task->pwrb_handle);
  3695. io_task->pwrb_handle = NULL;
  3696. }
  3697. if (io_task->psgl_handle) {
  3698. spin_lock_bh(&phba->mgmt_sgl_lock);
  3699. free_mgmt_sgl_handle(phba,
  3700. io_task->psgl_handle);
  3701. io_task->psgl_handle = NULL;
  3702. spin_unlock_bh(&phba->mgmt_sgl_lock);
  3703. }
  3704. if (io_task->mtask_addr)
  3705. pci_unmap_single(phba->pcidev,
  3706. io_task->mtask_addr,
  3707. io_task->mtask_data_count,
  3708. PCI_DMA_TODEVICE);
  3709. }
  3710. /**
  3711. * beiscsi_cleanup_task()- Free driver resources of the task
  3712. * @task: ptr to the iscsi task
  3713. *
  3714. **/
  3715. static void beiscsi_cleanup_task(struct iscsi_task *task)
  3716. {
  3717. struct beiscsi_io_task *io_task = task->dd_data;
  3718. struct iscsi_conn *conn = task->conn;
  3719. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3720. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3721. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3722. struct hwi_wrb_context *pwrb_context;
  3723. struct hwi_controller *phwi_ctrlr;
  3724. uint16_t cri_index = BE_GET_CRI_FROM_CID(
  3725. beiscsi_conn->beiscsi_conn_cid);
  3726. phwi_ctrlr = phba->phwi_ctrlr;
  3727. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  3728. if (io_task->cmd_bhs) {
  3729. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3730. io_task->bhs_pa.u.a64.address);
  3731. io_task->cmd_bhs = NULL;
  3732. }
  3733. if (task->sc) {
  3734. if (io_task->pwrb_handle) {
  3735. free_wrb_handle(phba, pwrb_context,
  3736. io_task->pwrb_handle);
  3737. io_task->pwrb_handle = NULL;
  3738. }
  3739. if (io_task->psgl_handle) {
  3740. spin_lock(&phba->io_sgl_lock);
  3741. free_io_sgl_handle(phba, io_task->psgl_handle);
  3742. spin_unlock(&phba->io_sgl_lock);
  3743. io_task->psgl_handle = NULL;
  3744. }
  3745. } else {
  3746. if (!beiscsi_conn->login_in_progress)
  3747. beiscsi_free_mgmt_task_handles(beiscsi_conn, task);
  3748. }
  3749. }
  3750. void
  3751. beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
  3752. struct beiscsi_offload_params *params)
  3753. {
  3754. struct wrb_handle *pwrb_handle;
  3755. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3756. struct iscsi_task *task = beiscsi_conn->task;
  3757. struct iscsi_session *session = task->conn->session;
  3758. u32 doorbell = 0;
  3759. /*
  3760. * We can always use 0 here because it is reserved by libiscsi for
  3761. * login/startup related tasks.
  3762. */
  3763. beiscsi_conn->login_in_progress = 0;
  3764. spin_lock_bh(&session->lock);
  3765. beiscsi_cleanup_task(task);
  3766. spin_unlock_bh(&session->lock);
  3767. pwrb_handle = alloc_wrb_handle(phba, beiscsi_conn->beiscsi_conn_cid);
  3768. /* Check for the adapter family */
  3769. if (is_chip_be2_be3r(phba))
  3770. beiscsi_offload_cxn_v0(params, pwrb_handle,
  3771. phba->init_mem);
  3772. else
  3773. beiscsi_offload_cxn_v2(params, pwrb_handle);
  3774. be_dws_le_to_cpu(pwrb_handle->pwrb,
  3775. sizeof(struct iscsi_target_context_update_wrb));
  3776. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3777. doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
  3778. << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3779. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3780. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3781. }
  3782. static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
  3783. int *index, int *age)
  3784. {
  3785. *index = (int)itt;
  3786. if (age)
  3787. *age = conn->session->age;
  3788. }
  3789. /**
  3790. * beiscsi_alloc_pdu - allocates pdu and related resources
  3791. * @task: libiscsi task
  3792. * @opcode: opcode of pdu for task
  3793. *
  3794. * This is called with the session lock held. It will allocate
  3795. * the wrb and sgl if needed for the command. And it will prep
  3796. * the pdu's itt. beiscsi_parse_pdu will later translate
  3797. * the pdu itt to the libiscsi task itt.
  3798. */
  3799. static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
  3800. {
  3801. struct beiscsi_io_task *io_task = task->dd_data;
  3802. struct iscsi_conn *conn = task->conn;
  3803. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3804. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3805. struct hwi_wrb_context *pwrb_context;
  3806. struct hwi_controller *phwi_ctrlr;
  3807. itt_t itt;
  3808. uint16_t cri_index = 0;
  3809. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3810. dma_addr_t paddr;
  3811. io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
  3812. GFP_ATOMIC, &paddr);
  3813. if (!io_task->cmd_bhs)
  3814. return -ENOMEM;
  3815. io_task->bhs_pa.u.a64.address = paddr;
  3816. io_task->libiscsi_itt = (itt_t)task->itt;
  3817. io_task->conn = beiscsi_conn;
  3818. task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
  3819. task->hdr_max = sizeof(struct be_cmd_bhs);
  3820. io_task->psgl_handle = NULL;
  3821. io_task->pwrb_handle = NULL;
  3822. if (task->sc) {
  3823. spin_lock(&phba->io_sgl_lock);
  3824. io_task->psgl_handle = alloc_io_sgl_handle(phba);
  3825. spin_unlock(&phba->io_sgl_lock);
  3826. if (!io_task->psgl_handle) {
  3827. beiscsi_log(phba, KERN_ERR,
  3828. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3829. "BM_%d : Alloc of IO_SGL_ICD Failed"
  3830. "for the CID : %d\n",
  3831. beiscsi_conn->beiscsi_conn_cid);
  3832. goto free_hndls;
  3833. }
  3834. io_task->pwrb_handle = alloc_wrb_handle(phba,
  3835. beiscsi_conn->beiscsi_conn_cid);
  3836. if (!io_task->pwrb_handle) {
  3837. beiscsi_log(phba, KERN_ERR,
  3838. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3839. "BM_%d : Alloc of WRB_HANDLE Failed"
  3840. "for the CID : %d\n",
  3841. beiscsi_conn->beiscsi_conn_cid);
  3842. goto free_io_hndls;
  3843. }
  3844. } else {
  3845. io_task->scsi_cmnd = NULL;
  3846. if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
  3847. beiscsi_conn->task = task;
  3848. if (!beiscsi_conn->login_in_progress) {
  3849. spin_lock(&phba->mgmt_sgl_lock);
  3850. io_task->psgl_handle = (struct sgl_handle *)
  3851. alloc_mgmt_sgl_handle(phba);
  3852. spin_unlock(&phba->mgmt_sgl_lock);
  3853. if (!io_task->psgl_handle) {
  3854. beiscsi_log(phba, KERN_ERR,
  3855. BEISCSI_LOG_IO |
  3856. BEISCSI_LOG_CONFIG,
  3857. "BM_%d : Alloc of MGMT_SGL_ICD Failed"
  3858. "for the CID : %d\n",
  3859. beiscsi_conn->
  3860. beiscsi_conn_cid);
  3861. goto free_hndls;
  3862. }
  3863. beiscsi_conn->login_in_progress = 1;
  3864. beiscsi_conn->plogin_sgl_handle =
  3865. io_task->psgl_handle;
  3866. io_task->pwrb_handle =
  3867. alloc_wrb_handle(phba,
  3868. beiscsi_conn->beiscsi_conn_cid);
  3869. if (!io_task->pwrb_handle) {
  3870. beiscsi_log(phba, KERN_ERR,
  3871. BEISCSI_LOG_IO |
  3872. BEISCSI_LOG_CONFIG,
  3873. "BM_%d : Alloc of WRB_HANDLE Failed"
  3874. "for the CID : %d\n",
  3875. beiscsi_conn->
  3876. beiscsi_conn_cid);
  3877. goto free_mgmt_hndls;
  3878. }
  3879. beiscsi_conn->plogin_wrb_handle =
  3880. io_task->pwrb_handle;
  3881. } else {
  3882. io_task->psgl_handle =
  3883. beiscsi_conn->plogin_sgl_handle;
  3884. io_task->pwrb_handle =
  3885. beiscsi_conn->plogin_wrb_handle;
  3886. }
  3887. } else {
  3888. spin_lock(&phba->mgmt_sgl_lock);
  3889. io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
  3890. spin_unlock(&phba->mgmt_sgl_lock);
  3891. if (!io_task->psgl_handle) {
  3892. beiscsi_log(phba, KERN_ERR,
  3893. BEISCSI_LOG_IO |
  3894. BEISCSI_LOG_CONFIG,
  3895. "BM_%d : Alloc of MGMT_SGL_ICD Failed"
  3896. "for the CID : %d\n",
  3897. beiscsi_conn->
  3898. beiscsi_conn_cid);
  3899. goto free_hndls;
  3900. }
  3901. io_task->pwrb_handle =
  3902. alloc_wrb_handle(phba,
  3903. beiscsi_conn->beiscsi_conn_cid);
  3904. if (!io_task->pwrb_handle) {
  3905. beiscsi_log(phba, KERN_ERR,
  3906. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3907. "BM_%d : Alloc of WRB_HANDLE Failed"
  3908. "for the CID : %d\n",
  3909. beiscsi_conn->beiscsi_conn_cid);
  3910. goto free_mgmt_hndls;
  3911. }
  3912. }
  3913. }
  3914. itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
  3915. wrb_index << 16) | (unsigned int)
  3916. (io_task->psgl_handle->sgl_index));
  3917. io_task->pwrb_handle->pio_handle = task;
  3918. io_task->cmd_bhs->iscsi_hdr.itt = itt;
  3919. return 0;
  3920. free_io_hndls:
  3921. spin_lock(&phba->io_sgl_lock);
  3922. free_io_sgl_handle(phba, io_task->psgl_handle);
  3923. spin_unlock(&phba->io_sgl_lock);
  3924. goto free_hndls;
  3925. free_mgmt_hndls:
  3926. spin_lock(&phba->mgmt_sgl_lock);
  3927. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  3928. io_task->psgl_handle = NULL;
  3929. spin_unlock(&phba->mgmt_sgl_lock);
  3930. free_hndls:
  3931. phwi_ctrlr = phba->phwi_ctrlr;
  3932. cri_index = BE_GET_CRI_FROM_CID(
  3933. beiscsi_conn->beiscsi_conn_cid);
  3934. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  3935. if (io_task->pwrb_handle)
  3936. free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
  3937. io_task->pwrb_handle = NULL;
  3938. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3939. io_task->bhs_pa.u.a64.address);
  3940. io_task->cmd_bhs = NULL;
  3941. return -ENOMEM;
  3942. }
  3943. int beiscsi_iotask_v2(struct iscsi_task *task, struct scatterlist *sg,
  3944. unsigned int num_sg, unsigned int xferlen,
  3945. unsigned int writedir)
  3946. {
  3947. struct beiscsi_io_task *io_task = task->dd_data;
  3948. struct iscsi_conn *conn = task->conn;
  3949. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3950. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3951. struct iscsi_wrb *pwrb = NULL;
  3952. unsigned int doorbell = 0;
  3953. pwrb = io_task->pwrb_handle->pwrb;
  3954. io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
  3955. io_task->bhs_len = sizeof(struct be_cmd_bhs);
  3956. if (writedir) {
  3957. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
  3958. INI_WR_CMD);
  3959. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 1);
  3960. } else {
  3961. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
  3962. INI_RD_CMD);
  3963. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 0);
  3964. }
  3965. io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb_v2,
  3966. type, pwrb);
  3967. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, lun, pwrb,
  3968. cpu_to_be16(*(unsigned short *)
  3969. &io_task->cmd_bhs->iscsi_hdr.lun));
  3970. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, xferlen);
  3971. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
  3972. io_task->pwrb_handle->wrb_index);
  3973. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
  3974. be32_to_cpu(task->cmdsn));
  3975. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
  3976. io_task->psgl_handle->sgl_index);
  3977. hwi_write_sgl_v2(pwrb, sg, num_sg, io_task);
  3978. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
  3979. io_task->pwrb_handle->nxt_wrb_index);
  3980. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3981. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3982. doorbell |= (io_task->pwrb_handle->wrb_index &
  3983. DB_DEF_PDU_WRB_INDEX_MASK) <<
  3984. DB_DEF_PDU_WRB_INDEX_SHIFT;
  3985. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3986. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3987. return 0;
  3988. }
  3989. static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
  3990. unsigned int num_sg, unsigned int xferlen,
  3991. unsigned int writedir)
  3992. {
  3993. struct beiscsi_io_task *io_task = task->dd_data;
  3994. struct iscsi_conn *conn = task->conn;
  3995. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3996. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3997. struct iscsi_wrb *pwrb = NULL;
  3998. unsigned int doorbell = 0;
  3999. pwrb = io_task->pwrb_handle->pwrb;
  4000. io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
  4001. io_task->bhs_len = sizeof(struct be_cmd_bhs);
  4002. if (writedir) {
  4003. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  4004. INI_WR_CMD);
  4005. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  4006. } else {
  4007. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  4008. INI_RD_CMD);
  4009. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  4010. }
  4011. io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb,
  4012. type, pwrb);
  4013. AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
  4014. cpu_to_be16(*(unsigned short *)
  4015. &io_task->cmd_bhs->iscsi_hdr.lun));
  4016. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
  4017. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  4018. io_task->pwrb_handle->wrb_index);
  4019. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  4020. be32_to_cpu(task->cmdsn));
  4021. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  4022. io_task->psgl_handle->sgl_index);
  4023. hwi_write_sgl(pwrb, sg, num_sg, io_task);
  4024. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  4025. io_task->pwrb_handle->nxt_wrb_index);
  4026. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  4027. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  4028. doorbell |= (io_task->pwrb_handle->wrb_index &
  4029. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  4030. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  4031. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  4032. return 0;
  4033. }
  4034. static int beiscsi_mtask(struct iscsi_task *task)
  4035. {
  4036. struct beiscsi_io_task *io_task = task->dd_data;
  4037. struct iscsi_conn *conn = task->conn;
  4038. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  4039. struct beiscsi_hba *phba = beiscsi_conn->phba;
  4040. struct iscsi_wrb *pwrb = NULL;
  4041. unsigned int doorbell = 0;
  4042. unsigned int cid;
  4043. unsigned int pwrb_typeoffset = 0;
  4044. cid = beiscsi_conn->beiscsi_conn_cid;
  4045. pwrb = io_task->pwrb_handle->pwrb;
  4046. memset(pwrb, 0, sizeof(*pwrb));
  4047. if (is_chip_be2_be3r(phba)) {
  4048. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  4049. be32_to_cpu(task->cmdsn));
  4050. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  4051. io_task->pwrb_handle->wrb_index);
  4052. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  4053. io_task->psgl_handle->sgl_index);
  4054. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
  4055. task->data_count);
  4056. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  4057. io_task->pwrb_handle->nxt_wrb_index);
  4058. pwrb_typeoffset = BE_WRB_TYPE_OFFSET;
  4059. } else {
  4060. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
  4061. be32_to_cpu(task->cmdsn));
  4062. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
  4063. io_task->pwrb_handle->wrb_index);
  4064. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
  4065. io_task->psgl_handle->sgl_index);
  4066. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb,
  4067. task->data_count);
  4068. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
  4069. io_task->pwrb_handle->nxt_wrb_index);
  4070. pwrb_typeoffset = SKH_WRB_TYPE_OFFSET;
  4071. }
  4072. switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
  4073. case ISCSI_OP_LOGIN:
  4074. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
  4075. ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
  4076. hwi_write_buffer(pwrb, task);
  4077. break;
  4078. case ISCSI_OP_NOOP_OUT:
  4079. if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
  4080. ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
  4081. if (is_chip_be2_be3r(phba))
  4082. AMAP_SET_BITS(struct amap_iscsi_wrb,
  4083. dmsg, pwrb, 1);
  4084. else
  4085. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  4086. dmsg, pwrb, 1);
  4087. } else {
  4088. ADAPTER_SET_WRB_TYPE(pwrb, INI_RD_CMD, pwrb_typeoffset);
  4089. if (is_chip_be2_be3r(phba))
  4090. AMAP_SET_BITS(struct amap_iscsi_wrb,
  4091. dmsg, pwrb, 0);
  4092. else
  4093. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  4094. dmsg, pwrb, 0);
  4095. }
  4096. hwi_write_buffer(pwrb, task);
  4097. break;
  4098. case ISCSI_OP_TEXT:
  4099. ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
  4100. hwi_write_buffer(pwrb, task);
  4101. break;
  4102. case ISCSI_OP_SCSI_TMFUNC:
  4103. ADAPTER_SET_WRB_TYPE(pwrb, INI_TMF_CMD, pwrb_typeoffset);
  4104. hwi_write_buffer(pwrb, task);
  4105. break;
  4106. case ISCSI_OP_LOGOUT:
  4107. ADAPTER_SET_WRB_TYPE(pwrb, HWH_TYPE_LOGOUT, pwrb_typeoffset);
  4108. hwi_write_buffer(pwrb, task);
  4109. break;
  4110. default:
  4111. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4112. "BM_%d : opcode =%d Not supported\n",
  4113. task->hdr->opcode & ISCSI_OPCODE_MASK);
  4114. return -EINVAL;
  4115. }
  4116. /* Set the task type */
  4117. io_task->wrb_type = (is_chip_be2_be3r(phba)) ?
  4118. AMAP_GET_BITS(struct amap_iscsi_wrb, type, pwrb) :
  4119. AMAP_GET_BITS(struct amap_iscsi_wrb_v2, type, pwrb);
  4120. doorbell |= cid & DB_WRB_POST_CID_MASK;
  4121. doorbell |= (io_task->pwrb_handle->wrb_index &
  4122. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  4123. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  4124. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  4125. return 0;
  4126. }
  4127. static int beiscsi_task_xmit(struct iscsi_task *task)
  4128. {
  4129. struct beiscsi_io_task *io_task = task->dd_data;
  4130. struct scsi_cmnd *sc = task->sc;
  4131. struct beiscsi_hba *phba = NULL;
  4132. struct scatterlist *sg;
  4133. int num_sg;
  4134. unsigned int writedir = 0, xferlen = 0;
  4135. phba = ((struct beiscsi_conn *)task->conn->dd_data)->phba;
  4136. if (!sc)
  4137. return beiscsi_mtask(task);
  4138. io_task->scsi_cmnd = sc;
  4139. num_sg = scsi_dma_map(sc);
  4140. if (num_sg < 0) {
  4141. struct iscsi_conn *conn = task->conn;
  4142. struct beiscsi_hba *phba = NULL;
  4143. phba = ((struct beiscsi_conn *)conn->dd_data)->phba;
  4144. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_IO,
  4145. "BM_%d : scsi_dma_map Failed\n");
  4146. return num_sg;
  4147. }
  4148. xferlen = scsi_bufflen(sc);
  4149. sg = scsi_sglist(sc);
  4150. if (sc->sc_data_direction == DMA_TO_DEVICE)
  4151. writedir = 1;
  4152. else
  4153. writedir = 0;
  4154. return phba->iotask_fn(task, sg, num_sg, xferlen, writedir);
  4155. }
  4156. /**
  4157. * beiscsi_bsg_request - handle bsg request from ISCSI transport
  4158. * @job: job to handle
  4159. */
  4160. static int beiscsi_bsg_request(struct bsg_job *job)
  4161. {
  4162. struct Scsi_Host *shost;
  4163. struct beiscsi_hba *phba;
  4164. struct iscsi_bsg_request *bsg_req = job->request;
  4165. int rc = -EINVAL;
  4166. unsigned int tag;
  4167. struct be_dma_mem nonemb_cmd;
  4168. struct be_cmd_resp_hdr *resp;
  4169. struct iscsi_bsg_reply *bsg_reply = job->reply;
  4170. unsigned short status, extd_status;
  4171. shost = iscsi_job_to_shost(job);
  4172. phba = iscsi_host_priv(shost);
  4173. switch (bsg_req->msgcode) {
  4174. case ISCSI_BSG_HST_VENDOR:
  4175. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  4176. job->request_payload.payload_len,
  4177. &nonemb_cmd.dma);
  4178. if (nonemb_cmd.va == NULL) {
  4179. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4180. "BM_%d : Failed to allocate memory for "
  4181. "beiscsi_bsg_request\n");
  4182. return -ENOMEM;
  4183. }
  4184. tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job,
  4185. &nonemb_cmd);
  4186. if (!tag) {
  4187. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4188. "BM_%d : MBX Tag Allocation Failed\n");
  4189. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  4190. nonemb_cmd.va, nonemb_cmd.dma);
  4191. return -EAGAIN;
  4192. }
  4193. rc = wait_event_interruptible_timeout(
  4194. phba->ctrl.mcc_wait[tag],
  4195. phba->ctrl.mcc_numtag[tag],
  4196. msecs_to_jiffies(
  4197. BEISCSI_HOST_MBX_TIMEOUT));
  4198. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  4199. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  4200. free_mcc_tag(&phba->ctrl, tag);
  4201. resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va;
  4202. sg_copy_from_buffer(job->reply_payload.sg_list,
  4203. job->reply_payload.sg_cnt,
  4204. nonemb_cmd.va, (resp->response_length
  4205. + sizeof(*resp)));
  4206. bsg_reply->reply_payload_rcv_len = resp->response_length;
  4207. bsg_reply->result = status;
  4208. bsg_job_done(job, bsg_reply->result,
  4209. bsg_reply->reply_payload_rcv_len);
  4210. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  4211. nonemb_cmd.va, nonemb_cmd.dma);
  4212. if (status || extd_status) {
  4213. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4214. "BM_%d : MBX Cmd Failed"
  4215. " status = %d extd_status = %d\n",
  4216. status, extd_status);
  4217. return -EIO;
  4218. } else {
  4219. rc = 0;
  4220. }
  4221. break;
  4222. default:
  4223. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4224. "BM_%d : Unsupported bsg command: 0x%x\n",
  4225. bsg_req->msgcode);
  4226. break;
  4227. }
  4228. return rc;
  4229. }
  4230. void beiscsi_hba_attrs_init(struct beiscsi_hba *phba)
  4231. {
  4232. /* Set the logging parameter */
  4233. beiscsi_log_enable_init(phba, beiscsi_log_enable);
  4234. }
  4235. /*
  4236. * beiscsi_quiesce()- Cleanup Driver resources
  4237. * @phba: Instance Priv structure
  4238. *
  4239. * Free the OS and HW resources held by the driver
  4240. **/
  4241. static void beiscsi_quiesce(struct beiscsi_hba *phba)
  4242. {
  4243. struct hwi_controller *phwi_ctrlr;
  4244. struct hwi_context_memory *phwi_context;
  4245. struct be_eq_obj *pbe_eq;
  4246. unsigned int i, msix_vec;
  4247. phwi_ctrlr = phba->phwi_ctrlr;
  4248. phwi_context = phwi_ctrlr->phwi_ctxt;
  4249. hwi_disable_intr(phba);
  4250. if (phba->msix_enabled) {
  4251. for (i = 0; i <= phba->num_cpus; i++) {
  4252. msix_vec = phba->msix_entries[i].vector;
  4253. free_irq(msix_vec, &phwi_context->be_eq[i]);
  4254. kfree(phba->msi_name[i]);
  4255. }
  4256. } else
  4257. if (phba->pcidev->irq)
  4258. free_irq(phba->pcidev->irq, phba);
  4259. pci_disable_msix(phba->pcidev);
  4260. destroy_workqueue(phba->wq);
  4261. if (blk_iopoll_enabled)
  4262. for (i = 0; i < phba->num_cpus; i++) {
  4263. pbe_eq = &phwi_context->be_eq[i];
  4264. blk_iopoll_disable(&pbe_eq->iopoll);
  4265. }
  4266. beiscsi_clean_port(phba);
  4267. beiscsi_free_mem(phba);
  4268. beiscsi_unmap_pci_function(phba);
  4269. pci_free_consistent(phba->pcidev,
  4270. phba->ctrl.mbox_mem_alloced.size,
  4271. phba->ctrl.mbox_mem_alloced.va,
  4272. phba->ctrl.mbox_mem_alloced.dma);
  4273. cancel_delayed_work_sync(&phba->beiscsi_hw_check_task);
  4274. }
  4275. static void beiscsi_remove(struct pci_dev *pcidev)
  4276. {
  4277. struct beiscsi_hba *phba = NULL;
  4278. phba = pci_get_drvdata(pcidev);
  4279. if (!phba) {
  4280. dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
  4281. return;
  4282. }
  4283. beiscsi_destroy_def_ifaces(phba);
  4284. beiscsi_quiesce(phba);
  4285. iscsi_boot_destroy_kset(phba->boot_kset);
  4286. iscsi_host_remove(phba->shost);
  4287. pci_dev_put(phba->pcidev);
  4288. iscsi_host_free(phba->shost);
  4289. pci_disable_device(pcidev);
  4290. }
  4291. static void beiscsi_shutdown(struct pci_dev *pcidev)
  4292. {
  4293. struct beiscsi_hba *phba = NULL;
  4294. phba = (struct beiscsi_hba *)pci_get_drvdata(pcidev);
  4295. if (!phba) {
  4296. dev_err(&pcidev->dev, "beiscsi_shutdown called with no phba\n");
  4297. return;
  4298. }
  4299. beiscsi_quiesce(phba);
  4300. pci_disable_device(pcidev);
  4301. }
  4302. static void beiscsi_msix_enable(struct beiscsi_hba *phba)
  4303. {
  4304. int i, status;
  4305. for (i = 0; i <= phba->num_cpus; i++)
  4306. phba->msix_entries[i].entry = i;
  4307. status = pci_enable_msix(phba->pcidev, phba->msix_entries,
  4308. (phba->num_cpus + 1));
  4309. if (!status)
  4310. phba->msix_enabled = true;
  4311. return;
  4312. }
  4313. /*
  4314. * beiscsi_hw_health_check()- Check adapter health
  4315. * @work: work item to check HW health
  4316. *
  4317. * Check if adapter in an unrecoverable state or not.
  4318. **/
  4319. static void
  4320. beiscsi_hw_health_check(struct work_struct *work)
  4321. {
  4322. struct beiscsi_hba *phba =
  4323. container_of(work, struct beiscsi_hba,
  4324. beiscsi_hw_check_task.work);
  4325. beiscsi_ue_detect(phba);
  4326. schedule_delayed_work(&phba->beiscsi_hw_check_task,
  4327. msecs_to_jiffies(1000));
  4328. }
  4329. static int beiscsi_dev_probe(struct pci_dev *pcidev,
  4330. const struct pci_device_id *id)
  4331. {
  4332. struct beiscsi_hba *phba = NULL;
  4333. struct hwi_controller *phwi_ctrlr;
  4334. struct hwi_context_memory *phwi_context;
  4335. struct be_eq_obj *pbe_eq;
  4336. int ret, i;
  4337. ret = beiscsi_enable_pci(pcidev);
  4338. if (ret < 0) {
  4339. dev_err(&pcidev->dev,
  4340. "beiscsi_dev_probe - Failed to enable pci device\n");
  4341. return ret;
  4342. }
  4343. phba = beiscsi_hba_alloc(pcidev);
  4344. if (!phba) {
  4345. dev_err(&pcidev->dev,
  4346. "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n");
  4347. goto disable_pci;
  4348. }
  4349. /* Initialize Driver configuration Paramters */
  4350. beiscsi_hba_attrs_init(phba);
  4351. phba->fw_timeout = false;
  4352. switch (pcidev->device) {
  4353. case BE_DEVICE_ID1:
  4354. case OC_DEVICE_ID1:
  4355. case OC_DEVICE_ID2:
  4356. phba->generation = BE_GEN2;
  4357. phba->iotask_fn = beiscsi_iotask;
  4358. break;
  4359. case BE_DEVICE_ID2:
  4360. case OC_DEVICE_ID3:
  4361. phba->generation = BE_GEN3;
  4362. phba->iotask_fn = beiscsi_iotask;
  4363. break;
  4364. case OC_SKH_ID1:
  4365. phba->generation = BE_GEN4;
  4366. phba->iotask_fn = beiscsi_iotask_v2;
  4367. break;
  4368. default:
  4369. phba->generation = 0;
  4370. }
  4371. if (enable_msix)
  4372. find_num_cpus(phba);
  4373. else
  4374. phba->num_cpus = 1;
  4375. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4376. "BM_%d : num_cpus = %d\n",
  4377. phba->num_cpus);
  4378. if (enable_msix) {
  4379. beiscsi_msix_enable(phba);
  4380. if (!phba->msix_enabled)
  4381. phba->num_cpus = 1;
  4382. }
  4383. ret = be_ctrl_init(phba, pcidev);
  4384. if (ret) {
  4385. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4386. "BM_%d : beiscsi_dev_probe-"
  4387. "Failed in be_ctrl_init\n");
  4388. goto hba_free;
  4389. }
  4390. ret = beiscsi_cmd_reset_function(phba);
  4391. if (ret) {
  4392. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4393. "BM_%d : Reset Failed. Aborting Crashdump\n");
  4394. goto hba_free;
  4395. }
  4396. ret = be_chk_reset_complete(phba);
  4397. if (ret) {
  4398. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4399. "BM_%d : Failed to get out of reset."
  4400. "Aborting Crashdump\n");
  4401. goto hba_free;
  4402. }
  4403. spin_lock_init(&phba->io_sgl_lock);
  4404. spin_lock_init(&phba->mgmt_sgl_lock);
  4405. spin_lock_init(&phba->isr_lock);
  4406. ret = mgmt_get_fw_config(&phba->ctrl, phba);
  4407. if (ret != 0) {
  4408. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4409. "BM_%d : Error getting fw config\n");
  4410. goto free_port;
  4411. }
  4412. phba->shost->max_id = phba->fw_config.iscsi_cid_count;
  4413. beiscsi_get_params(phba);
  4414. phba->shost->can_queue = phba->params.ios_per_ctrl;
  4415. ret = beiscsi_init_port(phba);
  4416. if (ret < 0) {
  4417. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4418. "BM_%d : beiscsi_dev_probe-"
  4419. "Failed in beiscsi_init_port\n");
  4420. goto free_port;
  4421. }
  4422. for (i = 0; i < MAX_MCC_CMD ; i++) {
  4423. init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
  4424. phba->ctrl.mcc_tag[i] = i + 1;
  4425. phba->ctrl.mcc_numtag[i + 1] = 0;
  4426. phba->ctrl.mcc_tag_available++;
  4427. }
  4428. phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
  4429. snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_%02x_wq",
  4430. phba->shost->host_no);
  4431. phba->wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 1, phba->wq_name);
  4432. if (!phba->wq) {
  4433. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4434. "BM_%d : beiscsi_dev_probe-"
  4435. "Failed to allocate work queue\n");
  4436. goto free_twq;
  4437. }
  4438. INIT_DELAYED_WORK(&phba->beiscsi_hw_check_task,
  4439. beiscsi_hw_health_check);
  4440. phwi_ctrlr = phba->phwi_ctrlr;
  4441. phwi_context = phwi_ctrlr->phwi_ctxt;
  4442. if (blk_iopoll_enabled) {
  4443. for (i = 0; i < phba->num_cpus; i++) {
  4444. pbe_eq = &phwi_context->be_eq[i];
  4445. blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget,
  4446. be_iopoll);
  4447. blk_iopoll_enable(&pbe_eq->iopoll);
  4448. }
  4449. i = (phba->msix_enabled) ? i : 0;
  4450. /* Work item for MCC handling */
  4451. pbe_eq = &phwi_context->be_eq[i];
  4452. INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs);
  4453. } else {
  4454. if (phba->msix_enabled) {
  4455. for (i = 0; i <= phba->num_cpus; i++) {
  4456. pbe_eq = &phwi_context->be_eq[i];
  4457. INIT_WORK(&pbe_eq->work_cqs,
  4458. beiscsi_process_all_cqs);
  4459. }
  4460. } else {
  4461. pbe_eq = &phwi_context->be_eq[0];
  4462. INIT_WORK(&pbe_eq->work_cqs,
  4463. beiscsi_process_all_cqs);
  4464. }
  4465. }
  4466. ret = beiscsi_init_irqs(phba);
  4467. if (ret < 0) {
  4468. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4469. "BM_%d : beiscsi_dev_probe-"
  4470. "Failed to beiscsi_init_irqs\n");
  4471. goto free_blkenbld;
  4472. }
  4473. hwi_enable_intr(phba);
  4474. if (beiscsi_setup_boot_info(phba))
  4475. /*
  4476. * log error but continue, because we may not be using
  4477. * iscsi boot.
  4478. */
  4479. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4480. "BM_%d : Could not set up "
  4481. "iSCSI boot info.\n");
  4482. beiscsi_create_def_ifaces(phba);
  4483. schedule_delayed_work(&phba->beiscsi_hw_check_task,
  4484. msecs_to_jiffies(1000));
  4485. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4486. "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n");
  4487. return 0;
  4488. free_blkenbld:
  4489. destroy_workqueue(phba->wq);
  4490. if (blk_iopoll_enabled)
  4491. for (i = 0; i < phba->num_cpus; i++) {
  4492. pbe_eq = &phwi_context->be_eq[i];
  4493. blk_iopoll_disable(&pbe_eq->iopoll);
  4494. }
  4495. free_twq:
  4496. beiscsi_clean_port(phba);
  4497. beiscsi_free_mem(phba);
  4498. free_port:
  4499. pci_free_consistent(phba->pcidev,
  4500. phba->ctrl.mbox_mem_alloced.size,
  4501. phba->ctrl.mbox_mem_alloced.va,
  4502. phba->ctrl.mbox_mem_alloced.dma);
  4503. beiscsi_unmap_pci_function(phba);
  4504. hba_free:
  4505. if (phba->msix_enabled)
  4506. pci_disable_msix(phba->pcidev);
  4507. iscsi_host_remove(phba->shost);
  4508. pci_dev_put(phba->pcidev);
  4509. iscsi_host_free(phba->shost);
  4510. disable_pci:
  4511. pci_disable_device(pcidev);
  4512. return ret;
  4513. }
  4514. struct iscsi_transport beiscsi_iscsi_transport = {
  4515. .owner = THIS_MODULE,
  4516. .name = DRV_NAME,
  4517. .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
  4518. CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
  4519. .create_session = beiscsi_session_create,
  4520. .destroy_session = beiscsi_session_destroy,
  4521. .create_conn = beiscsi_conn_create,
  4522. .bind_conn = beiscsi_conn_bind,
  4523. .destroy_conn = iscsi_conn_teardown,
  4524. .attr_is_visible = be2iscsi_attr_is_visible,
  4525. .set_iface_param = be2iscsi_iface_set_param,
  4526. .get_iface_param = be2iscsi_iface_get_param,
  4527. .set_param = beiscsi_set_param,
  4528. .get_conn_param = iscsi_conn_get_param,
  4529. .get_session_param = iscsi_session_get_param,
  4530. .get_host_param = beiscsi_get_host_param,
  4531. .start_conn = beiscsi_conn_start,
  4532. .stop_conn = iscsi_conn_stop,
  4533. .send_pdu = iscsi_conn_send_pdu,
  4534. .xmit_task = beiscsi_task_xmit,
  4535. .cleanup_task = beiscsi_cleanup_task,
  4536. .alloc_pdu = beiscsi_alloc_pdu,
  4537. .parse_pdu_itt = beiscsi_parse_pdu,
  4538. .get_stats = beiscsi_conn_get_stats,
  4539. .get_ep_param = beiscsi_ep_get_param,
  4540. .ep_connect = beiscsi_ep_connect,
  4541. .ep_poll = beiscsi_ep_poll,
  4542. .ep_disconnect = beiscsi_ep_disconnect,
  4543. .session_recovery_timedout = iscsi_session_recovery_timedout,
  4544. .bsg_request = beiscsi_bsg_request,
  4545. };
  4546. static struct pci_driver beiscsi_pci_driver = {
  4547. .name = DRV_NAME,
  4548. .probe = beiscsi_dev_probe,
  4549. .remove = beiscsi_remove,
  4550. .shutdown = beiscsi_shutdown,
  4551. .id_table = beiscsi_pci_id_table
  4552. };
  4553. static int __init beiscsi_module_init(void)
  4554. {
  4555. int ret;
  4556. beiscsi_scsi_transport =
  4557. iscsi_register_transport(&beiscsi_iscsi_transport);
  4558. if (!beiscsi_scsi_transport) {
  4559. printk(KERN_ERR
  4560. "beiscsi_module_init - Unable to register beiscsi transport.\n");
  4561. return -ENOMEM;
  4562. }
  4563. printk(KERN_INFO "In beiscsi_module_init, tt=%p\n",
  4564. &beiscsi_iscsi_transport);
  4565. ret = pci_register_driver(&beiscsi_pci_driver);
  4566. if (ret) {
  4567. printk(KERN_ERR
  4568. "beiscsi_module_init - Unable to register beiscsi pci driver.\n");
  4569. goto unregister_iscsi_transport;
  4570. }
  4571. return 0;
  4572. unregister_iscsi_transport:
  4573. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4574. return ret;
  4575. }
  4576. static void __exit beiscsi_module_exit(void)
  4577. {
  4578. pci_unregister_driver(&beiscsi_pci_driver);
  4579. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4580. }
  4581. module_init(beiscsi_module_init);
  4582. module_exit(beiscsi_module_exit);