rtc-stmp3xxx.c 10.0 KB

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  1. /*
  2. * Freescale STMP37XX/STMP378X Real Time Clock driver
  3. *
  4. * Copyright (c) 2007 Sigmatel, Inc.
  5. * Peter Hartley, <peter.hartley@sigmatel.com>
  6. *
  7. * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
  8. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
  9. * Copyright 2011 Wolfram Sang, Pengutronix e.K.
  10. */
  11. /*
  12. * The code contained herein is licensed under the GNU General Public
  13. * License. You may obtain a copy of the GNU General Public License
  14. * Version 2 or later at the following locations:
  15. *
  16. * http://www.opensource.org/licenses/gpl-license.html
  17. * http://www.gnu.org/copyleft/gpl.html
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/io.h>
  22. #include <linux/init.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/delay.h>
  26. #include <linux/rtc.h>
  27. #include <linux/slab.h>
  28. #include <linux/of_device.h>
  29. #include <linux/of.h>
  30. #include <linux/stmp_device.h>
  31. #include <linux/stmp3xxx_rtc_wdt.h>
  32. #define STMP3XXX_RTC_CTRL 0x0
  33. #define STMP3XXX_RTC_CTRL_SET 0x4
  34. #define STMP3XXX_RTC_CTRL_CLR 0x8
  35. #define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN 0x00000001
  36. #define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
  37. #define STMP3XXX_RTC_CTRL_ALARM_IRQ 0x00000004
  38. #define STMP3XXX_RTC_CTRL_WATCHDOGEN 0x00000010
  39. #define STMP3XXX_RTC_STAT 0x10
  40. #define STMP3XXX_RTC_STAT_STALE_SHIFT 16
  41. #define STMP3XXX_RTC_STAT_RTC_PRESENT 0x80000000
  42. #define STMP3XXX_RTC_SECONDS 0x30
  43. #define STMP3XXX_RTC_ALARM 0x40
  44. #define STMP3XXX_RTC_WATCHDOG 0x50
  45. #define STMP3XXX_RTC_PERSISTENT0 0x60
  46. #define STMP3XXX_RTC_PERSISTENT0_SET 0x64
  47. #define STMP3XXX_RTC_PERSISTENT0_CLR 0x68
  48. #define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002
  49. #define STMP3XXX_RTC_PERSISTENT0_ALARM_EN 0x00000004
  50. #define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE 0x00000080
  51. #define STMP3XXX_RTC_PERSISTENT1 0x70
  52. /* missing bitmask in headers */
  53. #define STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER 0x80000000
  54. struct stmp3xxx_rtc_data {
  55. struct rtc_device *rtc;
  56. void __iomem *io;
  57. int irq_alarm;
  58. };
  59. #if IS_ENABLED(CONFIG_STMP3XXX_RTC_WATCHDOG)
  60. /**
  61. * stmp3xxx_wdt_set_timeout - configure the watchdog inside the STMP3xxx RTC
  62. * @dev: the parent device of the watchdog (= the RTC)
  63. * @timeout: the desired value for the timeout register of the watchdog.
  64. * 0 disables the watchdog
  65. *
  66. * The watchdog needs one register and two bits which are in the RTC domain.
  67. * To handle the resource conflict, the RTC driver will create another
  68. * platform_device for the watchdog driver as a child of the RTC device.
  69. * The watchdog driver is passed the below accessor function via platform_data
  70. * to configure the watchdog. Locking is not needed because accessing SET/CLR
  71. * registers is atomic.
  72. */
  73. static void stmp3xxx_wdt_set_timeout(struct device *dev, u32 timeout)
  74. {
  75. struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
  76. if (timeout) {
  77. writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG);
  78. writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
  79. rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
  80. writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
  81. rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET);
  82. } else {
  83. writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
  84. rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
  85. writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
  86. rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR);
  87. }
  88. }
  89. static struct stmp3xxx_wdt_pdata wdt_pdata = {
  90. .wdt_set_timeout = stmp3xxx_wdt_set_timeout,
  91. };
  92. static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
  93. {
  94. struct platform_device *wdt_pdev =
  95. platform_device_alloc("stmp3xxx_rtc_wdt", rtc_pdev->id);
  96. if (wdt_pdev) {
  97. wdt_pdev->dev.parent = &rtc_pdev->dev;
  98. wdt_pdev->dev.platform_data = &wdt_pdata;
  99. platform_device_add(wdt_pdev);
  100. }
  101. }
  102. #else
  103. static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
  104. {
  105. }
  106. #endif /* CONFIG_STMP3XXX_RTC_WATCHDOG */
  107. static int stmp3xxx_wait_time(struct stmp3xxx_rtc_data *rtc_data)
  108. {
  109. int timeout = 5000; /* 3ms according to i.MX28 Ref Manual */
  110. /*
  111. * The i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
  112. * states:
  113. * | The order in which registers are updated is
  114. * | Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds.
  115. * | (This list is in bitfield order, from LSB to MSB, as they would
  116. * | appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT
  117. * | register. For example, the Seconds register corresponds to
  118. * | STALE_REGS or NEW_REGS containing 0x80.)
  119. */
  120. do {
  121. if (!(readl(rtc_data->io + STMP3XXX_RTC_STAT) &
  122. (0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)))
  123. return 0;
  124. udelay(1);
  125. } while (--timeout > 0);
  126. return (readl(rtc_data->io + STMP3XXX_RTC_STAT) &
  127. (0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)) ? -ETIME : 0;
  128. }
  129. /* Time read/write */
  130. static int stmp3xxx_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
  131. {
  132. int ret;
  133. struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
  134. ret = stmp3xxx_wait_time(rtc_data);
  135. if (ret)
  136. return ret;
  137. rtc_time_to_tm(readl(rtc_data->io + STMP3XXX_RTC_SECONDS), rtc_tm);
  138. return 0;
  139. }
  140. static int stmp3xxx_rtc_set_mmss(struct device *dev, unsigned long t)
  141. {
  142. struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
  143. writel(t, rtc_data->io + STMP3XXX_RTC_SECONDS);
  144. return stmp3xxx_wait_time(rtc_data);
  145. }
  146. /* interrupt(s) handler */
  147. static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id)
  148. {
  149. struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev_id);
  150. u32 status = readl(rtc_data->io + STMP3XXX_RTC_CTRL);
  151. if (status & STMP3XXX_RTC_CTRL_ALARM_IRQ) {
  152. writel(STMP3XXX_RTC_CTRL_ALARM_IRQ,
  153. rtc_data->io + STMP3XXX_RTC_CTRL_CLR);
  154. rtc_update_irq(rtc_data->rtc, 1, RTC_AF | RTC_IRQF);
  155. return IRQ_HANDLED;
  156. }
  157. return IRQ_NONE;
  158. }
  159. static int stmp3xxx_alarm_irq_enable(struct device *dev, unsigned int enabled)
  160. {
  161. struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
  162. if (enabled) {
  163. writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
  164. STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
  165. rtc_data->io + STMP3XXX_RTC_PERSISTENT0_SET);
  166. writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
  167. rtc_data->io + STMP3XXX_RTC_CTRL_SET);
  168. } else {
  169. writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
  170. STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
  171. rtc_data->io + STMP3XXX_RTC_PERSISTENT0_CLR);
  172. writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
  173. rtc_data->io + STMP3XXX_RTC_CTRL_CLR);
  174. }
  175. return 0;
  176. }
  177. static int stmp3xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
  178. {
  179. struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
  180. rtc_time_to_tm(readl(rtc_data->io + STMP3XXX_RTC_ALARM), &alm->time);
  181. return 0;
  182. }
  183. static int stmp3xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
  184. {
  185. unsigned long t;
  186. struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
  187. rtc_tm_to_time(&alm->time, &t);
  188. writel(t, rtc_data->io + STMP3XXX_RTC_ALARM);
  189. stmp3xxx_alarm_irq_enable(dev, alm->enabled);
  190. return 0;
  191. }
  192. static struct rtc_class_ops stmp3xxx_rtc_ops = {
  193. .alarm_irq_enable =
  194. stmp3xxx_alarm_irq_enable,
  195. .read_time = stmp3xxx_rtc_gettime,
  196. .set_mmss = stmp3xxx_rtc_set_mmss,
  197. .read_alarm = stmp3xxx_rtc_read_alarm,
  198. .set_alarm = stmp3xxx_rtc_set_alarm,
  199. };
  200. static int stmp3xxx_rtc_remove(struct platform_device *pdev)
  201. {
  202. struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(pdev);
  203. if (!rtc_data)
  204. return 0;
  205. writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
  206. rtc_data->io + STMP3XXX_RTC_CTRL_CLR);
  207. return 0;
  208. }
  209. static int stmp3xxx_rtc_probe(struct platform_device *pdev)
  210. {
  211. struct stmp3xxx_rtc_data *rtc_data;
  212. struct resource *r;
  213. int err;
  214. rtc_data = devm_kzalloc(&pdev->dev, sizeof(*rtc_data), GFP_KERNEL);
  215. if (!rtc_data)
  216. return -ENOMEM;
  217. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  218. if (!r) {
  219. dev_err(&pdev->dev, "failed to get resource\n");
  220. return -ENXIO;
  221. }
  222. rtc_data->io = devm_ioremap(&pdev->dev, r->start, resource_size(r));
  223. if (!rtc_data->io) {
  224. dev_err(&pdev->dev, "ioremap failed\n");
  225. return -EIO;
  226. }
  227. rtc_data->irq_alarm = platform_get_irq(pdev, 0);
  228. if (!(readl(STMP3XXX_RTC_STAT + rtc_data->io) &
  229. STMP3XXX_RTC_STAT_RTC_PRESENT)) {
  230. dev_err(&pdev->dev, "no device onboard\n");
  231. return -ENODEV;
  232. }
  233. platform_set_drvdata(pdev, rtc_data);
  234. err = stmp_reset_block(rtc_data->io);
  235. if (err) {
  236. dev_err(&pdev->dev, "stmp_reset_block failed: %d\n", err);
  237. return err;
  238. }
  239. writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
  240. STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
  241. STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
  242. rtc_data->io + STMP3XXX_RTC_PERSISTENT0_CLR);
  243. writel(STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN |
  244. STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
  245. rtc_data->io + STMP3XXX_RTC_CTRL_CLR);
  246. rtc_data->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
  247. &stmp3xxx_rtc_ops, THIS_MODULE);
  248. if (IS_ERR(rtc_data->rtc))
  249. return PTR_ERR(rtc_data->rtc);
  250. err = devm_request_irq(&pdev->dev, rtc_data->irq_alarm,
  251. stmp3xxx_rtc_interrupt, 0, "RTC alarm", &pdev->dev);
  252. if (err) {
  253. dev_err(&pdev->dev, "Cannot claim IRQ%d\n",
  254. rtc_data->irq_alarm);
  255. return err;
  256. }
  257. stmp3xxx_wdt_register(pdev);
  258. return 0;
  259. }
  260. #ifdef CONFIG_PM_SLEEP
  261. static int stmp3xxx_rtc_suspend(struct device *dev)
  262. {
  263. return 0;
  264. }
  265. static int stmp3xxx_rtc_resume(struct device *dev)
  266. {
  267. struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
  268. stmp_reset_block(rtc_data->io);
  269. writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
  270. STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
  271. STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
  272. rtc_data->io + STMP3XXX_RTC_PERSISTENT0_CLR);
  273. return 0;
  274. }
  275. #endif
  276. static SIMPLE_DEV_PM_OPS(stmp3xxx_rtc_pm_ops, stmp3xxx_rtc_suspend,
  277. stmp3xxx_rtc_resume);
  278. static const struct of_device_id rtc_dt_ids[] = {
  279. { .compatible = "fsl,stmp3xxx-rtc", },
  280. { /* sentinel */ }
  281. };
  282. MODULE_DEVICE_TABLE(of, rtc_dt_ids);
  283. static struct platform_driver stmp3xxx_rtcdrv = {
  284. .probe = stmp3xxx_rtc_probe,
  285. .remove = stmp3xxx_rtc_remove,
  286. .driver = {
  287. .name = "stmp3xxx-rtc",
  288. .owner = THIS_MODULE,
  289. .pm = &stmp3xxx_rtc_pm_ops,
  290. .of_match_table = of_match_ptr(rtc_dt_ids),
  291. },
  292. };
  293. module_platform_driver(stmp3xxx_rtcdrv);
  294. MODULE_DESCRIPTION("STMP3xxx RTC Driver");
  295. MODULE_AUTHOR("dmitry pervushin <dpervushin@embeddedalley.com> and "
  296. "Wolfram Sang <w.sang@pengutronix.de>");
  297. MODULE_LICENSE("GPL");