trans.c 42 KB

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  1. /******************************************************************************
  2. *
  3. * This file is provided under a dual BSD/GPLv2 license. When using or
  4. * redistributing this file, you may do so under either license.
  5. *
  6. * GPL LICENSE SUMMARY
  7. *
  8. * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of version 2 of the GNU General Public License as
  12. * published by the Free Software Foundation.
  13. *
  14. * This program is distributed in the hope that it will be useful, but
  15. * WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17. * General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  22. * USA
  23. *
  24. * The full GNU General Public License is included in this distribution
  25. * in the file called COPYING.
  26. *
  27. * Contact Information:
  28. * Intel Linux Wireless <ilw@linux.intel.com>
  29. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30. *
  31. * BSD LICENSE
  32. *
  33. * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
  34. * All rights reserved.
  35. *
  36. * Redistribution and use in source and binary forms, with or without
  37. * modification, are permitted provided that the following conditions
  38. * are met:
  39. *
  40. * * Redistributions of source code must retain the above copyright
  41. * notice, this list of conditions and the following disclaimer.
  42. * * Redistributions in binary form must reproduce the above copyright
  43. * notice, this list of conditions and the following disclaimer in
  44. * the documentation and/or other materials provided with the
  45. * distribution.
  46. * * Neither the name Intel Corporation nor the names of its
  47. * contributors may be used to endorse or promote products derived
  48. * from this software without specific prior written permission.
  49. *
  50. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61. *
  62. *****************************************************************************/
  63. #include <linux/pci.h>
  64. #include <linux/pci-aspm.h>
  65. #include <linux/interrupt.h>
  66. #include <linux/debugfs.h>
  67. #include <linux/sched.h>
  68. #include <linux/bitops.h>
  69. #include <linux/gfp.h>
  70. #include "iwl-drv.h"
  71. #include "iwl-trans.h"
  72. #include "iwl-csr.h"
  73. #include "iwl-prph.h"
  74. #include "iwl-agn-hw.h"
  75. #include "internal.h"
  76. static void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
  77. u32 reg, u32 mask, u32 value)
  78. {
  79. u32 v;
  80. #ifdef CONFIG_IWLWIFI_DEBUG
  81. WARN_ON_ONCE(value & ~mask);
  82. #endif
  83. v = iwl_read32(trans, reg);
  84. v &= ~mask;
  85. v |= value;
  86. iwl_write32(trans, reg, v);
  87. }
  88. static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
  89. u32 reg, u32 mask)
  90. {
  91. __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
  92. }
  93. static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
  94. u32 reg, u32 mask)
  95. {
  96. __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
  97. }
  98. static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
  99. {
  100. if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
  101. iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
  102. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  103. ~APMG_PS_CTRL_MSK_PWR_SRC);
  104. else
  105. iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
  106. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  107. ~APMG_PS_CTRL_MSK_PWR_SRC);
  108. }
  109. /* PCI registers */
  110. #define PCI_CFG_RETRY_TIMEOUT 0x041
  111. static void iwl_pcie_apm_config(struct iwl_trans *trans)
  112. {
  113. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  114. u16 lctl;
  115. /*
  116. * HW bug W/A for instability in PCIe bus L0S->L1 transition.
  117. * Check if BIOS (or OS) enabled L1-ASPM on this device.
  118. * If so (likely), disable L0S, so device moves directly L0->L1;
  119. * costs negligible amount of power savings.
  120. * If not (unlikely), enable L0S, so there is at least some
  121. * power savings, even without L1.
  122. */
  123. pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
  124. if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
  125. /* L1-ASPM enabled; disable(!) L0S */
  126. iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
  127. dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
  128. } else {
  129. /* L1-ASPM disabled; enable(!) L0S */
  130. iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
  131. dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
  132. }
  133. trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
  134. }
  135. /*
  136. * Start up NIC's basic functionality after it has been reset
  137. * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
  138. * NOTE: This does not load uCode nor start the embedded processor
  139. */
  140. static int iwl_pcie_apm_init(struct iwl_trans *trans)
  141. {
  142. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  143. int ret = 0;
  144. IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
  145. /*
  146. * Use "set_bit" below rather than "write", to preserve any hardware
  147. * bits already set by default after reset.
  148. */
  149. /* Disable L0S exit timer (platform NMI Work/Around) */
  150. iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
  151. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  152. /*
  153. * Disable L0s without affecting L1;
  154. * don't wait for ICH L0s (ICH bug W/A)
  155. */
  156. iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
  157. CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  158. /* Set FH wait threshold to maximum (HW error during stress W/A) */
  159. iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
  160. /*
  161. * Enable HAP INTA (interrupt from management bus) to
  162. * wake device's PCI Express link L1a -> L0s
  163. */
  164. iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
  165. CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
  166. iwl_pcie_apm_config(trans);
  167. /* Configure analog phase-lock-loop before activating to D0A */
  168. if (trans->cfg->base_params->pll_cfg_val)
  169. iwl_set_bit(trans, CSR_ANA_PLL_CFG,
  170. trans->cfg->base_params->pll_cfg_val);
  171. /*
  172. * Set "initialization complete" bit to move adapter from
  173. * D0U* --> D0A* (powered-up active) state.
  174. */
  175. iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  176. /*
  177. * Wait for clock stabilization; once stabilized, access to
  178. * device-internal resources is supported, e.g. iwl_write_prph()
  179. * and accesses to uCode SRAM.
  180. */
  181. ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
  182. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  183. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  184. if (ret < 0) {
  185. IWL_DEBUG_INFO(trans, "Failed to init the card\n");
  186. goto out;
  187. }
  188. /*
  189. * Enable DMA clock and wait for it to stabilize.
  190. *
  191. * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
  192. * do not disable clocks. This preserves any hardware bits already
  193. * set by default in "CLK_CTRL_REG" after reset.
  194. */
  195. iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  196. udelay(20);
  197. /* Disable L1-Active */
  198. iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
  199. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  200. set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
  201. out:
  202. return ret;
  203. }
  204. static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
  205. {
  206. int ret = 0;
  207. /* stop device's busmaster DMA activity */
  208. iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  209. ret = iwl_poll_bit(trans, CSR_RESET,
  210. CSR_RESET_REG_FLAG_MASTER_DISABLED,
  211. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  212. if (ret)
  213. IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
  214. IWL_DEBUG_INFO(trans, "stop master\n");
  215. return ret;
  216. }
  217. static void iwl_pcie_apm_stop(struct iwl_trans *trans)
  218. {
  219. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  220. IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
  221. clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
  222. /* Stop device's DMA activity */
  223. iwl_pcie_apm_stop_master(trans);
  224. /* Reset the entire device */
  225. iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  226. udelay(10);
  227. /*
  228. * Clear "initialization complete" bit to move adapter from
  229. * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
  230. */
  231. iwl_clear_bit(trans, CSR_GP_CNTRL,
  232. CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  233. }
  234. static int iwl_pcie_nic_init(struct iwl_trans *trans)
  235. {
  236. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  237. unsigned long flags;
  238. /* nic_init */
  239. spin_lock_irqsave(&trans_pcie->irq_lock, flags);
  240. iwl_pcie_apm_init(trans);
  241. /* Set interrupt coalescing calibration timer to default (512 usecs) */
  242. iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
  243. spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
  244. iwl_pcie_set_pwr(trans, false);
  245. iwl_op_mode_nic_config(trans->op_mode);
  246. /* Allocate the RX queue, or reset if it is already allocated */
  247. iwl_pcie_rx_init(trans);
  248. /* Allocate or reset and init all Tx and Command queues */
  249. if (iwl_pcie_tx_init(trans))
  250. return -ENOMEM;
  251. if (trans->cfg->base_params->shadow_reg_enable) {
  252. /* enable shadow regs in HW */
  253. iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
  254. IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
  255. }
  256. return 0;
  257. }
  258. #define HW_READY_TIMEOUT (50)
  259. /* Note: returns poll_bit return value, which is >= 0 if success */
  260. static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
  261. {
  262. int ret;
  263. iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
  264. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  265. /* See if we got it */
  266. ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
  267. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  268. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  269. HW_READY_TIMEOUT);
  270. IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
  271. return ret;
  272. }
  273. /* Note: returns standard 0/-ERROR code */
  274. static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
  275. {
  276. int ret;
  277. int t = 0;
  278. IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
  279. ret = iwl_pcie_set_hw_ready(trans);
  280. /* If the card is ready, exit 0 */
  281. if (ret >= 0)
  282. return 0;
  283. /* If HW is not ready, prepare the conditions to check again */
  284. iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
  285. CSR_HW_IF_CONFIG_REG_PREPARE);
  286. do {
  287. ret = iwl_pcie_set_hw_ready(trans);
  288. if (ret >= 0)
  289. return 0;
  290. usleep_range(200, 1000);
  291. t += 200;
  292. } while (t < 150000);
  293. return ret;
  294. }
  295. /*
  296. * ucode
  297. */
  298. static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
  299. dma_addr_t phy_addr, u32 byte_cnt)
  300. {
  301. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  302. int ret;
  303. trans_pcie->ucode_write_complete = false;
  304. iwl_write_direct32(trans,
  305. FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
  306. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
  307. iwl_write_direct32(trans,
  308. FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
  309. dst_addr);
  310. iwl_write_direct32(trans,
  311. FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
  312. phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
  313. iwl_write_direct32(trans,
  314. FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
  315. (iwl_get_dma_hi_addr(phy_addr)
  316. << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
  317. iwl_write_direct32(trans,
  318. FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
  319. 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
  320. 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
  321. FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
  322. iwl_write_direct32(trans,
  323. FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
  324. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
  325. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
  326. FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
  327. ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
  328. trans_pcie->ucode_write_complete, 5 * HZ);
  329. if (!ret) {
  330. IWL_ERR(trans, "Failed to load firmware chunk!\n");
  331. return -ETIMEDOUT;
  332. }
  333. return 0;
  334. }
  335. static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
  336. const struct fw_desc *section)
  337. {
  338. u8 *v_addr;
  339. dma_addr_t p_addr;
  340. u32 offset, chunk_sz = section->len;
  341. int ret = 0;
  342. IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
  343. section_num);
  344. v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
  345. GFP_KERNEL | __GFP_NOWARN);
  346. if (!v_addr) {
  347. IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
  348. chunk_sz = PAGE_SIZE;
  349. v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
  350. &p_addr, GFP_KERNEL);
  351. if (!v_addr)
  352. return -ENOMEM;
  353. }
  354. for (offset = 0; offset < section->len; offset += chunk_sz) {
  355. u32 copy_size;
  356. copy_size = min_t(u32, chunk_sz, section->len - offset);
  357. memcpy(v_addr, (u8 *)section->data + offset, copy_size);
  358. ret = iwl_pcie_load_firmware_chunk(trans,
  359. section->offset + offset,
  360. p_addr, copy_size);
  361. if (ret) {
  362. IWL_ERR(trans,
  363. "Could not load the [%d] uCode section\n",
  364. section_num);
  365. break;
  366. }
  367. }
  368. dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
  369. return ret;
  370. }
  371. static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
  372. const struct fw_img *image)
  373. {
  374. int i, ret = 0;
  375. for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
  376. if (!image->sec[i].data)
  377. break;
  378. ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
  379. if (ret)
  380. return ret;
  381. }
  382. /* Remove all resets to allow NIC to operate */
  383. iwl_write32(trans, CSR_RESET, 0);
  384. return 0;
  385. }
  386. static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
  387. const struct fw_img *fw, bool run_in_rfkill)
  388. {
  389. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  390. int ret;
  391. bool hw_rfkill;
  392. /* This may fail if AMT took ownership of the device */
  393. if (iwl_pcie_prepare_card_hw(trans)) {
  394. IWL_WARN(trans, "Exit HW not ready\n");
  395. return -EIO;
  396. }
  397. clear_bit(STATUS_FW_ERROR, &trans_pcie->status);
  398. iwl_enable_rfkill_int(trans);
  399. /* If platform's RF_KILL switch is NOT set to KILL */
  400. hw_rfkill = iwl_is_rfkill_set(trans);
  401. if (hw_rfkill)
  402. set_bit(STATUS_RFKILL, &trans_pcie->status);
  403. else
  404. clear_bit(STATUS_RFKILL, &trans_pcie->status);
  405. iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
  406. if (hw_rfkill && !run_in_rfkill)
  407. return -ERFKILL;
  408. iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
  409. ret = iwl_pcie_nic_init(trans);
  410. if (ret) {
  411. IWL_ERR(trans, "Unable to init nic\n");
  412. return ret;
  413. }
  414. /* make sure rfkill handshake bits are cleared */
  415. iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  416. iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
  417. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  418. /* clear (again), then enable host interrupts */
  419. iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
  420. iwl_enable_interrupts(trans);
  421. /* really make sure rfkill handshake bits are cleared */
  422. iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  423. iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  424. /* Load the given image to the HW */
  425. return iwl_pcie_load_given_ucode(trans, fw);
  426. }
  427. static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
  428. {
  429. iwl_pcie_reset_ict(trans);
  430. iwl_pcie_tx_start(trans, scd_addr);
  431. }
  432. static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
  433. {
  434. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  435. unsigned long flags;
  436. /* tell the device to stop sending interrupts */
  437. spin_lock_irqsave(&trans_pcie->irq_lock, flags);
  438. iwl_disable_interrupts(trans);
  439. spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
  440. /* device going down, Stop using ICT table */
  441. iwl_pcie_disable_ict(trans);
  442. /*
  443. * If a HW restart happens during firmware loading,
  444. * then the firmware loading might call this function
  445. * and later it might be called again due to the
  446. * restart. So don't process again if the device is
  447. * already dead.
  448. */
  449. if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
  450. iwl_pcie_tx_stop(trans);
  451. iwl_pcie_rx_stop(trans);
  452. /* Power-down device's busmaster DMA clocks */
  453. iwl_write_prph(trans, APMG_CLK_DIS_REG,
  454. APMG_CLK_VAL_DMA_CLK_RQT);
  455. udelay(5);
  456. }
  457. /* Make sure (redundant) we've released our request to stay awake */
  458. iwl_clear_bit(trans, CSR_GP_CNTRL,
  459. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  460. /* Stop the device, and put it in low power state */
  461. iwl_pcie_apm_stop(trans);
  462. /* Upon stop, the APM issues an interrupt if HW RF kill is set.
  463. * Clean again the interrupt here
  464. */
  465. spin_lock_irqsave(&trans_pcie->irq_lock, flags);
  466. iwl_disable_interrupts(trans);
  467. spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
  468. iwl_enable_rfkill_int(trans);
  469. /* stop and reset the on-board processor */
  470. iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  471. /* clear all status bits */
  472. clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
  473. clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
  474. clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
  475. clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
  476. clear_bit(STATUS_RFKILL, &trans_pcie->status);
  477. }
  478. static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
  479. {
  480. iwl_disable_interrupts(trans);
  481. /*
  482. * in testing mode, the host stays awake and the
  483. * hardware won't be reset (not even partially)
  484. */
  485. if (test)
  486. return;
  487. iwl_pcie_disable_ict(trans);
  488. iwl_clear_bit(trans, CSR_GP_CNTRL,
  489. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  490. iwl_clear_bit(trans, CSR_GP_CNTRL,
  491. CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  492. /*
  493. * reset TX queues -- some of their registers reset during S3
  494. * so if we don't reset everything here the D3 image would try
  495. * to execute some invalid memory upon resume
  496. */
  497. iwl_trans_pcie_tx_reset(trans);
  498. iwl_pcie_set_pwr(trans, true);
  499. }
  500. static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
  501. enum iwl_d3_status *status,
  502. bool test)
  503. {
  504. u32 val;
  505. int ret;
  506. if (test) {
  507. iwl_enable_interrupts(trans);
  508. *status = IWL_D3_STATUS_ALIVE;
  509. return 0;
  510. }
  511. iwl_pcie_set_pwr(trans, false);
  512. val = iwl_read32(trans, CSR_RESET);
  513. if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
  514. *status = IWL_D3_STATUS_RESET;
  515. return 0;
  516. }
  517. /*
  518. * Also enables interrupts - none will happen as the device doesn't
  519. * know we're waking it up, only when the opmode actually tells it
  520. * after this call.
  521. */
  522. iwl_pcie_reset_ict(trans);
  523. iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  524. iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  525. ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
  526. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  527. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  528. 25000);
  529. if (ret) {
  530. IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
  531. return ret;
  532. }
  533. iwl_trans_pcie_tx_reset(trans);
  534. ret = iwl_pcie_rx_init(trans);
  535. if (ret) {
  536. IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
  537. return ret;
  538. }
  539. *status = IWL_D3_STATUS_ALIVE;
  540. return 0;
  541. }
  542. static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
  543. {
  544. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  545. bool hw_rfkill;
  546. int err;
  547. err = iwl_pcie_prepare_card_hw(trans);
  548. if (err) {
  549. IWL_ERR(trans, "Error while preparing HW: %d\n", err);
  550. return err;
  551. }
  552. /* Reset the entire device */
  553. iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  554. usleep_range(10, 15);
  555. iwl_pcie_apm_init(trans);
  556. /* From now on, the op_mode will be kept updated about RF kill state */
  557. iwl_enable_rfkill_int(trans);
  558. hw_rfkill = iwl_is_rfkill_set(trans);
  559. if (hw_rfkill)
  560. set_bit(STATUS_RFKILL, &trans_pcie->status);
  561. else
  562. clear_bit(STATUS_RFKILL, &trans_pcie->status);
  563. iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
  564. return 0;
  565. }
  566. static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
  567. bool op_mode_leaving)
  568. {
  569. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  570. bool hw_rfkill;
  571. unsigned long flags;
  572. spin_lock_irqsave(&trans_pcie->irq_lock, flags);
  573. iwl_disable_interrupts(trans);
  574. spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
  575. iwl_pcie_apm_stop(trans);
  576. spin_lock_irqsave(&trans_pcie->irq_lock, flags);
  577. iwl_disable_interrupts(trans);
  578. spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
  579. iwl_pcie_disable_ict(trans);
  580. if (!op_mode_leaving) {
  581. /*
  582. * Even if we stop the HW, we still want the RF kill
  583. * interrupt
  584. */
  585. iwl_enable_rfkill_int(trans);
  586. /*
  587. * Check again since the RF kill state may have changed while
  588. * all the interrupts were disabled, in this case we couldn't
  589. * receive the RF kill interrupt and update the state in the
  590. * op_mode.
  591. */
  592. hw_rfkill = iwl_is_rfkill_set(trans);
  593. if (hw_rfkill)
  594. set_bit(STATUS_RFKILL, &trans_pcie->status);
  595. else
  596. clear_bit(STATUS_RFKILL, &trans_pcie->status);
  597. iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
  598. }
  599. }
  600. static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
  601. {
  602. writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
  603. }
  604. static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
  605. {
  606. writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
  607. }
  608. static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
  609. {
  610. return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
  611. }
  612. static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
  613. {
  614. iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
  615. ((reg & 0x000FFFFF) | (3 << 24)));
  616. return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
  617. }
  618. static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
  619. u32 val)
  620. {
  621. iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
  622. ((addr & 0x000FFFFF) | (3 << 24)));
  623. iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
  624. }
  625. static void iwl_trans_pcie_configure(struct iwl_trans *trans,
  626. const struct iwl_trans_config *trans_cfg)
  627. {
  628. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  629. trans_pcie->cmd_queue = trans_cfg->cmd_queue;
  630. trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
  631. if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
  632. trans_pcie->n_no_reclaim_cmds = 0;
  633. else
  634. trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
  635. if (trans_pcie->n_no_reclaim_cmds)
  636. memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
  637. trans_pcie->n_no_reclaim_cmds * sizeof(u8));
  638. trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
  639. if (trans_pcie->rx_buf_size_8k)
  640. trans_pcie->rx_page_order = get_order(8 * 1024);
  641. else
  642. trans_pcie->rx_page_order = get_order(4 * 1024);
  643. trans_pcie->wd_timeout =
  644. msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
  645. trans_pcie->command_names = trans_cfg->command_names;
  646. trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
  647. }
  648. void iwl_trans_pcie_free(struct iwl_trans *trans)
  649. {
  650. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  651. synchronize_irq(trans_pcie->pci_dev->irq);
  652. iwl_pcie_tx_free(trans);
  653. iwl_pcie_rx_free(trans);
  654. free_irq(trans_pcie->pci_dev->irq, trans);
  655. iwl_pcie_free_ict(trans);
  656. pci_disable_msi(trans_pcie->pci_dev);
  657. iounmap(trans_pcie->hw_base);
  658. pci_release_regions(trans_pcie->pci_dev);
  659. pci_disable_device(trans_pcie->pci_dev);
  660. kmem_cache_destroy(trans->dev_cmd_pool);
  661. kfree(trans);
  662. }
  663. static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
  664. {
  665. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  666. if (state)
  667. set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
  668. else
  669. clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
  670. }
  671. static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
  672. unsigned long *flags)
  673. {
  674. int ret;
  675. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  676. spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
  677. /* this bit wakes up the NIC */
  678. __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
  679. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  680. /*
  681. * These bits say the device is running, and should keep running for
  682. * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
  683. * but they do not indicate that embedded SRAM is restored yet;
  684. * 3945 and 4965 have volatile SRAM, and must save/restore contents
  685. * to/from host DRAM when sleeping/waking for power-saving.
  686. * Each direction takes approximately 1/4 millisecond; with this
  687. * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
  688. * series of register accesses are expected (e.g. reading Event Log),
  689. * to keep device from sleeping.
  690. *
  691. * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
  692. * SRAM is okay/restored. We don't check that here because this call
  693. * is just for hardware register access; but GP1 MAC_SLEEP check is a
  694. * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
  695. *
  696. * 5000 series and later (including 1000 series) have non-volatile SRAM,
  697. * and do not save/restore SRAM when power cycling.
  698. */
  699. ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
  700. CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
  701. (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
  702. CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
  703. if (unlikely(ret < 0)) {
  704. iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
  705. if (!silent) {
  706. u32 val = iwl_read32(trans, CSR_GP_CNTRL);
  707. WARN_ONCE(1,
  708. "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
  709. val);
  710. spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
  711. return false;
  712. }
  713. }
  714. /*
  715. * Fool sparse by faking we release the lock - sparse will
  716. * track nic_access anyway.
  717. */
  718. __release(&trans_pcie->reg_lock);
  719. return true;
  720. }
  721. static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
  722. unsigned long *flags)
  723. {
  724. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  725. lockdep_assert_held(&trans_pcie->reg_lock);
  726. /*
  727. * Fool sparse by faking we acquiring the lock - sparse will
  728. * track nic_access anyway.
  729. */
  730. __acquire(&trans_pcie->reg_lock);
  731. __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
  732. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  733. /*
  734. * Above we read the CSR_GP_CNTRL register, which will flush
  735. * any previous writes, but we need the write that clears the
  736. * MAC_ACCESS_REQ bit to be performed before any other writes
  737. * scheduled on different CPUs (after we drop reg_lock).
  738. */
  739. mmiowb();
  740. spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
  741. }
  742. static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
  743. void *buf, int dwords)
  744. {
  745. unsigned long flags;
  746. int offs, ret = 0;
  747. u32 *vals = buf;
  748. if (iwl_trans_grab_nic_access(trans, false, &flags)) {
  749. iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
  750. for (offs = 0; offs < dwords; offs++)
  751. vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
  752. iwl_trans_release_nic_access(trans, &flags);
  753. } else {
  754. ret = -EBUSY;
  755. }
  756. return ret;
  757. }
  758. static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
  759. const void *buf, int dwords)
  760. {
  761. unsigned long flags;
  762. int offs, ret = 0;
  763. const u32 *vals = buf;
  764. if (iwl_trans_grab_nic_access(trans, false, &flags)) {
  765. iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
  766. for (offs = 0; offs < dwords; offs++)
  767. iwl_write32(trans, HBUS_TARG_MEM_WDAT,
  768. vals ? vals[offs] : 0);
  769. iwl_trans_release_nic_access(trans, &flags);
  770. } else {
  771. ret = -EBUSY;
  772. }
  773. return ret;
  774. }
  775. #define IWL_FLUSH_WAIT_MS 2000
  776. static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
  777. {
  778. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  779. struct iwl_txq *txq;
  780. struct iwl_queue *q;
  781. int cnt;
  782. unsigned long now = jiffies;
  783. u32 scd_sram_addr;
  784. u8 buf[16];
  785. int ret = 0;
  786. /* waiting for all the tx frames complete might take a while */
  787. for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
  788. if (cnt == trans_pcie->cmd_queue)
  789. continue;
  790. txq = &trans_pcie->txq[cnt];
  791. q = &txq->q;
  792. while (q->read_ptr != q->write_ptr && !time_after(jiffies,
  793. now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
  794. msleep(1);
  795. if (q->read_ptr != q->write_ptr) {
  796. IWL_ERR(trans,
  797. "fail to flush all tx fifo queues Q %d\n", cnt);
  798. ret = -ETIMEDOUT;
  799. break;
  800. }
  801. }
  802. if (!ret)
  803. return 0;
  804. IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
  805. txq->q.read_ptr, txq->q.write_ptr);
  806. scd_sram_addr = trans_pcie->scd_base_addr +
  807. SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
  808. iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
  809. iwl_print_hex_error(trans, buf, sizeof(buf));
  810. for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
  811. IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
  812. iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
  813. for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
  814. u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
  815. u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
  816. bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
  817. u32 tbl_dw =
  818. iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
  819. SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
  820. if (cnt & 0x1)
  821. tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
  822. else
  823. tbl_dw = tbl_dw & 0x0000FFFF;
  824. IWL_ERR(trans,
  825. "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
  826. cnt, active ? "" : "in", fifo, tbl_dw,
  827. iwl_read_prph(trans,
  828. SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1),
  829. iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
  830. }
  831. return ret;
  832. }
  833. static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
  834. u32 mask, u32 value)
  835. {
  836. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  837. unsigned long flags;
  838. spin_lock_irqsave(&trans_pcie->reg_lock, flags);
  839. __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
  840. spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
  841. }
  842. static const char *get_csr_string(int cmd)
  843. {
  844. #define IWL_CMD(x) case x: return #x
  845. switch (cmd) {
  846. IWL_CMD(CSR_HW_IF_CONFIG_REG);
  847. IWL_CMD(CSR_INT_COALESCING);
  848. IWL_CMD(CSR_INT);
  849. IWL_CMD(CSR_INT_MASK);
  850. IWL_CMD(CSR_FH_INT_STATUS);
  851. IWL_CMD(CSR_GPIO_IN);
  852. IWL_CMD(CSR_RESET);
  853. IWL_CMD(CSR_GP_CNTRL);
  854. IWL_CMD(CSR_HW_REV);
  855. IWL_CMD(CSR_EEPROM_REG);
  856. IWL_CMD(CSR_EEPROM_GP);
  857. IWL_CMD(CSR_OTP_GP_REG);
  858. IWL_CMD(CSR_GIO_REG);
  859. IWL_CMD(CSR_GP_UCODE_REG);
  860. IWL_CMD(CSR_GP_DRIVER_REG);
  861. IWL_CMD(CSR_UCODE_DRV_GP1);
  862. IWL_CMD(CSR_UCODE_DRV_GP2);
  863. IWL_CMD(CSR_LED_REG);
  864. IWL_CMD(CSR_DRAM_INT_TBL_REG);
  865. IWL_CMD(CSR_GIO_CHICKEN_BITS);
  866. IWL_CMD(CSR_ANA_PLL_CFG);
  867. IWL_CMD(CSR_HW_REV_WA_REG);
  868. IWL_CMD(CSR_DBG_HPET_MEM_REG);
  869. default:
  870. return "UNKNOWN";
  871. }
  872. #undef IWL_CMD
  873. }
  874. void iwl_pcie_dump_csr(struct iwl_trans *trans)
  875. {
  876. int i;
  877. static const u32 csr_tbl[] = {
  878. CSR_HW_IF_CONFIG_REG,
  879. CSR_INT_COALESCING,
  880. CSR_INT,
  881. CSR_INT_MASK,
  882. CSR_FH_INT_STATUS,
  883. CSR_GPIO_IN,
  884. CSR_RESET,
  885. CSR_GP_CNTRL,
  886. CSR_HW_REV,
  887. CSR_EEPROM_REG,
  888. CSR_EEPROM_GP,
  889. CSR_OTP_GP_REG,
  890. CSR_GIO_REG,
  891. CSR_GP_UCODE_REG,
  892. CSR_GP_DRIVER_REG,
  893. CSR_UCODE_DRV_GP1,
  894. CSR_UCODE_DRV_GP2,
  895. CSR_LED_REG,
  896. CSR_DRAM_INT_TBL_REG,
  897. CSR_GIO_CHICKEN_BITS,
  898. CSR_ANA_PLL_CFG,
  899. CSR_HW_REV_WA_REG,
  900. CSR_DBG_HPET_MEM_REG
  901. };
  902. IWL_ERR(trans, "CSR values:\n");
  903. IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
  904. "CSR_INT_PERIODIC_REG)\n");
  905. for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
  906. IWL_ERR(trans, " %25s: 0X%08x\n",
  907. get_csr_string(csr_tbl[i]),
  908. iwl_read32(trans, csr_tbl[i]));
  909. }
  910. }
  911. #ifdef CONFIG_IWLWIFI_DEBUGFS
  912. /* create and remove of files */
  913. #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
  914. if (!debugfs_create_file(#name, mode, parent, trans, \
  915. &iwl_dbgfs_##name##_ops)) \
  916. goto err; \
  917. } while (0)
  918. /* file operation */
  919. #define DEBUGFS_READ_FILE_OPS(name) \
  920. static const struct file_operations iwl_dbgfs_##name##_ops = { \
  921. .read = iwl_dbgfs_##name##_read, \
  922. .open = simple_open, \
  923. .llseek = generic_file_llseek, \
  924. };
  925. #define DEBUGFS_WRITE_FILE_OPS(name) \
  926. static const struct file_operations iwl_dbgfs_##name##_ops = { \
  927. .write = iwl_dbgfs_##name##_write, \
  928. .open = simple_open, \
  929. .llseek = generic_file_llseek, \
  930. };
  931. #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
  932. static const struct file_operations iwl_dbgfs_##name##_ops = { \
  933. .write = iwl_dbgfs_##name##_write, \
  934. .read = iwl_dbgfs_##name##_read, \
  935. .open = simple_open, \
  936. .llseek = generic_file_llseek, \
  937. };
  938. static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
  939. char __user *user_buf,
  940. size_t count, loff_t *ppos)
  941. {
  942. struct iwl_trans *trans = file->private_data;
  943. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  944. struct iwl_txq *txq;
  945. struct iwl_queue *q;
  946. char *buf;
  947. int pos = 0;
  948. int cnt;
  949. int ret;
  950. size_t bufsz;
  951. bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
  952. if (!trans_pcie->txq)
  953. return -EAGAIN;
  954. buf = kzalloc(bufsz, GFP_KERNEL);
  955. if (!buf)
  956. return -ENOMEM;
  957. for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
  958. txq = &trans_pcie->txq[cnt];
  959. q = &txq->q;
  960. pos += scnprintf(buf + pos, bufsz - pos,
  961. "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
  962. cnt, q->read_ptr, q->write_ptr,
  963. !!test_bit(cnt, trans_pcie->queue_used),
  964. !!test_bit(cnt, trans_pcie->queue_stopped));
  965. }
  966. ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
  967. kfree(buf);
  968. return ret;
  969. }
  970. static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
  971. char __user *user_buf,
  972. size_t count, loff_t *ppos)
  973. {
  974. struct iwl_trans *trans = file->private_data;
  975. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  976. struct iwl_rxq *rxq = &trans_pcie->rxq;
  977. char buf[256];
  978. int pos = 0;
  979. const size_t bufsz = sizeof(buf);
  980. pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
  981. rxq->read);
  982. pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
  983. rxq->write);
  984. pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
  985. rxq->free_count);
  986. if (rxq->rb_stts) {
  987. pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
  988. le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
  989. } else {
  990. pos += scnprintf(buf + pos, bufsz - pos,
  991. "closed_rb_num: Not Allocated\n");
  992. }
  993. return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
  994. }
  995. static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
  996. char __user *user_buf,
  997. size_t count, loff_t *ppos)
  998. {
  999. struct iwl_trans *trans = file->private_data;
  1000. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  1001. struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
  1002. int pos = 0;
  1003. char *buf;
  1004. int bufsz = 24 * 64; /* 24 items * 64 char per item */
  1005. ssize_t ret;
  1006. buf = kzalloc(bufsz, GFP_KERNEL);
  1007. if (!buf)
  1008. return -ENOMEM;
  1009. pos += scnprintf(buf + pos, bufsz - pos,
  1010. "Interrupt Statistics Report:\n");
  1011. pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
  1012. isr_stats->hw);
  1013. pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
  1014. isr_stats->sw);
  1015. if (isr_stats->sw || isr_stats->hw) {
  1016. pos += scnprintf(buf + pos, bufsz - pos,
  1017. "\tLast Restarting Code: 0x%X\n",
  1018. isr_stats->err_code);
  1019. }
  1020. #ifdef CONFIG_IWLWIFI_DEBUG
  1021. pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
  1022. isr_stats->sch);
  1023. pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
  1024. isr_stats->alive);
  1025. #endif
  1026. pos += scnprintf(buf + pos, bufsz - pos,
  1027. "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
  1028. pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
  1029. isr_stats->ctkill);
  1030. pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
  1031. isr_stats->wakeup);
  1032. pos += scnprintf(buf + pos, bufsz - pos,
  1033. "Rx command responses:\t\t %u\n", isr_stats->rx);
  1034. pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
  1035. isr_stats->tx);
  1036. pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
  1037. isr_stats->unhandled);
  1038. ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
  1039. kfree(buf);
  1040. return ret;
  1041. }
  1042. static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
  1043. const char __user *user_buf,
  1044. size_t count, loff_t *ppos)
  1045. {
  1046. struct iwl_trans *trans = file->private_data;
  1047. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  1048. struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
  1049. char buf[8];
  1050. int buf_size;
  1051. u32 reset_flag;
  1052. memset(buf, 0, sizeof(buf));
  1053. buf_size = min(count, sizeof(buf) - 1);
  1054. if (copy_from_user(buf, user_buf, buf_size))
  1055. return -EFAULT;
  1056. if (sscanf(buf, "%x", &reset_flag) != 1)
  1057. return -EFAULT;
  1058. if (reset_flag == 0)
  1059. memset(isr_stats, 0, sizeof(*isr_stats));
  1060. return count;
  1061. }
  1062. static ssize_t iwl_dbgfs_csr_write(struct file *file,
  1063. const char __user *user_buf,
  1064. size_t count, loff_t *ppos)
  1065. {
  1066. struct iwl_trans *trans = file->private_data;
  1067. char buf[8];
  1068. int buf_size;
  1069. int csr;
  1070. memset(buf, 0, sizeof(buf));
  1071. buf_size = min(count, sizeof(buf) - 1);
  1072. if (copy_from_user(buf, user_buf, buf_size))
  1073. return -EFAULT;
  1074. if (sscanf(buf, "%d", &csr) != 1)
  1075. return -EFAULT;
  1076. iwl_pcie_dump_csr(trans);
  1077. return count;
  1078. }
  1079. static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
  1080. char __user *user_buf,
  1081. size_t count, loff_t *ppos)
  1082. {
  1083. struct iwl_trans *trans = file->private_data;
  1084. char *buf = NULL;
  1085. int pos = 0;
  1086. ssize_t ret = -EFAULT;
  1087. ret = pos = iwl_dump_fh(trans, &buf);
  1088. if (buf) {
  1089. ret = simple_read_from_buffer(user_buf,
  1090. count, ppos, buf, pos);
  1091. kfree(buf);
  1092. }
  1093. return ret;
  1094. }
  1095. DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
  1096. DEBUGFS_READ_FILE_OPS(fh_reg);
  1097. DEBUGFS_READ_FILE_OPS(rx_queue);
  1098. DEBUGFS_READ_FILE_OPS(tx_queue);
  1099. DEBUGFS_WRITE_FILE_OPS(csr);
  1100. /*
  1101. * Create the debugfs files and directories
  1102. *
  1103. */
  1104. static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
  1105. struct dentry *dir)
  1106. {
  1107. DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
  1108. DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
  1109. DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
  1110. DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
  1111. DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
  1112. return 0;
  1113. err:
  1114. IWL_ERR(trans, "failed to create the trans debugfs entry\n");
  1115. return -ENOMEM;
  1116. }
  1117. #else
  1118. static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
  1119. struct dentry *dir)
  1120. {
  1121. return 0;
  1122. }
  1123. #endif /*CONFIG_IWLWIFI_DEBUGFS */
  1124. static const struct iwl_trans_ops trans_ops_pcie = {
  1125. .start_hw = iwl_trans_pcie_start_hw,
  1126. .stop_hw = iwl_trans_pcie_stop_hw,
  1127. .fw_alive = iwl_trans_pcie_fw_alive,
  1128. .start_fw = iwl_trans_pcie_start_fw,
  1129. .stop_device = iwl_trans_pcie_stop_device,
  1130. .d3_suspend = iwl_trans_pcie_d3_suspend,
  1131. .d3_resume = iwl_trans_pcie_d3_resume,
  1132. .send_cmd = iwl_trans_pcie_send_hcmd,
  1133. .tx = iwl_trans_pcie_tx,
  1134. .reclaim = iwl_trans_pcie_reclaim,
  1135. .txq_disable = iwl_trans_pcie_txq_disable,
  1136. .txq_enable = iwl_trans_pcie_txq_enable,
  1137. .dbgfs_register = iwl_trans_pcie_dbgfs_register,
  1138. .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
  1139. .write8 = iwl_trans_pcie_write8,
  1140. .write32 = iwl_trans_pcie_write32,
  1141. .read32 = iwl_trans_pcie_read32,
  1142. .read_prph = iwl_trans_pcie_read_prph,
  1143. .write_prph = iwl_trans_pcie_write_prph,
  1144. .read_mem = iwl_trans_pcie_read_mem,
  1145. .write_mem = iwl_trans_pcie_write_mem,
  1146. .configure = iwl_trans_pcie_configure,
  1147. .set_pmi = iwl_trans_pcie_set_pmi,
  1148. .grab_nic_access = iwl_trans_pcie_grab_nic_access,
  1149. .release_nic_access = iwl_trans_pcie_release_nic_access,
  1150. .set_bits_mask = iwl_trans_pcie_set_bits_mask,
  1151. };
  1152. struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
  1153. const struct pci_device_id *ent,
  1154. const struct iwl_cfg *cfg)
  1155. {
  1156. struct iwl_trans_pcie *trans_pcie;
  1157. struct iwl_trans *trans;
  1158. u16 pci_cmd;
  1159. int err;
  1160. trans = kzalloc(sizeof(struct iwl_trans) +
  1161. sizeof(struct iwl_trans_pcie), GFP_KERNEL);
  1162. if (!trans) {
  1163. err = -ENOMEM;
  1164. goto out;
  1165. }
  1166. trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  1167. trans->ops = &trans_ops_pcie;
  1168. trans->cfg = cfg;
  1169. trans_lockdep_init(trans);
  1170. trans_pcie->trans = trans;
  1171. spin_lock_init(&trans_pcie->irq_lock);
  1172. spin_lock_init(&trans_pcie->reg_lock);
  1173. init_waitqueue_head(&trans_pcie->ucode_write_waitq);
  1174. if (!cfg->base_params->pcie_l1_allowed) {
  1175. /*
  1176. * W/A - seems to solve weird behavior. We need to remove this
  1177. * if we don't want to stay in L1 all the time. This wastes a
  1178. * lot of power.
  1179. */
  1180. pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
  1181. PCIE_LINK_STATE_L1 |
  1182. PCIE_LINK_STATE_CLKPM);
  1183. }
  1184. err = pci_enable_device(pdev);
  1185. if (err)
  1186. goto out_no_pci;
  1187. pci_set_master(pdev);
  1188. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  1189. if (!err)
  1190. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  1191. if (err) {
  1192. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  1193. if (!err)
  1194. err = pci_set_consistent_dma_mask(pdev,
  1195. DMA_BIT_MASK(32));
  1196. /* both attempts failed: */
  1197. if (err) {
  1198. dev_err(&pdev->dev, "No suitable DMA available\n");
  1199. goto out_pci_disable_device;
  1200. }
  1201. }
  1202. err = pci_request_regions(pdev, DRV_NAME);
  1203. if (err) {
  1204. dev_err(&pdev->dev, "pci_request_regions failed\n");
  1205. goto out_pci_disable_device;
  1206. }
  1207. trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
  1208. if (!trans_pcie->hw_base) {
  1209. dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
  1210. err = -ENODEV;
  1211. goto out_pci_release_regions;
  1212. }
  1213. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  1214. * PCI Tx retries from interfering with C3 CPU state */
  1215. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  1216. err = pci_enable_msi(pdev);
  1217. if (err) {
  1218. dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
  1219. /* enable rfkill interrupt: hw bug w/a */
  1220. pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
  1221. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  1222. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  1223. pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
  1224. }
  1225. }
  1226. trans->dev = &pdev->dev;
  1227. trans_pcie->pci_dev = pdev;
  1228. trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
  1229. trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
  1230. snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
  1231. "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
  1232. /* Initialize the wait queue for commands */
  1233. init_waitqueue_head(&trans_pcie->wait_command_queue);
  1234. snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
  1235. "iwl_cmd_pool:%s", dev_name(trans->dev));
  1236. trans->dev_cmd_headroom = 0;
  1237. trans->dev_cmd_pool =
  1238. kmem_cache_create(trans->dev_cmd_pool_name,
  1239. sizeof(struct iwl_device_cmd)
  1240. + trans->dev_cmd_headroom,
  1241. sizeof(void *),
  1242. SLAB_HWCACHE_ALIGN,
  1243. NULL);
  1244. if (!trans->dev_cmd_pool) {
  1245. err = -ENOMEM;
  1246. goto out_pci_disable_msi;
  1247. }
  1248. trans_pcie->inta_mask = CSR_INI_SET_MASK;
  1249. if (iwl_pcie_alloc_ict(trans))
  1250. goto out_free_cmd_pool;
  1251. err = request_threaded_irq(pdev->irq, iwl_pcie_isr_ict,
  1252. iwl_pcie_irq_handler,
  1253. IRQF_SHARED, DRV_NAME, trans);
  1254. if (err) {
  1255. IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
  1256. goto out_free_ict;
  1257. }
  1258. return trans;
  1259. out_free_ict:
  1260. iwl_pcie_free_ict(trans);
  1261. out_free_cmd_pool:
  1262. kmem_cache_destroy(trans->dev_cmd_pool);
  1263. out_pci_disable_msi:
  1264. pci_disable_msi(pdev);
  1265. out_pci_release_regions:
  1266. pci_release_regions(pdev);
  1267. out_pci_disable_device:
  1268. pci_disable_device(pdev);
  1269. out_no_pci:
  1270. kfree(trans);
  1271. out:
  1272. return ERR_PTR(err);
  1273. }