rx.c 39 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/sched.h>
  30. #include <linux/wait.h>
  31. #include <linux/gfp.h>
  32. #include "iwl-prph.h"
  33. #include "iwl-io.h"
  34. #include "internal.h"
  35. #include "iwl-op-mode.h"
  36. /******************************************************************************
  37. *
  38. * RX path functions
  39. *
  40. ******************************************************************************/
  41. /*
  42. * Rx theory of operation
  43. *
  44. * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  45. * each of which point to Receive Buffers to be filled by the NIC. These get
  46. * used not only for Rx frames, but for any command response or notification
  47. * from the NIC. The driver and NIC manage the Rx buffers by means
  48. * of indexes into the circular buffer.
  49. *
  50. * Rx Queue Indexes
  51. * The host/firmware share two index registers for managing the Rx buffers.
  52. *
  53. * The READ index maps to the first position that the firmware may be writing
  54. * to -- the driver can read up to (but not including) this position and get
  55. * good data.
  56. * The READ index is managed by the firmware once the card is enabled.
  57. *
  58. * The WRITE index maps to the last position the driver has read from -- the
  59. * position preceding WRITE is the last slot the firmware can place a packet.
  60. *
  61. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  62. * WRITE = READ.
  63. *
  64. * During initialization, the host sets up the READ queue position to the first
  65. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  66. *
  67. * When the firmware places a packet in a buffer, it will advance the READ index
  68. * and fire the RX interrupt. The driver can then query the READ index and
  69. * process as many packets as possible, moving the WRITE index forward as it
  70. * resets the Rx queue buffers with new memory.
  71. *
  72. * The management in the driver is as follows:
  73. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  74. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  75. * to replenish the iwl->rxq->rx_free.
  76. * + In iwl_pcie_rx_replenish (scheduled) if 'processed' != 'read' then the
  77. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  78. * 'processed' and 'read' driver indexes as well)
  79. * + A received packet is processed and handed to the kernel network stack,
  80. * detached from the iwl->rxq. The driver 'processed' index is updated.
  81. * + The Host/Firmware iwl->rxq is replenished at irq thread time from the
  82. * rx_free list. If there are no allocated buffers in iwl->rxq->rx_free,
  83. * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.
  84. * If there were enough free buffers and RX_STALLED is set it is cleared.
  85. *
  86. *
  87. * Driver sequence:
  88. *
  89. * iwl_rxq_alloc() Allocates rx_free
  90. * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls
  91. * iwl_pcie_rxq_restock
  92. * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx
  93. * queue, updates firmware pointers, and updates
  94. * the WRITE index. If insufficient rx_free buffers
  95. * are available, schedules iwl_pcie_rx_replenish
  96. *
  97. * -- enable interrupts --
  98. * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
  99. * READ INDEX, detaching the SKB from the pool.
  100. * Moves the packet buffer from queue to rx_used.
  101. * Calls iwl_pcie_rxq_restock to refill any empty
  102. * slots.
  103. * ...
  104. *
  105. */
  106. /*
  107. * iwl_rxq_space - Return number of free slots available in queue.
  108. */
  109. static int iwl_rxq_space(const struct iwl_rxq *rxq)
  110. {
  111. /* Make sure RX_QUEUE_SIZE is a power of 2 */
  112. BUILD_BUG_ON(RX_QUEUE_SIZE & (RX_QUEUE_SIZE - 1));
  113. /*
  114. * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity
  115. * between empty and completely full queues.
  116. * The following is equivalent to modulo by RX_QUEUE_SIZE and is well
  117. * defined for negative dividends.
  118. */
  119. return (rxq->read - rxq->write - 1) & (RX_QUEUE_SIZE - 1);
  120. }
  121. /*
  122. * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  123. */
  124. static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)
  125. {
  126. return cpu_to_le32((u32)(dma_addr >> 8));
  127. }
  128. /*
  129. * iwl_pcie_rx_stop - stops the Rx DMA
  130. */
  131. int iwl_pcie_rx_stop(struct iwl_trans *trans)
  132. {
  133. iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  134. return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
  135. FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
  136. }
  137. /*
  138. * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
  139. */
  140. static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans,
  141. struct iwl_rxq *rxq)
  142. {
  143. unsigned long flags;
  144. u32 reg;
  145. spin_lock_irqsave(&rxq->lock, flags);
  146. if (rxq->need_update == 0)
  147. goto exit_unlock;
  148. if (trans->cfg->base_params->shadow_reg_enable) {
  149. /* shadow register enabled */
  150. /* Device expects a multiple of 8 */
  151. rxq->write_actual = (rxq->write & ~0x7);
  152. iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);
  153. } else {
  154. struct iwl_trans_pcie *trans_pcie =
  155. IWL_TRANS_GET_PCIE_TRANS(trans);
  156. /* If power-saving is in use, make sure device is awake */
  157. if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) {
  158. reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
  159. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  160. IWL_DEBUG_INFO(trans,
  161. "Rx queue requesting wakeup,"
  162. " GP1 = 0x%x\n", reg);
  163. iwl_set_bit(trans, CSR_GP_CNTRL,
  164. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  165. goto exit_unlock;
  166. }
  167. rxq->write_actual = (rxq->write & ~0x7);
  168. iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
  169. rxq->write_actual);
  170. /* Else device is assumed to be awake */
  171. } else {
  172. /* Device expects a multiple of 8 */
  173. rxq->write_actual = (rxq->write & ~0x7);
  174. iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
  175. rxq->write_actual);
  176. }
  177. }
  178. rxq->need_update = 0;
  179. exit_unlock:
  180. spin_unlock_irqrestore(&rxq->lock, flags);
  181. }
  182. /*
  183. * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
  184. *
  185. * If there are slots in the RX queue that need to be restocked,
  186. * and we have free pre-allocated buffers, fill the ranks as much
  187. * as we can, pulling from rx_free.
  188. *
  189. * This moves the 'write' index forward to catch up with 'processed', and
  190. * also updates the memory address in the firmware to reference the new
  191. * target buffer.
  192. */
  193. static void iwl_pcie_rxq_restock(struct iwl_trans *trans)
  194. {
  195. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  196. struct iwl_rxq *rxq = &trans_pcie->rxq;
  197. struct iwl_rx_mem_buffer *rxb;
  198. unsigned long flags;
  199. /*
  200. * If the device isn't enabled - not need to try to add buffers...
  201. * This can happen when we stop the device and still have an interrupt
  202. * pending. We stop the APM before we sync the interrupts because we
  203. * have to (see comment there). On the other hand, since the APM is
  204. * stopped, we cannot access the HW (in particular not prph).
  205. * So don't try to restock if the APM has been already stopped.
  206. */
  207. if (!test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status))
  208. return;
  209. spin_lock_irqsave(&rxq->lock, flags);
  210. while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) {
  211. /* The overwritten rxb must be a used one */
  212. rxb = rxq->queue[rxq->write];
  213. BUG_ON(rxb && rxb->page);
  214. /* Get next free Rx buffer, remove from free list */
  215. rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
  216. list);
  217. list_del(&rxb->list);
  218. /* Point to Rx buffer via next RBD in circular buffer */
  219. rxq->bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma);
  220. rxq->queue[rxq->write] = rxb;
  221. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  222. rxq->free_count--;
  223. }
  224. spin_unlock_irqrestore(&rxq->lock, flags);
  225. /* If the pre-allocated buffer pool is dropping low, schedule to
  226. * refill it */
  227. if (rxq->free_count <= RX_LOW_WATERMARK)
  228. schedule_work(&trans_pcie->rx_replenish);
  229. /* If we've added more space for the firmware to place data, tell it.
  230. * Increment device's write pointer in multiples of 8. */
  231. if (rxq->write_actual != (rxq->write & ~0x7)) {
  232. spin_lock_irqsave(&rxq->lock, flags);
  233. rxq->need_update = 1;
  234. spin_unlock_irqrestore(&rxq->lock, flags);
  235. iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
  236. }
  237. }
  238. /*
  239. * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
  240. *
  241. * A used RBD is an Rx buffer that has been given to the stack. To use it again
  242. * a page must be allocated and the RBD must point to the page. This function
  243. * doesn't change the HW pointer but handles the list of pages that is used by
  244. * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
  245. * allocated buffers.
  246. */
  247. static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority)
  248. {
  249. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  250. struct iwl_rxq *rxq = &trans_pcie->rxq;
  251. struct iwl_rx_mem_buffer *rxb;
  252. struct page *page;
  253. unsigned long flags;
  254. gfp_t gfp_mask = priority;
  255. while (1) {
  256. spin_lock_irqsave(&rxq->lock, flags);
  257. if (list_empty(&rxq->rx_used)) {
  258. spin_unlock_irqrestore(&rxq->lock, flags);
  259. return;
  260. }
  261. spin_unlock_irqrestore(&rxq->lock, flags);
  262. if (rxq->free_count > RX_LOW_WATERMARK)
  263. gfp_mask |= __GFP_NOWARN;
  264. if (trans_pcie->rx_page_order > 0)
  265. gfp_mask |= __GFP_COMP;
  266. /* Alloc a new receive buffer */
  267. page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
  268. if (!page) {
  269. if (net_ratelimit())
  270. IWL_DEBUG_INFO(trans, "alloc_pages failed, "
  271. "order: %d\n",
  272. trans_pcie->rx_page_order);
  273. if ((rxq->free_count <= RX_LOW_WATERMARK) &&
  274. net_ratelimit())
  275. IWL_CRIT(trans, "Failed to alloc_pages with %s."
  276. "Only %u free buffers remaining.\n",
  277. priority == GFP_ATOMIC ?
  278. "GFP_ATOMIC" : "GFP_KERNEL",
  279. rxq->free_count);
  280. /* We don't reschedule replenish work here -- we will
  281. * call the restock method and if it still needs
  282. * more buffers it will schedule replenish */
  283. return;
  284. }
  285. spin_lock_irqsave(&rxq->lock, flags);
  286. if (list_empty(&rxq->rx_used)) {
  287. spin_unlock_irqrestore(&rxq->lock, flags);
  288. __free_pages(page, trans_pcie->rx_page_order);
  289. return;
  290. }
  291. rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer,
  292. list);
  293. list_del(&rxb->list);
  294. spin_unlock_irqrestore(&rxq->lock, flags);
  295. BUG_ON(rxb->page);
  296. rxb->page = page;
  297. /* Get physical address of the RB */
  298. rxb->page_dma =
  299. dma_map_page(trans->dev, page, 0,
  300. PAGE_SIZE << trans_pcie->rx_page_order,
  301. DMA_FROM_DEVICE);
  302. if (dma_mapping_error(trans->dev, rxb->page_dma)) {
  303. rxb->page = NULL;
  304. spin_lock_irqsave(&rxq->lock, flags);
  305. list_add(&rxb->list, &rxq->rx_used);
  306. spin_unlock_irqrestore(&rxq->lock, flags);
  307. __free_pages(page, trans_pcie->rx_page_order);
  308. return;
  309. }
  310. /* dma address must be no more than 36 bits */
  311. BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
  312. /* and also 256 byte aligned! */
  313. BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
  314. spin_lock_irqsave(&rxq->lock, flags);
  315. list_add_tail(&rxb->list, &rxq->rx_free);
  316. rxq->free_count++;
  317. spin_unlock_irqrestore(&rxq->lock, flags);
  318. }
  319. }
  320. static void iwl_pcie_rxq_free_rbs(struct iwl_trans *trans)
  321. {
  322. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  323. struct iwl_rxq *rxq = &trans_pcie->rxq;
  324. int i;
  325. lockdep_assert_held(&rxq->lock);
  326. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  327. if (!rxq->pool[i].page)
  328. continue;
  329. dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
  330. PAGE_SIZE << trans_pcie->rx_page_order,
  331. DMA_FROM_DEVICE);
  332. __free_pages(rxq->pool[i].page, trans_pcie->rx_page_order);
  333. rxq->pool[i].page = NULL;
  334. }
  335. }
  336. /*
  337. * iwl_pcie_rx_replenish - Move all used buffers from rx_used to rx_free
  338. *
  339. * When moving to rx_free an page is allocated for the slot.
  340. *
  341. * Also restock the Rx queue via iwl_pcie_rxq_restock.
  342. * This is called as a scheduled work item (except for during initialization)
  343. */
  344. static void iwl_pcie_rx_replenish(struct iwl_trans *trans)
  345. {
  346. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  347. unsigned long flags;
  348. iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL);
  349. spin_lock_irqsave(&trans_pcie->irq_lock, flags);
  350. iwl_pcie_rxq_restock(trans);
  351. spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
  352. }
  353. static void iwl_pcie_rx_replenish_now(struct iwl_trans *trans)
  354. {
  355. iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC);
  356. iwl_pcie_rxq_restock(trans);
  357. }
  358. static void iwl_pcie_rx_replenish_work(struct work_struct *data)
  359. {
  360. struct iwl_trans_pcie *trans_pcie =
  361. container_of(data, struct iwl_trans_pcie, rx_replenish);
  362. iwl_pcie_rx_replenish(trans_pcie->trans);
  363. }
  364. static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
  365. {
  366. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  367. struct iwl_rxq *rxq = &trans_pcie->rxq;
  368. struct device *dev = trans->dev;
  369. memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
  370. spin_lock_init(&rxq->lock);
  371. if (WARN_ON(rxq->bd || rxq->rb_stts))
  372. return -EINVAL;
  373. /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
  374. rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
  375. &rxq->bd_dma, GFP_KERNEL);
  376. if (!rxq->bd)
  377. goto err_bd;
  378. /*Allocate the driver's pointer to receive buffer status */
  379. rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
  380. &rxq->rb_stts_dma, GFP_KERNEL);
  381. if (!rxq->rb_stts)
  382. goto err_rb_stts;
  383. return 0;
  384. err_rb_stts:
  385. dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
  386. rxq->bd, rxq->bd_dma);
  387. rxq->bd_dma = 0;
  388. rxq->bd = NULL;
  389. err_bd:
  390. return -ENOMEM;
  391. }
  392. static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
  393. {
  394. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  395. u32 rb_size;
  396. const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
  397. if (trans_pcie->rx_buf_size_8k)
  398. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
  399. else
  400. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
  401. /* Stop Rx DMA */
  402. iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  403. /* reset and flush pointers */
  404. iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
  405. iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
  406. iwl_write_direct32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
  407. /* Reset driver's Rx queue write index */
  408. iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
  409. /* Tell device where to find RBD circular buffer in DRAM */
  410. iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
  411. (u32)(rxq->bd_dma >> 8));
  412. /* Tell device where in DRAM to update its Rx status */
  413. iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
  414. rxq->rb_stts_dma >> 4);
  415. /* Enable Rx DMA
  416. * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
  417. * the credit mechanism in 5000 HW RX FIFO
  418. * Direct rx interrupts to hosts
  419. * Rx buffer size 4 or 8k
  420. * RB timeout 0x10
  421. * 256 RBDs
  422. */
  423. iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
  424. FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
  425. FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
  426. FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
  427. rb_size|
  428. (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
  429. (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
  430. /* Set interrupt coalescing timer to default (2048 usecs) */
  431. iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
  432. }
  433. static void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq)
  434. {
  435. int i;
  436. lockdep_assert_held(&rxq->lock);
  437. INIT_LIST_HEAD(&rxq->rx_free);
  438. INIT_LIST_HEAD(&rxq->rx_used);
  439. rxq->free_count = 0;
  440. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  441. list_add(&rxq->pool[i].list, &rxq->rx_used);
  442. }
  443. int iwl_pcie_rx_init(struct iwl_trans *trans)
  444. {
  445. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  446. struct iwl_rxq *rxq = &trans_pcie->rxq;
  447. int i, err;
  448. unsigned long flags;
  449. if (!rxq->bd) {
  450. err = iwl_pcie_rx_alloc(trans);
  451. if (err)
  452. return err;
  453. }
  454. spin_lock_irqsave(&rxq->lock, flags);
  455. INIT_WORK(&trans_pcie->rx_replenish, iwl_pcie_rx_replenish_work);
  456. /* free all first - we might be reconfigured for a different size */
  457. iwl_pcie_rxq_free_rbs(trans);
  458. iwl_pcie_rx_init_rxb_lists(rxq);
  459. for (i = 0; i < RX_QUEUE_SIZE; i++)
  460. rxq->queue[i] = NULL;
  461. /* Set us so that we have processed and used all buffers, but have
  462. * not restocked the Rx queue with fresh buffers */
  463. rxq->read = rxq->write = 0;
  464. rxq->write_actual = 0;
  465. memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
  466. spin_unlock_irqrestore(&rxq->lock, flags);
  467. iwl_pcie_rx_replenish(trans);
  468. iwl_pcie_rx_hw_init(trans, rxq);
  469. spin_lock_irqsave(&trans_pcie->irq_lock, flags);
  470. rxq->need_update = 1;
  471. iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
  472. spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
  473. return 0;
  474. }
  475. void iwl_pcie_rx_free(struct iwl_trans *trans)
  476. {
  477. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  478. struct iwl_rxq *rxq = &trans_pcie->rxq;
  479. unsigned long flags;
  480. /*if rxq->bd is NULL, it means that nothing has been allocated,
  481. * exit now */
  482. if (!rxq->bd) {
  483. IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
  484. return;
  485. }
  486. cancel_work_sync(&trans_pcie->rx_replenish);
  487. spin_lock_irqsave(&rxq->lock, flags);
  488. iwl_pcie_rxq_free_rbs(trans);
  489. spin_unlock_irqrestore(&rxq->lock, flags);
  490. dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
  491. rxq->bd, rxq->bd_dma);
  492. rxq->bd_dma = 0;
  493. rxq->bd = NULL;
  494. if (rxq->rb_stts)
  495. dma_free_coherent(trans->dev,
  496. sizeof(struct iwl_rb_status),
  497. rxq->rb_stts, rxq->rb_stts_dma);
  498. else
  499. IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
  500. rxq->rb_stts_dma = 0;
  501. rxq->rb_stts = NULL;
  502. }
  503. static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
  504. struct iwl_rx_mem_buffer *rxb)
  505. {
  506. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  507. struct iwl_rxq *rxq = &trans_pcie->rxq;
  508. struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
  509. unsigned long flags;
  510. bool page_stolen = false;
  511. int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
  512. u32 offset = 0;
  513. if (WARN_ON(!rxb))
  514. return;
  515. dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
  516. while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
  517. struct iwl_rx_packet *pkt;
  518. struct iwl_device_cmd *cmd;
  519. u16 sequence;
  520. bool reclaim;
  521. int index, cmd_index, err, len;
  522. struct iwl_rx_cmd_buffer rxcb = {
  523. ._offset = offset,
  524. ._rx_page_order = trans_pcie->rx_page_order,
  525. ._page = rxb->page,
  526. ._page_stolen = false,
  527. .truesize = max_len,
  528. };
  529. pkt = rxb_addr(&rxcb);
  530. if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID))
  531. break;
  532. IWL_DEBUG_RX(trans, "cmd at offset %d: %s (0x%.2x)\n",
  533. rxcb._offset, get_cmd_string(trans_pcie, pkt->hdr.cmd),
  534. pkt->hdr.cmd);
  535. len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  536. len += sizeof(u32); /* account for status word */
  537. trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len);
  538. trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len);
  539. /* Reclaim a command buffer only if this packet is a response
  540. * to a (driver-originated) command.
  541. * If the packet (e.g. Rx frame) originated from uCode,
  542. * there is no command buffer to reclaim.
  543. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  544. * but apparently a few don't get set; catch them here. */
  545. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
  546. if (reclaim) {
  547. int i;
  548. for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
  549. if (trans_pcie->no_reclaim_cmds[i] ==
  550. pkt->hdr.cmd) {
  551. reclaim = false;
  552. break;
  553. }
  554. }
  555. }
  556. sequence = le16_to_cpu(pkt->hdr.sequence);
  557. index = SEQ_TO_INDEX(sequence);
  558. cmd_index = get_cmd_index(&txq->q, index);
  559. if (reclaim)
  560. cmd = txq->entries[cmd_index].cmd;
  561. else
  562. cmd = NULL;
  563. err = iwl_op_mode_rx(trans->op_mode, &rxcb, cmd);
  564. if (reclaim) {
  565. kfree(txq->entries[cmd_index].free_buf);
  566. txq->entries[cmd_index].free_buf = NULL;
  567. }
  568. /*
  569. * After here, we should always check rxcb._page_stolen,
  570. * if it is true then one of the handlers took the page.
  571. */
  572. if (reclaim) {
  573. /* Invoke any callbacks, transfer the buffer to caller,
  574. * and fire off the (possibly) blocking
  575. * iwl_trans_send_cmd()
  576. * as we reclaim the driver command queue */
  577. if (!rxcb._page_stolen)
  578. iwl_pcie_hcmd_complete(trans, &rxcb, err);
  579. else
  580. IWL_WARN(trans, "Claim null rxb?\n");
  581. }
  582. page_stolen |= rxcb._page_stolen;
  583. offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
  584. }
  585. /* page was stolen from us -- free our reference */
  586. if (page_stolen) {
  587. __free_pages(rxb->page, trans_pcie->rx_page_order);
  588. rxb->page = NULL;
  589. }
  590. /* Reuse the page if possible. For notification packets and
  591. * SKBs that fail to Rx correctly, add them back into the
  592. * rx_free list for reuse later. */
  593. spin_lock_irqsave(&rxq->lock, flags);
  594. if (rxb->page != NULL) {
  595. rxb->page_dma =
  596. dma_map_page(trans->dev, rxb->page, 0,
  597. PAGE_SIZE << trans_pcie->rx_page_order,
  598. DMA_FROM_DEVICE);
  599. if (dma_mapping_error(trans->dev, rxb->page_dma)) {
  600. /*
  601. * free the page(s) as well to not break
  602. * the invariant that the items on the used
  603. * list have no page(s)
  604. */
  605. __free_pages(rxb->page, trans_pcie->rx_page_order);
  606. rxb->page = NULL;
  607. list_add_tail(&rxb->list, &rxq->rx_used);
  608. } else {
  609. list_add_tail(&rxb->list, &rxq->rx_free);
  610. rxq->free_count++;
  611. }
  612. } else
  613. list_add_tail(&rxb->list, &rxq->rx_used);
  614. spin_unlock_irqrestore(&rxq->lock, flags);
  615. }
  616. /*
  617. * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
  618. */
  619. static void iwl_pcie_rx_handle(struct iwl_trans *trans)
  620. {
  621. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  622. struct iwl_rxq *rxq = &trans_pcie->rxq;
  623. u32 r, i;
  624. u8 fill_rx = 0;
  625. u32 count = 8;
  626. int total_empty;
  627. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  628. * buffer that the driver may process (last buffer filled by ucode). */
  629. r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
  630. i = rxq->read;
  631. /* Rx interrupt, but nothing sent from uCode */
  632. if (i == r)
  633. IWL_DEBUG_RX(trans, "HW = SW = %d\n", r);
  634. /* calculate total frames need to be restock after handling RX */
  635. total_empty = r - rxq->write_actual;
  636. if (total_empty < 0)
  637. total_empty += RX_QUEUE_SIZE;
  638. if (total_empty > (RX_QUEUE_SIZE / 2))
  639. fill_rx = 1;
  640. while (i != r) {
  641. struct iwl_rx_mem_buffer *rxb;
  642. rxb = rxq->queue[i];
  643. rxq->queue[i] = NULL;
  644. IWL_DEBUG_RX(trans, "rxbuf: HW = %d, SW = %d (%p)\n",
  645. r, i, rxb);
  646. iwl_pcie_rx_handle_rb(trans, rxb);
  647. i = (i + 1) & RX_QUEUE_MASK;
  648. /* If there are a lot of unused frames,
  649. * restock the Rx queue so ucode wont assert. */
  650. if (fill_rx) {
  651. count++;
  652. if (count >= 8) {
  653. rxq->read = i;
  654. iwl_pcie_rx_replenish_now(trans);
  655. count = 0;
  656. }
  657. }
  658. }
  659. /* Backtrack one entry */
  660. rxq->read = i;
  661. if (fill_rx)
  662. iwl_pcie_rx_replenish_now(trans);
  663. else
  664. iwl_pcie_rxq_restock(trans);
  665. }
  666. /*
  667. * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
  668. */
  669. static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
  670. {
  671. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  672. /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
  673. if (trans->cfg->internal_wimax_coex &&
  674. (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
  675. APMS_CLK_VAL_MRB_FUNC_MODE) ||
  676. (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
  677. APMG_PS_CTRL_VAL_RESET_REQ))) {
  678. clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
  679. iwl_op_mode_wimax_active(trans->op_mode);
  680. wake_up(&trans_pcie->wait_command_queue);
  681. return;
  682. }
  683. iwl_pcie_dump_csr(trans);
  684. iwl_dump_fh(trans, NULL);
  685. set_bit(STATUS_FW_ERROR, &trans_pcie->status);
  686. clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
  687. wake_up(&trans_pcie->wait_command_queue);
  688. local_bh_disable();
  689. iwl_op_mode_nic_error(trans->op_mode);
  690. local_bh_enable();
  691. }
  692. irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
  693. {
  694. struct iwl_trans *trans = dev_id;
  695. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  696. struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
  697. u32 inta = 0;
  698. u32 handled = 0;
  699. unsigned long flags;
  700. u32 i;
  701. lock_map_acquire(&trans->sync_cmd_lockdep_map);
  702. spin_lock_irqsave(&trans_pcie->irq_lock, flags);
  703. /* Ack/clear/reset pending uCode interrupts.
  704. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  705. */
  706. /* There is a hardware bug in the interrupt mask function that some
  707. * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
  708. * they are disabled in the CSR_INT_MASK register. Furthermore the
  709. * ICT interrupt handling mechanism has another bug that might cause
  710. * these unmasked interrupts fail to be detected. We workaround the
  711. * hardware bugs here by ACKing all the possible interrupts so that
  712. * interrupt coalescing can still be achieved.
  713. */
  714. iwl_write32(trans, CSR_INT,
  715. trans_pcie->inta | ~trans_pcie->inta_mask);
  716. inta = trans_pcie->inta;
  717. if (iwl_have_debug_level(IWL_DL_ISR))
  718. IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
  719. inta, iwl_read32(trans, CSR_INT_MASK));
  720. /* saved interrupt in inta variable now we can reset trans_pcie->inta */
  721. trans_pcie->inta = 0;
  722. spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
  723. /* Now service all interrupt bits discovered above. */
  724. if (inta & CSR_INT_BIT_HW_ERR) {
  725. IWL_ERR(trans, "Hardware error detected. Restarting.\n");
  726. /* Tell the device to stop sending interrupts */
  727. iwl_disable_interrupts(trans);
  728. isr_stats->hw++;
  729. iwl_pcie_irq_handle_error(trans);
  730. handled |= CSR_INT_BIT_HW_ERR;
  731. goto out;
  732. }
  733. if (iwl_have_debug_level(IWL_DL_ISR)) {
  734. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  735. if (inta & CSR_INT_BIT_SCD) {
  736. IWL_DEBUG_ISR(trans,
  737. "Scheduler finished to transmit the frame/frames.\n");
  738. isr_stats->sch++;
  739. }
  740. /* Alive notification via Rx interrupt will do the real work */
  741. if (inta & CSR_INT_BIT_ALIVE) {
  742. IWL_DEBUG_ISR(trans, "Alive interrupt\n");
  743. isr_stats->alive++;
  744. }
  745. }
  746. /* Safely ignore these bits for debug checks below */
  747. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  748. /* HW RF KILL switch toggled */
  749. if (inta & CSR_INT_BIT_RF_KILL) {
  750. bool hw_rfkill;
  751. hw_rfkill = iwl_is_rfkill_set(trans);
  752. IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
  753. hw_rfkill ? "disable radio" : "enable radio");
  754. isr_stats->rfkill++;
  755. iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
  756. if (hw_rfkill) {
  757. set_bit(STATUS_RFKILL, &trans_pcie->status);
  758. if (test_and_clear_bit(STATUS_HCMD_ACTIVE,
  759. &trans_pcie->status))
  760. IWL_DEBUG_RF_KILL(trans,
  761. "Rfkill while SYNC HCMD in flight\n");
  762. wake_up(&trans_pcie->wait_command_queue);
  763. } else {
  764. clear_bit(STATUS_RFKILL, &trans_pcie->status);
  765. }
  766. handled |= CSR_INT_BIT_RF_KILL;
  767. }
  768. /* Chip got too hot and stopped itself */
  769. if (inta & CSR_INT_BIT_CT_KILL) {
  770. IWL_ERR(trans, "Microcode CT kill error detected.\n");
  771. isr_stats->ctkill++;
  772. handled |= CSR_INT_BIT_CT_KILL;
  773. }
  774. /* Error detected by uCode */
  775. if (inta & CSR_INT_BIT_SW_ERR) {
  776. IWL_ERR(trans, "Microcode SW error detected. "
  777. " Restarting 0x%X.\n", inta);
  778. isr_stats->sw++;
  779. iwl_pcie_irq_handle_error(trans);
  780. handled |= CSR_INT_BIT_SW_ERR;
  781. }
  782. /* uCode wakes up after power-down sleep */
  783. if (inta & CSR_INT_BIT_WAKEUP) {
  784. IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
  785. iwl_pcie_rxq_inc_wr_ptr(trans, &trans_pcie->rxq);
  786. for (i = 0; i < trans->cfg->base_params->num_of_queues; i++)
  787. iwl_pcie_txq_inc_wr_ptr(trans, &trans_pcie->txq[i]);
  788. isr_stats->wakeup++;
  789. handled |= CSR_INT_BIT_WAKEUP;
  790. }
  791. /* All uCode command responses, including Tx command responses,
  792. * Rx "responses" (frame-received notification), and other
  793. * notifications from uCode come through here*/
  794. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  795. CSR_INT_BIT_RX_PERIODIC)) {
  796. IWL_DEBUG_ISR(trans, "Rx interrupt\n");
  797. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  798. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  799. iwl_write32(trans, CSR_FH_INT_STATUS,
  800. CSR_FH_INT_RX_MASK);
  801. }
  802. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  803. handled |= CSR_INT_BIT_RX_PERIODIC;
  804. iwl_write32(trans,
  805. CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  806. }
  807. /* Sending RX interrupt require many steps to be done in the
  808. * the device:
  809. * 1- write interrupt to current index in ICT table.
  810. * 2- dma RX frame.
  811. * 3- update RX shared data to indicate last write index.
  812. * 4- send interrupt.
  813. * This could lead to RX race, driver could receive RX interrupt
  814. * but the shared data changes does not reflect this;
  815. * periodic interrupt will detect any dangling Rx activity.
  816. */
  817. /* Disable periodic interrupt; we use it as just a one-shot. */
  818. iwl_write8(trans, CSR_INT_PERIODIC_REG,
  819. CSR_INT_PERIODIC_DIS);
  820. iwl_pcie_rx_handle(trans);
  821. /*
  822. * Enable periodic interrupt in 8 msec only if we received
  823. * real RX interrupt (instead of just periodic int), to catch
  824. * any dangling Rx interrupt. If it was just the periodic
  825. * interrupt, there was no dangling Rx activity, and no need
  826. * to extend the periodic interrupt; one-shot is enough.
  827. */
  828. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  829. iwl_write8(trans, CSR_INT_PERIODIC_REG,
  830. CSR_INT_PERIODIC_ENA);
  831. isr_stats->rx++;
  832. }
  833. /* This "Tx" DMA channel is used only for loading uCode */
  834. if (inta & CSR_INT_BIT_FH_TX) {
  835. iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
  836. IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
  837. isr_stats->tx++;
  838. handled |= CSR_INT_BIT_FH_TX;
  839. /* Wake up uCode load routine, now that load is complete */
  840. trans_pcie->ucode_write_complete = true;
  841. wake_up(&trans_pcie->ucode_write_waitq);
  842. }
  843. if (inta & ~handled) {
  844. IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  845. isr_stats->unhandled++;
  846. }
  847. if (inta & ~(trans_pcie->inta_mask)) {
  848. IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
  849. inta & ~trans_pcie->inta_mask);
  850. }
  851. /* Re-enable all interrupts */
  852. /* only Re-enable if disabled by irq */
  853. if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status))
  854. iwl_enable_interrupts(trans);
  855. /* Re-enable RF_KILL if it occurred */
  856. else if (handled & CSR_INT_BIT_RF_KILL)
  857. iwl_enable_rfkill_int(trans);
  858. out:
  859. lock_map_release(&trans->sync_cmd_lockdep_map);
  860. return IRQ_HANDLED;
  861. }
  862. /******************************************************************************
  863. *
  864. * ICT functions
  865. *
  866. ******************************************************************************/
  867. /* a device (PCI-E) page is 4096 bytes long */
  868. #define ICT_SHIFT 12
  869. #define ICT_SIZE (1 << ICT_SHIFT)
  870. #define ICT_COUNT (ICT_SIZE / sizeof(u32))
  871. /* Free dram table */
  872. void iwl_pcie_free_ict(struct iwl_trans *trans)
  873. {
  874. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  875. if (trans_pcie->ict_tbl) {
  876. dma_free_coherent(trans->dev, ICT_SIZE,
  877. trans_pcie->ict_tbl,
  878. trans_pcie->ict_tbl_dma);
  879. trans_pcie->ict_tbl = NULL;
  880. trans_pcie->ict_tbl_dma = 0;
  881. }
  882. }
  883. /*
  884. * allocate dram shared table, it is an aligned memory
  885. * block of ICT_SIZE.
  886. * also reset all data related to ICT table interrupt.
  887. */
  888. int iwl_pcie_alloc_ict(struct iwl_trans *trans)
  889. {
  890. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  891. trans_pcie->ict_tbl =
  892. dma_alloc_coherent(trans->dev, ICT_SIZE,
  893. &trans_pcie->ict_tbl_dma,
  894. GFP_KERNEL);
  895. if (!trans_pcie->ict_tbl)
  896. return -ENOMEM;
  897. /* just an API sanity check ... it is guaranteed to be aligned */
  898. if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
  899. iwl_pcie_free_ict(trans);
  900. return -EINVAL;
  901. }
  902. IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
  903. (unsigned long long)trans_pcie->ict_tbl_dma);
  904. IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);
  905. /* reset table and index to all 0 */
  906. memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
  907. trans_pcie->ict_index = 0;
  908. /* add periodic RX interrupt */
  909. trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
  910. return 0;
  911. }
  912. /* Device is going up inform it about using ICT interrupt table,
  913. * also we need to tell the driver to start using ICT interrupt.
  914. */
  915. void iwl_pcie_reset_ict(struct iwl_trans *trans)
  916. {
  917. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  918. u32 val;
  919. unsigned long flags;
  920. if (!trans_pcie->ict_tbl)
  921. return;
  922. spin_lock_irqsave(&trans_pcie->irq_lock, flags);
  923. iwl_disable_interrupts(trans);
  924. memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
  925. val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
  926. val |= CSR_DRAM_INT_TBL_ENABLE;
  927. val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
  928. IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
  929. iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
  930. trans_pcie->use_ict = true;
  931. trans_pcie->ict_index = 0;
  932. iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
  933. iwl_enable_interrupts(trans);
  934. spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
  935. }
  936. /* Device is going down disable ict interrupt usage */
  937. void iwl_pcie_disable_ict(struct iwl_trans *trans)
  938. {
  939. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  940. unsigned long flags;
  941. spin_lock_irqsave(&trans_pcie->irq_lock, flags);
  942. trans_pcie->use_ict = false;
  943. spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
  944. }
  945. /* legacy (non-ICT) ISR. Assumes that trans_pcie->irq_lock is held */
  946. static irqreturn_t iwl_pcie_isr(int irq, void *data)
  947. {
  948. struct iwl_trans *trans = data;
  949. struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  950. u32 inta, inta_mask;
  951. irqreturn_t ret = IRQ_NONE;
  952. lockdep_assert_held(&trans_pcie->irq_lock);
  953. trace_iwlwifi_dev_irq(trans->dev);
  954. /* Disable (but don't clear!) interrupts here to avoid
  955. * back-to-back ISRs and sporadic interrupts from our NIC.
  956. * If we have something to service, the irq thread will re-enable ints.
  957. * If we *don't* have something, we'll re-enable before leaving here. */
  958. inta_mask = iwl_read32(trans, CSR_INT_MASK);
  959. iwl_write32(trans, CSR_INT_MASK, 0x00000000);
  960. /* Discover which interrupts are active/pending */
  961. inta = iwl_read32(trans, CSR_INT);
  962. if (inta & (~inta_mask)) {
  963. IWL_DEBUG_ISR(trans,
  964. "We got a masked interrupt (0x%08x)...Ack and ignore\n",
  965. inta & (~inta_mask));
  966. iwl_write32(trans, CSR_INT, inta & (~inta_mask));
  967. inta &= inta_mask;
  968. }
  969. /* Ignore interrupt if there's nothing in NIC to service.
  970. * This may be due to IRQ shared with another device,
  971. * or due to sporadic interrupts thrown from our NIC. */
  972. if (!inta) {
  973. IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
  974. goto none;
  975. }
  976. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  977. /* Hardware disappeared. It might have already raised
  978. * an interrupt */
  979. IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  980. return IRQ_HANDLED;
  981. }
  982. if (iwl_have_debug_level(IWL_DL_ISR))
  983. IWL_DEBUG_ISR(trans,
  984. "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  985. inta, inta_mask,
  986. iwl_read32(trans, CSR_FH_INT_STATUS));
  987. trans_pcie->inta |= inta;
  988. /* the thread will service interrupts and re-enable them */
  989. if (likely(inta))
  990. return IRQ_WAKE_THREAD;
  991. ret = IRQ_HANDLED;
  992. none:
  993. /* re-enable interrupts here since we don't have anything to service. */
  994. /* only Re-enable if disabled by irq and no schedules tasklet. */
  995. if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
  996. !trans_pcie->inta)
  997. iwl_enable_interrupts(trans);
  998. return ret;
  999. }
  1000. /* interrupt handler using ict table, with this interrupt driver will
  1001. * stop using INTA register to get device's interrupt, reading this register
  1002. * is expensive, device will write interrupts in ICT dram table, increment
  1003. * index then will fire interrupt to driver, driver will OR all ICT table
  1004. * entries from current index up to table entry with 0 value. the result is
  1005. * the interrupt we need to service, driver will set the entries back to 0 and
  1006. * set index.
  1007. */
  1008. irqreturn_t iwl_pcie_isr_ict(int irq, void *data)
  1009. {
  1010. struct iwl_trans *trans = data;
  1011. struct iwl_trans_pcie *trans_pcie;
  1012. u32 inta;
  1013. u32 val = 0;
  1014. u32 read;
  1015. unsigned long flags;
  1016. irqreturn_t ret = IRQ_NONE;
  1017. if (!trans)
  1018. return IRQ_NONE;
  1019. trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  1020. spin_lock_irqsave(&trans_pcie->irq_lock, flags);
  1021. /* dram interrupt table not set yet,
  1022. * use legacy interrupt.
  1023. */
  1024. if (unlikely(!trans_pcie->use_ict)) {
  1025. ret = iwl_pcie_isr(irq, data);
  1026. spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
  1027. return ret;
  1028. }
  1029. trace_iwlwifi_dev_irq(trans->dev);
  1030. /* Disable (but don't clear!) interrupts here to avoid
  1031. * back-to-back ISRs and sporadic interrupts from our NIC.
  1032. * If we have something to service, the tasklet will re-enable ints.
  1033. * If we *don't* have something, we'll re-enable before leaving here.
  1034. */
  1035. iwl_write32(trans, CSR_INT_MASK, 0x00000000);
  1036. /* Ignore interrupt if there's nothing in NIC to service.
  1037. * This may be due to IRQ shared with another device,
  1038. * or due to sporadic interrupts thrown from our NIC. */
  1039. read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
  1040. trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
  1041. if (!read) {
  1042. IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
  1043. goto none;
  1044. }
  1045. /*
  1046. * Collect all entries up to the first 0, starting from ict_index;
  1047. * note we already read at ict_index.
  1048. */
  1049. do {
  1050. val |= read;
  1051. IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
  1052. trans_pcie->ict_index, read);
  1053. trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
  1054. trans_pcie->ict_index =
  1055. iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
  1056. read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
  1057. trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
  1058. read);
  1059. } while (read);
  1060. /* We should not get this value, just ignore it. */
  1061. if (val == 0xffffffff)
  1062. val = 0;
  1063. /*
  1064. * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
  1065. * (bit 15 before shifting it to 31) to clear when using interrupt
  1066. * coalescing. fortunately, bits 18 and 19 stay set when this happens
  1067. * so we use them to decide on the real state of the Rx bit.
  1068. * In order words, bit 15 is set if bit 18 or bit 19 are set.
  1069. */
  1070. if (val & 0xC0000)
  1071. val |= 0x8000;
  1072. inta = (0xff & val) | ((0xff00 & val) << 16);
  1073. IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled(sw) 0x%08x ict 0x%08x\n",
  1074. inta, trans_pcie->inta_mask, val);
  1075. if (iwl_have_debug_level(IWL_DL_ISR))
  1076. IWL_DEBUG_ISR(trans, "enabled(hw) 0x%08x\n",
  1077. iwl_read32(trans, CSR_INT_MASK));
  1078. inta &= trans_pcie->inta_mask;
  1079. trans_pcie->inta |= inta;
  1080. /* iwl_pcie_tasklet() will service interrupts and re-enable them */
  1081. if (likely(inta)) {
  1082. spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
  1083. return IRQ_WAKE_THREAD;
  1084. }
  1085. ret = IRQ_HANDLED;
  1086. none:
  1087. /* re-enable interrupts here since we don't have anything to service.
  1088. * only Re-enable if disabled by irq.
  1089. */
  1090. if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
  1091. !trans_pcie->inta)
  1092. iwl_enable_interrupts(trans);
  1093. spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
  1094. return ret;
  1095. }