txrx.c 24 KB

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  1. /*
  2. * Copyright (c) 2012 Qualcomm Atheros, Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/etherdevice.h>
  17. #include <net/ieee80211_radiotap.h>
  18. #include <linux/if_arp.h>
  19. #include <linux/moduleparam.h>
  20. #include <linux/ip.h>
  21. #include <linux/ipv6.h>
  22. #include <net/ipv6.h>
  23. #include "wil6210.h"
  24. #include "wmi.h"
  25. #include "txrx.h"
  26. #include "trace.h"
  27. static bool rtap_include_phy_info;
  28. module_param(rtap_include_phy_info, bool, S_IRUGO);
  29. MODULE_PARM_DESC(rtap_include_phy_info,
  30. " Include PHY info in the radiotap header, default - no");
  31. static inline int wil_vring_is_empty(struct vring *vring)
  32. {
  33. return vring->swhead == vring->swtail;
  34. }
  35. static inline u32 wil_vring_next_tail(struct vring *vring)
  36. {
  37. return (vring->swtail + 1) % vring->size;
  38. }
  39. static inline void wil_vring_advance_head(struct vring *vring, int n)
  40. {
  41. vring->swhead = (vring->swhead + n) % vring->size;
  42. }
  43. static inline int wil_vring_is_full(struct vring *vring)
  44. {
  45. return wil_vring_next_tail(vring) == vring->swhead;
  46. }
  47. /*
  48. * Available space in Tx Vring
  49. */
  50. static inline int wil_vring_avail_tx(struct vring *vring)
  51. {
  52. u32 swhead = vring->swhead;
  53. u32 swtail = vring->swtail;
  54. int used = (vring->size + swhead - swtail) % vring->size;
  55. return vring->size - used - 1;
  56. }
  57. static int wil_vring_alloc(struct wil6210_priv *wil, struct vring *vring)
  58. {
  59. struct device *dev = wil_to_dev(wil);
  60. size_t sz = vring->size * sizeof(vring->va[0]);
  61. uint i;
  62. BUILD_BUG_ON(sizeof(vring->va[0]) != 32);
  63. vring->swhead = 0;
  64. vring->swtail = 0;
  65. vring->ctx = kcalloc(vring->size, sizeof(vring->ctx[0]), GFP_KERNEL);
  66. if (!vring->ctx) {
  67. vring->va = NULL;
  68. return -ENOMEM;
  69. }
  70. /*
  71. * vring->va should be aligned on its size rounded up to power of 2
  72. * This is granted by the dma_alloc_coherent
  73. */
  74. vring->va = dma_alloc_coherent(dev, sz, &vring->pa, GFP_KERNEL);
  75. if (!vring->va) {
  76. kfree(vring->ctx);
  77. vring->ctx = NULL;
  78. return -ENOMEM;
  79. }
  80. /* initially, all descriptors are SW owned
  81. * For Tx and Rx, ownership bit is at the same location, thus
  82. * we can use any
  83. */
  84. for (i = 0; i < vring->size; i++) {
  85. volatile struct vring_tx_desc *_d = &(vring->va[i].tx);
  86. _d->dma.status = TX_DMA_STATUS_DU;
  87. }
  88. wil_dbg_misc(wil, "vring[%d] 0x%p:0x%016llx 0x%p\n", vring->size,
  89. vring->va, (unsigned long long)vring->pa, vring->ctx);
  90. return 0;
  91. }
  92. static void wil_vring_free(struct wil6210_priv *wil, struct vring *vring,
  93. int tx)
  94. {
  95. struct device *dev = wil_to_dev(wil);
  96. size_t sz = vring->size * sizeof(vring->va[0]);
  97. while (!wil_vring_is_empty(vring)) {
  98. dma_addr_t pa;
  99. u16 dmalen;
  100. struct wil_ctx *ctx;
  101. if (tx) {
  102. struct vring_tx_desc dd, *d = &dd;
  103. volatile struct vring_tx_desc *_d =
  104. &vring->va[vring->swtail].tx;
  105. ctx = &vring->ctx[vring->swtail];
  106. *d = *_d;
  107. pa = wil_desc_addr(&d->dma.addr);
  108. dmalen = le16_to_cpu(d->dma.length);
  109. if (vring->ctx[vring->swtail].mapped_as_page) {
  110. dma_unmap_page(dev, pa, dmalen,
  111. DMA_TO_DEVICE);
  112. } else {
  113. dma_unmap_single(dev, pa, dmalen,
  114. DMA_TO_DEVICE);
  115. }
  116. if (ctx->skb)
  117. dev_kfree_skb_any(ctx->skb);
  118. vring->swtail = wil_vring_next_tail(vring);
  119. } else { /* rx */
  120. struct vring_rx_desc dd, *d = &dd;
  121. volatile struct vring_rx_desc *_d =
  122. &vring->va[vring->swhead].rx;
  123. ctx = &vring->ctx[vring->swhead];
  124. *d = *_d;
  125. pa = wil_desc_addr(&d->dma.addr);
  126. dmalen = le16_to_cpu(d->dma.length);
  127. dma_unmap_single(dev, pa, dmalen, DMA_FROM_DEVICE);
  128. kfree_skb(ctx->skb);
  129. wil_vring_advance_head(vring, 1);
  130. }
  131. }
  132. dma_free_coherent(dev, sz, (void *)vring->va, vring->pa);
  133. kfree(vring->ctx);
  134. vring->pa = 0;
  135. vring->va = NULL;
  136. vring->ctx = NULL;
  137. }
  138. /**
  139. * Allocate one skb for Rx VRING
  140. *
  141. * Safe to call from IRQ
  142. */
  143. static int wil_vring_alloc_skb(struct wil6210_priv *wil, struct vring *vring,
  144. u32 i, int headroom)
  145. {
  146. struct device *dev = wil_to_dev(wil);
  147. unsigned int sz = RX_BUF_LEN;
  148. struct vring_rx_desc dd, *d = &dd;
  149. volatile struct vring_rx_desc *_d = &(vring->va[i].rx);
  150. dma_addr_t pa;
  151. /* TODO align */
  152. struct sk_buff *skb = dev_alloc_skb(sz + headroom);
  153. if (unlikely(!skb))
  154. return -ENOMEM;
  155. skb_reserve(skb, headroom);
  156. skb_put(skb, sz);
  157. pa = dma_map_single(dev, skb->data, skb->len, DMA_FROM_DEVICE);
  158. if (unlikely(dma_mapping_error(dev, pa))) {
  159. kfree_skb(skb);
  160. return -ENOMEM;
  161. }
  162. d->dma.d0 = BIT(9) | RX_DMA_D0_CMD_DMA_IT;
  163. wil_desc_addr_set(&d->dma.addr, pa);
  164. /* ip_length don't care */
  165. /* b11 don't care */
  166. /* error don't care */
  167. d->dma.status = 0; /* BIT(0) should be 0 for HW_OWNED */
  168. d->dma.length = cpu_to_le16(sz);
  169. *_d = *d;
  170. vring->ctx[i].skb = skb;
  171. return 0;
  172. }
  173. /**
  174. * Adds radiotap header
  175. *
  176. * Any error indicated as "Bad FCS"
  177. *
  178. * Vendor data for 04:ce:14-1 (Wilocity-1) consists of:
  179. * - Rx descriptor: 32 bytes
  180. * - Phy info
  181. */
  182. static void wil_rx_add_radiotap_header(struct wil6210_priv *wil,
  183. struct sk_buff *skb)
  184. {
  185. struct wireless_dev *wdev = wil->wdev;
  186. struct wil6210_rtap {
  187. struct ieee80211_radiotap_header rthdr;
  188. /* fields should be in the order of bits in rthdr.it_present */
  189. /* flags */
  190. u8 flags;
  191. /* channel */
  192. __le16 chnl_freq __aligned(2);
  193. __le16 chnl_flags;
  194. /* MCS */
  195. u8 mcs_present;
  196. u8 mcs_flags;
  197. u8 mcs_index;
  198. } __packed;
  199. struct wil6210_rtap_vendor {
  200. struct wil6210_rtap rtap;
  201. /* vendor */
  202. u8 vendor_oui[3] __aligned(2);
  203. u8 vendor_ns;
  204. __le16 vendor_skip;
  205. u8 vendor_data[0];
  206. } __packed;
  207. struct vring_rx_desc *d = wil_skb_rxdesc(skb);
  208. struct wil6210_rtap_vendor *rtap_vendor;
  209. int rtap_len = sizeof(struct wil6210_rtap);
  210. int phy_length = 0; /* phy info header size, bytes */
  211. static char phy_data[128];
  212. struct ieee80211_channel *ch = wdev->preset_chandef.chan;
  213. if (rtap_include_phy_info) {
  214. rtap_len = sizeof(*rtap_vendor) + sizeof(*d);
  215. /* calculate additional length */
  216. if (d->dma.status & RX_DMA_STATUS_PHY_INFO) {
  217. /**
  218. * PHY info starts from 8-byte boundary
  219. * there are 8-byte lines, last line may be partially
  220. * written (HW bug), thus FW configures for last line
  221. * to be excessive. Driver skips this last line.
  222. */
  223. int len = min_t(int, 8 + sizeof(phy_data),
  224. wil_rxdesc_phy_length(d));
  225. if (len > 8) {
  226. void *p = skb_tail_pointer(skb);
  227. void *pa = PTR_ALIGN(p, 8);
  228. if (skb_tailroom(skb) >= len + (pa - p)) {
  229. phy_length = len - 8;
  230. memcpy(phy_data, pa, phy_length);
  231. }
  232. }
  233. }
  234. rtap_len += phy_length;
  235. }
  236. if (skb_headroom(skb) < rtap_len &&
  237. pskb_expand_head(skb, rtap_len, 0, GFP_ATOMIC)) {
  238. wil_err(wil, "Unable to expand headrom to %d\n", rtap_len);
  239. return;
  240. }
  241. rtap_vendor = (void *)skb_push(skb, rtap_len);
  242. memset(rtap_vendor, 0, rtap_len);
  243. rtap_vendor->rtap.rthdr.it_version = PKTHDR_RADIOTAP_VERSION;
  244. rtap_vendor->rtap.rthdr.it_len = cpu_to_le16(rtap_len);
  245. rtap_vendor->rtap.rthdr.it_present = cpu_to_le32(
  246. (1 << IEEE80211_RADIOTAP_FLAGS) |
  247. (1 << IEEE80211_RADIOTAP_CHANNEL) |
  248. (1 << IEEE80211_RADIOTAP_MCS));
  249. if (d->dma.status & RX_DMA_STATUS_ERROR)
  250. rtap_vendor->rtap.flags |= IEEE80211_RADIOTAP_F_BADFCS;
  251. rtap_vendor->rtap.chnl_freq = cpu_to_le16(ch ? ch->center_freq : 58320);
  252. rtap_vendor->rtap.chnl_flags = cpu_to_le16(0);
  253. rtap_vendor->rtap.mcs_present = IEEE80211_RADIOTAP_MCS_HAVE_MCS;
  254. rtap_vendor->rtap.mcs_flags = 0;
  255. rtap_vendor->rtap.mcs_index = wil_rxdesc_mcs(d);
  256. if (rtap_include_phy_info) {
  257. rtap_vendor->rtap.rthdr.it_present |= cpu_to_le32(1 <<
  258. IEEE80211_RADIOTAP_VENDOR_NAMESPACE);
  259. /* OUI for Wilocity 04:ce:14 */
  260. rtap_vendor->vendor_oui[0] = 0x04;
  261. rtap_vendor->vendor_oui[1] = 0xce;
  262. rtap_vendor->vendor_oui[2] = 0x14;
  263. rtap_vendor->vendor_ns = 1;
  264. /* Rx descriptor + PHY data */
  265. rtap_vendor->vendor_skip = cpu_to_le16(sizeof(*d) +
  266. phy_length);
  267. memcpy(rtap_vendor->vendor_data, (void *)d, sizeof(*d));
  268. memcpy(rtap_vendor->vendor_data + sizeof(*d), phy_data,
  269. phy_length);
  270. }
  271. }
  272. /*
  273. * Fast swap in place between 2 registers
  274. */
  275. static void wil_swap_u16(u16 *a, u16 *b)
  276. {
  277. *a ^= *b;
  278. *b ^= *a;
  279. *a ^= *b;
  280. }
  281. static void wil_swap_ethaddr(void *data)
  282. {
  283. struct ethhdr *eth = data;
  284. u16 *s = (u16 *)eth->h_source;
  285. u16 *d = (u16 *)eth->h_dest;
  286. wil_swap_u16(s++, d++);
  287. wil_swap_u16(s++, d++);
  288. wil_swap_u16(s, d);
  289. }
  290. /**
  291. * reap 1 frame from @swhead
  292. *
  293. * Rx descriptor copied to skb->cb
  294. *
  295. * Safe to call from IRQ
  296. */
  297. static struct sk_buff *wil_vring_reap_rx(struct wil6210_priv *wil,
  298. struct vring *vring)
  299. {
  300. struct device *dev = wil_to_dev(wil);
  301. struct net_device *ndev = wil_to_ndev(wil);
  302. volatile struct vring_rx_desc *_d;
  303. struct vring_rx_desc *d;
  304. struct sk_buff *skb;
  305. dma_addr_t pa;
  306. unsigned int sz = RX_BUF_LEN;
  307. u16 dmalen;
  308. u8 ftype;
  309. u8 ds_bits;
  310. BUILD_BUG_ON(sizeof(struct vring_rx_desc) > sizeof(skb->cb));
  311. if (wil_vring_is_empty(vring))
  312. return NULL;
  313. _d = &(vring->va[vring->swhead].rx);
  314. if (!(_d->dma.status & RX_DMA_STATUS_DU)) {
  315. /* it is not error, we just reached end of Rx done area */
  316. return NULL;
  317. }
  318. skb = vring->ctx[vring->swhead].skb;
  319. d = wil_skb_rxdesc(skb);
  320. *d = *_d;
  321. pa = wil_desc_addr(&d->dma.addr);
  322. vring->ctx[vring->swhead].skb = NULL;
  323. wil_vring_advance_head(vring, 1);
  324. dma_unmap_single(dev, pa, sz, DMA_FROM_DEVICE);
  325. dmalen = le16_to_cpu(d->dma.length);
  326. trace_wil6210_rx(vring->swhead, d);
  327. wil_dbg_txrx(wil, "Rx[%3d] : %d bytes\n", vring->swhead, dmalen);
  328. wil_hex_dump_txrx("Rx ", DUMP_PREFIX_NONE, 32, 4,
  329. (const void *)d, sizeof(*d), false);
  330. if (dmalen > sz) {
  331. wil_err(wil, "Rx size too large: %d bytes!\n", dmalen);
  332. kfree_skb(skb);
  333. return NULL;
  334. }
  335. skb_trim(skb, dmalen);
  336. wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1,
  337. skb->data, skb_headlen(skb), false);
  338. wil->stats.last_mcs_rx = wil_rxdesc_mcs(d);
  339. /* use radiotap header only if required */
  340. if (ndev->type == ARPHRD_IEEE80211_RADIOTAP)
  341. wil_rx_add_radiotap_header(wil, skb);
  342. /* no extra checks if in sniffer mode */
  343. if (ndev->type != ARPHRD_ETHER)
  344. return skb;
  345. /*
  346. * Non-data frames may be delivered through Rx DMA channel (ex: BAR)
  347. * Driver should recognize it by frame type, that is found
  348. * in Rx descriptor. If type is not data, it is 802.11 frame as is
  349. */
  350. ftype = wil_rxdesc_ftype(d) << 2;
  351. if (ftype != IEEE80211_FTYPE_DATA) {
  352. wil_dbg_txrx(wil, "Non-data frame ftype 0x%08x\n", ftype);
  353. /* TODO: process it */
  354. kfree_skb(skb);
  355. return NULL;
  356. }
  357. if (skb->len < ETH_HLEN) {
  358. wil_err(wil, "Short frame, len = %d\n", skb->len);
  359. /* TODO: process it (i.e. BAR) */
  360. kfree_skb(skb);
  361. return NULL;
  362. }
  363. /* L4 IDENT is on when HW calculated checksum, check status
  364. * and in case of error drop the packet
  365. * higher stack layers will handle retransmission (if required)
  366. */
  367. if (d->dma.status & RX_DMA_STATUS_L4_IDENT) {
  368. /* L4 protocol identified, csum calculated */
  369. if ((d->dma.error & RX_DMA_ERROR_L4_ERR) == 0)
  370. skb->ip_summed = CHECKSUM_UNNECESSARY;
  371. /* If HW reports bad checksum, let IP stack re-check it
  372. * For example, HW don't understand Microsoft IP stack that
  373. * mis-calculates TCP checksum - if it should be 0x0,
  374. * it writes 0xffff in violation of RFC 1624
  375. */
  376. }
  377. ds_bits = wil_rxdesc_ds_bits(d);
  378. if (ds_bits == 1) {
  379. /*
  380. * HW bug - in ToDS mode, i.e. Rx on AP side,
  381. * addresses get swapped
  382. */
  383. wil_swap_ethaddr(skb->data);
  384. }
  385. return skb;
  386. }
  387. /**
  388. * allocate and fill up to @count buffers in rx ring
  389. * buffers posted at @swtail
  390. */
  391. static int wil_rx_refill(struct wil6210_priv *wil, int count)
  392. {
  393. struct net_device *ndev = wil_to_ndev(wil);
  394. struct vring *v = &wil->vring_rx;
  395. u32 next_tail;
  396. int rc = 0;
  397. int headroom = ndev->type == ARPHRD_IEEE80211_RADIOTAP ?
  398. WIL6210_RTAP_SIZE : 0;
  399. for (; next_tail = wil_vring_next_tail(v),
  400. (next_tail != v->swhead) && (count-- > 0);
  401. v->swtail = next_tail) {
  402. rc = wil_vring_alloc_skb(wil, v, v->swtail, headroom);
  403. if (rc) {
  404. wil_err(wil, "Error %d in wil_rx_refill[%d]\n",
  405. rc, v->swtail);
  406. break;
  407. }
  408. }
  409. iowrite32(v->swtail, wil->csr + HOSTADDR(v->hwtail));
  410. return rc;
  411. }
  412. /*
  413. * Pass Rx packet to the netif. Update statistics.
  414. * Called in softirq context (NAPI poll).
  415. */
  416. static void wil_netif_rx_any(struct sk_buff *skb, struct net_device *ndev)
  417. {
  418. int rc;
  419. unsigned int len = skb->len;
  420. skb_orphan(skb);
  421. rc = netif_receive_skb(skb);
  422. if (likely(rc == NET_RX_SUCCESS)) {
  423. ndev->stats.rx_packets++;
  424. ndev->stats.rx_bytes += len;
  425. } else {
  426. ndev->stats.rx_dropped++;
  427. }
  428. }
  429. /**
  430. * Proceed all completed skb's from Rx VRING
  431. *
  432. * Safe to call from NAPI poll, i.e. softirq with interrupts enabled
  433. */
  434. void wil_rx_handle(struct wil6210_priv *wil, int *quota)
  435. {
  436. struct net_device *ndev = wil_to_ndev(wil);
  437. struct vring *v = &wil->vring_rx;
  438. struct sk_buff *skb;
  439. if (!v->va) {
  440. wil_err(wil, "Rx IRQ while Rx not yet initialized\n");
  441. return;
  442. }
  443. wil_dbg_txrx(wil, "%s()\n", __func__);
  444. while ((*quota > 0) && (NULL != (skb = wil_vring_reap_rx(wil, v)))) {
  445. (*quota)--;
  446. if (wil->wdev->iftype == NL80211_IFTYPE_MONITOR) {
  447. skb->dev = ndev;
  448. skb_reset_mac_header(skb);
  449. skb->ip_summed = CHECKSUM_UNNECESSARY;
  450. skb->pkt_type = PACKET_OTHERHOST;
  451. skb->protocol = htons(ETH_P_802_2);
  452. } else {
  453. skb->protocol = eth_type_trans(skb, ndev);
  454. }
  455. wil_netif_rx_any(skb, ndev);
  456. }
  457. wil_rx_refill(wil, v->size);
  458. }
  459. int wil_rx_init(struct wil6210_priv *wil)
  460. {
  461. struct vring *vring = &wil->vring_rx;
  462. int rc;
  463. vring->size = WIL6210_RX_RING_SIZE;
  464. rc = wil_vring_alloc(wil, vring);
  465. if (rc)
  466. return rc;
  467. rc = wmi_rx_chain_add(wil, vring);
  468. if (rc)
  469. goto err_free;
  470. rc = wil_rx_refill(wil, vring->size);
  471. if (rc)
  472. goto err_free;
  473. return 0;
  474. err_free:
  475. wil_vring_free(wil, vring, 0);
  476. return rc;
  477. }
  478. void wil_rx_fini(struct wil6210_priv *wil)
  479. {
  480. struct vring *vring = &wil->vring_rx;
  481. if (vring->va)
  482. wil_vring_free(wil, vring, 0);
  483. }
  484. int wil_vring_init_tx(struct wil6210_priv *wil, int id, int size,
  485. int cid, int tid)
  486. {
  487. int rc;
  488. struct wmi_vring_cfg_cmd cmd = {
  489. .action = cpu_to_le32(WMI_VRING_CMD_ADD),
  490. .vring_cfg = {
  491. .tx_sw_ring = {
  492. .max_mpdu_size = cpu_to_le16(TX_BUF_LEN),
  493. .ring_size = cpu_to_le16(size),
  494. },
  495. .ringid = id,
  496. .cidxtid = (cid & 0xf) | ((tid & 0xf) << 4),
  497. .encap_trans_type = WMI_VRING_ENC_TYPE_802_3,
  498. .mac_ctrl = 0,
  499. .to_resolution = 0,
  500. .agg_max_wsize = 16,
  501. .schd_params = {
  502. .priority = cpu_to_le16(0),
  503. .timeslot_us = cpu_to_le16(0xfff),
  504. },
  505. },
  506. };
  507. struct {
  508. struct wil6210_mbox_hdr_wmi wmi;
  509. struct wmi_vring_cfg_done_event cmd;
  510. } __packed reply;
  511. struct vring *vring = &wil->vring_tx[id];
  512. if (vring->va) {
  513. wil_err(wil, "Tx ring [%d] already allocated\n", id);
  514. rc = -EINVAL;
  515. goto out;
  516. }
  517. vring->size = size;
  518. rc = wil_vring_alloc(wil, vring);
  519. if (rc)
  520. goto out;
  521. cmd.vring_cfg.tx_sw_ring.ring_mem_base = cpu_to_le64(vring->pa);
  522. rc = wmi_call(wil, WMI_VRING_CFG_CMDID, &cmd, sizeof(cmd),
  523. WMI_VRING_CFG_DONE_EVENTID, &reply, sizeof(reply), 100);
  524. if (rc)
  525. goto out_free;
  526. if (reply.cmd.status != WMI_FW_STATUS_SUCCESS) {
  527. wil_err(wil, "Tx config failed, status 0x%02x\n",
  528. reply.cmd.status);
  529. rc = -EINVAL;
  530. goto out_free;
  531. }
  532. vring->hwtail = le32_to_cpu(reply.cmd.tx_vring_tail_ptr);
  533. return 0;
  534. out_free:
  535. wil_vring_free(wil, vring, 1);
  536. out:
  537. return rc;
  538. }
  539. void wil_vring_fini_tx(struct wil6210_priv *wil, int id)
  540. {
  541. struct vring *vring = &wil->vring_tx[id];
  542. if (!vring->va)
  543. return;
  544. wil_vring_free(wil, vring, 1);
  545. }
  546. static struct vring *wil_find_tx_vring(struct wil6210_priv *wil,
  547. struct sk_buff *skb)
  548. {
  549. struct vring *v = &wil->vring_tx[0];
  550. if (v->va)
  551. return v;
  552. return NULL;
  553. }
  554. static int wil_tx_desc_map(struct vring_tx_desc *d, dma_addr_t pa, u32 len,
  555. int vring_index)
  556. {
  557. wil_desc_addr_set(&d->dma.addr, pa);
  558. d->dma.ip_length = 0;
  559. /* 0..6: mac_length; 7:ip_version 0-IP6 1-IP4*/
  560. d->dma.b11 = 0/*14 | BIT(7)*/;
  561. d->dma.error = 0;
  562. d->dma.status = 0; /* BIT(0) should be 0 for HW_OWNED */
  563. d->dma.length = cpu_to_le16((u16)len);
  564. d->dma.d0 = (vring_index << DMA_CFG_DESC_TX_0_QID_POS);
  565. d->mac.d[0] = 0;
  566. d->mac.d[1] = 0;
  567. d->mac.d[2] = 0;
  568. d->mac.ucode_cmd = 0;
  569. /* use dst index 0 */
  570. d->mac.d[1] |= BIT(MAC_CFG_DESC_TX_1_DST_INDEX_EN_POS) |
  571. (0 << MAC_CFG_DESC_TX_1_DST_INDEX_POS);
  572. /* translation type: 0 - bypass; 1 - 802.3; 2 - native wifi */
  573. d->mac.d[2] = BIT(MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS) |
  574. (1 << MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS);
  575. return 0;
  576. }
  577. static int wil_tx_desc_offload_cksum_set(struct wil6210_priv *wil,
  578. struct vring_tx_desc *d,
  579. struct sk_buff *skb)
  580. {
  581. int protocol;
  582. if (skb->ip_summed != CHECKSUM_PARTIAL)
  583. return 0;
  584. switch (skb->protocol) {
  585. case cpu_to_be16(ETH_P_IP):
  586. protocol = ip_hdr(skb)->protocol;
  587. break;
  588. case cpu_to_be16(ETH_P_IPV6):
  589. protocol = ipv6_hdr(skb)->nexthdr;
  590. break;
  591. default:
  592. return -EINVAL;
  593. }
  594. switch (protocol) {
  595. case IPPROTO_TCP:
  596. d->dma.d0 |= (2 << DMA_CFG_DESC_TX_0_L4_TYPE_POS);
  597. /* L4 header len: TCP header length */
  598. d->dma.d0 |=
  599. (tcp_hdrlen(skb) & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK);
  600. break;
  601. case IPPROTO_UDP:
  602. /* L4 header len: UDP header length */
  603. d->dma.d0 |=
  604. (sizeof(struct udphdr) & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK);
  605. break;
  606. default:
  607. return -EINVAL;
  608. }
  609. d->dma.ip_length = skb_network_header_len(skb);
  610. d->dma.b11 = ETH_HLEN; /* MAC header length */
  611. d->dma.b11 |= BIT(DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS);
  612. /* Enable TCP/UDP checksum */
  613. d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS);
  614. /* Calculate pseudo-header */
  615. d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS);
  616. return 0;
  617. }
  618. static int wil_tx_vring(struct wil6210_priv *wil, struct vring *vring,
  619. struct sk_buff *skb)
  620. {
  621. struct device *dev = wil_to_dev(wil);
  622. struct vring_tx_desc dd, *d = &dd;
  623. volatile struct vring_tx_desc *_d;
  624. u32 swhead = vring->swhead;
  625. int avail = wil_vring_avail_tx(vring);
  626. int nr_frags = skb_shinfo(skb)->nr_frags;
  627. uint f = 0;
  628. int vring_index = vring - wil->vring_tx;
  629. uint i = swhead;
  630. dma_addr_t pa;
  631. wil_dbg_txrx(wil, "%s()\n", __func__);
  632. if (avail < vring->size/8)
  633. netif_tx_stop_all_queues(wil_to_ndev(wil));
  634. if (avail < 1 + nr_frags) {
  635. wil_err(wil, "Tx ring full. No space for %d fragments\n",
  636. 1 + nr_frags);
  637. return -ENOMEM;
  638. }
  639. _d = &(vring->va[i].tx);
  640. /* FIXME FW can accept only unicast frames for the peer */
  641. memcpy(skb->data, wil->dst_addr[vring_index], ETH_ALEN);
  642. pa = dma_map_single(dev, skb->data,
  643. skb_headlen(skb), DMA_TO_DEVICE);
  644. wil_dbg_txrx(wil, "Tx skb %d bytes %p -> %#08llx\n", skb_headlen(skb),
  645. skb->data, (unsigned long long)pa);
  646. wil_hex_dump_txrx("Tx ", DUMP_PREFIX_OFFSET, 16, 1,
  647. skb->data, skb_headlen(skb), false);
  648. if (unlikely(dma_mapping_error(dev, pa)))
  649. return -EINVAL;
  650. /* 1-st segment */
  651. wil_tx_desc_map(d, pa, skb_headlen(skb), vring_index);
  652. /* Process TCP/UDP checksum offloading */
  653. if (wil_tx_desc_offload_cksum_set(wil, d, skb)) {
  654. wil_err(wil, "VRING #%d Failed to set cksum, drop packet\n",
  655. vring_index);
  656. goto dma_error;
  657. }
  658. d->mac.d[2] |= ((nr_frags + 1) <<
  659. MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_POS);
  660. if (nr_frags)
  661. *_d = *d;
  662. /* middle segments */
  663. for (; f < nr_frags; f++) {
  664. const struct skb_frag_struct *frag =
  665. &skb_shinfo(skb)->frags[f];
  666. int len = skb_frag_size(frag);
  667. i = (swhead + f + 1) % vring->size;
  668. _d = &(vring->va[i].tx);
  669. pa = skb_frag_dma_map(dev, frag, 0, skb_frag_size(frag),
  670. DMA_TO_DEVICE);
  671. if (unlikely(dma_mapping_error(dev, pa)))
  672. goto dma_error;
  673. wil_tx_desc_map(d, pa, len, vring_index);
  674. vring->ctx[i].mapped_as_page = 1;
  675. *_d = *d;
  676. }
  677. /* for the last seg only */
  678. d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_EOP_POS);
  679. d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_MARK_WB_POS);
  680. d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_DMA_IT_POS);
  681. *_d = *d;
  682. /* hold reference to skb
  683. * to prevent skb release before accounting
  684. * in case of immediate "tx done"
  685. */
  686. vring->ctx[i].skb = skb_get(skb);
  687. wil_hex_dump_txrx("Tx ", DUMP_PREFIX_NONE, 32, 4,
  688. (const void *)d, sizeof(*d), false);
  689. /* advance swhead */
  690. wil_vring_advance_head(vring, nr_frags + 1);
  691. wil_dbg_txrx(wil, "Tx swhead %d -> %d\n", swhead, vring->swhead);
  692. trace_wil6210_tx(vring_index, swhead, skb->len, nr_frags);
  693. iowrite32(vring->swhead, wil->csr + HOSTADDR(vring->hwtail));
  694. return 0;
  695. dma_error:
  696. /* unmap what we have mapped */
  697. nr_frags = f + 1; /* frags mapped + one for skb head */
  698. for (f = 0; f < nr_frags; f++) {
  699. u16 dmalen;
  700. struct wil_ctx *ctx;
  701. i = (swhead + f) % vring->size;
  702. ctx = &vring->ctx[i];
  703. _d = &(vring->va[i].tx);
  704. *d = *_d;
  705. _d->dma.status = TX_DMA_STATUS_DU;
  706. pa = wil_desc_addr(&d->dma.addr);
  707. dmalen = le16_to_cpu(d->dma.length);
  708. if (ctx->mapped_as_page)
  709. dma_unmap_page(dev, pa, dmalen, DMA_TO_DEVICE);
  710. else
  711. dma_unmap_single(dev, pa, dmalen, DMA_TO_DEVICE);
  712. if (ctx->skb)
  713. dev_kfree_skb_any(ctx->skb);
  714. memset(ctx, 0, sizeof(*ctx));
  715. }
  716. return -EINVAL;
  717. }
  718. netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev)
  719. {
  720. struct wil6210_priv *wil = ndev_to_wil(ndev);
  721. struct vring *vring;
  722. int rc;
  723. wil_dbg_txrx(wil, "%s()\n", __func__);
  724. if (!test_bit(wil_status_fwready, &wil->status)) {
  725. wil_err(wil, "FW not ready\n");
  726. goto drop;
  727. }
  728. if (!test_bit(wil_status_fwconnected, &wil->status)) {
  729. wil_err(wil, "FW not connected\n");
  730. goto drop;
  731. }
  732. if (wil->wdev->iftype == NL80211_IFTYPE_MONITOR) {
  733. wil_err(wil, "Xmit in monitor mode not supported\n");
  734. goto drop;
  735. }
  736. /* find vring */
  737. vring = wil_find_tx_vring(wil, skb);
  738. if (!vring) {
  739. wil_err(wil, "No Tx VRING available\n");
  740. goto drop;
  741. }
  742. /* set up vring entry */
  743. rc = wil_tx_vring(wil, vring, skb);
  744. switch (rc) {
  745. case 0:
  746. /* statistics will be updated on the tx_complete */
  747. dev_kfree_skb_any(skb);
  748. return NETDEV_TX_OK;
  749. case -ENOMEM:
  750. return NETDEV_TX_BUSY;
  751. default:
  752. break; /* goto drop; */
  753. }
  754. drop:
  755. ndev->stats.tx_dropped++;
  756. dev_kfree_skb_any(skb);
  757. return NET_XMIT_DROP;
  758. }
  759. /**
  760. * Clean up transmitted skb's from the Tx VRING
  761. *
  762. * Return number of descriptors cleared
  763. *
  764. * Safe to call from IRQ
  765. */
  766. int wil_tx_complete(struct wil6210_priv *wil, int ringid)
  767. {
  768. struct net_device *ndev = wil_to_ndev(wil);
  769. struct device *dev = wil_to_dev(wil);
  770. struct vring *vring = &wil->vring_tx[ringid];
  771. int done = 0;
  772. if (!vring->va) {
  773. wil_err(wil, "Tx irq[%d]: vring not initialized\n", ringid);
  774. return 0;
  775. }
  776. wil_dbg_txrx(wil, "%s(%d)\n", __func__, ringid);
  777. while (!wil_vring_is_empty(vring)) {
  778. volatile struct vring_tx_desc *_d =
  779. &vring->va[vring->swtail].tx;
  780. struct vring_tx_desc dd, *d = &dd;
  781. dma_addr_t pa;
  782. u16 dmalen;
  783. struct wil_ctx *ctx = &vring->ctx[vring->swtail];
  784. struct sk_buff *skb = ctx->skb;
  785. *d = *_d;
  786. if (!(d->dma.status & TX_DMA_STATUS_DU))
  787. break;
  788. dmalen = le16_to_cpu(d->dma.length);
  789. trace_wil6210_tx_done(ringid, vring->swtail, dmalen,
  790. d->dma.error);
  791. wil_dbg_txrx(wil,
  792. "Tx[%3d] : %d bytes, status 0x%02x err 0x%02x\n",
  793. vring->swtail, dmalen, d->dma.status,
  794. d->dma.error);
  795. wil_hex_dump_txrx("TxC ", DUMP_PREFIX_NONE, 32, 4,
  796. (const void *)d, sizeof(*d), false);
  797. pa = wil_desc_addr(&d->dma.addr);
  798. if (ctx->mapped_as_page)
  799. dma_unmap_page(dev, pa, dmalen, DMA_TO_DEVICE);
  800. else
  801. dma_unmap_single(dev, pa, dmalen, DMA_TO_DEVICE);
  802. if (skb) {
  803. if (d->dma.error == 0) {
  804. ndev->stats.tx_packets++;
  805. ndev->stats.tx_bytes += skb->len;
  806. } else {
  807. ndev->stats.tx_errors++;
  808. }
  809. dev_kfree_skb_any(skb);
  810. }
  811. memset(ctx, 0, sizeof(*ctx));
  812. /*
  813. * There is no need to touch HW descriptor:
  814. * - ststus bit TX_DMA_STATUS_DU is set by design,
  815. * so hardware will not try to process this desc.,
  816. * - rest of descriptor will be initialized on Tx.
  817. */
  818. vring->swtail = wil_vring_next_tail(vring);
  819. done++;
  820. }
  821. if (wil_vring_avail_tx(vring) > vring->size/4)
  822. netif_tx_wake_all_queues(wil_to_ndev(wil));
  823. return done;
  824. }