smsc75xx.c 56 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2007-2010 SMSC
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. *
  19. *****************************************************************************/
  20. #include <linux/module.h>
  21. #include <linux/kmod.h>
  22. #include <linux/init.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/mii.h>
  27. #include <linux/usb.h>
  28. #include <linux/bitrev.h>
  29. #include <linux/crc16.h>
  30. #include <linux/crc32.h>
  31. #include <linux/usb/usbnet.h>
  32. #include <linux/slab.h>
  33. #include "smsc75xx.h"
  34. #define SMSC_CHIPNAME "smsc75xx"
  35. #define SMSC_DRIVER_VERSION "1.0.0"
  36. #define HS_USB_PKT_SIZE (512)
  37. #define FS_USB_PKT_SIZE (64)
  38. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  39. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  40. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  41. #define MAX_SINGLE_PACKET_SIZE (9000)
  42. #define LAN75XX_EEPROM_MAGIC (0x7500)
  43. #define EEPROM_MAC_OFFSET (0x01)
  44. #define DEFAULT_TX_CSUM_ENABLE (true)
  45. #define DEFAULT_RX_CSUM_ENABLE (true)
  46. #define SMSC75XX_INTERNAL_PHY_ID (1)
  47. #define SMSC75XX_TX_OVERHEAD (8)
  48. #define MAX_RX_FIFO_SIZE (20 * 1024)
  49. #define MAX_TX_FIFO_SIZE (12 * 1024)
  50. #define USB_VENDOR_ID_SMSC (0x0424)
  51. #define USB_PRODUCT_ID_LAN7500 (0x7500)
  52. #define USB_PRODUCT_ID_LAN7505 (0x7505)
  53. #define RXW_PADDING 2
  54. #define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
  55. WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
  56. #define SUSPEND_SUSPEND0 (0x01)
  57. #define SUSPEND_SUSPEND1 (0x02)
  58. #define SUSPEND_SUSPEND2 (0x04)
  59. #define SUSPEND_SUSPEND3 (0x08)
  60. #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
  61. SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
  62. struct smsc75xx_priv {
  63. struct usbnet *dev;
  64. u32 rfe_ctl;
  65. u32 wolopts;
  66. u32 multicast_hash_table[DP_SEL_VHF_HASH_LEN];
  67. struct mutex dataport_mutex;
  68. spinlock_t rfe_ctl_lock;
  69. struct work_struct set_multicast;
  70. u8 suspend_flags;
  71. };
  72. struct usb_context {
  73. struct usb_ctrlrequest req;
  74. struct usbnet *dev;
  75. };
  76. static bool turbo_mode = true;
  77. module_param(turbo_mode, bool, 0644);
  78. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  79. static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index,
  80. u32 *data, int in_pm)
  81. {
  82. u32 buf;
  83. int ret;
  84. int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
  85. BUG_ON(!dev);
  86. if (!in_pm)
  87. fn = usbnet_read_cmd;
  88. else
  89. fn = usbnet_read_cmd_nopm;
  90. ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
  91. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  92. 0, index, &buf, 4);
  93. if (unlikely(ret < 0))
  94. netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
  95. index, ret);
  96. le32_to_cpus(&buf);
  97. *data = buf;
  98. return ret;
  99. }
  100. static int __must_check __smsc75xx_write_reg(struct usbnet *dev, u32 index,
  101. u32 data, int in_pm)
  102. {
  103. u32 buf;
  104. int ret;
  105. int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
  106. BUG_ON(!dev);
  107. if (!in_pm)
  108. fn = usbnet_write_cmd;
  109. else
  110. fn = usbnet_write_cmd_nopm;
  111. buf = data;
  112. cpu_to_le32s(&buf);
  113. ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
  114. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  115. 0, index, &buf, 4);
  116. if (unlikely(ret < 0))
  117. netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
  118. index, ret);
  119. return ret;
  120. }
  121. static int __must_check smsc75xx_read_reg_nopm(struct usbnet *dev, u32 index,
  122. u32 *data)
  123. {
  124. return __smsc75xx_read_reg(dev, index, data, 1);
  125. }
  126. static int __must_check smsc75xx_write_reg_nopm(struct usbnet *dev, u32 index,
  127. u32 data)
  128. {
  129. return __smsc75xx_write_reg(dev, index, data, 1);
  130. }
  131. static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index,
  132. u32 *data)
  133. {
  134. return __smsc75xx_read_reg(dev, index, data, 0);
  135. }
  136. static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index,
  137. u32 data)
  138. {
  139. return __smsc75xx_write_reg(dev, index, data, 0);
  140. }
  141. /* Loop until the read is completed with timeout
  142. * called with phy_mutex held */
  143. static __must_check int __smsc75xx_phy_wait_not_busy(struct usbnet *dev,
  144. int in_pm)
  145. {
  146. unsigned long start_time = jiffies;
  147. u32 val;
  148. int ret;
  149. do {
  150. ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm);
  151. if (ret < 0) {
  152. netdev_warn(dev->net, "Error reading MII_ACCESS\n");
  153. return ret;
  154. }
  155. if (!(val & MII_ACCESS_BUSY))
  156. return 0;
  157. } while (!time_after(jiffies, start_time + HZ));
  158. return -EIO;
  159. }
  160. static int __smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
  161. int in_pm)
  162. {
  163. struct usbnet *dev = netdev_priv(netdev);
  164. u32 val, addr;
  165. int ret;
  166. mutex_lock(&dev->phy_mutex);
  167. /* confirm MII not busy */
  168. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  169. if (ret < 0) {
  170. netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_read\n");
  171. goto done;
  172. }
  173. /* set the address, index & direction (read from PHY) */
  174. phy_id &= dev->mii.phy_id_mask;
  175. idx &= dev->mii.reg_num_mask;
  176. addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
  177. | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
  178. | MII_ACCESS_READ | MII_ACCESS_BUSY;
  179. ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
  180. if (ret < 0) {
  181. netdev_warn(dev->net, "Error writing MII_ACCESS\n");
  182. goto done;
  183. }
  184. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  185. if (ret < 0) {
  186. netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
  187. goto done;
  188. }
  189. ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm);
  190. if (ret < 0) {
  191. netdev_warn(dev->net, "Error reading MII_DATA\n");
  192. goto done;
  193. }
  194. ret = (u16)(val & 0xFFFF);
  195. done:
  196. mutex_unlock(&dev->phy_mutex);
  197. return ret;
  198. }
  199. static void __smsc75xx_mdio_write(struct net_device *netdev, int phy_id,
  200. int idx, int regval, int in_pm)
  201. {
  202. struct usbnet *dev = netdev_priv(netdev);
  203. u32 val, addr;
  204. int ret;
  205. mutex_lock(&dev->phy_mutex);
  206. /* confirm MII not busy */
  207. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  208. if (ret < 0) {
  209. netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_write\n");
  210. goto done;
  211. }
  212. val = regval;
  213. ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm);
  214. if (ret < 0) {
  215. netdev_warn(dev->net, "Error writing MII_DATA\n");
  216. goto done;
  217. }
  218. /* set the address, index & direction (write to PHY) */
  219. phy_id &= dev->mii.phy_id_mask;
  220. idx &= dev->mii.reg_num_mask;
  221. addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
  222. | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
  223. | MII_ACCESS_WRITE | MII_ACCESS_BUSY;
  224. ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
  225. if (ret < 0) {
  226. netdev_warn(dev->net, "Error writing MII_ACCESS\n");
  227. goto done;
  228. }
  229. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  230. if (ret < 0) {
  231. netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
  232. goto done;
  233. }
  234. done:
  235. mutex_unlock(&dev->phy_mutex);
  236. }
  237. static int smsc75xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
  238. int idx)
  239. {
  240. return __smsc75xx_mdio_read(netdev, phy_id, idx, 1);
  241. }
  242. static void smsc75xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
  243. int idx, int regval)
  244. {
  245. __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1);
  246. }
  247. static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  248. {
  249. return __smsc75xx_mdio_read(netdev, phy_id, idx, 0);
  250. }
  251. static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  252. int regval)
  253. {
  254. __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0);
  255. }
  256. static int smsc75xx_wait_eeprom(struct usbnet *dev)
  257. {
  258. unsigned long start_time = jiffies;
  259. u32 val;
  260. int ret;
  261. do {
  262. ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
  263. if (ret < 0) {
  264. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  265. return ret;
  266. }
  267. if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT))
  268. break;
  269. udelay(40);
  270. } while (!time_after(jiffies, start_time + HZ));
  271. if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) {
  272. netdev_warn(dev->net, "EEPROM read operation timeout\n");
  273. return -EIO;
  274. }
  275. return 0;
  276. }
  277. static int smsc75xx_eeprom_confirm_not_busy(struct usbnet *dev)
  278. {
  279. unsigned long start_time = jiffies;
  280. u32 val;
  281. int ret;
  282. do {
  283. ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
  284. if (ret < 0) {
  285. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  286. return ret;
  287. }
  288. if (!(val & E2P_CMD_BUSY))
  289. return 0;
  290. udelay(40);
  291. } while (!time_after(jiffies, start_time + HZ));
  292. netdev_warn(dev->net, "EEPROM is busy\n");
  293. return -EIO;
  294. }
  295. static int smsc75xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  296. u8 *data)
  297. {
  298. u32 val;
  299. int i, ret;
  300. BUG_ON(!dev);
  301. BUG_ON(!data);
  302. ret = smsc75xx_eeprom_confirm_not_busy(dev);
  303. if (ret)
  304. return ret;
  305. for (i = 0; i < length; i++) {
  306. val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR);
  307. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  308. if (ret < 0) {
  309. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  310. return ret;
  311. }
  312. ret = smsc75xx_wait_eeprom(dev);
  313. if (ret < 0)
  314. return ret;
  315. ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
  316. if (ret < 0) {
  317. netdev_warn(dev->net, "Error reading E2P_DATA\n");
  318. return ret;
  319. }
  320. data[i] = val & 0xFF;
  321. offset++;
  322. }
  323. return 0;
  324. }
  325. static int smsc75xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  326. u8 *data)
  327. {
  328. u32 val;
  329. int i, ret;
  330. BUG_ON(!dev);
  331. BUG_ON(!data);
  332. ret = smsc75xx_eeprom_confirm_not_busy(dev);
  333. if (ret)
  334. return ret;
  335. /* Issue write/erase enable command */
  336. val = E2P_CMD_BUSY | E2P_CMD_EWEN;
  337. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  338. if (ret < 0) {
  339. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  340. return ret;
  341. }
  342. ret = smsc75xx_wait_eeprom(dev);
  343. if (ret < 0)
  344. return ret;
  345. for (i = 0; i < length; i++) {
  346. /* Fill data register */
  347. val = data[i];
  348. ret = smsc75xx_write_reg(dev, E2P_DATA, val);
  349. if (ret < 0) {
  350. netdev_warn(dev->net, "Error writing E2P_DATA\n");
  351. return ret;
  352. }
  353. /* Send "write" command */
  354. val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR);
  355. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  356. if (ret < 0) {
  357. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  358. return ret;
  359. }
  360. ret = smsc75xx_wait_eeprom(dev);
  361. if (ret < 0)
  362. return ret;
  363. offset++;
  364. }
  365. return 0;
  366. }
  367. static int smsc75xx_dataport_wait_not_busy(struct usbnet *dev)
  368. {
  369. int i, ret;
  370. for (i = 0; i < 100; i++) {
  371. u32 dp_sel;
  372. ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
  373. if (ret < 0) {
  374. netdev_warn(dev->net, "Error reading DP_SEL\n");
  375. return ret;
  376. }
  377. if (dp_sel & DP_SEL_DPRDY)
  378. return 0;
  379. udelay(40);
  380. }
  381. netdev_warn(dev->net, "smsc75xx_dataport_wait_not_busy timed out\n");
  382. return -EIO;
  383. }
  384. static int smsc75xx_dataport_write(struct usbnet *dev, u32 ram_select, u32 addr,
  385. u32 length, u32 *buf)
  386. {
  387. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  388. u32 dp_sel;
  389. int i, ret;
  390. mutex_lock(&pdata->dataport_mutex);
  391. ret = smsc75xx_dataport_wait_not_busy(dev);
  392. if (ret < 0) {
  393. netdev_warn(dev->net, "smsc75xx_dataport_write busy on entry\n");
  394. goto done;
  395. }
  396. ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
  397. if (ret < 0) {
  398. netdev_warn(dev->net, "Error reading DP_SEL\n");
  399. goto done;
  400. }
  401. dp_sel &= ~DP_SEL_RSEL;
  402. dp_sel |= ram_select;
  403. ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
  404. if (ret < 0) {
  405. netdev_warn(dev->net, "Error writing DP_SEL\n");
  406. goto done;
  407. }
  408. for (i = 0; i < length; i++) {
  409. ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
  410. if (ret < 0) {
  411. netdev_warn(dev->net, "Error writing DP_ADDR\n");
  412. goto done;
  413. }
  414. ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
  415. if (ret < 0) {
  416. netdev_warn(dev->net, "Error writing DP_DATA\n");
  417. goto done;
  418. }
  419. ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
  420. if (ret < 0) {
  421. netdev_warn(dev->net, "Error writing DP_CMD\n");
  422. goto done;
  423. }
  424. ret = smsc75xx_dataport_wait_not_busy(dev);
  425. if (ret < 0) {
  426. netdev_warn(dev->net, "smsc75xx_dataport_write timeout\n");
  427. goto done;
  428. }
  429. }
  430. done:
  431. mutex_unlock(&pdata->dataport_mutex);
  432. return ret;
  433. }
  434. /* returns hash bit number for given MAC address */
  435. static u32 smsc75xx_hash(char addr[ETH_ALEN])
  436. {
  437. return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
  438. }
  439. static void smsc75xx_deferred_multicast_write(struct work_struct *param)
  440. {
  441. struct smsc75xx_priv *pdata =
  442. container_of(param, struct smsc75xx_priv, set_multicast);
  443. struct usbnet *dev = pdata->dev;
  444. int ret;
  445. netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
  446. pdata->rfe_ctl);
  447. smsc75xx_dataport_write(dev, DP_SEL_VHF, DP_SEL_VHF_VLAN_LEN,
  448. DP_SEL_VHF_HASH_LEN, pdata->multicast_hash_table);
  449. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  450. if (ret < 0)
  451. netdev_warn(dev->net, "Error writing RFE_CRL\n");
  452. }
  453. static void smsc75xx_set_multicast(struct net_device *netdev)
  454. {
  455. struct usbnet *dev = netdev_priv(netdev);
  456. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  457. unsigned long flags;
  458. int i;
  459. spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
  460. pdata->rfe_ctl &=
  461. ~(RFE_CTL_AU | RFE_CTL_AM | RFE_CTL_DPF | RFE_CTL_MHF);
  462. pdata->rfe_ctl |= RFE_CTL_AB;
  463. for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
  464. pdata->multicast_hash_table[i] = 0;
  465. if (dev->net->flags & IFF_PROMISC) {
  466. netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
  467. pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_AU;
  468. } else if (dev->net->flags & IFF_ALLMULTI) {
  469. netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
  470. pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_DPF;
  471. } else if (!netdev_mc_empty(dev->net)) {
  472. struct netdev_hw_addr *ha;
  473. netif_dbg(dev, drv, dev->net, "receive multicast hash filter\n");
  474. pdata->rfe_ctl |= RFE_CTL_MHF | RFE_CTL_DPF;
  475. netdev_for_each_mc_addr(ha, netdev) {
  476. u32 bitnum = smsc75xx_hash(ha->addr);
  477. pdata->multicast_hash_table[bitnum / 32] |=
  478. (1 << (bitnum % 32));
  479. }
  480. } else {
  481. netif_dbg(dev, drv, dev->net, "receive own packets only\n");
  482. pdata->rfe_ctl |= RFE_CTL_DPF;
  483. }
  484. spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
  485. /* defer register writes to a sleepable context */
  486. schedule_work(&pdata->set_multicast);
  487. }
  488. static int smsc75xx_update_flowcontrol(struct usbnet *dev, u8 duplex,
  489. u16 lcladv, u16 rmtadv)
  490. {
  491. u32 flow = 0, fct_flow = 0;
  492. int ret;
  493. if (duplex == DUPLEX_FULL) {
  494. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  495. if (cap & FLOW_CTRL_TX) {
  496. flow = (FLOW_TX_FCEN | 0xFFFF);
  497. /* set fct_flow thresholds to 20% and 80% */
  498. fct_flow = (8 << 8) | 32;
  499. }
  500. if (cap & FLOW_CTRL_RX)
  501. flow |= FLOW_RX_FCEN;
  502. netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
  503. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  504. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  505. } else {
  506. netif_dbg(dev, link, dev->net, "half duplex\n");
  507. }
  508. ret = smsc75xx_write_reg(dev, FLOW, flow);
  509. if (ret < 0) {
  510. netdev_warn(dev->net, "Error writing FLOW\n");
  511. return ret;
  512. }
  513. ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
  514. if (ret < 0) {
  515. netdev_warn(dev->net, "Error writing FCT_FLOW\n");
  516. return ret;
  517. }
  518. return 0;
  519. }
  520. static int smsc75xx_link_reset(struct usbnet *dev)
  521. {
  522. struct mii_if_info *mii = &dev->mii;
  523. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  524. u16 lcladv, rmtadv;
  525. int ret;
  526. /* write to clear phy interrupt status */
  527. smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC,
  528. PHY_INT_SRC_CLEAR_ALL);
  529. ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
  530. if (ret < 0) {
  531. netdev_warn(dev->net, "Error writing INT_STS\n");
  532. return ret;
  533. }
  534. mii_check_media(mii, 1, 1);
  535. mii_ethtool_gset(&dev->mii, &ecmd);
  536. lcladv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  537. rmtadv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  538. netif_dbg(dev, link, dev->net, "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
  539. ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
  540. return smsc75xx_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  541. }
  542. static void smsc75xx_status(struct usbnet *dev, struct urb *urb)
  543. {
  544. u32 intdata;
  545. if (urb->actual_length != 4) {
  546. netdev_warn(dev->net, "unexpected urb length %d\n",
  547. urb->actual_length);
  548. return;
  549. }
  550. memcpy(&intdata, urb->transfer_buffer, 4);
  551. le32_to_cpus(&intdata);
  552. netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
  553. if (intdata & INT_ENP_PHY_INT)
  554. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  555. else
  556. netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
  557. intdata);
  558. }
  559. static int smsc75xx_ethtool_get_eeprom_len(struct net_device *net)
  560. {
  561. return MAX_EEPROM_SIZE;
  562. }
  563. static int smsc75xx_ethtool_get_eeprom(struct net_device *netdev,
  564. struct ethtool_eeprom *ee, u8 *data)
  565. {
  566. struct usbnet *dev = netdev_priv(netdev);
  567. ee->magic = LAN75XX_EEPROM_MAGIC;
  568. return smsc75xx_read_eeprom(dev, ee->offset, ee->len, data);
  569. }
  570. static int smsc75xx_ethtool_set_eeprom(struct net_device *netdev,
  571. struct ethtool_eeprom *ee, u8 *data)
  572. {
  573. struct usbnet *dev = netdev_priv(netdev);
  574. if (ee->magic != LAN75XX_EEPROM_MAGIC) {
  575. netdev_warn(dev->net, "EEPROM: magic value mismatch: 0x%x\n",
  576. ee->magic);
  577. return -EINVAL;
  578. }
  579. return smsc75xx_write_eeprom(dev, ee->offset, ee->len, data);
  580. }
  581. static void smsc75xx_ethtool_get_wol(struct net_device *net,
  582. struct ethtool_wolinfo *wolinfo)
  583. {
  584. struct usbnet *dev = netdev_priv(net);
  585. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  586. wolinfo->supported = SUPPORTED_WAKE;
  587. wolinfo->wolopts = pdata->wolopts;
  588. }
  589. static int smsc75xx_ethtool_set_wol(struct net_device *net,
  590. struct ethtool_wolinfo *wolinfo)
  591. {
  592. struct usbnet *dev = netdev_priv(net);
  593. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  594. int ret;
  595. pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
  596. ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
  597. if (ret < 0)
  598. netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
  599. return ret;
  600. }
  601. static const struct ethtool_ops smsc75xx_ethtool_ops = {
  602. .get_link = usbnet_get_link,
  603. .nway_reset = usbnet_nway_reset,
  604. .get_drvinfo = usbnet_get_drvinfo,
  605. .get_msglevel = usbnet_get_msglevel,
  606. .set_msglevel = usbnet_set_msglevel,
  607. .get_settings = usbnet_get_settings,
  608. .set_settings = usbnet_set_settings,
  609. .get_eeprom_len = smsc75xx_ethtool_get_eeprom_len,
  610. .get_eeprom = smsc75xx_ethtool_get_eeprom,
  611. .set_eeprom = smsc75xx_ethtool_set_eeprom,
  612. .get_wol = smsc75xx_ethtool_get_wol,
  613. .set_wol = smsc75xx_ethtool_set_wol,
  614. };
  615. static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  616. {
  617. struct usbnet *dev = netdev_priv(netdev);
  618. if (!netif_running(netdev))
  619. return -EINVAL;
  620. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  621. }
  622. static void smsc75xx_init_mac_address(struct usbnet *dev)
  623. {
  624. /* try reading mac address from EEPROM */
  625. if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
  626. dev->net->dev_addr) == 0) {
  627. if (is_valid_ether_addr(dev->net->dev_addr)) {
  628. /* eeprom values are valid so use them */
  629. netif_dbg(dev, ifup, dev->net,
  630. "MAC address read from EEPROM\n");
  631. return;
  632. }
  633. }
  634. /* no eeprom, or eeprom values are invalid. generate random MAC */
  635. eth_hw_addr_random(dev->net);
  636. netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
  637. }
  638. static int smsc75xx_set_mac_address(struct usbnet *dev)
  639. {
  640. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  641. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  642. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  643. int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
  644. if (ret < 0) {
  645. netdev_warn(dev->net, "Failed to write RX_ADDRH: %d\n", ret);
  646. return ret;
  647. }
  648. ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
  649. if (ret < 0) {
  650. netdev_warn(dev->net, "Failed to write RX_ADDRL: %d\n", ret);
  651. return ret;
  652. }
  653. addr_hi |= ADDR_FILTX_FB_VALID;
  654. ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
  655. if (ret < 0) {
  656. netdev_warn(dev->net, "Failed to write ADDR_FILTX: %d\n", ret);
  657. return ret;
  658. }
  659. ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
  660. if (ret < 0)
  661. netdev_warn(dev->net, "Failed to write ADDR_FILTX+4: %d\n", ret);
  662. return ret;
  663. }
  664. static int smsc75xx_phy_initialize(struct usbnet *dev)
  665. {
  666. int bmcr, ret, timeout = 0;
  667. /* Initialize MII structure */
  668. dev->mii.dev = dev->net;
  669. dev->mii.mdio_read = smsc75xx_mdio_read;
  670. dev->mii.mdio_write = smsc75xx_mdio_write;
  671. dev->mii.phy_id_mask = 0x1f;
  672. dev->mii.reg_num_mask = 0x1f;
  673. dev->mii.supports_gmii = 1;
  674. dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID;
  675. /* reset phy and wait for reset to complete */
  676. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  677. do {
  678. msleep(10);
  679. bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
  680. if (bmcr < 0) {
  681. netdev_warn(dev->net, "Error reading MII_BMCR\n");
  682. return bmcr;
  683. }
  684. timeout++;
  685. } while ((bmcr & BMCR_RESET) && (timeout < 100));
  686. if (timeout >= 100) {
  687. netdev_warn(dev->net, "timeout on PHY Reset\n");
  688. return -EIO;
  689. }
  690. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  691. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  692. ADVERTISE_PAUSE_ASYM);
  693. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
  694. ADVERTISE_1000FULL);
  695. /* read and write to clear phy interrupt status */
  696. ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  697. if (ret < 0) {
  698. netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
  699. return ret;
  700. }
  701. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff);
  702. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  703. PHY_INT_MASK_DEFAULT);
  704. mii_nway_restart(&dev->mii);
  705. netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
  706. return 0;
  707. }
  708. static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
  709. {
  710. int ret = 0;
  711. u32 buf;
  712. bool rxenabled;
  713. ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
  714. if (ret < 0) {
  715. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  716. return ret;
  717. }
  718. rxenabled = ((buf & MAC_RX_RXEN) != 0);
  719. if (rxenabled) {
  720. buf &= ~MAC_RX_RXEN;
  721. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  722. if (ret < 0) {
  723. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  724. return ret;
  725. }
  726. }
  727. /* add 4 to size for FCS */
  728. buf &= ~MAC_RX_MAX_SIZE;
  729. buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT) & MAC_RX_MAX_SIZE);
  730. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  731. if (ret < 0) {
  732. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  733. return ret;
  734. }
  735. if (rxenabled) {
  736. buf |= MAC_RX_RXEN;
  737. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  738. if (ret < 0) {
  739. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  740. return ret;
  741. }
  742. }
  743. return 0;
  744. }
  745. static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
  746. {
  747. struct usbnet *dev = netdev_priv(netdev);
  748. int ret;
  749. if (new_mtu > MAX_SINGLE_PACKET_SIZE)
  750. return -EINVAL;
  751. ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
  752. if (ret < 0) {
  753. netdev_warn(dev->net, "Failed to set mac rx frame length\n");
  754. return ret;
  755. }
  756. return usbnet_change_mtu(netdev, new_mtu);
  757. }
  758. /* Enable or disable Rx checksum offload engine */
  759. static int smsc75xx_set_features(struct net_device *netdev,
  760. netdev_features_t features)
  761. {
  762. struct usbnet *dev = netdev_priv(netdev);
  763. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  764. unsigned long flags;
  765. int ret;
  766. spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
  767. if (features & NETIF_F_RXCSUM)
  768. pdata->rfe_ctl |= RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM;
  769. else
  770. pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM);
  771. spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
  772. /* it's racing here! */
  773. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  774. if (ret < 0)
  775. netdev_warn(dev->net, "Error writing RFE_CTL\n");
  776. return ret;
  777. }
  778. static int smsc75xx_wait_ready(struct usbnet *dev, int in_pm)
  779. {
  780. int timeout = 0;
  781. do {
  782. u32 buf;
  783. int ret;
  784. ret = __smsc75xx_read_reg(dev, PMT_CTL, &buf, in_pm);
  785. if (ret < 0) {
  786. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  787. return ret;
  788. }
  789. if (buf & PMT_CTL_DEV_RDY)
  790. return 0;
  791. msleep(10);
  792. timeout++;
  793. } while (timeout < 100);
  794. netdev_warn(dev->net, "timeout waiting for device ready\n");
  795. return -EIO;
  796. }
  797. static int smsc75xx_reset(struct usbnet *dev)
  798. {
  799. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  800. u32 buf;
  801. int ret = 0, timeout;
  802. netif_dbg(dev, ifup, dev->net, "entering smsc75xx_reset\n");
  803. ret = smsc75xx_wait_ready(dev, 0);
  804. if (ret < 0) {
  805. netdev_warn(dev->net, "device not ready in smsc75xx_reset\n");
  806. return ret;
  807. }
  808. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  809. if (ret < 0) {
  810. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  811. return ret;
  812. }
  813. buf |= HW_CFG_LRST;
  814. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  815. if (ret < 0) {
  816. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  817. return ret;
  818. }
  819. timeout = 0;
  820. do {
  821. msleep(10);
  822. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  823. if (ret < 0) {
  824. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  825. return ret;
  826. }
  827. timeout++;
  828. } while ((buf & HW_CFG_LRST) && (timeout < 100));
  829. if (timeout >= 100) {
  830. netdev_warn(dev->net, "timeout on completion of Lite Reset\n");
  831. return -EIO;
  832. }
  833. netif_dbg(dev, ifup, dev->net, "Lite reset complete, resetting PHY\n");
  834. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  835. if (ret < 0) {
  836. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  837. return ret;
  838. }
  839. buf |= PMT_CTL_PHY_RST;
  840. ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
  841. if (ret < 0) {
  842. netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
  843. return ret;
  844. }
  845. timeout = 0;
  846. do {
  847. msleep(10);
  848. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  849. if (ret < 0) {
  850. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  851. return ret;
  852. }
  853. timeout++;
  854. } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
  855. if (timeout >= 100) {
  856. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  857. return -EIO;
  858. }
  859. netif_dbg(dev, ifup, dev->net, "PHY reset complete\n");
  860. ret = smsc75xx_set_mac_address(dev);
  861. if (ret < 0) {
  862. netdev_warn(dev->net, "Failed to set mac address\n");
  863. return ret;
  864. }
  865. netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
  866. dev->net->dev_addr);
  867. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  868. if (ret < 0) {
  869. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  870. return ret;
  871. }
  872. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
  873. buf);
  874. buf |= HW_CFG_BIR;
  875. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  876. if (ret < 0) {
  877. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  878. return ret;
  879. }
  880. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  881. if (ret < 0) {
  882. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  883. return ret;
  884. }
  885. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG after writing HW_CFG_BIR: 0x%08x\n",
  886. buf);
  887. if (!turbo_mode) {
  888. buf = 0;
  889. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  890. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  891. buf = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  892. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  893. } else {
  894. buf = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  895. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  896. }
  897. netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
  898. (ulong)dev->rx_urb_size);
  899. ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
  900. if (ret < 0) {
  901. netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
  902. return ret;
  903. }
  904. ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
  905. if (ret < 0) {
  906. netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
  907. return ret;
  908. }
  909. netif_dbg(dev, ifup, dev->net,
  910. "Read Value from BURST_CAP after writing: 0x%08x\n", buf);
  911. ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
  912. if (ret < 0) {
  913. netdev_warn(dev->net, "Failed to write BULK_IN_DLY: %d\n", ret);
  914. return ret;
  915. }
  916. ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
  917. if (ret < 0) {
  918. netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
  919. return ret;
  920. }
  921. netif_dbg(dev, ifup, dev->net,
  922. "Read Value from BULK_IN_DLY after writing: 0x%08x\n", buf);
  923. if (turbo_mode) {
  924. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  925. if (ret < 0) {
  926. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  927. return ret;
  928. }
  929. netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
  930. buf |= (HW_CFG_MEF | HW_CFG_BCE);
  931. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  932. if (ret < 0) {
  933. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  934. return ret;
  935. }
  936. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  937. if (ret < 0) {
  938. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  939. return ret;
  940. }
  941. netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
  942. }
  943. /* set FIFO sizes */
  944. buf = (MAX_RX_FIFO_SIZE - 512) / 512;
  945. ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
  946. if (ret < 0) {
  947. netdev_warn(dev->net, "Failed to write FCT_RX_FIFO_END: %d\n", ret);
  948. return ret;
  949. }
  950. netif_dbg(dev, ifup, dev->net, "FCT_RX_FIFO_END set to 0x%08x\n", buf);
  951. buf = (MAX_TX_FIFO_SIZE - 512) / 512;
  952. ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
  953. if (ret < 0) {
  954. netdev_warn(dev->net, "Failed to write FCT_TX_FIFO_END: %d\n", ret);
  955. return ret;
  956. }
  957. netif_dbg(dev, ifup, dev->net, "FCT_TX_FIFO_END set to 0x%08x\n", buf);
  958. ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
  959. if (ret < 0) {
  960. netdev_warn(dev->net, "Failed to write INT_STS: %d\n", ret);
  961. return ret;
  962. }
  963. ret = smsc75xx_read_reg(dev, ID_REV, &buf);
  964. if (ret < 0) {
  965. netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
  966. return ret;
  967. }
  968. netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", buf);
  969. ret = smsc75xx_read_reg(dev, E2P_CMD, &buf);
  970. if (ret < 0) {
  971. netdev_warn(dev->net, "Failed to read E2P_CMD: %d\n", ret);
  972. return ret;
  973. }
  974. /* only set default GPIO/LED settings if no EEPROM is detected */
  975. if (!(buf & E2P_CMD_LOADED)) {
  976. ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf);
  977. if (ret < 0) {
  978. netdev_warn(dev->net, "Failed to read LED_GPIO_CFG: %d\n", ret);
  979. return ret;
  980. }
  981. buf &= ~(LED_GPIO_CFG_LED2_FUN_SEL | LED_GPIO_CFG_LED10_FUN_SEL);
  982. buf |= LED_GPIO_CFG_LEDGPIO_EN | LED_GPIO_CFG_LED2_FUN_SEL;
  983. ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf);
  984. if (ret < 0) {
  985. netdev_warn(dev->net, "Failed to write LED_GPIO_CFG: %d\n", ret);
  986. return ret;
  987. }
  988. }
  989. ret = smsc75xx_write_reg(dev, FLOW, 0);
  990. if (ret < 0) {
  991. netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
  992. return ret;
  993. }
  994. ret = smsc75xx_write_reg(dev, FCT_FLOW, 0);
  995. if (ret < 0) {
  996. netdev_warn(dev->net, "Failed to write FCT_FLOW: %d\n", ret);
  997. return ret;
  998. }
  999. /* Don't need rfe_ctl_lock during initialisation */
  1000. ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
  1001. if (ret < 0) {
  1002. netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
  1003. return ret;
  1004. }
  1005. pdata->rfe_ctl |= RFE_CTL_AB | RFE_CTL_DPF;
  1006. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  1007. if (ret < 0) {
  1008. netdev_warn(dev->net, "Failed to write RFE_CTL: %d\n", ret);
  1009. return ret;
  1010. }
  1011. ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
  1012. if (ret < 0) {
  1013. netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
  1014. return ret;
  1015. }
  1016. netif_dbg(dev, ifup, dev->net, "RFE_CTL set to 0x%08x\n",
  1017. pdata->rfe_ctl);
  1018. /* Enable or disable checksum offload engines */
  1019. smsc75xx_set_features(dev->net, dev->net->features);
  1020. smsc75xx_set_multicast(dev->net);
  1021. ret = smsc75xx_phy_initialize(dev);
  1022. if (ret < 0) {
  1023. netdev_warn(dev->net, "Failed to initialize PHY: %d\n", ret);
  1024. return ret;
  1025. }
  1026. ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf);
  1027. if (ret < 0) {
  1028. netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
  1029. return ret;
  1030. }
  1031. /* enable PHY interrupts */
  1032. buf |= INT_ENP_PHY_INT;
  1033. ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
  1034. if (ret < 0) {
  1035. netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
  1036. return ret;
  1037. }
  1038. /* allow mac to detect speed and duplex from phy */
  1039. ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
  1040. if (ret < 0) {
  1041. netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
  1042. return ret;
  1043. }
  1044. buf |= (MAC_CR_ADD | MAC_CR_ASD);
  1045. ret = smsc75xx_write_reg(dev, MAC_CR, buf);
  1046. if (ret < 0) {
  1047. netdev_warn(dev->net, "Failed to write MAC_CR: %d\n", ret);
  1048. return ret;
  1049. }
  1050. ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
  1051. if (ret < 0) {
  1052. netdev_warn(dev->net, "Failed to read MAC_TX: %d\n", ret);
  1053. return ret;
  1054. }
  1055. buf |= MAC_TX_TXEN;
  1056. ret = smsc75xx_write_reg(dev, MAC_TX, buf);
  1057. if (ret < 0) {
  1058. netdev_warn(dev->net, "Failed to write MAC_TX: %d\n", ret);
  1059. return ret;
  1060. }
  1061. netif_dbg(dev, ifup, dev->net, "MAC_TX set to 0x%08x\n", buf);
  1062. ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf);
  1063. if (ret < 0) {
  1064. netdev_warn(dev->net, "Failed to read FCT_TX_CTL: %d\n", ret);
  1065. return ret;
  1066. }
  1067. buf |= FCT_TX_CTL_EN;
  1068. ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf);
  1069. if (ret < 0) {
  1070. netdev_warn(dev->net, "Failed to write FCT_TX_CTL: %d\n", ret);
  1071. return ret;
  1072. }
  1073. netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x\n", buf);
  1074. ret = smsc75xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN);
  1075. if (ret < 0) {
  1076. netdev_warn(dev->net, "Failed to set max rx frame length\n");
  1077. return ret;
  1078. }
  1079. ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
  1080. if (ret < 0) {
  1081. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  1082. return ret;
  1083. }
  1084. buf |= MAC_RX_RXEN;
  1085. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  1086. if (ret < 0) {
  1087. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  1088. return ret;
  1089. }
  1090. netif_dbg(dev, ifup, dev->net, "MAC_RX set to 0x%08x\n", buf);
  1091. ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf);
  1092. if (ret < 0) {
  1093. netdev_warn(dev->net, "Failed to read FCT_RX_CTL: %d\n", ret);
  1094. return ret;
  1095. }
  1096. buf |= FCT_RX_CTL_EN;
  1097. ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf);
  1098. if (ret < 0) {
  1099. netdev_warn(dev->net, "Failed to write FCT_RX_CTL: %d\n", ret);
  1100. return ret;
  1101. }
  1102. netif_dbg(dev, ifup, dev->net, "FCT_RX_CTL set to 0x%08x\n", buf);
  1103. netif_dbg(dev, ifup, dev->net, "smsc75xx_reset, return 0\n");
  1104. return 0;
  1105. }
  1106. static const struct net_device_ops smsc75xx_netdev_ops = {
  1107. .ndo_open = usbnet_open,
  1108. .ndo_stop = usbnet_stop,
  1109. .ndo_start_xmit = usbnet_start_xmit,
  1110. .ndo_tx_timeout = usbnet_tx_timeout,
  1111. .ndo_change_mtu = smsc75xx_change_mtu,
  1112. .ndo_set_mac_address = eth_mac_addr,
  1113. .ndo_validate_addr = eth_validate_addr,
  1114. .ndo_do_ioctl = smsc75xx_ioctl,
  1115. .ndo_set_rx_mode = smsc75xx_set_multicast,
  1116. .ndo_set_features = smsc75xx_set_features,
  1117. };
  1118. static int smsc75xx_bind(struct usbnet *dev, struct usb_interface *intf)
  1119. {
  1120. struct smsc75xx_priv *pdata = NULL;
  1121. int ret;
  1122. printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
  1123. ret = usbnet_get_endpoints(dev, intf);
  1124. if (ret < 0) {
  1125. netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
  1126. return ret;
  1127. }
  1128. dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc75xx_priv),
  1129. GFP_KERNEL);
  1130. pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1131. if (!pdata)
  1132. return -ENOMEM;
  1133. pdata->dev = dev;
  1134. spin_lock_init(&pdata->rfe_ctl_lock);
  1135. mutex_init(&pdata->dataport_mutex);
  1136. INIT_WORK(&pdata->set_multicast, smsc75xx_deferred_multicast_write);
  1137. if (DEFAULT_TX_CSUM_ENABLE)
  1138. dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
  1139. if (DEFAULT_RX_CSUM_ENABLE)
  1140. dev->net->features |= NETIF_F_RXCSUM;
  1141. dev->net->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1142. NETIF_F_RXCSUM;
  1143. ret = smsc75xx_wait_ready(dev, 0);
  1144. if (ret < 0) {
  1145. netdev_warn(dev->net, "device not ready in smsc75xx_bind\n");
  1146. return ret;
  1147. }
  1148. smsc75xx_init_mac_address(dev);
  1149. /* Init all registers */
  1150. ret = smsc75xx_reset(dev);
  1151. if (ret < 0) {
  1152. netdev_warn(dev->net, "smsc75xx_reset error %d\n", ret);
  1153. return ret;
  1154. }
  1155. dev->net->netdev_ops = &smsc75xx_netdev_ops;
  1156. dev->net->ethtool_ops = &smsc75xx_ethtool_ops;
  1157. dev->net->flags |= IFF_MULTICAST;
  1158. dev->net->hard_header_len += SMSC75XX_TX_OVERHEAD;
  1159. dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
  1160. return 0;
  1161. }
  1162. static void smsc75xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  1163. {
  1164. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1165. if (pdata) {
  1166. netif_dbg(dev, ifdown, dev->net, "free pdata\n");
  1167. kfree(pdata);
  1168. pdata = NULL;
  1169. dev->data[0] = 0;
  1170. }
  1171. }
  1172. static u16 smsc_crc(const u8 *buffer, size_t len)
  1173. {
  1174. return bitrev16(crc16(0xFFFF, buffer, len));
  1175. }
  1176. static int smsc75xx_write_wuff(struct usbnet *dev, int filter, u32 wuf_cfg,
  1177. u32 wuf_mask1)
  1178. {
  1179. int cfg_base = WUF_CFGX + filter * 4;
  1180. int mask_base = WUF_MASKX + filter * 16;
  1181. int ret;
  1182. ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg);
  1183. if (ret < 0) {
  1184. netdev_warn(dev->net, "Error writing WUF_CFGX\n");
  1185. return ret;
  1186. }
  1187. ret = smsc75xx_write_reg(dev, mask_base, wuf_mask1);
  1188. if (ret < 0) {
  1189. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1190. return ret;
  1191. }
  1192. ret = smsc75xx_write_reg(dev, mask_base + 4, 0);
  1193. if (ret < 0) {
  1194. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1195. return ret;
  1196. }
  1197. ret = smsc75xx_write_reg(dev, mask_base + 8, 0);
  1198. if (ret < 0) {
  1199. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1200. return ret;
  1201. }
  1202. ret = smsc75xx_write_reg(dev, mask_base + 12, 0);
  1203. if (ret < 0) {
  1204. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1205. return ret;
  1206. }
  1207. return 0;
  1208. }
  1209. static int smsc75xx_enter_suspend0(struct usbnet *dev)
  1210. {
  1211. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1212. u32 val;
  1213. int ret;
  1214. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1215. if (ret < 0) {
  1216. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1217. return ret;
  1218. }
  1219. val &= (~(PMT_CTL_SUS_MODE | PMT_CTL_PHY_RST));
  1220. val |= PMT_CTL_SUS_MODE_0 | PMT_CTL_WOL_EN | PMT_CTL_WUPS;
  1221. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1222. if (ret < 0) {
  1223. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1224. return ret;
  1225. }
  1226. pdata->suspend_flags |= SUSPEND_SUSPEND0;
  1227. return 0;
  1228. }
  1229. static int smsc75xx_enter_suspend1(struct usbnet *dev)
  1230. {
  1231. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1232. u32 val;
  1233. int ret;
  1234. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1235. if (ret < 0) {
  1236. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1237. return ret;
  1238. }
  1239. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1240. val |= PMT_CTL_SUS_MODE_1;
  1241. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1242. if (ret < 0) {
  1243. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1244. return ret;
  1245. }
  1246. /* clear wol status, enable energy detection */
  1247. val &= ~PMT_CTL_WUPS;
  1248. val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
  1249. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1250. if (ret < 0) {
  1251. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1252. return ret;
  1253. }
  1254. pdata->suspend_flags |= SUSPEND_SUSPEND1;
  1255. return 0;
  1256. }
  1257. static int smsc75xx_enter_suspend2(struct usbnet *dev)
  1258. {
  1259. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1260. u32 val;
  1261. int ret;
  1262. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1263. if (ret < 0) {
  1264. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1265. return ret;
  1266. }
  1267. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1268. val |= PMT_CTL_SUS_MODE_2;
  1269. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1270. if (ret < 0) {
  1271. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1272. return ret;
  1273. }
  1274. pdata->suspend_flags |= SUSPEND_SUSPEND2;
  1275. return 0;
  1276. }
  1277. static int smsc75xx_enter_suspend3(struct usbnet *dev)
  1278. {
  1279. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1280. u32 val;
  1281. int ret;
  1282. ret = smsc75xx_read_reg_nopm(dev, FCT_RX_CTL, &val);
  1283. if (ret < 0) {
  1284. netdev_warn(dev->net, "Error reading FCT_RX_CTL\n");
  1285. return ret;
  1286. }
  1287. if (val & FCT_RX_CTL_RXUSED) {
  1288. netdev_dbg(dev->net, "rx fifo not empty in autosuspend\n");
  1289. return -EBUSY;
  1290. }
  1291. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1292. if (ret < 0) {
  1293. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1294. return ret;
  1295. }
  1296. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1297. val |= PMT_CTL_SUS_MODE_3 | PMT_CTL_RES_CLR_WKP_EN;
  1298. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1299. if (ret < 0) {
  1300. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1301. return ret;
  1302. }
  1303. /* clear wol status */
  1304. val &= ~PMT_CTL_WUPS;
  1305. val |= PMT_CTL_WUPS_WOL;
  1306. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1307. if (ret < 0) {
  1308. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1309. return ret;
  1310. }
  1311. pdata->suspend_flags |= SUSPEND_SUSPEND3;
  1312. return 0;
  1313. }
  1314. static int smsc75xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
  1315. {
  1316. struct mii_if_info *mii = &dev->mii;
  1317. int ret;
  1318. netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
  1319. /* read to clear */
  1320. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
  1321. if (ret < 0) {
  1322. netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
  1323. return ret;
  1324. }
  1325. /* enable interrupt source */
  1326. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
  1327. if (ret < 0) {
  1328. netdev_warn(dev->net, "Error reading PHY_INT_MASK\n");
  1329. return ret;
  1330. }
  1331. ret |= mask;
  1332. smsc75xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
  1333. return 0;
  1334. }
  1335. static int smsc75xx_link_ok_nopm(struct usbnet *dev)
  1336. {
  1337. struct mii_if_info *mii = &dev->mii;
  1338. int ret;
  1339. /* first, a dummy read, needed to latch some MII phys */
  1340. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1341. if (ret < 0) {
  1342. netdev_warn(dev->net, "Error reading MII_BMSR\n");
  1343. return ret;
  1344. }
  1345. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1346. if (ret < 0) {
  1347. netdev_warn(dev->net, "Error reading MII_BMSR\n");
  1348. return ret;
  1349. }
  1350. return !!(ret & BMSR_LSTATUS);
  1351. }
  1352. static int smsc75xx_autosuspend(struct usbnet *dev, u32 link_up)
  1353. {
  1354. int ret;
  1355. if (!netif_running(dev->net)) {
  1356. /* interface is ifconfig down so fully power down hw */
  1357. netdev_dbg(dev->net, "autosuspend entering SUSPEND2\n");
  1358. return smsc75xx_enter_suspend2(dev);
  1359. }
  1360. if (!link_up) {
  1361. /* link is down so enter EDPD mode */
  1362. netdev_dbg(dev->net, "autosuspend entering SUSPEND1\n");
  1363. /* enable PHY wakeup events for if cable is attached */
  1364. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1365. PHY_INT_MASK_ANEG_COMP);
  1366. if (ret < 0) {
  1367. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1368. return ret;
  1369. }
  1370. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1371. return smsc75xx_enter_suspend1(dev);
  1372. }
  1373. /* enable PHY wakeup events so we remote wakeup if cable is pulled */
  1374. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1375. PHY_INT_MASK_LINK_DOWN);
  1376. if (ret < 0) {
  1377. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1378. return ret;
  1379. }
  1380. netdev_dbg(dev->net, "autosuspend entering SUSPEND3\n");
  1381. return smsc75xx_enter_suspend3(dev);
  1382. }
  1383. static int smsc75xx_suspend(struct usb_interface *intf, pm_message_t message)
  1384. {
  1385. struct usbnet *dev = usb_get_intfdata(intf);
  1386. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1387. u32 val, link_up;
  1388. int ret;
  1389. ret = usbnet_suspend(intf, message);
  1390. if (ret < 0) {
  1391. netdev_warn(dev->net, "usbnet_suspend error\n");
  1392. return ret;
  1393. }
  1394. if (pdata->suspend_flags) {
  1395. netdev_warn(dev->net, "error during last resume\n");
  1396. pdata->suspend_flags = 0;
  1397. }
  1398. /* determine if link is up using only _nopm functions */
  1399. link_up = smsc75xx_link_ok_nopm(dev);
  1400. if (message.event == PM_EVENT_AUTO_SUSPEND) {
  1401. ret = smsc75xx_autosuspend(dev, link_up);
  1402. goto done;
  1403. }
  1404. /* if we get this far we're not autosuspending */
  1405. /* if no wol options set, or if link is down and we're not waking on
  1406. * PHY activity, enter lowest power SUSPEND2 mode
  1407. */
  1408. if (!(pdata->wolopts & SUPPORTED_WAKE) ||
  1409. !(link_up || (pdata->wolopts & WAKE_PHY))) {
  1410. netdev_info(dev->net, "entering SUSPEND2 mode\n");
  1411. /* disable energy detect (link up) & wake up events */
  1412. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1413. if (ret < 0) {
  1414. netdev_warn(dev->net, "Error reading WUCSR\n");
  1415. goto done;
  1416. }
  1417. val &= ~(WUCSR_MPEN | WUCSR_WUEN);
  1418. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1419. if (ret < 0) {
  1420. netdev_warn(dev->net, "Error writing WUCSR\n");
  1421. goto done;
  1422. }
  1423. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1424. if (ret < 0) {
  1425. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1426. goto done;
  1427. }
  1428. val &= ~(PMT_CTL_ED_EN | PMT_CTL_WOL_EN);
  1429. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1430. if (ret < 0) {
  1431. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1432. goto done;
  1433. }
  1434. ret = smsc75xx_enter_suspend2(dev);
  1435. goto done;
  1436. }
  1437. if (pdata->wolopts & WAKE_PHY) {
  1438. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1439. (PHY_INT_MASK_ANEG_COMP | PHY_INT_MASK_LINK_DOWN));
  1440. if (ret < 0) {
  1441. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1442. goto done;
  1443. }
  1444. /* if link is down then configure EDPD and enter SUSPEND1,
  1445. * otherwise enter SUSPEND0 below
  1446. */
  1447. if (!link_up) {
  1448. struct mii_if_info *mii = &dev->mii;
  1449. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1450. /* enable energy detect power-down mode */
  1451. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id,
  1452. PHY_MODE_CTRL_STS);
  1453. if (ret < 0) {
  1454. netdev_warn(dev->net, "Error reading PHY_MODE_CTRL_STS\n");
  1455. goto done;
  1456. }
  1457. ret |= MODE_CTRL_STS_EDPWRDOWN;
  1458. smsc75xx_mdio_write_nopm(dev->net, mii->phy_id,
  1459. PHY_MODE_CTRL_STS, ret);
  1460. /* enter SUSPEND1 mode */
  1461. ret = smsc75xx_enter_suspend1(dev);
  1462. goto done;
  1463. }
  1464. }
  1465. if (pdata->wolopts & (WAKE_MCAST | WAKE_ARP)) {
  1466. int i, filter = 0;
  1467. /* disable all filters */
  1468. for (i = 0; i < WUF_NUM; i++) {
  1469. ret = smsc75xx_write_reg_nopm(dev, WUF_CFGX + i * 4, 0);
  1470. if (ret < 0) {
  1471. netdev_warn(dev->net, "Error writing WUF_CFGX\n");
  1472. goto done;
  1473. }
  1474. }
  1475. if (pdata->wolopts & WAKE_MCAST) {
  1476. const u8 mcast[] = {0x01, 0x00, 0x5E};
  1477. netdev_info(dev->net, "enabling multicast detection\n");
  1478. val = WUF_CFGX_EN | WUF_CFGX_ATYPE_MULTICAST
  1479. | smsc_crc(mcast, 3);
  1480. ret = smsc75xx_write_wuff(dev, filter++, val, 0x0007);
  1481. if (ret < 0) {
  1482. netdev_warn(dev->net, "Error writing wakeup filter\n");
  1483. goto done;
  1484. }
  1485. }
  1486. if (pdata->wolopts & WAKE_ARP) {
  1487. const u8 arp[] = {0x08, 0x06};
  1488. netdev_info(dev->net, "enabling ARP detection\n");
  1489. val = WUF_CFGX_EN | WUF_CFGX_ATYPE_ALL | (0x0C << 16)
  1490. | smsc_crc(arp, 2);
  1491. ret = smsc75xx_write_wuff(dev, filter++, val, 0x0003);
  1492. if (ret < 0) {
  1493. netdev_warn(dev->net, "Error writing wakeup filter\n");
  1494. goto done;
  1495. }
  1496. }
  1497. /* clear any pending pattern match packet status */
  1498. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1499. if (ret < 0) {
  1500. netdev_warn(dev->net, "Error reading WUCSR\n");
  1501. goto done;
  1502. }
  1503. val |= WUCSR_WUFR;
  1504. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1505. if (ret < 0) {
  1506. netdev_warn(dev->net, "Error writing WUCSR\n");
  1507. goto done;
  1508. }
  1509. netdev_info(dev->net, "enabling packet match detection\n");
  1510. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1511. if (ret < 0) {
  1512. netdev_warn(dev->net, "Error reading WUCSR\n");
  1513. goto done;
  1514. }
  1515. val |= WUCSR_WUEN;
  1516. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1517. if (ret < 0) {
  1518. netdev_warn(dev->net, "Error writing WUCSR\n");
  1519. goto done;
  1520. }
  1521. } else {
  1522. netdev_info(dev->net, "disabling packet match detection\n");
  1523. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1524. if (ret < 0) {
  1525. netdev_warn(dev->net, "Error reading WUCSR\n");
  1526. goto done;
  1527. }
  1528. val &= ~WUCSR_WUEN;
  1529. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1530. if (ret < 0) {
  1531. netdev_warn(dev->net, "Error writing WUCSR\n");
  1532. goto done;
  1533. }
  1534. }
  1535. /* disable magic, bcast & unicast wakeup sources */
  1536. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1537. if (ret < 0) {
  1538. netdev_warn(dev->net, "Error reading WUCSR\n");
  1539. goto done;
  1540. }
  1541. val &= ~(WUCSR_MPEN | WUCSR_BCST_EN | WUCSR_PFDA_EN);
  1542. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1543. if (ret < 0) {
  1544. netdev_warn(dev->net, "Error writing WUCSR\n");
  1545. goto done;
  1546. }
  1547. if (pdata->wolopts & WAKE_PHY) {
  1548. netdev_info(dev->net, "enabling PHY wakeup\n");
  1549. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1550. if (ret < 0) {
  1551. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1552. goto done;
  1553. }
  1554. /* clear wol status, enable energy detection */
  1555. val &= ~PMT_CTL_WUPS;
  1556. val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
  1557. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1558. if (ret < 0) {
  1559. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1560. goto done;
  1561. }
  1562. }
  1563. if (pdata->wolopts & WAKE_MAGIC) {
  1564. netdev_info(dev->net, "enabling magic packet wakeup\n");
  1565. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1566. if (ret < 0) {
  1567. netdev_warn(dev->net, "Error reading WUCSR\n");
  1568. goto done;
  1569. }
  1570. /* clear any pending magic packet status */
  1571. val |= WUCSR_MPR | WUCSR_MPEN;
  1572. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1573. if (ret < 0) {
  1574. netdev_warn(dev->net, "Error writing WUCSR\n");
  1575. goto done;
  1576. }
  1577. }
  1578. if (pdata->wolopts & WAKE_BCAST) {
  1579. netdev_info(dev->net, "enabling broadcast detection\n");
  1580. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1581. if (ret < 0) {
  1582. netdev_warn(dev->net, "Error reading WUCSR\n");
  1583. goto done;
  1584. }
  1585. val |= WUCSR_BCAST_FR | WUCSR_BCST_EN;
  1586. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1587. if (ret < 0) {
  1588. netdev_warn(dev->net, "Error writing WUCSR\n");
  1589. goto done;
  1590. }
  1591. }
  1592. if (pdata->wolopts & WAKE_UCAST) {
  1593. netdev_info(dev->net, "enabling unicast detection\n");
  1594. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1595. if (ret < 0) {
  1596. netdev_warn(dev->net, "Error reading WUCSR\n");
  1597. goto done;
  1598. }
  1599. val |= WUCSR_WUFR | WUCSR_PFDA_EN;
  1600. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1601. if (ret < 0) {
  1602. netdev_warn(dev->net, "Error writing WUCSR\n");
  1603. goto done;
  1604. }
  1605. }
  1606. /* enable receiver to enable frame reception */
  1607. ret = smsc75xx_read_reg_nopm(dev, MAC_RX, &val);
  1608. if (ret < 0) {
  1609. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  1610. goto done;
  1611. }
  1612. val |= MAC_RX_RXEN;
  1613. ret = smsc75xx_write_reg_nopm(dev, MAC_RX, val);
  1614. if (ret < 0) {
  1615. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  1616. goto done;
  1617. }
  1618. /* some wol options are enabled, so enter SUSPEND0 */
  1619. netdev_info(dev->net, "entering SUSPEND0 mode\n");
  1620. ret = smsc75xx_enter_suspend0(dev);
  1621. done:
  1622. /*
  1623. * TODO: resume() might need to handle the suspend failure
  1624. * in system sleep
  1625. */
  1626. if (ret && PMSG_IS_AUTO(message))
  1627. usbnet_resume(intf);
  1628. return ret;
  1629. }
  1630. static int smsc75xx_resume(struct usb_interface *intf)
  1631. {
  1632. struct usbnet *dev = usb_get_intfdata(intf);
  1633. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1634. u8 suspend_flags = pdata->suspend_flags;
  1635. int ret;
  1636. u32 val;
  1637. netdev_dbg(dev->net, "resume suspend_flags=0x%02x\n", suspend_flags);
  1638. /* do this first to ensure it's cleared even in error case */
  1639. pdata->suspend_flags = 0;
  1640. if (suspend_flags & SUSPEND_ALLMODES) {
  1641. /* Disable wakeup sources */
  1642. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1643. if (ret < 0) {
  1644. netdev_warn(dev->net, "Error reading WUCSR\n");
  1645. return ret;
  1646. }
  1647. val &= ~(WUCSR_WUEN | WUCSR_MPEN | WUCSR_PFDA_EN
  1648. | WUCSR_BCST_EN);
  1649. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1650. if (ret < 0) {
  1651. netdev_warn(dev->net, "Error writing WUCSR\n");
  1652. return ret;
  1653. }
  1654. /* clear wake-up status */
  1655. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1656. if (ret < 0) {
  1657. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1658. return ret;
  1659. }
  1660. val &= ~PMT_CTL_WOL_EN;
  1661. val |= PMT_CTL_WUPS;
  1662. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1663. if (ret < 0) {
  1664. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1665. return ret;
  1666. }
  1667. }
  1668. if (suspend_flags & SUSPEND_SUSPEND2) {
  1669. netdev_info(dev->net, "resuming from SUSPEND2\n");
  1670. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1671. if (ret < 0) {
  1672. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1673. return ret;
  1674. }
  1675. val |= PMT_CTL_PHY_PWRUP;
  1676. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1677. if (ret < 0) {
  1678. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1679. return ret;
  1680. }
  1681. }
  1682. ret = smsc75xx_wait_ready(dev, 1);
  1683. if (ret < 0) {
  1684. netdev_warn(dev->net, "device not ready in smsc75xx_resume\n");
  1685. return ret;
  1686. }
  1687. return usbnet_resume(intf);
  1688. }
  1689. static void smsc75xx_rx_csum_offload(struct usbnet *dev, struct sk_buff *skb,
  1690. u32 rx_cmd_a, u32 rx_cmd_b)
  1691. {
  1692. if (!(dev->net->features & NETIF_F_RXCSUM) ||
  1693. unlikely(rx_cmd_a & RX_CMD_A_LCSM)) {
  1694. skb->ip_summed = CHECKSUM_NONE;
  1695. } else {
  1696. skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT));
  1697. skb->ip_summed = CHECKSUM_COMPLETE;
  1698. }
  1699. }
  1700. static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  1701. {
  1702. while (skb->len > 0) {
  1703. u32 rx_cmd_a, rx_cmd_b, align_count, size;
  1704. struct sk_buff *ax_skb;
  1705. unsigned char *packet;
  1706. memcpy(&rx_cmd_a, skb->data, sizeof(rx_cmd_a));
  1707. le32_to_cpus(&rx_cmd_a);
  1708. skb_pull(skb, 4);
  1709. memcpy(&rx_cmd_b, skb->data, sizeof(rx_cmd_b));
  1710. le32_to_cpus(&rx_cmd_b);
  1711. skb_pull(skb, 4 + RXW_PADDING);
  1712. packet = skb->data;
  1713. /* get the packet length */
  1714. size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING;
  1715. align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
  1716. if (unlikely(rx_cmd_a & RX_CMD_A_RED)) {
  1717. netif_dbg(dev, rx_err, dev->net,
  1718. "Error rx_cmd_a=0x%08x\n", rx_cmd_a);
  1719. dev->net->stats.rx_errors++;
  1720. dev->net->stats.rx_dropped++;
  1721. if (rx_cmd_a & RX_CMD_A_FCS)
  1722. dev->net->stats.rx_crc_errors++;
  1723. else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT))
  1724. dev->net->stats.rx_frame_errors++;
  1725. } else {
  1726. /* MAX_SINGLE_PACKET_SIZE + 4(CRC) + 2(COE) + 4(Vlan) */
  1727. if (unlikely(size > (MAX_SINGLE_PACKET_SIZE + ETH_HLEN + 12))) {
  1728. netif_dbg(dev, rx_err, dev->net,
  1729. "size err rx_cmd_a=0x%08x\n",
  1730. rx_cmd_a);
  1731. return 0;
  1732. }
  1733. /* last frame in this batch */
  1734. if (skb->len == size) {
  1735. smsc75xx_rx_csum_offload(dev, skb, rx_cmd_a,
  1736. rx_cmd_b);
  1737. skb_trim(skb, skb->len - 4); /* remove fcs */
  1738. skb->truesize = size + sizeof(struct sk_buff);
  1739. return 1;
  1740. }
  1741. ax_skb = skb_clone(skb, GFP_ATOMIC);
  1742. if (unlikely(!ax_skb)) {
  1743. netdev_warn(dev->net, "Error allocating skb\n");
  1744. return 0;
  1745. }
  1746. ax_skb->len = size;
  1747. ax_skb->data = packet;
  1748. skb_set_tail_pointer(ax_skb, size);
  1749. smsc75xx_rx_csum_offload(dev, ax_skb, rx_cmd_a,
  1750. rx_cmd_b);
  1751. skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
  1752. ax_skb->truesize = size + sizeof(struct sk_buff);
  1753. usbnet_skb_return(dev, ax_skb);
  1754. }
  1755. skb_pull(skb, size);
  1756. /* padding bytes before the next frame starts */
  1757. if (skb->len)
  1758. skb_pull(skb, align_count);
  1759. }
  1760. if (unlikely(skb->len < 0)) {
  1761. netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len);
  1762. return 0;
  1763. }
  1764. return 1;
  1765. }
  1766. static struct sk_buff *smsc75xx_tx_fixup(struct usbnet *dev,
  1767. struct sk_buff *skb, gfp_t flags)
  1768. {
  1769. u32 tx_cmd_a, tx_cmd_b;
  1770. if (skb_headroom(skb) < SMSC75XX_TX_OVERHEAD) {
  1771. struct sk_buff *skb2 =
  1772. skb_copy_expand(skb, SMSC75XX_TX_OVERHEAD, 0, flags);
  1773. dev_kfree_skb_any(skb);
  1774. skb = skb2;
  1775. if (!skb)
  1776. return NULL;
  1777. }
  1778. tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN) | TX_CMD_A_FCS;
  1779. if (skb->ip_summed == CHECKSUM_PARTIAL)
  1780. tx_cmd_a |= TX_CMD_A_IPE | TX_CMD_A_TPE;
  1781. if (skb_is_gso(skb)) {
  1782. u16 mss = max(skb_shinfo(skb)->gso_size, TX_MSS_MIN);
  1783. tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT) & TX_CMD_B_MSS;
  1784. tx_cmd_a |= TX_CMD_A_LSO;
  1785. } else {
  1786. tx_cmd_b = 0;
  1787. }
  1788. skb_push(skb, 4);
  1789. cpu_to_le32s(&tx_cmd_b);
  1790. memcpy(skb->data, &tx_cmd_b, 4);
  1791. skb_push(skb, 4);
  1792. cpu_to_le32s(&tx_cmd_a);
  1793. memcpy(skb->data, &tx_cmd_a, 4);
  1794. return skb;
  1795. }
  1796. static int smsc75xx_manage_power(struct usbnet *dev, int on)
  1797. {
  1798. dev->intf->needs_remote_wakeup = on;
  1799. return 0;
  1800. }
  1801. static const struct driver_info smsc75xx_info = {
  1802. .description = "smsc75xx USB 2.0 Gigabit Ethernet",
  1803. .bind = smsc75xx_bind,
  1804. .unbind = smsc75xx_unbind,
  1805. .link_reset = smsc75xx_link_reset,
  1806. .reset = smsc75xx_reset,
  1807. .rx_fixup = smsc75xx_rx_fixup,
  1808. .tx_fixup = smsc75xx_tx_fixup,
  1809. .status = smsc75xx_status,
  1810. .manage_power = smsc75xx_manage_power,
  1811. .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
  1812. };
  1813. static const struct usb_device_id products[] = {
  1814. {
  1815. /* SMSC7500 USB Gigabit Ethernet Device */
  1816. USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7500),
  1817. .driver_info = (unsigned long) &smsc75xx_info,
  1818. },
  1819. {
  1820. /* SMSC7500 USB Gigabit Ethernet Device */
  1821. USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7505),
  1822. .driver_info = (unsigned long) &smsc75xx_info,
  1823. },
  1824. { }, /* END */
  1825. };
  1826. MODULE_DEVICE_TABLE(usb, products);
  1827. static struct usb_driver smsc75xx_driver = {
  1828. .name = SMSC_CHIPNAME,
  1829. .id_table = products,
  1830. .probe = usbnet_probe,
  1831. .suspend = smsc75xx_suspend,
  1832. .resume = smsc75xx_resume,
  1833. .reset_resume = smsc75xx_resume,
  1834. .disconnect = usbnet_disconnect,
  1835. .disable_hub_initiated_lpm = 1,
  1836. .supports_autosuspend = 1,
  1837. };
  1838. module_usb_driver(smsc75xx_driver);
  1839. MODULE_AUTHOR("Nancy Lin");
  1840. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
  1841. MODULE_DESCRIPTION("SMSC75XX USB 2.0 Gigabit Ethernet Devices");
  1842. MODULE_LICENSE("GPL");