rrunner.c 41 KB

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  1. /*
  2. * rrunner.c: Linux driver for the Essential RoadRunner HIPPI board.
  3. *
  4. * Copyright (C) 1998-2002 by Jes Sorensen, <jes@wildopensource.com>.
  5. *
  6. * Thanks to Essential Communication for providing us with hardware
  7. * and very comprehensive documentation without which I would not have
  8. * been able to write this driver. A special thank you to John Gibbon
  9. * for sorting out the legal issues, with the NDA, allowing the code to
  10. * be released under the GPL.
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2 of the License, or
  15. * (at your option) any later version.
  16. *
  17. * Thanks to Jayaram Bhat from ODS/Essential for fixing some of the
  18. * stupid bugs in my code.
  19. *
  20. * Softnet support and various other patches from Val Henson of
  21. * ODS/Essential.
  22. *
  23. * PCI DMA mapping code partly based on work by Francois Romieu.
  24. */
  25. #define DEBUG 1
  26. #define RX_DMA_SKBUFF 1
  27. #define PKT_COPY_THRESHOLD 512
  28. #include <linux/module.h>
  29. #include <linux/types.h>
  30. #include <linux/errno.h>
  31. #include <linux/ioport.h>
  32. #include <linux/pci.h>
  33. #include <linux/kernel.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/hippidevice.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/init.h>
  38. #include <linux/delay.h>
  39. #include <linux/mm.h>
  40. #include <linux/slab.h>
  41. #include <net/sock.h>
  42. #include <asm/cache.h>
  43. #include <asm/byteorder.h>
  44. #include <asm/io.h>
  45. #include <asm/irq.h>
  46. #include <asm/uaccess.h>
  47. #define rr_if_busy(dev) netif_queue_stopped(dev)
  48. #define rr_if_running(dev) netif_running(dev)
  49. #include "rrunner.h"
  50. #define RUN_AT(x) (jiffies + (x))
  51. MODULE_AUTHOR("Jes Sorensen <jes@wildopensource.com>");
  52. MODULE_DESCRIPTION("Essential RoadRunner HIPPI driver");
  53. MODULE_LICENSE("GPL");
  54. static char version[] = "rrunner.c: v0.50 11/11/2002 Jes Sorensen (jes@wildopensource.com)\n";
  55. static const struct net_device_ops rr_netdev_ops = {
  56. .ndo_open = rr_open,
  57. .ndo_stop = rr_close,
  58. .ndo_do_ioctl = rr_ioctl,
  59. .ndo_start_xmit = rr_start_xmit,
  60. .ndo_change_mtu = hippi_change_mtu,
  61. .ndo_set_mac_address = hippi_mac_addr,
  62. };
  63. /*
  64. * Implementation notes:
  65. *
  66. * The DMA engine only allows for DMA within physical 64KB chunks of
  67. * memory. The current approach of the driver (and stack) is to use
  68. * linear blocks of memory for the skbuffs. However, as the data block
  69. * is always the first part of the skb and skbs are 2^n aligned so we
  70. * are guarantted to get the whole block within one 64KB align 64KB
  71. * chunk.
  72. *
  73. * On the long term, relying on being able to allocate 64KB linear
  74. * chunks of memory is not feasible and the skb handling code and the
  75. * stack will need to know about I/O vectors or something similar.
  76. */
  77. static int rr_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  78. {
  79. struct net_device *dev;
  80. static int version_disp;
  81. u8 pci_latency;
  82. struct rr_private *rrpriv;
  83. void *tmpptr;
  84. dma_addr_t ring_dma;
  85. int ret = -ENOMEM;
  86. dev = alloc_hippi_dev(sizeof(struct rr_private));
  87. if (!dev)
  88. goto out3;
  89. ret = pci_enable_device(pdev);
  90. if (ret) {
  91. ret = -ENODEV;
  92. goto out2;
  93. }
  94. rrpriv = netdev_priv(dev);
  95. SET_NETDEV_DEV(dev, &pdev->dev);
  96. ret = pci_request_regions(pdev, "rrunner");
  97. if (ret < 0)
  98. goto out;
  99. pci_set_drvdata(pdev, dev);
  100. rrpriv->pci_dev = pdev;
  101. spin_lock_init(&rrpriv->lock);
  102. dev->netdev_ops = &rr_netdev_ops;
  103. /* display version info if adapter is found */
  104. if (!version_disp) {
  105. /* set display flag to TRUE so that */
  106. /* we only display this string ONCE */
  107. version_disp = 1;
  108. printk(version);
  109. }
  110. pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
  111. if (pci_latency <= 0x58){
  112. pci_latency = 0x58;
  113. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, pci_latency);
  114. }
  115. pci_set_master(pdev);
  116. printk(KERN_INFO "%s: Essential RoadRunner serial HIPPI "
  117. "at 0x%llx, irq %i, PCI latency %i\n", dev->name,
  118. (unsigned long long)pci_resource_start(pdev, 0),
  119. pdev->irq, pci_latency);
  120. /*
  121. * Remap the MMIO regs into kernel space.
  122. */
  123. rrpriv->regs = pci_iomap(pdev, 0, 0x1000);
  124. if (!rrpriv->regs) {
  125. printk(KERN_ERR "%s: Unable to map I/O register, "
  126. "RoadRunner will be disabled.\n", dev->name);
  127. ret = -EIO;
  128. goto out;
  129. }
  130. tmpptr = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
  131. rrpriv->tx_ring = tmpptr;
  132. rrpriv->tx_ring_dma = ring_dma;
  133. if (!tmpptr) {
  134. ret = -ENOMEM;
  135. goto out;
  136. }
  137. tmpptr = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
  138. rrpriv->rx_ring = tmpptr;
  139. rrpriv->rx_ring_dma = ring_dma;
  140. if (!tmpptr) {
  141. ret = -ENOMEM;
  142. goto out;
  143. }
  144. tmpptr = pci_alloc_consistent(pdev, EVT_RING_SIZE, &ring_dma);
  145. rrpriv->evt_ring = tmpptr;
  146. rrpriv->evt_ring_dma = ring_dma;
  147. if (!tmpptr) {
  148. ret = -ENOMEM;
  149. goto out;
  150. }
  151. /*
  152. * Don't access any register before this point!
  153. */
  154. #ifdef __BIG_ENDIAN
  155. writel(readl(&rrpriv->regs->HostCtrl) | NO_SWAP,
  156. &rrpriv->regs->HostCtrl);
  157. #endif
  158. /*
  159. * Need to add a case for little-endian 64-bit hosts here.
  160. */
  161. rr_init(dev);
  162. ret = register_netdev(dev);
  163. if (ret)
  164. goto out;
  165. return 0;
  166. out:
  167. if (rrpriv->evt_ring)
  168. pci_free_consistent(pdev, EVT_RING_SIZE, rrpriv->evt_ring,
  169. rrpriv->evt_ring_dma);
  170. if (rrpriv->rx_ring)
  171. pci_free_consistent(pdev, RX_TOTAL_SIZE, rrpriv->rx_ring,
  172. rrpriv->rx_ring_dma);
  173. if (rrpriv->tx_ring)
  174. pci_free_consistent(pdev, TX_TOTAL_SIZE, rrpriv->tx_ring,
  175. rrpriv->tx_ring_dma);
  176. if (rrpriv->regs)
  177. pci_iounmap(pdev, rrpriv->regs);
  178. if (pdev) {
  179. pci_release_regions(pdev);
  180. pci_set_drvdata(pdev, NULL);
  181. }
  182. out2:
  183. free_netdev(dev);
  184. out3:
  185. return ret;
  186. }
  187. static void rr_remove_one(struct pci_dev *pdev)
  188. {
  189. struct net_device *dev = pci_get_drvdata(pdev);
  190. struct rr_private *rr = netdev_priv(dev);
  191. if (!(readl(&rr->regs->HostCtrl) & NIC_HALTED)) {
  192. printk(KERN_ERR "%s: trying to unload running NIC\n",
  193. dev->name);
  194. writel(HALT_NIC, &rr->regs->HostCtrl);
  195. }
  196. unregister_netdev(dev);
  197. pci_free_consistent(pdev, EVT_RING_SIZE, rr->evt_ring,
  198. rr->evt_ring_dma);
  199. pci_free_consistent(pdev, RX_TOTAL_SIZE, rr->rx_ring,
  200. rr->rx_ring_dma);
  201. pci_free_consistent(pdev, TX_TOTAL_SIZE, rr->tx_ring,
  202. rr->tx_ring_dma);
  203. pci_iounmap(pdev, rr->regs);
  204. pci_release_regions(pdev);
  205. pci_disable_device(pdev);
  206. pci_set_drvdata(pdev, NULL);
  207. free_netdev(dev);
  208. }
  209. /*
  210. * Commands are considered to be slow, thus there is no reason to
  211. * inline this.
  212. */
  213. static void rr_issue_cmd(struct rr_private *rrpriv, struct cmd *cmd)
  214. {
  215. struct rr_regs __iomem *regs;
  216. u32 idx;
  217. regs = rrpriv->regs;
  218. /*
  219. * This is temporary - it will go away in the final version.
  220. * We probably also want to make this function inline.
  221. */
  222. if (readl(&regs->HostCtrl) & NIC_HALTED){
  223. printk("issuing command for halted NIC, code 0x%x, "
  224. "HostCtrl %08x\n", cmd->code, readl(&regs->HostCtrl));
  225. if (readl(&regs->Mode) & FATAL_ERR)
  226. printk("error codes Fail1 %02x, Fail2 %02x\n",
  227. readl(&regs->Fail1), readl(&regs->Fail2));
  228. }
  229. idx = rrpriv->info->cmd_ctrl.pi;
  230. writel(*(u32*)(cmd), &regs->CmdRing[idx]);
  231. wmb();
  232. idx = (idx - 1) % CMD_RING_ENTRIES;
  233. rrpriv->info->cmd_ctrl.pi = idx;
  234. wmb();
  235. if (readl(&regs->Mode) & FATAL_ERR)
  236. printk("error code %02x\n", readl(&regs->Fail1));
  237. }
  238. /*
  239. * Reset the board in a sensible manner. The NIC is already halted
  240. * when we get here and a spin-lock is held.
  241. */
  242. static int rr_reset(struct net_device *dev)
  243. {
  244. struct rr_private *rrpriv;
  245. struct rr_regs __iomem *regs;
  246. u32 start_pc;
  247. int i;
  248. rrpriv = netdev_priv(dev);
  249. regs = rrpriv->regs;
  250. rr_load_firmware(dev);
  251. writel(0x01000000, &regs->TX_state);
  252. writel(0xff800000, &regs->RX_state);
  253. writel(0, &regs->AssistState);
  254. writel(CLEAR_INTA, &regs->LocalCtrl);
  255. writel(0x01, &regs->BrkPt);
  256. writel(0, &regs->Timer);
  257. writel(0, &regs->TimerRef);
  258. writel(RESET_DMA, &regs->DmaReadState);
  259. writel(RESET_DMA, &regs->DmaWriteState);
  260. writel(0, &regs->DmaWriteHostHi);
  261. writel(0, &regs->DmaWriteHostLo);
  262. writel(0, &regs->DmaReadHostHi);
  263. writel(0, &regs->DmaReadHostLo);
  264. writel(0, &regs->DmaReadLen);
  265. writel(0, &regs->DmaWriteLen);
  266. writel(0, &regs->DmaWriteLcl);
  267. writel(0, &regs->DmaWriteIPchecksum);
  268. writel(0, &regs->DmaReadLcl);
  269. writel(0, &regs->DmaReadIPchecksum);
  270. writel(0, &regs->PciState);
  271. #if (BITS_PER_LONG == 64) && defined __LITTLE_ENDIAN
  272. writel(SWAP_DATA | PTR64BIT | PTR_WD_SWAP, &regs->Mode);
  273. #elif (BITS_PER_LONG == 64)
  274. writel(SWAP_DATA | PTR64BIT | PTR_WD_NOSWAP, &regs->Mode);
  275. #else
  276. writel(SWAP_DATA | PTR32BIT | PTR_WD_NOSWAP, &regs->Mode);
  277. #endif
  278. #if 0
  279. /*
  280. * Don't worry, this is just black magic.
  281. */
  282. writel(0xdf000, &regs->RxBase);
  283. writel(0xdf000, &regs->RxPrd);
  284. writel(0xdf000, &regs->RxCon);
  285. writel(0xce000, &regs->TxBase);
  286. writel(0xce000, &regs->TxPrd);
  287. writel(0xce000, &regs->TxCon);
  288. writel(0, &regs->RxIndPro);
  289. writel(0, &regs->RxIndCon);
  290. writel(0, &regs->RxIndRef);
  291. writel(0, &regs->TxIndPro);
  292. writel(0, &regs->TxIndCon);
  293. writel(0, &regs->TxIndRef);
  294. writel(0xcc000, &regs->pad10[0]);
  295. writel(0, &regs->DrCmndPro);
  296. writel(0, &regs->DrCmndCon);
  297. writel(0, &regs->DwCmndPro);
  298. writel(0, &regs->DwCmndCon);
  299. writel(0, &regs->DwCmndRef);
  300. writel(0, &regs->DrDataPro);
  301. writel(0, &regs->DrDataCon);
  302. writel(0, &regs->DrDataRef);
  303. writel(0, &regs->DwDataPro);
  304. writel(0, &regs->DwDataCon);
  305. writel(0, &regs->DwDataRef);
  306. #endif
  307. writel(0xffffffff, &regs->MbEvent);
  308. writel(0, &regs->Event);
  309. writel(0, &regs->TxPi);
  310. writel(0, &regs->IpRxPi);
  311. writel(0, &regs->EvtCon);
  312. writel(0, &regs->EvtPrd);
  313. rrpriv->info->evt_ctrl.pi = 0;
  314. for (i = 0; i < CMD_RING_ENTRIES; i++)
  315. writel(0, &regs->CmdRing[i]);
  316. /*
  317. * Why 32 ? is this not cache line size dependent?
  318. */
  319. writel(RBURST_64|WBURST_64, &regs->PciState);
  320. wmb();
  321. start_pc = rr_read_eeprom_word(rrpriv,
  322. offsetof(struct eeprom, rncd_info.FwStart));
  323. #if (DEBUG > 1)
  324. printk("%s: Executing firmware at address 0x%06x\n",
  325. dev->name, start_pc);
  326. #endif
  327. writel(start_pc + 0x800, &regs->Pc);
  328. wmb();
  329. udelay(5);
  330. writel(start_pc, &regs->Pc);
  331. wmb();
  332. return 0;
  333. }
  334. /*
  335. * Read a string from the EEPROM.
  336. */
  337. static unsigned int rr_read_eeprom(struct rr_private *rrpriv,
  338. unsigned long offset,
  339. unsigned char *buf,
  340. unsigned long length)
  341. {
  342. struct rr_regs __iomem *regs = rrpriv->regs;
  343. u32 misc, io, host, i;
  344. io = readl(&regs->ExtIo);
  345. writel(0, &regs->ExtIo);
  346. misc = readl(&regs->LocalCtrl);
  347. writel(0, &regs->LocalCtrl);
  348. host = readl(&regs->HostCtrl);
  349. writel(host | HALT_NIC, &regs->HostCtrl);
  350. mb();
  351. for (i = 0; i < length; i++){
  352. writel((EEPROM_BASE + ((offset+i) << 3)), &regs->WinBase);
  353. mb();
  354. buf[i] = (readl(&regs->WinData) >> 24) & 0xff;
  355. mb();
  356. }
  357. writel(host, &regs->HostCtrl);
  358. writel(misc, &regs->LocalCtrl);
  359. writel(io, &regs->ExtIo);
  360. mb();
  361. return i;
  362. }
  363. /*
  364. * Shortcut to read one word (4 bytes) out of the EEPROM and convert
  365. * it to our CPU byte-order.
  366. */
  367. static u32 rr_read_eeprom_word(struct rr_private *rrpriv,
  368. size_t offset)
  369. {
  370. __be32 word;
  371. if ((rr_read_eeprom(rrpriv, offset,
  372. (unsigned char *)&word, 4) == 4))
  373. return be32_to_cpu(word);
  374. return 0;
  375. }
  376. /*
  377. * Write a string to the EEPROM.
  378. *
  379. * This is only called when the firmware is not running.
  380. */
  381. static unsigned int write_eeprom(struct rr_private *rrpriv,
  382. unsigned long offset,
  383. unsigned char *buf,
  384. unsigned long length)
  385. {
  386. struct rr_regs __iomem *regs = rrpriv->regs;
  387. u32 misc, io, data, i, j, ready, error = 0;
  388. io = readl(&regs->ExtIo);
  389. writel(0, &regs->ExtIo);
  390. misc = readl(&regs->LocalCtrl);
  391. writel(ENABLE_EEPROM_WRITE, &regs->LocalCtrl);
  392. mb();
  393. for (i = 0; i < length; i++){
  394. writel((EEPROM_BASE + ((offset+i) << 3)), &regs->WinBase);
  395. mb();
  396. data = buf[i] << 24;
  397. /*
  398. * Only try to write the data if it is not the same
  399. * value already.
  400. */
  401. if ((readl(&regs->WinData) & 0xff000000) != data){
  402. writel(data, &regs->WinData);
  403. ready = 0;
  404. j = 0;
  405. mb();
  406. while(!ready){
  407. udelay(20);
  408. if ((readl(&regs->WinData) & 0xff000000) ==
  409. data)
  410. ready = 1;
  411. mb();
  412. if (j++ > 5000){
  413. printk("data mismatch: %08x, "
  414. "WinData %08x\n", data,
  415. readl(&regs->WinData));
  416. ready = 1;
  417. error = 1;
  418. }
  419. }
  420. }
  421. }
  422. writel(misc, &regs->LocalCtrl);
  423. writel(io, &regs->ExtIo);
  424. mb();
  425. return error;
  426. }
  427. static int rr_init(struct net_device *dev)
  428. {
  429. struct rr_private *rrpriv;
  430. struct rr_regs __iomem *regs;
  431. u32 sram_size, rev;
  432. rrpriv = netdev_priv(dev);
  433. regs = rrpriv->regs;
  434. rev = readl(&regs->FwRev);
  435. rrpriv->fw_rev = rev;
  436. if (rev > 0x00020024)
  437. printk(" Firmware revision: %i.%i.%i\n", (rev >> 16),
  438. ((rev >> 8) & 0xff), (rev & 0xff));
  439. else if (rev >= 0x00020000) {
  440. printk(" Firmware revision: %i.%i.%i (2.0.37 or "
  441. "later is recommended)\n", (rev >> 16),
  442. ((rev >> 8) & 0xff), (rev & 0xff));
  443. }else{
  444. printk(" Firmware revision too old: %i.%i.%i, please "
  445. "upgrade to 2.0.37 or later.\n",
  446. (rev >> 16), ((rev >> 8) & 0xff), (rev & 0xff));
  447. }
  448. #if (DEBUG > 2)
  449. printk(" Maximum receive rings %i\n", readl(&regs->MaxRxRng));
  450. #endif
  451. /*
  452. * Read the hardware address from the eeprom. The HW address
  453. * is not really necessary for HIPPI but awfully convenient.
  454. * The pointer arithmetic to put it in dev_addr is ugly, but
  455. * Donald Becker does it this way for the GigE version of this
  456. * card and it's shorter and more portable than any
  457. * other method I've seen. -VAL
  458. */
  459. *(__be16 *)(dev->dev_addr) =
  460. htons(rr_read_eeprom_word(rrpriv, offsetof(struct eeprom, manf.BoardULA)));
  461. *(__be32 *)(dev->dev_addr+2) =
  462. htonl(rr_read_eeprom_word(rrpriv, offsetof(struct eeprom, manf.BoardULA[4])));
  463. printk(" MAC: %pM\n", dev->dev_addr);
  464. sram_size = rr_read_eeprom_word(rrpriv, 8);
  465. printk(" SRAM size 0x%06x\n", sram_size);
  466. return 0;
  467. }
  468. static int rr_init1(struct net_device *dev)
  469. {
  470. struct rr_private *rrpriv;
  471. struct rr_regs __iomem *regs;
  472. unsigned long myjif, flags;
  473. struct cmd cmd;
  474. u32 hostctrl;
  475. int ecode = 0;
  476. short i;
  477. rrpriv = netdev_priv(dev);
  478. regs = rrpriv->regs;
  479. spin_lock_irqsave(&rrpriv->lock, flags);
  480. hostctrl = readl(&regs->HostCtrl);
  481. writel(hostctrl | HALT_NIC | RR_CLEAR_INT, &regs->HostCtrl);
  482. wmb();
  483. if (hostctrl & PARITY_ERR){
  484. printk("%s: Parity error halting NIC - this is serious!\n",
  485. dev->name);
  486. spin_unlock_irqrestore(&rrpriv->lock, flags);
  487. ecode = -EFAULT;
  488. goto error;
  489. }
  490. set_rxaddr(regs, rrpriv->rx_ctrl_dma);
  491. set_infoaddr(regs, rrpriv->info_dma);
  492. rrpriv->info->evt_ctrl.entry_size = sizeof(struct event);
  493. rrpriv->info->evt_ctrl.entries = EVT_RING_ENTRIES;
  494. rrpriv->info->evt_ctrl.mode = 0;
  495. rrpriv->info->evt_ctrl.pi = 0;
  496. set_rraddr(&rrpriv->info->evt_ctrl.rngptr, rrpriv->evt_ring_dma);
  497. rrpriv->info->cmd_ctrl.entry_size = sizeof(struct cmd);
  498. rrpriv->info->cmd_ctrl.entries = CMD_RING_ENTRIES;
  499. rrpriv->info->cmd_ctrl.mode = 0;
  500. rrpriv->info->cmd_ctrl.pi = 15;
  501. for (i = 0; i < CMD_RING_ENTRIES; i++) {
  502. writel(0, &regs->CmdRing[i]);
  503. }
  504. for (i = 0; i < TX_RING_ENTRIES; i++) {
  505. rrpriv->tx_ring[i].size = 0;
  506. set_rraddr(&rrpriv->tx_ring[i].addr, 0);
  507. rrpriv->tx_skbuff[i] = NULL;
  508. }
  509. rrpriv->info->tx_ctrl.entry_size = sizeof(struct tx_desc);
  510. rrpriv->info->tx_ctrl.entries = TX_RING_ENTRIES;
  511. rrpriv->info->tx_ctrl.mode = 0;
  512. rrpriv->info->tx_ctrl.pi = 0;
  513. set_rraddr(&rrpriv->info->tx_ctrl.rngptr, rrpriv->tx_ring_dma);
  514. /*
  515. * Set dirty_tx before we start receiving interrupts, otherwise
  516. * the interrupt handler might think it is supposed to process
  517. * tx ints before we are up and running, which may cause a null
  518. * pointer access in the int handler.
  519. */
  520. rrpriv->tx_full = 0;
  521. rrpriv->cur_rx = 0;
  522. rrpriv->dirty_rx = rrpriv->dirty_tx = 0;
  523. rr_reset(dev);
  524. /* Tuning values */
  525. writel(0x5000, &regs->ConRetry);
  526. writel(0x100, &regs->ConRetryTmr);
  527. writel(0x500000, &regs->ConTmout);
  528. writel(0x60, &regs->IntrTmr);
  529. writel(0x500000, &regs->TxDataMvTimeout);
  530. writel(0x200000, &regs->RxDataMvTimeout);
  531. writel(0x80, &regs->WriteDmaThresh);
  532. writel(0x80, &regs->ReadDmaThresh);
  533. rrpriv->fw_running = 0;
  534. wmb();
  535. hostctrl &= ~(HALT_NIC | INVALID_INST_B | PARITY_ERR);
  536. writel(hostctrl, &regs->HostCtrl);
  537. wmb();
  538. spin_unlock_irqrestore(&rrpriv->lock, flags);
  539. for (i = 0; i < RX_RING_ENTRIES; i++) {
  540. struct sk_buff *skb;
  541. dma_addr_t addr;
  542. rrpriv->rx_ring[i].mode = 0;
  543. skb = alloc_skb(dev->mtu + HIPPI_HLEN, GFP_ATOMIC);
  544. if (!skb) {
  545. printk(KERN_WARNING "%s: Unable to allocate memory "
  546. "for receive ring - halting NIC\n", dev->name);
  547. ecode = -ENOMEM;
  548. goto error;
  549. }
  550. rrpriv->rx_skbuff[i] = skb;
  551. addr = pci_map_single(rrpriv->pci_dev, skb->data,
  552. dev->mtu + HIPPI_HLEN, PCI_DMA_FROMDEVICE);
  553. /*
  554. * Sanity test to see if we conflict with the DMA
  555. * limitations of the Roadrunner.
  556. */
  557. if ((((unsigned long)skb->data) & 0xfff) > ~65320)
  558. printk("skb alloc error\n");
  559. set_rraddr(&rrpriv->rx_ring[i].addr, addr);
  560. rrpriv->rx_ring[i].size = dev->mtu + HIPPI_HLEN;
  561. }
  562. rrpriv->rx_ctrl[4].entry_size = sizeof(struct rx_desc);
  563. rrpriv->rx_ctrl[4].entries = RX_RING_ENTRIES;
  564. rrpriv->rx_ctrl[4].mode = 8;
  565. rrpriv->rx_ctrl[4].pi = 0;
  566. wmb();
  567. set_rraddr(&rrpriv->rx_ctrl[4].rngptr, rrpriv->rx_ring_dma);
  568. udelay(1000);
  569. /*
  570. * Now start the FirmWare.
  571. */
  572. cmd.code = C_START_FW;
  573. cmd.ring = 0;
  574. cmd.index = 0;
  575. rr_issue_cmd(rrpriv, &cmd);
  576. /*
  577. * Give the FirmWare time to chew on the `get running' command.
  578. */
  579. myjif = jiffies + 5 * HZ;
  580. while (time_before(jiffies, myjif) && !rrpriv->fw_running)
  581. cpu_relax();
  582. netif_start_queue(dev);
  583. return ecode;
  584. error:
  585. /*
  586. * We might have gotten here because we are out of memory,
  587. * make sure we release everything we allocated before failing
  588. */
  589. for (i = 0; i < RX_RING_ENTRIES; i++) {
  590. struct sk_buff *skb = rrpriv->rx_skbuff[i];
  591. if (skb) {
  592. pci_unmap_single(rrpriv->pci_dev,
  593. rrpriv->rx_ring[i].addr.addrlo,
  594. dev->mtu + HIPPI_HLEN,
  595. PCI_DMA_FROMDEVICE);
  596. rrpriv->rx_ring[i].size = 0;
  597. set_rraddr(&rrpriv->rx_ring[i].addr, 0);
  598. dev_kfree_skb(skb);
  599. rrpriv->rx_skbuff[i] = NULL;
  600. }
  601. }
  602. return ecode;
  603. }
  604. /*
  605. * All events are considered to be slow (RX/TX ints do not generate
  606. * events) and are handled here, outside the main interrupt handler,
  607. * to reduce the size of the handler.
  608. */
  609. static u32 rr_handle_event(struct net_device *dev, u32 prodidx, u32 eidx)
  610. {
  611. struct rr_private *rrpriv;
  612. struct rr_regs __iomem *regs;
  613. u32 tmp;
  614. rrpriv = netdev_priv(dev);
  615. regs = rrpriv->regs;
  616. while (prodidx != eidx){
  617. switch (rrpriv->evt_ring[eidx].code){
  618. case E_NIC_UP:
  619. tmp = readl(&regs->FwRev);
  620. printk(KERN_INFO "%s: Firmware revision %i.%i.%i "
  621. "up and running\n", dev->name,
  622. (tmp >> 16), ((tmp >> 8) & 0xff), (tmp & 0xff));
  623. rrpriv->fw_running = 1;
  624. writel(RX_RING_ENTRIES - 1, &regs->IpRxPi);
  625. wmb();
  626. break;
  627. case E_LINK_ON:
  628. printk(KERN_INFO "%s: Optical link ON\n", dev->name);
  629. break;
  630. case E_LINK_OFF:
  631. printk(KERN_INFO "%s: Optical link OFF\n", dev->name);
  632. break;
  633. case E_RX_IDLE:
  634. printk(KERN_WARNING "%s: RX data not moving\n",
  635. dev->name);
  636. goto drop;
  637. case E_WATCHDOG:
  638. printk(KERN_INFO "%s: The watchdog is here to see "
  639. "us\n", dev->name);
  640. break;
  641. case E_INTERN_ERR:
  642. printk(KERN_ERR "%s: HIPPI Internal NIC error\n",
  643. dev->name);
  644. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  645. &regs->HostCtrl);
  646. wmb();
  647. break;
  648. case E_HOST_ERR:
  649. printk(KERN_ERR "%s: Host software error\n",
  650. dev->name);
  651. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  652. &regs->HostCtrl);
  653. wmb();
  654. break;
  655. /*
  656. * TX events.
  657. */
  658. case E_CON_REJ:
  659. printk(KERN_WARNING "%s: Connection rejected\n",
  660. dev->name);
  661. dev->stats.tx_aborted_errors++;
  662. break;
  663. case E_CON_TMOUT:
  664. printk(KERN_WARNING "%s: Connection timeout\n",
  665. dev->name);
  666. break;
  667. case E_DISC_ERR:
  668. printk(KERN_WARNING "%s: HIPPI disconnect error\n",
  669. dev->name);
  670. dev->stats.tx_aborted_errors++;
  671. break;
  672. case E_INT_PRTY:
  673. printk(KERN_ERR "%s: HIPPI Internal Parity error\n",
  674. dev->name);
  675. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  676. &regs->HostCtrl);
  677. wmb();
  678. break;
  679. case E_TX_IDLE:
  680. printk(KERN_WARNING "%s: Transmitter idle\n",
  681. dev->name);
  682. break;
  683. case E_TX_LINK_DROP:
  684. printk(KERN_WARNING "%s: Link lost during transmit\n",
  685. dev->name);
  686. dev->stats.tx_aborted_errors++;
  687. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  688. &regs->HostCtrl);
  689. wmb();
  690. break;
  691. case E_TX_INV_RNG:
  692. printk(KERN_ERR "%s: Invalid send ring block\n",
  693. dev->name);
  694. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  695. &regs->HostCtrl);
  696. wmb();
  697. break;
  698. case E_TX_INV_BUF:
  699. printk(KERN_ERR "%s: Invalid send buffer address\n",
  700. dev->name);
  701. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  702. &regs->HostCtrl);
  703. wmb();
  704. break;
  705. case E_TX_INV_DSC:
  706. printk(KERN_ERR "%s: Invalid descriptor address\n",
  707. dev->name);
  708. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  709. &regs->HostCtrl);
  710. wmb();
  711. break;
  712. /*
  713. * RX events.
  714. */
  715. case E_RX_RNG_OUT:
  716. printk(KERN_INFO "%s: Receive ring full\n", dev->name);
  717. break;
  718. case E_RX_PAR_ERR:
  719. printk(KERN_WARNING "%s: Receive parity error\n",
  720. dev->name);
  721. goto drop;
  722. case E_RX_LLRC_ERR:
  723. printk(KERN_WARNING "%s: Receive LLRC error\n",
  724. dev->name);
  725. goto drop;
  726. case E_PKT_LN_ERR:
  727. printk(KERN_WARNING "%s: Receive packet length "
  728. "error\n", dev->name);
  729. goto drop;
  730. case E_DTA_CKSM_ERR:
  731. printk(KERN_WARNING "%s: Data checksum error\n",
  732. dev->name);
  733. goto drop;
  734. case E_SHT_BST:
  735. printk(KERN_WARNING "%s: Unexpected short burst "
  736. "error\n", dev->name);
  737. goto drop;
  738. case E_STATE_ERR:
  739. printk(KERN_WARNING "%s: Recv. state transition"
  740. " error\n", dev->name);
  741. goto drop;
  742. case E_UNEXP_DATA:
  743. printk(KERN_WARNING "%s: Unexpected data error\n",
  744. dev->name);
  745. goto drop;
  746. case E_LST_LNK_ERR:
  747. printk(KERN_WARNING "%s: Link lost error\n",
  748. dev->name);
  749. goto drop;
  750. case E_FRM_ERR:
  751. printk(KERN_WARNING "%s: Framming Error\n",
  752. dev->name);
  753. goto drop;
  754. case E_FLG_SYN_ERR:
  755. printk(KERN_WARNING "%s: Flag sync. lost during "
  756. "packet\n", dev->name);
  757. goto drop;
  758. case E_RX_INV_BUF:
  759. printk(KERN_ERR "%s: Invalid receive buffer "
  760. "address\n", dev->name);
  761. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  762. &regs->HostCtrl);
  763. wmb();
  764. break;
  765. case E_RX_INV_DSC:
  766. printk(KERN_ERR "%s: Invalid receive descriptor "
  767. "address\n", dev->name);
  768. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  769. &regs->HostCtrl);
  770. wmb();
  771. break;
  772. case E_RNG_BLK:
  773. printk(KERN_ERR "%s: Invalid ring block\n",
  774. dev->name);
  775. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  776. &regs->HostCtrl);
  777. wmb();
  778. break;
  779. drop:
  780. /* Label packet to be dropped.
  781. * Actual dropping occurs in rx
  782. * handling.
  783. *
  784. * The index of packet we get to drop is
  785. * the index of the packet following
  786. * the bad packet. -kbf
  787. */
  788. {
  789. u16 index = rrpriv->evt_ring[eidx].index;
  790. index = (index + (RX_RING_ENTRIES - 1)) %
  791. RX_RING_ENTRIES;
  792. rrpriv->rx_ring[index].mode |=
  793. (PACKET_BAD | PACKET_END);
  794. }
  795. break;
  796. default:
  797. printk(KERN_WARNING "%s: Unhandled event 0x%02x\n",
  798. dev->name, rrpriv->evt_ring[eidx].code);
  799. }
  800. eidx = (eidx + 1) % EVT_RING_ENTRIES;
  801. }
  802. rrpriv->info->evt_ctrl.pi = eidx;
  803. wmb();
  804. return eidx;
  805. }
  806. static void rx_int(struct net_device *dev, u32 rxlimit, u32 index)
  807. {
  808. struct rr_private *rrpriv = netdev_priv(dev);
  809. struct rr_regs __iomem *regs = rrpriv->regs;
  810. do {
  811. struct rx_desc *desc;
  812. u32 pkt_len;
  813. desc = &(rrpriv->rx_ring[index]);
  814. pkt_len = desc->size;
  815. #if (DEBUG > 2)
  816. printk("index %i, rxlimit %i\n", index, rxlimit);
  817. printk("len %x, mode %x\n", pkt_len, desc->mode);
  818. #endif
  819. if ( (rrpriv->rx_ring[index].mode & PACKET_BAD) == PACKET_BAD){
  820. dev->stats.rx_dropped++;
  821. goto defer;
  822. }
  823. if (pkt_len > 0){
  824. struct sk_buff *skb, *rx_skb;
  825. rx_skb = rrpriv->rx_skbuff[index];
  826. if (pkt_len < PKT_COPY_THRESHOLD) {
  827. skb = alloc_skb(pkt_len, GFP_ATOMIC);
  828. if (skb == NULL){
  829. printk(KERN_WARNING "%s: Unable to allocate skb (%i bytes), deferring packet\n", dev->name, pkt_len);
  830. dev->stats.rx_dropped++;
  831. goto defer;
  832. } else {
  833. pci_dma_sync_single_for_cpu(rrpriv->pci_dev,
  834. desc->addr.addrlo,
  835. pkt_len,
  836. PCI_DMA_FROMDEVICE);
  837. memcpy(skb_put(skb, pkt_len),
  838. rx_skb->data, pkt_len);
  839. pci_dma_sync_single_for_device(rrpriv->pci_dev,
  840. desc->addr.addrlo,
  841. pkt_len,
  842. PCI_DMA_FROMDEVICE);
  843. }
  844. }else{
  845. struct sk_buff *newskb;
  846. newskb = alloc_skb(dev->mtu + HIPPI_HLEN,
  847. GFP_ATOMIC);
  848. if (newskb){
  849. dma_addr_t addr;
  850. pci_unmap_single(rrpriv->pci_dev,
  851. desc->addr.addrlo, dev->mtu +
  852. HIPPI_HLEN, PCI_DMA_FROMDEVICE);
  853. skb = rx_skb;
  854. skb_put(skb, pkt_len);
  855. rrpriv->rx_skbuff[index] = newskb;
  856. addr = pci_map_single(rrpriv->pci_dev,
  857. newskb->data,
  858. dev->mtu + HIPPI_HLEN,
  859. PCI_DMA_FROMDEVICE);
  860. set_rraddr(&desc->addr, addr);
  861. } else {
  862. printk("%s: Out of memory, deferring "
  863. "packet\n", dev->name);
  864. dev->stats.rx_dropped++;
  865. goto defer;
  866. }
  867. }
  868. skb->protocol = hippi_type_trans(skb, dev);
  869. netif_rx(skb); /* send it up */
  870. dev->stats.rx_packets++;
  871. dev->stats.rx_bytes += pkt_len;
  872. }
  873. defer:
  874. desc->mode = 0;
  875. desc->size = dev->mtu + HIPPI_HLEN;
  876. if ((index & 7) == 7)
  877. writel(index, &regs->IpRxPi);
  878. index = (index + 1) % RX_RING_ENTRIES;
  879. } while(index != rxlimit);
  880. rrpriv->cur_rx = index;
  881. wmb();
  882. }
  883. static irqreturn_t rr_interrupt(int irq, void *dev_id)
  884. {
  885. struct rr_private *rrpriv;
  886. struct rr_regs __iomem *regs;
  887. struct net_device *dev = (struct net_device *)dev_id;
  888. u32 prodidx, rxindex, eidx, txcsmr, rxlimit, txcon;
  889. rrpriv = netdev_priv(dev);
  890. regs = rrpriv->regs;
  891. if (!(readl(&regs->HostCtrl) & RR_INT))
  892. return IRQ_NONE;
  893. spin_lock(&rrpriv->lock);
  894. prodidx = readl(&regs->EvtPrd);
  895. txcsmr = (prodidx >> 8) & 0xff;
  896. rxlimit = (prodidx >> 16) & 0xff;
  897. prodidx &= 0xff;
  898. #if (DEBUG > 2)
  899. printk("%s: interrupt, prodidx = %i, eidx = %i\n", dev->name,
  900. prodidx, rrpriv->info->evt_ctrl.pi);
  901. #endif
  902. /*
  903. * Order here is important. We must handle events
  904. * before doing anything else in order to catch
  905. * such things as LLRC errors, etc -kbf
  906. */
  907. eidx = rrpriv->info->evt_ctrl.pi;
  908. if (prodidx != eidx)
  909. eidx = rr_handle_event(dev, prodidx, eidx);
  910. rxindex = rrpriv->cur_rx;
  911. if (rxindex != rxlimit)
  912. rx_int(dev, rxlimit, rxindex);
  913. txcon = rrpriv->dirty_tx;
  914. if (txcsmr != txcon) {
  915. do {
  916. /* Due to occational firmware TX producer/consumer out
  917. * of sync. error need to check entry in ring -kbf
  918. */
  919. if(rrpriv->tx_skbuff[txcon]){
  920. struct tx_desc *desc;
  921. struct sk_buff *skb;
  922. desc = &(rrpriv->tx_ring[txcon]);
  923. skb = rrpriv->tx_skbuff[txcon];
  924. dev->stats.tx_packets++;
  925. dev->stats.tx_bytes += skb->len;
  926. pci_unmap_single(rrpriv->pci_dev,
  927. desc->addr.addrlo, skb->len,
  928. PCI_DMA_TODEVICE);
  929. dev_kfree_skb_irq(skb);
  930. rrpriv->tx_skbuff[txcon] = NULL;
  931. desc->size = 0;
  932. set_rraddr(&rrpriv->tx_ring[txcon].addr, 0);
  933. desc->mode = 0;
  934. }
  935. txcon = (txcon + 1) % TX_RING_ENTRIES;
  936. } while (txcsmr != txcon);
  937. wmb();
  938. rrpriv->dirty_tx = txcon;
  939. if (rrpriv->tx_full && rr_if_busy(dev) &&
  940. (((rrpriv->info->tx_ctrl.pi + 1) % TX_RING_ENTRIES)
  941. != rrpriv->dirty_tx)){
  942. rrpriv->tx_full = 0;
  943. netif_wake_queue(dev);
  944. }
  945. }
  946. eidx |= ((txcsmr << 8) | (rxlimit << 16));
  947. writel(eidx, &regs->EvtCon);
  948. wmb();
  949. spin_unlock(&rrpriv->lock);
  950. return IRQ_HANDLED;
  951. }
  952. static inline void rr_raz_tx(struct rr_private *rrpriv,
  953. struct net_device *dev)
  954. {
  955. int i;
  956. for (i = 0; i < TX_RING_ENTRIES; i++) {
  957. struct sk_buff *skb = rrpriv->tx_skbuff[i];
  958. if (skb) {
  959. struct tx_desc *desc = &(rrpriv->tx_ring[i]);
  960. pci_unmap_single(rrpriv->pci_dev, desc->addr.addrlo,
  961. skb->len, PCI_DMA_TODEVICE);
  962. desc->size = 0;
  963. set_rraddr(&desc->addr, 0);
  964. dev_kfree_skb(skb);
  965. rrpriv->tx_skbuff[i] = NULL;
  966. }
  967. }
  968. }
  969. static inline void rr_raz_rx(struct rr_private *rrpriv,
  970. struct net_device *dev)
  971. {
  972. int i;
  973. for (i = 0; i < RX_RING_ENTRIES; i++) {
  974. struct sk_buff *skb = rrpriv->rx_skbuff[i];
  975. if (skb) {
  976. struct rx_desc *desc = &(rrpriv->rx_ring[i]);
  977. pci_unmap_single(rrpriv->pci_dev, desc->addr.addrlo,
  978. dev->mtu + HIPPI_HLEN, PCI_DMA_FROMDEVICE);
  979. desc->size = 0;
  980. set_rraddr(&desc->addr, 0);
  981. dev_kfree_skb(skb);
  982. rrpriv->rx_skbuff[i] = NULL;
  983. }
  984. }
  985. }
  986. static void rr_timer(unsigned long data)
  987. {
  988. struct net_device *dev = (struct net_device *)data;
  989. struct rr_private *rrpriv = netdev_priv(dev);
  990. struct rr_regs __iomem *regs = rrpriv->regs;
  991. unsigned long flags;
  992. if (readl(&regs->HostCtrl) & NIC_HALTED){
  993. printk("%s: Restarting nic\n", dev->name);
  994. memset(rrpriv->rx_ctrl, 0, 256 * sizeof(struct ring_ctrl));
  995. memset(rrpriv->info, 0, sizeof(struct rr_info));
  996. wmb();
  997. rr_raz_tx(rrpriv, dev);
  998. rr_raz_rx(rrpriv, dev);
  999. if (rr_init1(dev)) {
  1000. spin_lock_irqsave(&rrpriv->lock, flags);
  1001. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  1002. &regs->HostCtrl);
  1003. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1004. }
  1005. }
  1006. rrpriv->timer.expires = RUN_AT(5*HZ);
  1007. add_timer(&rrpriv->timer);
  1008. }
  1009. static int rr_open(struct net_device *dev)
  1010. {
  1011. struct rr_private *rrpriv = netdev_priv(dev);
  1012. struct pci_dev *pdev = rrpriv->pci_dev;
  1013. struct rr_regs __iomem *regs;
  1014. int ecode = 0;
  1015. unsigned long flags;
  1016. dma_addr_t dma_addr;
  1017. regs = rrpriv->regs;
  1018. if (rrpriv->fw_rev < 0x00020000) {
  1019. printk(KERN_WARNING "%s: trying to configure device with "
  1020. "obsolete firmware\n", dev->name);
  1021. ecode = -EBUSY;
  1022. goto error;
  1023. }
  1024. rrpriv->rx_ctrl = pci_alloc_consistent(pdev,
  1025. 256 * sizeof(struct ring_ctrl),
  1026. &dma_addr);
  1027. if (!rrpriv->rx_ctrl) {
  1028. ecode = -ENOMEM;
  1029. goto error;
  1030. }
  1031. rrpriv->rx_ctrl_dma = dma_addr;
  1032. memset(rrpriv->rx_ctrl, 0, 256*sizeof(struct ring_ctrl));
  1033. rrpriv->info = pci_alloc_consistent(pdev, sizeof(struct rr_info),
  1034. &dma_addr);
  1035. if (!rrpriv->info) {
  1036. ecode = -ENOMEM;
  1037. goto error;
  1038. }
  1039. rrpriv->info_dma = dma_addr;
  1040. memset(rrpriv->info, 0, sizeof(struct rr_info));
  1041. wmb();
  1042. spin_lock_irqsave(&rrpriv->lock, flags);
  1043. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, &regs->HostCtrl);
  1044. readl(&regs->HostCtrl);
  1045. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1046. if (request_irq(pdev->irq, rr_interrupt, IRQF_SHARED, dev->name, dev)) {
  1047. printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
  1048. dev->name, pdev->irq);
  1049. ecode = -EAGAIN;
  1050. goto error;
  1051. }
  1052. if ((ecode = rr_init1(dev)))
  1053. goto error;
  1054. /* Set the timer to switch to check for link beat and perhaps switch
  1055. to an alternate media type. */
  1056. init_timer(&rrpriv->timer);
  1057. rrpriv->timer.expires = RUN_AT(5*HZ); /* 5 sec. watchdog */
  1058. rrpriv->timer.data = (unsigned long)dev;
  1059. rrpriv->timer.function = rr_timer; /* timer handler */
  1060. add_timer(&rrpriv->timer);
  1061. netif_start_queue(dev);
  1062. return ecode;
  1063. error:
  1064. spin_lock_irqsave(&rrpriv->lock, flags);
  1065. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, &regs->HostCtrl);
  1066. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1067. if (rrpriv->info) {
  1068. pci_free_consistent(pdev, sizeof(struct rr_info), rrpriv->info,
  1069. rrpriv->info_dma);
  1070. rrpriv->info = NULL;
  1071. }
  1072. if (rrpriv->rx_ctrl) {
  1073. pci_free_consistent(pdev, sizeof(struct ring_ctrl),
  1074. rrpriv->rx_ctrl, rrpriv->rx_ctrl_dma);
  1075. rrpriv->rx_ctrl = NULL;
  1076. }
  1077. netif_stop_queue(dev);
  1078. return ecode;
  1079. }
  1080. static void rr_dump(struct net_device *dev)
  1081. {
  1082. struct rr_private *rrpriv;
  1083. struct rr_regs __iomem *regs;
  1084. u32 index, cons;
  1085. short i;
  1086. int len;
  1087. rrpriv = netdev_priv(dev);
  1088. regs = rrpriv->regs;
  1089. printk("%s: dumping NIC TX rings\n", dev->name);
  1090. printk("RxPrd %08x, TxPrd %02x, EvtPrd %08x, TxPi %02x, TxCtrlPi %02x\n",
  1091. readl(&regs->RxPrd), readl(&regs->TxPrd),
  1092. readl(&regs->EvtPrd), readl(&regs->TxPi),
  1093. rrpriv->info->tx_ctrl.pi);
  1094. printk("Error code 0x%x\n", readl(&regs->Fail1));
  1095. index = (((readl(&regs->EvtPrd) >> 8) & 0xff) - 1) % TX_RING_ENTRIES;
  1096. cons = rrpriv->dirty_tx;
  1097. printk("TX ring index %i, TX consumer %i\n",
  1098. index, cons);
  1099. if (rrpriv->tx_skbuff[index]){
  1100. len = min_t(int, 0x80, rrpriv->tx_skbuff[index]->len);
  1101. printk("skbuff for index %i is valid - dumping data (0x%x bytes - DMA len 0x%x)\n", index, len, rrpriv->tx_ring[index].size);
  1102. for (i = 0; i < len; i++){
  1103. if (!(i & 7))
  1104. printk("\n");
  1105. printk("%02x ", (unsigned char) rrpriv->tx_skbuff[index]->data[i]);
  1106. }
  1107. printk("\n");
  1108. }
  1109. if (rrpriv->tx_skbuff[cons]){
  1110. len = min_t(int, 0x80, rrpriv->tx_skbuff[cons]->len);
  1111. printk("skbuff for cons %i is valid - dumping data (0x%x bytes - skbuff len 0x%x)\n", cons, len, rrpriv->tx_skbuff[cons]->len);
  1112. printk("mode 0x%x, size 0x%x,\n phys %08Lx, skbuff-addr %08lx, truesize 0x%x\n",
  1113. rrpriv->tx_ring[cons].mode,
  1114. rrpriv->tx_ring[cons].size,
  1115. (unsigned long long) rrpriv->tx_ring[cons].addr.addrlo,
  1116. (unsigned long)rrpriv->tx_skbuff[cons]->data,
  1117. (unsigned int)rrpriv->tx_skbuff[cons]->truesize);
  1118. for (i = 0; i < len; i++){
  1119. if (!(i & 7))
  1120. printk("\n");
  1121. printk("%02x ", (unsigned char)rrpriv->tx_ring[cons].size);
  1122. }
  1123. printk("\n");
  1124. }
  1125. printk("dumping TX ring info:\n");
  1126. for (i = 0; i < TX_RING_ENTRIES; i++)
  1127. printk("mode 0x%x, size 0x%x, phys-addr %08Lx\n",
  1128. rrpriv->tx_ring[i].mode,
  1129. rrpriv->tx_ring[i].size,
  1130. (unsigned long long) rrpriv->tx_ring[i].addr.addrlo);
  1131. }
  1132. static int rr_close(struct net_device *dev)
  1133. {
  1134. struct rr_private *rrpriv = netdev_priv(dev);
  1135. struct rr_regs __iomem *regs = rrpriv->regs;
  1136. struct pci_dev *pdev = rrpriv->pci_dev;
  1137. unsigned long flags;
  1138. u32 tmp;
  1139. short i;
  1140. netif_stop_queue(dev);
  1141. /*
  1142. * Lock to make sure we are not cleaning up while another CPU
  1143. * is handling interrupts.
  1144. */
  1145. spin_lock_irqsave(&rrpriv->lock, flags);
  1146. tmp = readl(&regs->HostCtrl);
  1147. if (tmp & NIC_HALTED){
  1148. printk("%s: NIC already halted\n", dev->name);
  1149. rr_dump(dev);
  1150. }else{
  1151. tmp |= HALT_NIC | RR_CLEAR_INT;
  1152. writel(tmp, &regs->HostCtrl);
  1153. readl(&regs->HostCtrl);
  1154. }
  1155. rrpriv->fw_running = 0;
  1156. del_timer_sync(&rrpriv->timer);
  1157. writel(0, &regs->TxPi);
  1158. writel(0, &regs->IpRxPi);
  1159. writel(0, &regs->EvtCon);
  1160. writel(0, &regs->EvtPrd);
  1161. for (i = 0; i < CMD_RING_ENTRIES; i++)
  1162. writel(0, &regs->CmdRing[i]);
  1163. rrpriv->info->tx_ctrl.entries = 0;
  1164. rrpriv->info->cmd_ctrl.pi = 0;
  1165. rrpriv->info->evt_ctrl.pi = 0;
  1166. rrpriv->rx_ctrl[4].entries = 0;
  1167. rr_raz_tx(rrpriv, dev);
  1168. rr_raz_rx(rrpriv, dev);
  1169. pci_free_consistent(pdev, 256 * sizeof(struct ring_ctrl),
  1170. rrpriv->rx_ctrl, rrpriv->rx_ctrl_dma);
  1171. rrpriv->rx_ctrl = NULL;
  1172. pci_free_consistent(pdev, sizeof(struct rr_info), rrpriv->info,
  1173. rrpriv->info_dma);
  1174. rrpriv->info = NULL;
  1175. free_irq(pdev->irq, dev);
  1176. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1177. return 0;
  1178. }
  1179. static netdev_tx_t rr_start_xmit(struct sk_buff *skb,
  1180. struct net_device *dev)
  1181. {
  1182. struct rr_private *rrpriv = netdev_priv(dev);
  1183. struct rr_regs __iomem *regs = rrpriv->regs;
  1184. struct hippi_cb *hcb = (struct hippi_cb *) skb->cb;
  1185. struct ring_ctrl *txctrl;
  1186. unsigned long flags;
  1187. u32 index, len = skb->len;
  1188. u32 *ifield;
  1189. struct sk_buff *new_skb;
  1190. if (readl(&regs->Mode) & FATAL_ERR)
  1191. printk("error codes Fail1 %02x, Fail2 %02x\n",
  1192. readl(&regs->Fail1), readl(&regs->Fail2));
  1193. /*
  1194. * We probably need to deal with tbusy here to prevent overruns.
  1195. */
  1196. if (skb_headroom(skb) < 8){
  1197. printk("incoming skb too small - reallocating\n");
  1198. if (!(new_skb = dev_alloc_skb(len + 8))) {
  1199. dev_kfree_skb(skb);
  1200. netif_wake_queue(dev);
  1201. return NETDEV_TX_OK;
  1202. }
  1203. skb_reserve(new_skb, 8);
  1204. skb_put(new_skb, len);
  1205. skb_copy_from_linear_data(skb, new_skb->data, len);
  1206. dev_kfree_skb(skb);
  1207. skb = new_skb;
  1208. }
  1209. ifield = (u32 *)skb_push(skb, 8);
  1210. ifield[0] = 0;
  1211. ifield[1] = hcb->ifield;
  1212. /*
  1213. * We don't need the lock before we are actually going to start
  1214. * fiddling with the control blocks.
  1215. */
  1216. spin_lock_irqsave(&rrpriv->lock, flags);
  1217. txctrl = &rrpriv->info->tx_ctrl;
  1218. index = txctrl->pi;
  1219. rrpriv->tx_skbuff[index] = skb;
  1220. set_rraddr(&rrpriv->tx_ring[index].addr, pci_map_single(
  1221. rrpriv->pci_dev, skb->data, len + 8, PCI_DMA_TODEVICE));
  1222. rrpriv->tx_ring[index].size = len + 8; /* include IFIELD */
  1223. rrpriv->tx_ring[index].mode = PACKET_START | PACKET_END;
  1224. txctrl->pi = (index + 1) % TX_RING_ENTRIES;
  1225. wmb();
  1226. writel(txctrl->pi, &regs->TxPi);
  1227. if (txctrl->pi == rrpriv->dirty_tx){
  1228. rrpriv->tx_full = 1;
  1229. netif_stop_queue(dev);
  1230. }
  1231. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1232. return NETDEV_TX_OK;
  1233. }
  1234. /*
  1235. * Read the firmware out of the EEPROM and put it into the SRAM
  1236. * (or from user space - later)
  1237. *
  1238. * This operation requires the NIC to be halted and is performed with
  1239. * interrupts disabled and with the spinlock hold.
  1240. */
  1241. static int rr_load_firmware(struct net_device *dev)
  1242. {
  1243. struct rr_private *rrpriv;
  1244. struct rr_regs __iomem *regs;
  1245. size_t eptr, segptr;
  1246. int i, j;
  1247. u32 localctrl, sptr, len, tmp;
  1248. u32 p2len, p2size, nr_seg, revision, io, sram_size;
  1249. rrpriv = netdev_priv(dev);
  1250. regs = rrpriv->regs;
  1251. if (dev->flags & IFF_UP)
  1252. return -EBUSY;
  1253. if (!(readl(&regs->HostCtrl) & NIC_HALTED)){
  1254. printk("%s: Trying to load firmware to a running NIC.\n",
  1255. dev->name);
  1256. return -EBUSY;
  1257. }
  1258. localctrl = readl(&regs->LocalCtrl);
  1259. writel(0, &regs->LocalCtrl);
  1260. writel(0, &regs->EvtPrd);
  1261. writel(0, &regs->RxPrd);
  1262. writel(0, &regs->TxPrd);
  1263. /*
  1264. * First wipe the entire SRAM, otherwise we might run into all
  1265. * kinds of trouble ... sigh, this took almost all afternoon
  1266. * to track down ;-(
  1267. */
  1268. io = readl(&regs->ExtIo);
  1269. writel(0, &regs->ExtIo);
  1270. sram_size = rr_read_eeprom_word(rrpriv, 8);
  1271. for (i = 200; i < sram_size / 4; i++){
  1272. writel(i * 4, &regs->WinBase);
  1273. mb();
  1274. writel(0, &regs->WinData);
  1275. mb();
  1276. }
  1277. writel(io, &regs->ExtIo);
  1278. mb();
  1279. eptr = rr_read_eeprom_word(rrpriv,
  1280. offsetof(struct eeprom, rncd_info.AddrRunCodeSegs));
  1281. eptr = ((eptr & 0x1fffff) >> 3);
  1282. p2len = rr_read_eeprom_word(rrpriv, 0x83*4);
  1283. p2len = (p2len << 2);
  1284. p2size = rr_read_eeprom_word(rrpriv, 0x84*4);
  1285. p2size = ((p2size & 0x1fffff) >> 3);
  1286. if ((eptr < p2size) || (eptr > (p2size + p2len))){
  1287. printk("%s: eptr is invalid\n", dev->name);
  1288. goto out;
  1289. }
  1290. revision = rr_read_eeprom_word(rrpriv,
  1291. offsetof(struct eeprom, manf.HeaderFmt));
  1292. if (revision != 1){
  1293. printk("%s: invalid firmware format (%i)\n",
  1294. dev->name, revision);
  1295. goto out;
  1296. }
  1297. nr_seg = rr_read_eeprom_word(rrpriv, eptr);
  1298. eptr +=4;
  1299. #if (DEBUG > 1)
  1300. printk("%s: nr_seg %i\n", dev->name, nr_seg);
  1301. #endif
  1302. for (i = 0; i < nr_seg; i++){
  1303. sptr = rr_read_eeprom_word(rrpriv, eptr);
  1304. eptr += 4;
  1305. len = rr_read_eeprom_word(rrpriv, eptr);
  1306. eptr += 4;
  1307. segptr = rr_read_eeprom_word(rrpriv, eptr);
  1308. segptr = ((segptr & 0x1fffff) >> 3);
  1309. eptr += 4;
  1310. #if (DEBUG > 1)
  1311. printk("%s: segment %i, sram address %06x, length %04x, segptr %06x\n",
  1312. dev->name, i, sptr, len, segptr);
  1313. #endif
  1314. for (j = 0; j < len; j++){
  1315. tmp = rr_read_eeprom_word(rrpriv, segptr);
  1316. writel(sptr, &regs->WinBase);
  1317. mb();
  1318. writel(tmp, &regs->WinData);
  1319. mb();
  1320. segptr += 4;
  1321. sptr += 4;
  1322. }
  1323. }
  1324. out:
  1325. writel(localctrl, &regs->LocalCtrl);
  1326. mb();
  1327. return 0;
  1328. }
  1329. static int rr_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  1330. {
  1331. struct rr_private *rrpriv;
  1332. unsigned char *image, *oldimage;
  1333. unsigned long flags;
  1334. unsigned int i;
  1335. int error = -EOPNOTSUPP;
  1336. rrpriv = netdev_priv(dev);
  1337. switch(cmd){
  1338. case SIOCRRGFW:
  1339. if (!capable(CAP_SYS_RAWIO)){
  1340. return -EPERM;
  1341. }
  1342. image = kmalloc(EEPROM_WORDS * sizeof(u32), GFP_KERNEL);
  1343. if (!image)
  1344. return -ENOMEM;
  1345. if (rrpriv->fw_running){
  1346. printk("%s: Firmware already running\n", dev->name);
  1347. error = -EPERM;
  1348. goto gf_out;
  1349. }
  1350. spin_lock_irqsave(&rrpriv->lock, flags);
  1351. i = rr_read_eeprom(rrpriv, 0, image, EEPROM_BYTES);
  1352. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1353. if (i != EEPROM_BYTES){
  1354. printk(KERN_ERR "%s: Error reading EEPROM\n",
  1355. dev->name);
  1356. error = -EFAULT;
  1357. goto gf_out;
  1358. }
  1359. error = copy_to_user(rq->ifr_data, image, EEPROM_BYTES);
  1360. if (error)
  1361. error = -EFAULT;
  1362. gf_out:
  1363. kfree(image);
  1364. return error;
  1365. case SIOCRRPFW:
  1366. if (!capable(CAP_SYS_RAWIO)){
  1367. return -EPERM;
  1368. }
  1369. image = kmalloc(EEPROM_WORDS * sizeof(u32), GFP_KERNEL);
  1370. oldimage = kmalloc(EEPROM_WORDS * sizeof(u32), GFP_KERNEL);
  1371. if (!image || !oldimage) {
  1372. error = -ENOMEM;
  1373. goto wf_out;
  1374. }
  1375. error = copy_from_user(image, rq->ifr_data, EEPROM_BYTES);
  1376. if (error) {
  1377. error = -EFAULT;
  1378. goto wf_out;
  1379. }
  1380. if (rrpriv->fw_running){
  1381. printk("%s: Firmware already running\n", dev->name);
  1382. error = -EPERM;
  1383. goto wf_out;
  1384. }
  1385. printk("%s: Updating EEPROM firmware\n", dev->name);
  1386. spin_lock_irqsave(&rrpriv->lock, flags);
  1387. error = write_eeprom(rrpriv, 0, image, EEPROM_BYTES);
  1388. if (error)
  1389. printk(KERN_ERR "%s: Error writing EEPROM\n",
  1390. dev->name);
  1391. i = rr_read_eeprom(rrpriv, 0, oldimage, EEPROM_BYTES);
  1392. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1393. if (i != EEPROM_BYTES)
  1394. printk(KERN_ERR "%s: Error reading back EEPROM "
  1395. "image\n", dev->name);
  1396. error = memcmp(image, oldimage, EEPROM_BYTES);
  1397. if (error){
  1398. printk(KERN_ERR "%s: Error verifying EEPROM image\n",
  1399. dev->name);
  1400. error = -EFAULT;
  1401. }
  1402. wf_out:
  1403. kfree(oldimage);
  1404. kfree(image);
  1405. return error;
  1406. case SIOCRRID:
  1407. return put_user(0x52523032, (int __user *)rq->ifr_data);
  1408. default:
  1409. return error;
  1410. }
  1411. }
  1412. static DEFINE_PCI_DEVICE_TABLE(rr_pci_tbl) = {
  1413. { PCI_VENDOR_ID_ESSENTIAL, PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER,
  1414. PCI_ANY_ID, PCI_ANY_ID, },
  1415. { 0,}
  1416. };
  1417. MODULE_DEVICE_TABLE(pci, rr_pci_tbl);
  1418. static struct pci_driver rr_driver = {
  1419. .name = "rrunner",
  1420. .id_table = rr_pci_tbl,
  1421. .probe = rr_init_one,
  1422. .remove = rr_remove_one,
  1423. };
  1424. module_pci_driver(rr_driver);