siena_sriov.c 45 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare network controllers and boards
  3. * Copyright 2010-2012 Solarflare Communications Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published
  7. * by the Free Software Foundation, incorporated herein by reference.
  8. */
  9. #include <linux/pci.h>
  10. #include <linux/module.h>
  11. #include "net_driver.h"
  12. #include "efx.h"
  13. #include "nic.h"
  14. #include "io.h"
  15. #include "mcdi.h"
  16. #include "filter.h"
  17. #include "mcdi_pcol.h"
  18. #include "farch_regs.h"
  19. #include "vfdi.h"
  20. /* Number of longs required to track all the VIs in a VF */
  21. #define VI_MASK_LENGTH BITS_TO_LONGS(1 << EFX_VI_SCALE_MAX)
  22. /* Maximum number of RX queues supported */
  23. #define VF_MAX_RX_QUEUES 63
  24. /**
  25. * enum efx_vf_tx_filter_mode - TX MAC filtering behaviour
  26. * @VF_TX_FILTER_OFF: Disabled
  27. * @VF_TX_FILTER_AUTO: Enabled if MAC address assigned to VF and only
  28. * 2 TX queues allowed per VF.
  29. * @VF_TX_FILTER_ON: Enabled
  30. */
  31. enum efx_vf_tx_filter_mode {
  32. VF_TX_FILTER_OFF,
  33. VF_TX_FILTER_AUTO,
  34. VF_TX_FILTER_ON,
  35. };
  36. /**
  37. * struct efx_vf - Back-end resource and protocol state for a PCI VF
  38. * @efx: The Efx NIC owning this VF
  39. * @pci_rid: The PCI requester ID for this VF
  40. * @pci_name: The PCI name (formatted address) of this VF
  41. * @index: Index of VF within its port and PF.
  42. * @req: VFDI incoming request work item. Incoming USR_EV events are received
  43. * by the NAPI handler, but must be handled by executing MCDI requests
  44. * inside a work item.
  45. * @req_addr: VFDI incoming request DMA address (in VF's PCI address space).
  46. * @req_type: Expected next incoming (from VF) %VFDI_EV_TYPE member.
  47. * @req_seqno: Expected next incoming (from VF) %VFDI_EV_SEQ member.
  48. * @msg_seqno: Next %VFDI_EV_SEQ member to reply to VF. Protected by
  49. * @status_lock
  50. * @busy: VFDI request queued to be processed or being processed. Receiving
  51. * a VFDI request when @busy is set is an error condition.
  52. * @buf: Incoming VFDI requests are DMA from the VF into this buffer.
  53. * @buftbl_base: Buffer table entries for this VF start at this index.
  54. * @rx_filtering: Receive filtering has been requested by the VF driver.
  55. * @rx_filter_flags: The flags sent in the %VFDI_OP_INSERT_FILTER request.
  56. * @rx_filter_qid: VF relative qid for RX filter requested by VF.
  57. * @rx_filter_id: Receive MAC filter ID. Only one filter per VF is supported.
  58. * @tx_filter_mode: Transmit MAC filtering mode.
  59. * @tx_filter_id: Transmit MAC filter ID.
  60. * @addr: The MAC address and outer vlan tag of the VF.
  61. * @status_addr: VF DMA address of page for &struct vfdi_status updates.
  62. * @status_lock: Mutex protecting @msg_seqno, @status_addr, @addr,
  63. * @peer_page_addrs and @peer_page_count from simultaneous
  64. * updates by the VM and consumption by
  65. * efx_sriov_update_vf_addr()
  66. * @peer_page_addrs: Pointer to an array of guest pages for local addresses.
  67. * @peer_page_count: Number of entries in @peer_page_count.
  68. * @evq0_addrs: Array of guest pages backing evq0.
  69. * @evq0_count: Number of entries in @evq0_addrs.
  70. * @flush_waitq: wait queue used by %VFDI_OP_FINI_ALL_QUEUES handler
  71. * to wait for flush completions.
  72. * @txq_lock: Mutex for TX queue allocation.
  73. * @txq_mask: Mask of initialized transmit queues.
  74. * @txq_count: Number of initialized transmit queues.
  75. * @rxq_mask: Mask of initialized receive queues.
  76. * @rxq_count: Number of initialized receive queues.
  77. * @rxq_retry_mask: Mask or receive queues that need to be flushed again
  78. * due to flush failure.
  79. * @rxq_retry_count: Number of receive queues in @rxq_retry_mask.
  80. * @reset_work: Work item to schedule a VF reset.
  81. */
  82. struct efx_vf {
  83. struct efx_nic *efx;
  84. unsigned int pci_rid;
  85. char pci_name[13]; /* dddd:bb:dd.f */
  86. unsigned int index;
  87. struct work_struct req;
  88. u64 req_addr;
  89. int req_type;
  90. unsigned req_seqno;
  91. unsigned msg_seqno;
  92. bool busy;
  93. struct efx_buffer buf;
  94. unsigned buftbl_base;
  95. bool rx_filtering;
  96. enum efx_filter_flags rx_filter_flags;
  97. unsigned rx_filter_qid;
  98. int rx_filter_id;
  99. enum efx_vf_tx_filter_mode tx_filter_mode;
  100. int tx_filter_id;
  101. struct vfdi_endpoint addr;
  102. u64 status_addr;
  103. struct mutex status_lock;
  104. u64 *peer_page_addrs;
  105. unsigned peer_page_count;
  106. u64 evq0_addrs[EFX_MAX_VF_EVQ_SIZE * sizeof(efx_qword_t) /
  107. EFX_BUF_SIZE];
  108. unsigned evq0_count;
  109. wait_queue_head_t flush_waitq;
  110. struct mutex txq_lock;
  111. unsigned long txq_mask[VI_MASK_LENGTH];
  112. unsigned txq_count;
  113. unsigned long rxq_mask[VI_MASK_LENGTH];
  114. unsigned rxq_count;
  115. unsigned long rxq_retry_mask[VI_MASK_LENGTH];
  116. atomic_t rxq_retry_count;
  117. struct work_struct reset_work;
  118. };
  119. struct efx_memcpy_req {
  120. unsigned int from_rid;
  121. void *from_buf;
  122. u64 from_addr;
  123. unsigned int to_rid;
  124. u64 to_addr;
  125. unsigned length;
  126. };
  127. /**
  128. * struct efx_local_addr - A MAC address on the vswitch without a VF.
  129. *
  130. * Siena does not have a switch, so VFs can't transmit data to each
  131. * other. Instead the VFs must be made aware of the local addresses
  132. * on the vswitch, so that they can arrange for an alternative
  133. * software datapath to be used.
  134. *
  135. * @link: List head for insertion into efx->local_addr_list.
  136. * @addr: Ethernet address
  137. */
  138. struct efx_local_addr {
  139. struct list_head link;
  140. u8 addr[ETH_ALEN];
  141. };
  142. /**
  143. * struct efx_endpoint_page - Page of vfdi_endpoint structures
  144. *
  145. * @link: List head for insertion into efx->local_page_list.
  146. * @ptr: Pointer to page.
  147. * @addr: DMA address of page.
  148. */
  149. struct efx_endpoint_page {
  150. struct list_head link;
  151. void *ptr;
  152. dma_addr_t addr;
  153. };
  154. /* Buffer table entries are reserved txq0,rxq0,evq0,txq1,rxq1,evq1 */
  155. #define EFX_BUFTBL_TXQ_BASE(_vf, _qid) \
  156. ((_vf)->buftbl_base + EFX_VF_BUFTBL_PER_VI * (_qid))
  157. #define EFX_BUFTBL_RXQ_BASE(_vf, _qid) \
  158. (EFX_BUFTBL_TXQ_BASE(_vf, _qid) + \
  159. (EFX_MAX_DMAQ_SIZE * sizeof(efx_qword_t) / EFX_BUF_SIZE))
  160. #define EFX_BUFTBL_EVQ_BASE(_vf, _qid) \
  161. (EFX_BUFTBL_TXQ_BASE(_vf, _qid) + \
  162. (2 * EFX_MAX_DMAQ_SIZE * sizeof(efx_qword_t) / EFX_BUF_SIZE))
  163. #define EFX_FIELD_MASK(_field) \
  164. ((1 << _field ## _WIDTH) - 1)
  165. /* VFs can only use this many transmit channels */
  166. static unsigned int vf_max_tx_channels = 2;
  167. module_param(vf_max_tx_channels, uint, 0444);
  168. MODULE_PARM_DESC(vf_max_tx_channels,
  169. "Limit the number of TX channels VFs can use");
  170. static int max_vfs = -1;
  171. module_param(max_vfs, int, 0444);
  172. MODULE_PARM_DESC(max_vfs,
  173. "Reduce the number of VFs initialized by the driver");
  174. /* Workqueue used by VFDI communication. We can't use the global
  175. * workqueue because it may be running the VF driver's probe()
  176. * routine, which will be blocked there waiting for a VFDI response.
  177. */
  178. static struct workqueue_struct *vfdi_workqueue;
  179. static unsigned abs_index(struct efx_vf *vf, unsigned index)
  180. {
  181. return EFX_VI_BASE + vf->index * efx_vf_size(vf->efx) + index;
  182. }
  183. static int efx_sriov_cmd(struct efx_nic *efx, bool enable,
  184. unsigned *vi_scale_out, unsigned *vf_total_out)
  185. {
  186. MCDI_DECLARE_BUF(inbuf, MC_CMD_SRIOV_IN_LEN);
  187. MCDI_DECLARE_BUF(outbuf, MC_CMD_SRIOV_OUT_LEN);
  188. unsigned vi_scale, vf_total;
  189. size_t outlen;
  190. int rc;
  191. MCDI_SET_DWORD(inbuf, SRIOV_IN_ENABLE, enable ? 1 : 0);
  192. MCDI_SET_DWORD(inbuf, SRIOV_IN_VI_BASE, EFX_VI_BASE);
  193. MCDI_SET_DWORD(inbuf, SRIOV_IN_VF_COUNT, efx->vf_count);
  194. rc = efx_mcdi_rpc(efx, MC_CMD_SRIOV, inbuf, MC_CMD_SRIOV_IN_LEN,
  195. outbuf, MC_CMD_SRIOV_OUT_LEN, &outlen);
  196. if (rc)
  197. return rc;
  198. if (outlen < MC_CMD_SRIOV_OUT_LEN)
  199. return -EIO;
  200. vf_total = MCDI_DWORD(outbuf, SRIOV_OUT_VF_TOTAL);
  201. vi_scale = MCDI_DWORD(outbuf, SRIOV_OUT_VI_SCALE);
  202. if (vi_scale > EFX_VI_SCALE_MAX)
  203. return -EOPNOTSUPP;
  204. if (vi_scale_out)
  205. *vi_scale_out = vi_scale;
  206. if (vf_total_out)
  207. *vf_total_out = vf_total;
  208. return 0;
  209. }
  210. static void efx_sriov_usrev(struct efx_nic *efx, bool enabled)
  211. {
  212. efx_oword_t reg;
  213. EFX_POPULATE_OWORD_2(reg,
  214. FRF_CZ_USREV_DIS, enabled ? 0 : 1,
  215. FRF_CZ_DFLT_EVQ, efx->vfdi_channel->channel);
  216. efx_writeo(efx, &reg, FR_CZ_USR_EV_CFG);
  217. }
  218. static int efx_sriov_memcpy(struct efx_nic *efx, struct efx_memcpy_req *req,
  219. unsigned int count)
  220. {
  221. MCDI_DECLARE_BUF(inbuf, MCDI_CTL_SDU_LEN_MAX_V1);
  222. MCDI_DECLARE_STRUCT_PTR(record);
  223. unsigned int index, used;
  224. u64 from_addr;
  225. u32 from_rid;
  226. int rc;
  227. mb(); /* Finish writing source/reading dest before DMA starts */
  228. if (WARN_ON(count > MC_CMD_MEMCPY_IN_RECORD_MAXNUM))
  229. return -ENOBUFS;
  230. used = MC_CMD_MEMCPY_IN_LEN(count);
  231. for (index = 0; index < count; index++) {
  232. record = MCDI_ARRAY_STRUCT_PTR(inbuf, MEMCPY_IN_RECORD, index);
  233. MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_NUM_RECORDS,
  234. count);
  235. MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_TO_RID,
  236. req->to_rid);
  237. MCDI_SET_QWORD(record, MEMCPY_RECORD_TYPEDEF_TO_ADDR,
  238. req->to_addr);
  239. if (req->from_buf == NULL) {
  240. from_rid = req->from_rid;
  241. from_addr = req->from_addr;
  242. } else {
  243. if (WARN_ON(used + req->length >
  244. MCDI_CTL_SDU_LEN_MAX_V1)) {
  245. rc = -ENOBUFS;
  246. goto out;
  247. }
  248. from_rid = MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE;
  249. from_addr = used;
  250. memcpy(_MCDI_PTR(inbuf, used), req->from_buf,
  251. req->length);
  252. used += req->length;
  253. }
  254. MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_FROM_RID, from_rid);
  255. MCDI_SET_QWORD(record, MEMCPY_RECORD_TYPEDEF_FROM_ADDR,
  256. from_addr);
  257. MCDI_SET_DWORD(record, MEMCPY_RECORD_TYPEDEF_LENGTH,
  258. req->length);
  259. ++req;
  260. }
  261. rc = efx_mcdi_rpc(efx, MC_CMD_MEMCPY, inbuf, used, NULL, 0, NULL);
  262. out:
  263. mb(); /* Don't write source/read dest before DMA is complete */
  264. return rc;
  265. }
  266. /* The TX filter is entirely controlled by this driver, and is modified
  267. * underneath the feet of the VF
  268. */
  269. static void efx_sriov_reset_tx_filter(struct efx_vf *vf)
  270. {
  271. struct efx_nic *efx = vf->efx;
  272. struct efx_filter_spec filter;
  273. u16 vlan;
  274. int rc;
  275. if (vf->tx_filter_id != -1) {
  276. efx_filter_remove_id_safe(efx, EFX_FILTER_PRI_REQUIRED,
  277. vf->tx_filter_id);
  278. netif_dbg(efx, hw, efx->net_dev, "Removed vf %s tx filter %d\n",
  279. vf->pci_name, vf->tx_filter_id);
  280. vf->tx_filter_id = -1;
  281. }
  282. if (is_zero_ether_addr(vf->addr.mac_addr))
  283. return;
  284. /* Turn on TX filtering automatically if not explicitly
  285. * enabled or disabled.
  286. */
  287. if (vf->tx_filter_mode == VF_TX_FILTER_AUTO && vf_max_tx_channels <= 2)
  288. vf->tx_filter_mode = VF_TX_FILTER_ON;
  289. vlan = ntohs(vf->addr.tci) & VLAN_VID_MASK;
  290. efx_filter_init_tx(&filter, abs_index(vf, 0));
  291. rc = efx_filter_set_eth_local(&filter,
  292. vlan ? vlan : EFX_FILTER_VID_UNSPEC,
  293. vf->addr.mac_addr);
  294. BUG_ON(rc);
  295. rc = efx_filter_insert_filter(efx, &filter, true);
  296. if (rc < 0) {
  297. netif_warn(efx, hw, efx->net_dev,
  298. "Unable to migrate tx filter for vf %s\n",
  299. vf->pci_name);
  300. } else {
  301. netif_dbg(efx, hw, efx->net_dev, "Inserted vf %s tx filter %d\n",
  302. vf->pci_name, rc);
  303. vf->tx_filter_id = rc;
  304. }
  305. }
  306. /* The RX filter is managed here on behalf of the VF driver */
  307. static void efx_sriov_reset_rx_filter(struct efx_vf *vf)
  308. {
  309. struct efx_nic *efx = vf->efx;
  310. struct efx_filter_spec filter;
  311. u16 vlan;
  312. int rc;
  313. if (vf->rx_filter_id != -1) {
  314. efx_filter_remove_id_safe(efx, EFX_FILTER_PRI_REQUIRED,
  315. vf->rx_filter_id);
  316. netif_dbg(efx, hw, efx->net_dev, "Removed vf %s rx filter %d\n",
  317. vf->pci_name, vf->rx_filter_id);
  318. vf->rx_filter_id = -1;
  319. }
  320. if (!vf->rx_filtering || is_zero_ether_addr(vf->addr.mac_addr))
  321. return;
  322. vlan = ntohs(vf->addr.tci) & VLAN_VID_MASK;
  323. efx_filter_init_rx(&filter, EFX_FILTER_PRI_REQUIRED,
  324. vf->rx_filter_flags,
  325. abs_index(vf, vf->rx_filter_qid));
  326. rc = efx_filter_set_eth_local(&filter,
  327. vlan ? vlan : EFX_FILTER_VID_UNSPEC,
  328. vf->addr.mac_addr);
  329. BUG_ON(rc);
  330. rc = efx_filter_insert_filter(efx, &filter, true);
  331. if (rc < 0) {
  332. netif_warn(efx, hw, efx->net_dev,
  333. "Unable to insert rx filter for vf %s\n",
  334. vf->pci_name);
  335. } else {
  336. netif_dbg(efx, hw, efx->net_dev, "Inserted vf %s rx filter %d\n",
  337. vf->pci_name, rc);
  338. vf->rx_filter_id = rc;
  339. }
  340. }
  341. static void __efx_sriov_update_vf_addr(struct efx_vf *vf)
  342. {
  343. efx_sriov_reset_tx_filter(vf);
  344. efx_sriov_reset_rx_filter(vf);
  345. queue_work(vfdi_workqueue, &vf->efx->peer_work);
  346. }
  347. /* Push the peer list to this VF. The caller must hold status_lock to interlock
  348. * with VFDI requests, and they must be serialised against manipulation of
  349. * local_page_list, either by acquiring local_lock or by running from
  350. * efx_sriov_peer_work()
  351. */
  352. static void __efx_sriov_push_vf_status(struct efx_vf *vf)
  353. {
  354. struct efx_nic *efx = vf->efx;
  355. struct vfdi_status *status = efx->vfdi_status.addr;
  356. struct efx_memcpy_req copy[4];
  357. struct efx_endpoint_page *epp;
  358. unsigned int pos, count;
  359. unsigned data_offset;
  360. efx_qword_t event;
  361. WARN_ON(!mutex_is_locked(&vf->status_lock));
  362. WARN_ON(!vf->status_addr);
  363. status->local = vf->addr;
  364. status->generation_end = ++status->generation_start;
  365. memset(copy, '\0', sizeof(copy));
  366. /* Write generation_start */
  367. copy[0].from_buf = &status->generation_start;
  368. copy[0].to_rid = vf->pci_rid;
  369. copy[0].to_addr = vf->status_addr + offsetof(struct vfdi_status,
  370. generation_start);
  371. copy[0].length = sizeof(status->generation_start);
  372. /* DMA the rest of the structure (excluding the generations). This
  373. * assumes that the non-generation portion of vfdi_status is in
  374. * one chunk starting at the version member.
  375. */
  376. data_offset = offsetof(struct vfdi_status, version);
  377. copy[1].from_rid = efx->pci_dev->devfn;
  378. copy[1].from_addr = efx->vfdi_status.dma_addr + data_offset;
  379. copy[1].to_rid = vf->pci_rid;
  380. copy[1].to_addr = vf->status_addr + data_offset;
  381. copy[1].length = status->length - data_offset;
  382. /* Copy the peer pages */
  383. pos = 2;
  384. count = 0;
  385. list_for_each_entry(epp, &efx->local_page_list, link) {
  386. if (count == vf->peer_page_count) {
  387. /* The VF driver will know they need to provide more
  388. * pages because peer_addr_count is too large.
  389. */
  390. break;
  391. }
  392. copy[pos].from_buf = NULL;
  393. copy[pos].from_rid = efx->pci_dev->devfn;
  394. copy[pos].from_addr = epp->addr;
  395. copy[pos].to_rid = vf->pci_rid;
  396. copy[pos].to_addr = vf->peer_page_addrs[count];
  397. copy[pos].length = EFX_PAGE_SIZE;
  398. if (++pos == ARRAY_SIZE(copy)) {
  399. efx_sriov_memcpy(efx, copy, ARRAY_SIZE(copy));
  400. pos = 0;
  401. }
  402. ++count;
  403. }
  404. /* Write generation_end */
  405. copy[pos].from_buf = &status->generation_end;
  406. copy[pos].to_rid = vf->pci_rid;
  407. copy[pos].to_addr = vf->status_addr + offsetof(struct vfdi_status,
  408. generation_end);
  409. copy[pos].length = sizeof(status->generation_end);
  410. efx_sriov_memcpy(efx, copy, pos + 1);
  411. /* Notify the guest */
  412. EFX_POPULATE_QWORD_3(event,
  413. FSF_AZ_EV_CODE, FSE_CZ_EV_CODE_USER_EV,
  414. VFDI_EV_SEQ, (vf->msg_seqno & 0xff),
  415. VFDI_EV_TYPE, VFDI_EV_TYPE_STATUS);
  416. ++vf->msg_seqno;
  417. efx_farch_generate_event(efx,
  418. EFX_VI_BASE + vf->index * efx_vf_size(efx),
  419. &event);
  420. }
  421. static void efx_sriov_bufs(struct efx_nic *efx, unsigned offset,
  422. u64 *addr, unsigned count)
  423. {
  424. efx_qword_t buf;
  425. unsigned pos;
  426. for (pos = 0; pos < count; ++pos) {
  427. EFX_POPULATE_QWORD_3(buf,
  428. FRF_AZ_BUF_ADR_REGION, 0,
  429. FRF_AZ_BUF_ADR_FBUF,
  430. addr ? addr[pos] >> 12 : 0,
  431. FRF_AZ_BUF_OWNER_ID_FBUF, 0);
  432. efx_sram_writeq(efx, efx->membase + FR_BZ_BUF_FULL_TBL,
  433. &buf, offset + pos);
  434. }
  435. }
  436. static bool bad_vf_index(struct efx_nic *efx, unsigned index)
  437. {
  438. return index >= efx_vf_size(efx);
  439. }
  440. static bool bad_buf_count(unsigned buf_count, unsigned max_entry_count)
  441. {
  442. unsigned max_buf_count = max_entry_count *
  443. sizeof(efx_qword_t) / EFX_BUF_SIZE;
  444. return ((buf_count & (buf_count - 1)) || buf_count > max_buf_count);
  445. }
  446. /* Check that VI specified by per-port index belongs to a VF.
  447. * Optionally set VF index and VI index within the VF.
  448. */
  449. static bool map_vi_index(struct efx_nic *efx, unsigned abs_index,
  450. struct efx_vf **vf_out, unsigned *rel_index_out)
  451. {
  452. unsigned vf_i;
  453. if (abs_index < EFX_VI_BASE)
  454. return true;
  455. vf_i = (abs_index - EFX_VI_BASE) / efx_vf_size(efx);
  456. if (vf_i >= efx->vf_init_count)
  457. return true;
  458. if (vf_out)
  459. *vf_out = efx->vf + vf_i;
  460. if (rel_index_out)
  461. *rel_index_out = abs_index % efx_vf_size(efx);
  462. return false;
  463. }
  464. static int efx_vfdi_init_evq(struct efx_vf *vf)
  465. {
  466. struct efx_nic *efx = vf->efx;
  467. struct vfdi_req *req = vf->buf.addr;
  468. unsigned vf_evq = req->u.init_evq.index;
  469. unsigned buf_count = req->u.init_evq.buf_count;
  470. unsigned abs_evq = abs_index(vf, vf_evq);
  471. unsigned buftbl = EFX_BUFTBL_EVQ_BASE(vf, vf_evq);
  472. efx_oword_t reg;
  473. if (bad_vf_index(efx, vf_evq) ||
  474. bad_buf_count(buf_count, EFX_MAX_VF_EVQ_SIZE)) {
  475. if (net_ratelimit())
  476. netif_err(efx, hw, efx->net_dev,
  477. "ERROR: Invalid INIT_EVQ from %s: evq %d bufs %d\n",
  478. vf->pci_name, vf_evq, buf_count);
  479. return VFDI_RC_EINVAL;
  480. }
  481. efx_sriov_bufs(efx, buftbl, req->u.init_evq.addr, buf_count);
  482. EFX_POPULATE_OWORD_3(reg,
  483. FRF_CZ_TIMER_Q_EN, 1,
  484. FRF_CZ_HOST_NOTIFY_MODE, 0,
  485. FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
  486. efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, abs_evq);
  487. EFX_POPULATE_OWORD_3(reg,
  488. FRF_AZ_EVQ_EN, 1,
  489. FRF_AZ_EVQ_SIZE, __ffs(buf_count),
  490. FRF_AZ_EVQ_BUF_BASE_ID, buftbl);
  491. efx_writeo_table(efx, &reg, FR_BZ_EVQ_PTR_TBL, abs_evq);
  492. if (vf_evq == 0) {
  493. memcpy(vf->evq0_addrs, req->u.init_evq.addr,
  494. buf_count * sizeof(u64));
  495. vf->evq0_count = buf_count;
  496. }
  497. return VFDI_RC_SUCCESS;
  498. }
  499. static int efx_vfdi_init_rxq(struct efx_vf *vf)
  500. {
  501. struct efx_nic *efx = vf->efx;
  502. struct vfdi_req *req = vf->buf.addr;
  503. unsigned vf_rxq = req->u.init_rxq.index;
  504. unsigned vf_evq = req->u.init_rxq.evq;
  505. unsigned buf_count = req->u.init_rxq.buf_count;
  506. unsigned buftbl = EFX_BUFTBL_RXQ_BASE(vf, vf_rxq);
  507. unsigned label;
  508. efx_oword_t reg;
  509. if (bad_vf_index(efx, vf_evq) || bad_vf_index(efx, vf_rxq) ||
  510. vf_rxq >= VF_MAX_RX_QUEUES ||
  511. bad_buf_count(buf_count, EFX_MAX_DMAQ_SIZE)) {
  512. if (net_ratelimit())
  513. netif_err(efx, hw, efx->net_dev,
  514. "ERROR: Invalid INIT_RXQ from %s: rxq %d evq %d "
  515. "buf_count %d\n", vf->pci_name, vf_rxq,
  516. vf_evq, buf_count);
  517. return VFDI_RC_EINVAL;
  518. }
  519. if (__test_and_set_bit(req->u.init_rxq.index, vf->rxq_mask))
  520. ++vf->rxq_count;
  521. efx_sriov_bufs(efx, buftbl, req->u.init_rxq.addr, buf_count);
  522. label = req->u.init_rxq.label & EFX_FIELD_MASK(FRF_AZ_RX_DESCQ_LABEL);
  523. EFX_POPULATE_OWORD_6(reg,
  524. FRF_AZ_RX_DESCQ_BUF_BASE_ID, buftbl,
  525. FRF_AZ_RX_DESCQ_EVQ_ID, abs_index(vf, vf_evq),
  526. FRF_AZ_RX_DESCQ_LABEL, label,
  527. FRF_AZ_RX_DESCQ_SIZE, __ffs(buf_count),
  528. FRF_AZ_RX_DESCQ_JUMBO,
  529. !!(req->u.init_rxq.flags &
  530. VFDI_RXQ_FLAG_SCATTER_EN),
  531. FRF_AZ_RX_DESCQ_EN, 1);
  532. efx_writeo_table(efx, &reg, FR_BZ_RX_DESC_PTR_TBL,
  533. abs_index(vf, vf_rxq));
  534. return VFDI_RC_SUCCESS;
  535. }
  536. static int efx_vfdi_init_txq(struct efx_vf *vf)
  537. {
  538. struct efx_nic *efx = vf->efx;
  539. struct vfdi_req *req = vf->buf.addr;
  540. unsigned vf_txq = req->u.init_txq.index;
  541. unsigned vf_evq = req->u.init_txq.evq;
  542. unsigned buf_count = req->u.init_txq.buf_count;
  543. unsigned buftbl = EFX_BUFTBL_TXQ_BASE(vf, vf_txq);
  544. unsigned label, eth_filt_en;
  545. efx_oword_t reg;
  546. if (bad_vf_index(efx, vf_evq) || bad_vf_index(efx, vf_txq) ||
  547. vf_txq >= vf_max_tx_channels ||
  548. bad_buf_count(buf_count, EFX_MAX_DMAQ_SIZE)) {
  549. if (net_ratelimit())
  550. netif_err(efx, hw, efx->net_dev,
  551. "ERROR: Invalid INIT_TXQ from %s: txq %d evq %d "
  552. "buf_count %d\n", vf->pci_name, vf_txq,
  553. vf_evq, buf_count);
  554. return VFDI_RC_EINVAL;
  555. }
  556. mutex_lock(&vf->txq_lock);
  557. if (__test_and_set_bit(req->u.init_txq.index, vf->txq_mask))
  558. ++vf->txq_count;
  559. mutex_unlock(&vf->txq_lock);
  560. efx_sriov_bufs(efx, buftbl, req->u.init_txq.addr, buf_count);
  561. eth_filt_en = vf->tx_filter_mode == VF_TX_FILTER_ON;
  562. label = req->u.init_txq.label & EFX_FIELD_MASK(FRF_AZ_TX_DESCQ_LABEL);
  563. EFX_POPULATE_OWORD_8(reg,
  564. FRF_CZ_TX_DPT_Q_MASK_WIDTH, min(efx->vi_scale, 1U),
  565. FRF_CZ_TX_DPT_ETH_FILT_EN, eth_filt_en,
  566. FRF_AZ_TX_DESCQ_EN, 1,
  567. FRF_AZ_TX_DESCQ_BUF_BASE_ID, buftbl,
  568. FRF_AZ_TX_DESCQ_EVQ_ID, abs_index(vf, vf_evq),
  569. FRF_AZ_TX_DESCQ_LABEL, label,
  570. FRF_AZ_TX_DESCQ_SIZE, __ffs(buf_count),
  571. FRF_BZ_TX_NON_IP_DROP_DIS, 1);
  572. efx_writeo_table(efx, &reg, FR_BZ_TX_DESC_PTR_TBL,
  573. abs_index(vf, vf_txq));
  574. return VFDI_RC_SUCCESS;
  575. }
  576. /* Returns true when efx_vfdi_fini_all_queues should wake */
  577. static bool efx_vfdi_flush_wake(struct efx_vf *vf)
  578. {
  579. /* Ensure that all updates are visible to efx_vfdi_fini_all_queues() */
  580. smp_mb();
  581. return (!vf->txq_count && !vf->rxq_count) ||
  582. atomic_read(&vf->rxq_retry_count);
  583. }
  584. static void efx_vfdi_flush_clear(struct efx_vf *vf)
  585. {
  586. memset(vf->txq_mask, 0, sizeof(vf->txq_mask));
  587. vf->txq_count = 0;
  588. memset(vf->rxq_mask, 0, sizeof(vf->rxq_mask));
  589. vf->rxq_count = 0;
  590. memset(vf->rxq_retry_mask, 0, sizeof(vf->rxq_retry_mask));
  591. atomic_set(&vf->rxq_retry_count, 0);
  592. }
  593. static int efx_vfdi_fini_all_queues(struct efx_vf *vf)
  594. {
  595. struct efx_nic *efx = vf->efx;
  596. efx_oword_t reg;
  597. unsigned count = efx_vf_size(efx);
  598. unsigned vf_offset = EFX_VI_BASE + vf->index * efx_vf_size(efx);
  599. unsigned timeout = HZ;
  600. unsigned index, rxqs_count;
  601. MCDI_DECLARE_BUF(inbuf, MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX);
  602. int rc;
  603. BUILD_BUG_ON(VF_MAX_RX_QUEUES >
  604. MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM);
  605. rtnl_lock();
  606. siena_prepare_flush(efx);
  607. rtnl_unlock();
  608. /* Flush all the initialized queues */
  609. rxqs_count = 0;
  610. for (index = 0; index < count; ++index) {
  611. if (test_bit(index, vf->txq_mask)) {
  612. EFX_POPULATE_OWORD_2(reg,
  613. FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
  614. FRF_AZ_TX_FLUSH_DESCQ,
  615. vf_offset + index);
  616. efx_writeo(efx, &reg, FR_AZ_TX_FLUSH_DESCQ);
  617. }
  618. if (test_bit(index, vf->rxq_mask)) {
  619. MCDI_SET_ARRAY_DWORD(
  620. inbuf, FLUSH_RX_QUEUES_IN_QID_OFST,
  621. rxqs_count, vf_offset + index);
  622. rxqs_count++;
  623. }
  624. }
  625. atomic_set(&vf->rxq_retry_count, 0);
  626. while (timeout && (vf->rxq_count || vf->txq_count)) {
  627. rc = efx_mcdi_rpc(efx, MC_CMD_FLUSH_RX_QUEUES, inbuf,
  628. MC_CMD_FLUSH_RX_QUEUES_IN_LEN(rxqs_count),
  629. NULL, 0, NULL);
  630. WARN_ON(rc < 0);
  631. timeout = wait_event_timeout(vf->flush_waitq,
  632. efx_vfdi_flush_wake(vf),
  633. timeout);
  634. rxqs_count = 0;
  635. for (index = 0; index < count; ++index) {
  636. if (test_and_clear_bit(index, vf->rxq_retry_mask)) {
  637. atomic_dec(&vf->rxq_retry_count);
  638. MCDI_SET_ARRAY_DWORD(
  639. inbuf, FLUSH_RX_QUEUES_IN_QID_OFST,
  640. rxqs_count, vf_offset + index);
  641. rxqs_count++;
  642. }
  643. }
  644. }
  645. rtnl_lock();
  646. siena_finish_flush(efx);
  647. rtnl_unlock();
  648. /* Irrespective of success/failure, fini the queues */
  649. EFX_ZERO_OWORD(reg);
  650. for (index = 0; index < count; ++index) {
  651. efx_writeo_table(efx, &reg, FR_BZ_RX_DESC_PTR_TBL,
  652. vf_offset + index);
  653. efx_writeo_table(efx, &reg, FR_BZ_TX_DESC_PTR_TBL,
  654. vf_offset + index);
  655. efx_writeo_table(efx, &reg, FR_BZ_EVQ_PTR_TBL,
  656. vf_offset + index);
  657. efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL,
  658. vf_offset + index);
  659. }
  660. efx_sriov_bufs(efx, vf->buftbl_base, NULL,
  661. EFX_VF_BUFTBL_PER_VI * efx_vf_size(efx));
  662. efx_vfdi_flush_clear(vf);
  663. vf->evq0_count = 0;
  664. return timeout ? 0 : VFDI_RC_ETIMEDOUT;
  665. }
  666. static int efx_vfdi_insert_filter(struct efx_vf *vf)
  667. {
  668. struct efx_nic *efx = vf->efx;
  669. struct vfdi_req *req = vf->buf.addr;
  670. unsigned vf_rxq = req->u.mac_filter.rxq;
  671. unsigned flags;
  672. if (bad_vf_index(efx, vf_rxq) || vf->rx_filtering) {
  673. if (net_ratelimit())
  674. netif_err(efx, hw, efx->net_dev,
  675. "ERROR: Invalid INSERT_FILTER from %s: rxq %d "
  676. "flags 0x%x\n", vf->pci_name, vf_rxq,
  677. req->u.mac_filter.flags);
  678. return VFDI_RC_EINVAL;
  679. }
  680. flags = 0;
  681. if (req->u.mac_filter.flags & VFDI_MAC_FILTER_FLAG_RSS)
  682. flags |= EFX_FILTER_FLAG_RX_RSS;
  683. if (req->u.mac_filter.flags & VFDI_MAC_FILTER_FLAG_SCATTER)
  684. flags |= EFX_FILTER_FLAG_RX_SCATTER;
  685. vf->rx_filter_flags = flags;
  686. vf->rx_filter_qid = vf_rxq;
  687. vf->rx_filtering = true;
  688. efx_sriov_reset_rx_filter(vf);
  689. queue_work(vfdi_workqueue, &efx->peer_work);
  690. return VFDI_RC_SUCCESS;
  691. }
  692. static int efx_vfdi_remove_all_filters(struct efx_vf *vf)
  693. {
  694. vf->rx_filtering = false;
  695. efx_sriov_reset_rx_filter(vf);
  696. queue_work(vfdi_workqueue, &vf->efx->peer_work);
  697. return VFDI_RC_SUCCESS;
  698. }
  699. static int efx_vfdi_set_status_page(struct efx_vf *vf)
  700. {
  701. struct efx_nic *efx = vf->efx;
  702. struct vfdi_req *req = vf->buf.addr;
  703. u64 page_count = req->u.set_status_page.peer_page_count;
  704. u64 max_page_count =
  705. (EFX_PAGE_SIZE -
  706. offsetof(struct vfdi_req, u.set_status_page.peer_page_addr[0]))
  707. / sizeof(req->u.set_status_page.peer_page_addr[0]);
  708. if (!req->u.set_status_page.dma_addr || page_count > max_page_count) {
  709. if (net_ratelimit())
  710. netif_err(efx, hw, efx->net_dev,
  711. "ERROR: Invalid SET_STATUS_PAGE from %s\n",
  712. vf->pci_name);
  713. return VFDI_RC_EINVAL;
  714. }
  715. mutex_lock(&efx->local_lock);
  716. mutex_lock(&vf->status_lock);
  717. vf->status_addr = req->u.set_status_page.dma_addr;
  718. kfree(vf->peer_page_addrs);
  719. vf->peer_page_addrs = NULL;
  720. vf->peer_page_count = 0;
  721. if (page_count) {
  722. vf->peer_page_addrs = kcalloc(page_count, sizeof(u64),
  723. GFP_KERNEL);
  724. if (vf->peer_page_addrs) {
  725. memcpy(vf->peer_page_addrs,
  726. req->u.set_status_page.peer_page_addr,
  727. page_count * sizeof(u64));
  728. vf->peer_page_count = page_count;
  729. }
  730. }
  731. __efx_sriov_push_vf_status(vf);
  732. mutex_unlock(&vf->status_lock);
  733. mutex_unlock(&efx->local_lock);
  734. return VFDI_RC_SUCCESS;
  735. }
  736. static int efx_vfdi_clear_status_page(struct efx_vf *vf)
  737. {
  738. mutex_lock(&vf->status_lock);
  739. vf->status_addr = 0;
  740. mutex_unlock(&vf->status_lock);
  741. return VFDI_RC_SUCCESS;
  742. }
  743. typedef int (*efx_vfdi_op_t)(struct efx_vf *vf);
  744. static const efx_vfdi_op_t vfdi_ops[VFDI_OP_LIMIT] = {
  745. [VFDI_OP_INIT_EVQ] = efx_vfdi_init_evq,
  746. [VFDI_OP_INIT_TXQ] = efx_vfdi_init_txq,
  747. [VFDI_OP_INIT_RXQ] = efx_vfdi_init_rxq,
  748. [VFDI_OP_FINI_ALL_QUEUES] = efx_vfdi_fini_all_queues,
  749. [VFDI_OP_INSERT_FILTER] = efx_vfdi_insert_filter,
  750. [VFDI_OP_REMOVE_ALL_FILTERS] = efx_vfdi_remove_all_filters,
  751. [VFDI_OP_SET_STATUS_PAGE] = efx_vfdi_set_status_page,
  752. [VFDI_OP_CLEAR_STATUS_PAGE] = efx_vfdi_clear_status_page,
  753. };
  754. static void efx_sriov_vfdi(struct work_struct *work)
  755. {
  756. struct efx_vf *vf = container_of(work, struct efx_vf, req);
  757. struct efx_nic *efx = vf->efx;
  758. struct vfdi_req *req = vf->buf.addr;
  759. struct efx_memcpy_req copy[2];
  760. int rc;
  761. /* Copy this page into the local address space */
  762. memset(copy, '\0', sizeof(copy));
  763. copy[0].from_rid = vf->pci_rid;
  764. copy[0].from_addr = vf->req_addr;
  765. copy[0].to_rid = efx->pci_dev->devfn;
  766. copy[0].to_addr = vf->buf.dma_addr;
  767. copy[0].length = EFX_PAGE_SIZE;
  768. rc = efx_sriov_memcpy(efx, copy, 1);
  769. if (rc) {
  770. /* If we can't get the request, we can't reply to the caller */
  771. if (net_ratelimit())
  772. netif_err(efx, hw, efx->net_dev,
  773. "ERROR: Unable to fetch VFDI request from %s rc %d\n",
  774. vf->pci_name, -rc);
  775. vf->busy = false;
  776. return;
  777. }
  778. if (req->op < VFDI_OP_LIMIT && vfdi_ops[req->op] != NULL) {
  779. rc = vfdi_ops[req->op](vf);
  780. if (rc == 0) {
  781. netif_dbg(efx, hw, efx->net_dev,
  782. "vfdi request %d from %s ok\n",
  783. req->op, vf->pci_name);
  784. }
  785. } else {
  786. netif_dbg(efx, hw, efx->net_dev,
  787. "ERROR: Unrecognised request %d from VF %s addr "
  788. "%llx\n", req->op, vf->pci_name,
  789. (unsigned long long)vf->req_addr);
  790. rc = VFDI_RC_EOPNOTSUPP;
  791. }
  792. /* Allow subsequent VF requests */
  793. vf->busy = false;
  794. smp_wmb();
  795. /* Respond to the request */
  796. req->rc = rc;
  797. req->op = VFDI_OP_RESPONSE;
  798. memset(copy, '\0', sizeof(copy));
  799. copy[0].from_buf = &req->rc;
  800. copy[0].to_rid = vf->pci_rid;
  801. copy[0].to_addr = vf->req_addr + offsetof(struct vfdi_req, rc);
  802. copy[0].length = sizeof(req->rc);
  803. copy[1].from_buf = &req->op;
  804. copy[1].to_rid = vf->pci_rid;
  805. copy[1].to_addr = vf->req_addr + offsetof(struct vfdi_req, op);
  806. copy[1].length = sizeof(req->op);
  807. (void) efx_sriov_memcpy(efx, copy, ARRAY_SIZE(copy));
  808. }
  809. /* After a reset the event queues inside the guests no longer exist. Fill the
  810. * event ring in guest memory with VFDI reset events, then (re-initialise) the
  811. * event queue to raise an interrupt. The guest driver will then recover.
  812. */
  813. static void efx_sriov_reset_vf(struct efx_vf *vf, struct efx_buffer *buffer)
  814. {
  815. struct efx_nic *efx = vf->efx;
  816. struct efx_memcpy_req copy_req[4];
  817. efx_qword_t event;
  818. unsigned int pos, count, k, buftbl, abs_evq;
  819. efx_oword_t reg;
  820. efx_dword_t ptr;
  821. int rc;
  822. BUG_ON(buffer->len != EFX_PAGE_SIZE);
  823. if (!vf->evq0_count)
  824. return;
  825. BUG_ON(vf->evq0_count & (vf->evq0_count - 1));
  826. mutex_lock(&vf->status_lock);
  827. EFX_POPULATE_QWORD_3(event,
  828. FSF_AZ_EV_CODE, FSE_CZ_EV_CODE_USER_EV,
  829. VFDI_EV_SEQ, vf->msg_seqno,
  830. VFDI_EV_TYPE, VFDI_EV_TYPE_RESET);
  831. vf->msg_seqno++;
  832. for (pos = 0; pos < EFX_PAGE_SIZE; pos += sizeof(event))
  833. memcpy(buffer->addr + pos, &event, sizeof(event));
  834. for (pos = 0; pos < vf->evq0_count; pos += count) {
  835. count = min_t(unsigned, vf->evq0_count - pos,
  836. ARRAY_SIZE(copy_req));
  837. for (k = 0; k < count; k++) {
  838. copy_req[k].from_buf = NULL;
  839. copy_req[k].from_rid = efx->pci_dev->devfn;
  840. copy_req[k].from_addr = buffer->dma_addr;
  841. copy_req[k].to_rid = vf->pci_rid;
  842. copy_req[k].to_addr = vf->evq0_addrs[pos + k];
  843. copy_req[k].length = EFX_PAGE_SIZE;
  844. }
  845. rc = efx_sriov_memcpy(efx, copy_req, count);
  846. if (rc) {
  847. if (net_ratelimit())
  848. netif_err(efx, hw, efx->net_dev,
  849. "ERROR: Unable to notify %s of reset"
  850. ": %d\n", vf->pci_name, -rc);
  851. break;
  852. }
  853. }
  854. /* Reinitialise, arm and trigger evq0 */
  855. abs_evq = abs_index(vf, 0);
  856. buftbl = EFX_BUFTBL_EVQ_BASE(vf, 0);
  857. efx_sriov_bufs(efx, buftbl, vf->evq0_addrs, vf->evq0_count);
  858. EFX_POPULATE_OWORD_3(reg,
  859. FRF_CZ_TIMER_Q_EN, 1,
  860. FRF_CZ_HOST_NOTIFY_MODE, 0,
  861. FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
  862. efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, abs_evq);
  863. EFX_POPULATE_OWORD_3(reg,
  864. FRF_AZ_EVQ_EN, 1,
  865. FRF_AZ_EVQ_SIZE, __ffs(vf->evq0_count),
  866. FRF_AZ_EVQ_BUF_BASE_ID, buftbl);
  867. efx_writeo_table(efx, &reg, FR_BZ_EVQ_PTR_TBL, abs_evq);
  868. EFX_POPULATE_DWORD_1(ptr, FRF_AZ_EVQ_RPTR, 0);
  869. efx_writed(efx, &ptr, FR_BZ_EVQ_RPTR + FR_BZ_EVQ_RPTR_STEP * abs_evq);
  870. mutex_unlock(&vf->status_lock);
  871. }
  872. static void efx_sriov_reset_vf_work(struct work_struct *work)
  873. {
  874. struct efx_vf *vf = container_of(work, struct efx_vf, req);
  875. struct efx_nic *efx = vf->efx;
  876. struct efx_buffer buf;
  877. if (!efx_nic_alloc_buffer(efx, &buf, EFX_PAGE_SIZE, GFP_NOIO)) {
  878. efx_sriov_reset_vf(vf, &buf);
  879. efx_nic_free_buffer(efx, &buf);
  880. }
  881. }
  882. static void efx_sriov_handle_no_channel(struct efx_nic *efx)
  883. {
  884. netif_err(efx, drv, efx->net_dev,
  885. "ERROR: IOV requires MSI-X and 1 additional interrupt"
  886. "vector. IOV disabled\n");
  887. efx->vf_count = 0;
  888. }
  889. static int efx_sriov_probe_channel(struct efx_channel *channel)
  890. {
  891. channel->efx->vfdi_channel = channel;
  892. return 0;
  893. }
  894. static void
  895. efx_sriov_get_channel_name(struct efx_channel *channel, char *buf, size_t len)
  896. {
  897. snprintf(buf, len, "%s-iov", channel->efx->name);
  898. }
  899. static const struct efx_channel_type efx_sriov_channel_type = {
  900. .handle_no_channel = efx_sriov_handle_no_channel,
  901. .pre_probe = efx_sriov_probe_channel,
  902. .post_remove = efx_channel_dummy_op_void,
  903. .get_name = efx_sriov_get_channel_name,
  904. /* no copy operation; channel must not be reallocated */
  905. .keep_eventq = true,
  906. };
  907. void efx_sriov_probe(struct efx_nic *efx)
  908. {
  909. unsigned count;
  910. if (!max_vfs)
  911. return;
  912. if (efx_sriov_cmd(efx, false, &efx->vi_scale, &count))
  913. return;
  914. if (count > 0 && count > max_vfs)
  915. count = max_vfs;
  916. /* efx_nic_dimension_resources() will reduce vf_count as appopriate */
  917. efx->vf_count = count;
  918. efx->extra_channel_type[EFX_EXTRA_CHANNEL_IOV] = &efx_sriov_channel_type;
  919. }
  920. /* Copy the list of individual addresses into the vfdi_status.peers
  921. * array and auxillary pages, protected by %local_lock. Drop that lock
  922. * and then broadcast the address list to every VF.
  923. */
  924. static void efx_sriov_peer_work(struct work_struct *data)
  925. {
  926. struct efx_nic *efx = container_of(data, struct efx_nic, peer_work);
  927. struct vfdi_status *vfdi_status = efx->vfdi_status.addr;
  928. struct efx_vf *vf;
  929. struct efx_local_addr *local_addr;
  930. struct vfdi_endpoint *peer;
  931. struct efx_endpoint_page *epp;
  932. struct list_head pages;
  933. unsigned int peer_space;
  934. unsigned int peer_count;
  935. unsigned int pos;
  936. mutex_lock(&efx->local_lock);
  937. /* Move the existing peer pages off %local_page_list */
  938. INIT_LIST_HEAD(&pages);
  939. list_splice_tail_init(&efx->local_page_list, &pages);
  940. /* Populate the VF addresses starting from entry 1 (entry 0 is
  941. * the PF address)
  942. */
  943. peer = vfdi_status->peers + 1;
  944. peer_space = ARRAY_SIZE(vfdi_status->peers) - 1;
  945. peer_count = 1;
  946. for (pos = 0; pos < efx->vf_count; ++pos) {
  947. vf = efx->vf + pos;
  948. mutex_lock(&vf->status_lock);
  949. if (vf->rx_filtering && !is_zero_ether_addr(vf->addr.mac_addr)) {
  950. *peer++ = vf->addr;
  951. ++peer_count;
  952. --peer_space;
  953. BUG_ON(peer_space == 0);
  954. }
  955. mutex_unlock(&vf->status_lock);
  956. }
  957. /* Fill the remaining addresses */
  958. list_for_each_entry(local_addr, &efx->local_addr_list, link) {
  959. memcpy(peer->mac_addr, local_addr->addr, ETH_ALEN);
  960. peer->tci = 0;
  961. ++peer;
  962. ++peer_count;
  963. if (--peer_space == 0) {
  964. if (list_empty(&pages)) {
  965. epp = kmalloc(sizeof(*epp), GFP_KERNEL);
  966. if (!epp)
  967. break;
  968. epp->ptr = dma_alloc_coherent(
  969. &efx->pci_dev->dev, EFX_PAGE_SIZE,
  970. &epp->addr, GFP_KERNEL);
  971. if (!epp->ptr) {
  972. kfree(epp);
  973. break;
  974. }
  975. } else {
  976. epp = list_first_entry(
  977. &pages, struct efx_endpoint_page, link);
  978. list_del(&epp->link);
  979. }
  980. list_add_tail(&epp->link, &efx->local_page_list);
  981. peer = (struct vfdi_endpoint *)epp->ptr;
  982. peer_space = EFX_PAGE_SIZE / sizeof(struct vfdi_endpoint);
  983. }
  984. }
  985. vfdi_status->peer_count = peer_count;
  986. mutex_unlock(&efx->local_lock);
  987. /* Free any now unused endpoint pages */
  988. while (!list_empty(&pages)) {
  989. epp = list_first_entry(
  990. &pages, struct efx_endpoint_page, link);
  991. list_del(&epp->link);
  992. dma_free_coherent(&efx->pci_dev->dev, EFX_PAGE_SIZE,
  993. epp->ptr, epp->addr);
  994. kfree(epp);
  995. }
  996. /* Finally, push the pages */
  997. for (pos = 0; pos < efx->vf_count; ++pos) {
  998. vf = efx->vf + pos;
  999. mutex_lock(&vf->status_lock);
  1000. if (vf->status_addr)
  1001. __efx_sriov_push_vf_status(vf);
  1002. mutex_unlock(&vf->status_lock);
  1003. }
  1004. }
  1005. static void efx_sriov_free_local(struct efx_nic *efx)
  1006. {
  1007. struct efx_local_addr *local_addr;
  1008. struct efx_endpoint_page *epp;
  1009. while (!list_empty(&efx->local_addr_list)) {
  1010. local_addr = list_first_entry(&efx->local_addr_list,
  1011. struct efx_local_addr, link);
  1012. list_del(&local_addr->link);
  1013. kfree(local_addr);
  1014. }
  1015. while (!list_empty(&efx->local_page_list)) {
  1016. epp = list_first_entry(&efx->local_page_list,
  1017. struct efx_endpoint_page, link);
  1018. list_del(&epp->link);
  1019. dma_free_coherent(&efx->pci_dev->dev, EFX_PAGE_SIZE,
  1020. epp->ptr, epp->addr);
  1021. kfree(epp);
  1022. }
  1023. }
  1024. static int efx_sriov_vf_alloc(struct efx_nic *efx)
  1025. {
  1026. unsigned index;
  1027. struct efx_vf *vf;
  1028. efx->vf = kzalloc(sizeof(struct efx_vf) * efx->vf_count, GFP_KERNEL);
  1029. if (!efx->vf)
  1030. return -ENOMEM;
  1031. for (index = 0; index < efx->vf_count; ++index) {
  1032. vf = efx->vf + index;
  1033. vf->efx = efx;
  1034. vf->index = index;
  1035. vf->rx_filter_id = -1;
  1036. vf->tx_filter_mode = VF_TX_FILTER_AUTO;
  1037. vf->tx_filter_id = -1;
  1038. INIT_WORK(&vf->req, efx_sriov_vfdi);
  1039. INIT_WORK(&vf->reset_work, efx_sriov_reset_vf_work);
  1040. init_waitqueue_head(&vf->flush_waitq);
  1041. mutex_init(&vf->status_lock);
  1042. mutex_init(&vf->txq_lock);
  1043. }
  1044. return 0;
  1045. }
  1046. static void efx_sriov_vfs_fini(struct efx_nic *efx)
  1047. {
  1048. struct efx_vf *vf;
  1049. unsigned int pos;
  1050. for (pos = 0; pos < efx->vf_count; ++pos) {
  1051. vf = efx->vf + pos;
  1052. efx_nic_free_buffer(efx, &vf->buf);
  1053. kfree(vf->peer_page_addrs);
  1054. vf->peer_page_addrs = NULL;
  1055. vf->peer_page_count = 0;
  1056. vf->evq0_count = 0;
  1057. }
  1058. }
  1059. static int efx_sriov_vfs_init(struct efx_nic *efx)
  1060. {
  1061. struct pci_dev *pci_dev = efx->pci_dev;
  1062. unsigned index, devfn, sriov, buftbl_base;
  1063. u16 offset, stride;
  1064. struct efx_vf *vf;
  1065. int rc;
  1066. sriov = pci_find_ext_capability(pci_dev, PCI_EXT_CAP_ID_SRIOV);
  1067. if (!sriov)
  1068. return -ENOENT;
  1069. pci_read_config_word(pci_dev, sriov + PCI_SRIOV_VF_OFFSET, &offset);
  1070. pci_read_config_word(pci_dev, sriov + PCI_SRIOV_VF_STRIDE, &stride);
  1071. buftbl_base = efx->vf_buftbl_base;
  1072. devfn = pci_dev->devfn + offset;
  1073. for (index = 0; index < efx->vf_count; ++index) {
  1074. vf = efx->vf + index;
  1075. /* Reserve buffer entries */
  1076. vf->buftbl_base = buftbl_base;
  1077. buftbl_base += EFX_VF_BUFTBL_PER_VI * efx_vf_size(efx);
  1078. vf->pci_rid = devfn;
  1079. snprintf(vf->pci_name, sizeof(vf->pci_name),
  1080. "%04x:%02x:%02x.%d",
  1081. pci_domain_nr(pci_dev->bus), pci_dev->bus->number,
  1082. PCI_SLOT(devfn), PCI_FUNC(devfn));
  1083. rc = efx_nic_alloc_buffer(efx, &vf->buf, EFX_PAGE_SIZE,
  1084. GFP_KERNEL);
  1085. if (rc)
  1086. goto fail;
  1087. devfn += stride;
  1088. }
  1089. return 0;
  1090. fail:
  1091. efx_sriov_vfs_fini(efx);
  1092. return rc;
  1093. }
  1094. int efx_sriov_init(struct efx_nic *efx)
  1095. {
  1096. struct net_device *net_dev = efx->net_dev;
  1097. struct vfdi_status *vfdi_status;
  1098. int rc;
  1099. /* Ensure there's room for vf_channel */
  1100. BUILD_BUG_ON(EFX_MAX_CHANNELS + 1 >= EFX_VI_BASE);
  1101. /* Ensure that VI_BASE is aligned on VI_SCALE */
  1102. BUILD_BUG_ON(EFX_VI_BASE & ((1 << EFX_VI_SCALE_MAX) - 1));
  1103. if (efx->vf_count == 0)
  1104. return 0;
  1105. rc = efx_sriov_cmd(efx, true, NULL, NULL);
  1106. if (rc)
  1107. goto fail_cmd;
  1108. rc = efx_nic_alloc_buffer(efx, &efx->vfdi_status, sizeof(*vfdi_status),
  1109. GFP_KERNEL);
  1110. if (rc)
  1111. goto fail_status;
  1112. vfdi_status = efx->vfdi_status.addr;
  1113. memset(vfdi_status, 0, sizeof(*vfdi_status));
  1114. vfdi_status->version = 1;
  1115. vfdi_status->length = sizeof(*vfdi_status);
  1116. vfdi_status->max_tx_channels = vf_max_tx_channels;
  1117. vfdi_status->vi_scale = efx->vi_scale;
  1118. vfdi_status->rss_rxq_count = efx->rss_spread;
  1119. vfdi_status->peer_count = 1 + efx->vf_count;
  1120. vfdi_status->timer_quantum_ns = efx->timer_quantum_ns;
  1121. rc = efx_sriov_vf_alloc(efx);
  1122. if (rc)
  1123. goto fail_alloc;
  1124. mutex_init(&efx->local_lock);
  1125. INIT_WORK(&efx->peer_work, efx_sriov_peer_work);
  1126. INIT_LIST_HEAD(&efx->local_addr_list);
  1127. INIT_LIST_HEAD(&efx->local_page_list);
  1128. rc = efx_sriov_vfs_init(efx);
  1129. if (rc)
  1130. goto fail_vfs;
  1131. rtnl_lock();
  1132. memcpy(vfdi_status->peers[0].mac_addr,
  1133. net_dev->dev_addr, ETH_ALEN);
  1134. efx->vf_init_count = efx->vf_count;
  1135. rtnl_unlock();
  1136. efx_sriov_usrev(efx, true);
  1137. /* At this point we must be ready to accept VFDI requests */
  1138. rc = pci_enable_sriov(efx->pci_dev, efx->vf_count);
  1139. if (rc)
  1140. goto fail_pci;
  1141. netif_info(efx, probe, net_dev,
  1142. "enabled SR-IOV for %d VFs, %d VI per VF\n",
  1143. efx->vf_count, efx_vf_size(efx));
  1144. return 0;
  1145. fail_pci:
  1146. efx_sriov_usrev(efx, false);
  1147. rtnl_lock();
  1148. efx->vf_init_count = 0;
  1149. rtnl_unlock();
  1150. efx_sriov_vfs_fini(efx);
  1151. fail_vfs:
  1152. cancel_work_sync(&efx->peer_work);
  1153. efx_sriov_free_local(efx);
  1154. kfree(efx->vf);
  1155. fail_alloc:
  1156. efx_nic_free_buffer(efx, &efx->vfdi_status);
  1157. fail_status:
  1158. efx_sriov_cmd(efx, false, NULL, NULL);
  1159. fail_cmd:
  1160. return rc;
  1161. }
  1162. void efx_sriov_fini(struct efx_nic *efx)
  1163. {
  1164. struct efx_vf *vf;
  1165. unsigned int pos;
  1166. if (efx->vf_init_count == 0)
  1167. return;
  1168. /* Disable all interfaces to reconfiguration */
  1169. BUG_ON(efx->vfdi_channel->enabled);
  1170. efx_sriov_usrev(efx, false);
  1171. rtnl_lock();
  1172. efx->vf_init_count = 0;
  1173. rtnl_unlock();
  1174. /* Flush all reconfiguration work */
  1175. for (pos = 0; pos < efx->vf_count; ++pos) {
  1176. vf = efx->vf + pos;
  1177. cancel_work_sync(&vf->req);
  1178. cancel_work_sync(&vf->reset_work);
  1179. }
  1180. cancel_work_sync(&efx->peer_work);
  1181. pci_disable_sriov(efx->pci_dev);
  1182. /* Tear down back-end state */
  1183. efx_sriov_vfs_fini(efx);
  1184. efx_sriov_free_local(efx);
  1185. kfree(efx->vf);
  1186. efx_nic_free_buffer(efx, &efx->vfdi_status);
  1187. efx_sriov_cmd(efx, false, NULL, NULL);
  1188. }
  1189. void efx_sriov_event(struct efx_channel *channel, efx_qword_t *event)
  1190. {
  1191. struct efx_nic *efx = channel->efx;
  1192. struct efx_vf *vf;
  1193. unsigned qid, seq, type, data;
  1194. qid = EFX_QWORD_FIELD(*event, FSF_CZ_USER_QID);
  1195. /* USR_EV_REG_VALUE is dword0, so access the VFDI_EV fields directly */
  1196. BUILD_BUG_ON(FSF_CZ_USER_EV_REG_VALUE_LBN != 0);
  1197. seq = EFX_QWORD_FIELD(*event, VFDI_EV_SEQ);
  1198. type = EFX_QWORD_FIELD(*event, VFDI_EV_TYPE);
  1199. data = EFX_QWORD_FIELD(*event, VFDI_EV_DATA);
  1200. netif_vdbg(efx, hw, efx->net_dev,
  1201. "USR_EV event from qid %d seq 0x%x type %d data 0x%x\n",
  1202. qid, seq, type, data);
  1203. if (map_vi_index(efx, qid, &vf, NULL))
  1204. return;
  1205. if (vf->busy)
  1206. goto error;
  1207. if (type == VFDI_EV_TYPE_REQ_WORD0) {
  1208. /* Resynchronise */
  1209. vf->req_type = VFDI_EV_TYPE_REQ_WORD0;
  1210. vf->req_seqno = seq + 1;
  1211. vf->req_addr = 0;
  1212. } else if (seq != (vf->req_seqno++ & 0xff) || type != vf->req_type)
  1213. goto error;
  1214. switch (vf->req_type) {
  1215. case VFDI_EV_TYPE_REQ_WORD0:
  1216. case VFDI_EV_TYPE_REQ_WORD1:
  1217. case VFDI_EV_TYPE_REQ_WORD2:
  1218. vf->req_addr |= (u64)data << (vf->req_type << 4);
  1219. ++vf->req_type;
  1220. return;
  1221. case VFDI_EV_TYPE_REQ_WORD3:
  1222. vf->req_addr |= (u64)data << 48;
  1223. vf->req_type = VFDI_EV_TYPE_REQ_WORD0;
  1224. vf->busy = true;
  1225. queue_work(vfdi_workqueue, &vf->req);
  1226. return;
  1227. }
  1228. error:
  1229. if (net_ratelimit())
  1230. netif_err(efx, hw, efx->net_dev,
  1231. "ERROR: Screaming VFDI request from %s\n",
  1232. vf->pci_name);
  1233. /* Reset the request and sequence number */
  1234. vf->req_type = VFDI_EV_TYPE_REQ_WORD0;
  1235. vf->req_seqno = seq + 1;
  1236. }
  1237. void efx_sriov_flr(struct efx_nic *efx, unsigned vf_i)
  1238. {
  1239. struct efx_vf *vf;
  1240. if (vf_i > efx->vf_init_count)
  1241. return;
  1242. vf = efx->vf + vf_i;
  1243. netif_info(efx, hw, efx->net_dev,
  1244. "FLR on VF %s\n", vf->pci_name);
  1245. vf->status_addr = 0;
  1246. efx_vfdi_remove_all_filters(vf);
  1247. efx_vfdi_flush_clear(vf);
  1248. vf->evq0_count = 0;
  1249. }
  1250. void efx_sriov_mac_address_changed(struct efx_nic *efx)
  1251. {
  1252. struct vfdi_status *vfdi_status = efx->vfdi_status.addr;
  1253. if (!efx->vf_init_count)
  1254. return;
  1255. memcpy(vfdi_status->peers[0].mac_addr,
  1256. efx->net_dev->dev_addr, ETH_ALEN);
  1257. queue_work(vfdi_workqueue, &efx->peer_work);
  1258. }
  1259. void efx_sriov_tx_flush_done(struct efx_nic *efx, efx_qword_t *event)
  1260. {
  1261. struct efx_vf *vf;
  1262. unsigned queue, qid;
  1263. queue = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
  1264. if (map_vi_index(efx, queue, &vf, &qid))
  1265. return;
  1266. /* Ignore flush completions triggered by an FLR */
  1267. if (!test_bit(qid, vf->txq_mask))
  1268. return;
  1269. __clear_bit(qid, vf->txq_mask);
  1270. --vf->txq_count;
  1271. if (efx_vfdi_flush_wake(vf))
  1272. wake_up(&vf->flush_waitq);
  1273. }
  1274. void efx_sriov_rx_flush_done(struct efx_nic *efx, efx_qword_t *event)
  1275. {
  1276. struct efx_vf *vf;
  1277. unsigned ev_failed, queue, qid;
  1278. queue = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
  1279. ev_failed = EFX_QWORD_FIELD(*event,
  1280. FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
  1281. if (map_vi_index(efx, queue, &vf, &qid))
  1282. return;
  1283. if (!test_bit(qid, vf->rxq_mask))
  1284. return;
  1285. if (ev_failed) {
  1286. set_bit(qid, vf->rxq_retry_mask);
  1287. atomic_inc(&vf->rxq_retry_count);
  1288. } else {
  1289. __clear_bit(qid, vf->rxq_mask);
  1290. --vf->rxq_count;
  1291. }
  1292. if (efx_vfdi_flush_wake(vf))
  1293. wake_up(&vf->flush_waitq);
  1294. }
  1295. /* Called from napi. Schedule the reset work item */
  1296. void efx_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq)
  1297. {
  1298. struct efx_vf *vf;
  1299. unsigned int rel;
  1300. if (map_vi_index(efx, dmaq, &vf, &rel))
  1301. return;
  1302. if (net_ratelimit())
  1303. netif_err(efx, hw, efx->net_dev,
  1304. "VF %d DMA Q %d reports descriptor fetch error.\n",
  1305. vf->index, rel);
  1306. queue_work(vfdi_workqueue, &vf->reset_work);
  1307. }
  1308. /* Reset all VFs */
  1309. void efx_sriov_reset(struct efx_nic *efx)
  1310. {
  1311. unsigned int vf_i;
  1312. struct efx_buffer buf;
  1313. struct efx_vf *vf;
  1314. ASSERT_RTNL();
  1315. if (efx->vf_init_count == 0)
  1316. return;
  1317. efx_sriov_usrev(efx, true);
  1318. (void)efx_sriov_cmd(efx, true, NULL, NULL);
  1319. if (efx_nic_alloc_buffer(efx, &buf, EFX_PAGE_SIZE, GFP_NOIO))
  1320. return;
  1321. for (vf_i = 0; vf_i < efx->vf_init_count; ++vf_i) {
  1322. vf = efx->vf + vf_i;
  1323. efx_sriov_reset_vf(vf, &buf);
  1324. }
  1325. efx_nic_free_buffer(efx, &buf);
  1326. }
  1327. int efx_init_sriov(void)
  1328. {
  1329. /* A single threaded workqueue is sufficient. efx_sriov_vfdi() and
  1330. * efx_sriov_peer_work() spend almost all their time sleeping for
  1331. * MCDI to complete anyway
  1332. */
  1333. vfdi_workqueue = create_singlethread_workqueue("sfc_vfdi");
  1334. if (!vfdi_workqueue)
  1335. return -ENOMEM;
  1336. return 0;
  1337. }
  1338. void efx_fini_sriov(void)
  1339. {
  1340. destroy_workqueue(vfdi_workqueue);
  1341. }
  1342. int efx_sriov_set_vf_mac(struct net_device *net_dev, int vf_i, u8 *mac)
  1343. {
  1344. struct efx_nic *efx = netdev_priv(net_dev);
  1345. struct efx_vf *vf;
  1346. if (vf_i >= efx->vf_init_count)
  1347. return -EINVAL;
  1348. vf = efx->vf + vf_i;
  1349. mutex_lock(&vf->status_lock);
  1350. memcpy(vf->addr.mac_addr, mac, ETH_ALEN);
  1351. __efx_sriov_update_vf_addr(vf);
  1352. mutex_unlock(&vf->status_lock);
  1353. return 0;
  1354. }
  1355. int efx_sriov_set_vf_vlan(struct net_device *net_dev, int vf_i,
  1356. u16 vlan, u8 qos)
  1357. {
  1358. struct efx_nic *efx = netdev_priv(net_dev);
  1359. struct efx_vf *vf;
  1360. u16 tci;
  1361. if (vf_i >= efx->vf_init_count)
  1362. return -EINVAL;
  1363. vf = efx->vf + vf_i;
  1364. mutex_lock(&vf->status_lock);
  1365. tci = (vlan & VLAN_VID_MASK) | ((qos & 0x7) << VLAN_PRIO_SHIFT);
  1366. vf->addr.tci = htons(tci);
  1367. __efx_sriov_update_vf_addr(vf);
  1368. mutex_unlock(&vf->status_lock);
  1369. return 0;
  1370. }
  1371. int efx_sriov_set_vf_spoofchk(struct net_device *net_dev, int vf_i,
  1372. bool spoofchk)
  1373. {
  1374. struct efx_nic *efx = netdev_priv(net_dev);
  1375. struct efx_vf *vf;
  1376. int rc;
  1377. if (vf_i >= efx->vf_init_count)
  1378. return -EINVAL;
  1379. vf = efx->vf + vf_i;
  1380. mutex_lock(&vf->txq_lock);
  1381. if (vf->txq_count == 0) {
  1382. vf->tx_filter_mode =
  1383. spoofchk ? VF_TX_FILTER_ON : VF_TX_FILTER_OFF;
  1384. rc = 0;
  1385. } else {
  1386. /* This cannot be changed while TX queues are running */
  1387. rc = -EBUSY;
  1388. }
  1389. mutex_unlock(&vf->txq_lock);
  1390. return rc;
  1391. }
  1392. int efx_sriov_get_vf_config(struct net_device *net_dev, int vf_i,
  1393. struct ifla_vf_info *ivi)
  1394. {
  1395. struct efx_nic *efx = netdev_priv(net_dev);
  1396. struct efx_vf *vf;
  1397. u16 tci;
  1398. if (vf_i >= efx->vf_init_count)
  1399. return -EINVAL;
  1400. vf = efx->vf + vf_i;
  1401. ivi->vf = vf_i;
  1402. memcpy(ivi->mac, vf->addr.mac_addr, ETH_ALEN);
  1403. ivi->tx_rate = 0;
  1404. tci = ntohs(vf->addr.tci);
  1405. ivi->vlan = tci & VLAN_VID_MASK;
  1406. ivi->qos = (tci >> VLAN_PRIO_SHIFT) & 0x7;
  1407. ivi->spoofchk = vf->tx_filter_mode == VF_TX_FILTER_ON;
  1408. return 0;
  1409. }