qlcnic_ctx.c 38 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417
  1. /*
  2. * QLogic qlcnic NIC Driver
  3. * Copyright (c) 2009-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qlcnic for copyright and licensing details.
  6. */
  7. #include "qlcnic.h"
  8. static const struct qlcnic_mailbox_metadata qlcnic_mbx_tbl[] = {
  9. {QLCNIC_CMD_CREATE_RX_CTX, 4, 1},
  10. {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
  11. {QLCNIC_CMD_CREATE_TX_CTX, 4, 1},
  12. {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
  13. {QLCNIC_CMD_INTRPT_TEST, 4, 1},
  14. {QLCNIC_CMD_SET_MTU, 4, 1},
  15. {QLCNIC_CMD_READ_PHY, 4, 2},
  16. {QLCNIC_CMD_WRITE_PHY, 5, 1},
  17. {QLCNIC_CMD_READ_HW_REG, 4, 1},
  18. {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
  19. {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
  20. {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
  21. {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
  22. {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
  23. {QLCNIC_CMD_GET_PCI_INFO, 4, 1},
  24. {QLCNIC_CMD_GET_NIC_INFO, 4, 1},
  25. {QLCNIC_CMD_SET_NIC_INFO, 4, 1},
  26. {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
  27. {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
  28. {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
  29. {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
  30. {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
  31. {QLCNIC_CMD_GET_MAC_STATS, 4, 1},
  32. {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
  33. {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
  34. {QLCNIC_CMD_CONFIG_PORT, 4, 1},
  35. {QLCNIC_CMD_TEMP_SIZE, 4, 4},
  36. {QLCNIC_CMD_GET_TEMP_HDR, 4, 1},
  37. {QLCNIC_CMD_82XX_SET_DRV_VER, 4, 1},
  38. {QLCNIC_CMD_GET_LED_STATUS, 4, 2},
  39. {QLCNIC_CMD_MQ_TX_CONFIG_INTR, 2, 3},
  40. {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
  41. {QLCNIC_CMD_DCB_QUERY_PARAM, 4, 1},
  42. };
  43. static inline u32 qlcnic_get_cmd_signature(struct qlcnic_hardware_context *ahw)
  44. {
  45. return (ahw->pci_func & 0xff) | ((ahw->fw_hal_version & 0xff) << 8) |
  46. (0xcafe << 16);
  47. }
  48. /* Allocate mailbox registers */
  49. int qlcnic_82xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
  50. struct qlcnic_adapter *adapter, u32 type)
  51. {
  52. int i, size;
  53. const struct qlcnic_mailbox_metadata *mbx_tbl;
  54. mbx_tbl = qlcnic_mbx_tbl;
  55. size = ARRAY_SIZE(qlcnic_mbx_tbl);
  56. for (i = 0; i < size; i++) {
  57. if (type == mbx_tbl[i].cmd) {
  58. mbx->req.num = mbx_tbl[i].in_args;
  59. mbx->rsp.num = mbx_tbl[i].out_args;
  60. mbx->req.arg = kcalloc(mbx->req.num,
  61. sizeof(u32), GFP_ATOMIC);
  62. if (!mbx->req.arg)
  63. return -ENOMEM;
  64. mbx->rsp.arg = kcalloc(mbx->rsp.num,
  65. sizeof(u32), GFP_ATOMIC);
  66. if (!mbx->rsp.arg) {
  67. kfree(mbx->req.arg);
  68. mbx->req.arg = NULL;
  69. return -ENOMEM;
  70. }
  71. memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
  72. memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
  73. mbx->req.arg[0] = type;
  74. break;
  75. }
  76. }
  77. return 0;
  78. }
  79. /* Free up mailbox registers */
  80. void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd)
  81. {
  82. kfree(cmd->req.arg);
  83. cmd->req.arg = NULL;
  84. kfree(cmd->rsp.arg);
  85. cmd->rsp.arg = NULL;
  86. }
  87. static int qlcnic_is_valid_nic_func(struct qlcnic_adapter *adapter, u8 pci_func)
  88. {
  89. int i;
  90. for (i = 0; i < adapter->ahw->act_pci_func; i++) {
  91. if (adapter->npars[i].pci_func == pci_func)
  92. return i;
  93. }
  94. return -1;
  95. }
  96. static u32
  97. qlcnic_poll_rsp(struct qlcnic_adapter *adapter)
  98. {
  99. u32 rsp;
  100. int timeout = 0, err = 0;
  101. do {
  102. /* give atleast 1ms for firmware to respond */
  103. mdelay(1);
  104. if (++timeout > QLCNIC_OS_CRB_RETRY_COUNT)
  105. return QLCNIC_CDRP_RSP_TIMEOUT;
  106. rsp = QLCRD32(adapter, QLCNIC_CDRP_CRB_OFFSET, &err);
  107. } while (!QLCNIC_CDRP_IS_RSP(rsp));
  108. return rsp;
  109. }
  110. int qlcnic_82xx_issue_cmd(struct qlcnic_adapter *adapter,
  111. struct qlcnic_cmd_args *cmd)
  112. {
  113. int i, err = 0;
  114. u32 rsp;
  115. u32 signature;
  116. struct pci_dev *pdev = adapter->pdev;
  117. struct qlcnic_hardware_context *ahw = adapter->ahw;
  118. const char *fmt;
  119. signature = qlcnic_get_cmd_signature(ahw);
  120. /* Acquire semaphore before accessing CRB */
  121. if (qlcnic_api_lock(adapter)) {
  122. cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
  123. return cmd->rsp.arg[0];
  124. }
  125. QLCWR32(adapter, QLCNIC_SIGN_CRB_OFFSET, signature);
  126. for (i = 1; i < QLCNIC_CDRP_MAX_ARGS; i++)
  127. QLCWR32(adapter, QLCNIC_CDRP_ARG(i), cmd->req.arg[i]);
  128. QLCWR32(adapter, QLCNIC_CDRP_CRB_OFFSET,
  129. QLCNIC_CDRP_FORM_CMD(cmd->req.arg[0]));
  130. rsp = qlcnic_poll_rsp(adapter);
  131. if (rsp == QLCNIC_CDRP_RSP_TIMEOUT) {
  132. dev_err(&pdev->dev, "card response timeout.\n");
  133. cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
  134. } else if (rsp == QLCNIC_CDRP_RSP_FAIL) {
  135. cmd->rsp.arg[0] = QLCRD32(adapter, QLCNIC_CDRP_ARG(1), &err);
  136. switch (cmd->rsp.arg[0]) {
  137. case QLCNIC_RCODE_INVALID_ARGS:
  138. fmt = "CDRP invalid args: [%d]\n";
  139. break;
  140. case QLCNIC_RCODE_NOT_SUPPORTED:
  141. case QLCNIC_RCODE_NOT_IMPL:
  142. fmt = "CDRP command not supported: [%d]\n";
  143. break;
  144. case QLCNIC_RCODE_NOT_PERMITTED:
  145. fmt = "CDRP requested action not permitted: [%d]\n";
  146. break;
  147. case QLCNIC_RCODE_INVALID:
  148. fmt = "CDRP invalid or unknown cmd received: [%d]\n";
  149. break;
  150. case QLCNIC_RCODE_TIMEOUT:
  151. fmt = "CDRP command timeout: [%d]\n";
  152. break;
  153. default:
  154. fmt = "CDRP command failed: [%d]\n";
  155. break;
  156. }
  157. dev_err(&pdev->dev, fmt, cmd->rsp.arg[0]);
  158. qlcnic_dump_mbx(adapter, cmd);
  159. } else if (rsp == QLCNIC_CDRP_RSP_OK)
  160. cmd->rsp.arg[0] = QLCNIC_RCODE_SUCCESS;
  161. for (i = 1; i < cmd->rsp.num; i++)
  162. cmd->rsp.arg[i] = QLCRD32(adapter, QLCNIC_CDRP_ARG(i), &err);
  163. /* Release semaphore */
  164. qlcnic_api_unlock(adapter);
  165. return cmd->rsp.arg[0];
  166. }
  167. int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *adapter, u32 fw_cmd)
  168. {
  169. struct qlcnic_cmd_args cmd;
  170. u32 arg1, arg2, arg3;
  171. char drv_string[12];
  172. int err = 0;
  173. memset(drv_string, 0, sizeof(drv_string));
  174. snprintf(drv_string, sizeof(drv_string), "%d"".""%d"".""%d",
  175. _QLCNIC_LINUX_MAJOR, _QLCNIC_LINUX_MINOR,
  176. _QLCNIC_LINUX_SUBVERSION);
  177. err = qlcnic_alloc_mbx_args(&cmd, adapter, fw_cmd);
  178. if (err)
  179. return err;
  180. memcpy(&arg1, drv_string, sizeof(u32));
  181. memcpy(&arg2, drv_string + 4, sizeof(u32));
  182. memcpy(&arg3, drv_string + 8, sizeof(u32));
  183. cmd.req.arg[1] = arg1;
  184. cmd.req.arg[2] = arg2;
  185. cmd.req.arg[3] = arg3;
  186. err = qlcnic_issue_cmd(adapter, &cmd);
  187. if (err) {
  188. dev_info(&adapter->pdev->dev,
  189. "Failed to set driver version in firmware\n");
  190. err = -EIO;
  191. }
  192. qlcnic_free_mbx_args(&cmd);
  193. return err;
  194. }
  195. int
  196. qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu)
  197. {
  198. int err = 0;
  199. struct qlcnic_cmd_args cmd;
  200. struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
  201. if (recv_ctx->state != QLCNIC_HOST_CTX_STATE_ACTIVE)
  202. return err;
  203. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_MTU);
  204. if (err)
  205. return err;
  206. cmd.req.arg[1] = recv_ctx->context_id;
  207. cmd.req.arg[2] = mtu;
  208. err = qlcnic_issue_cmd(adapter, &cmd);
  209. if (err) {
  210. dev_err(&adapter->pdev->dev, "Failed to set mtu\n");
  211. err = -EIO;
  212. }
  213. qlcnic_free_mbx_args(&cmd);
  214. return err;
  215. }
  216. int qlcnic_82xx_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
  217. {
  218. struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
  219. struct qlcnic_hardware_context *ahw = adapter->ahw;
  220. dma_addr_t hostrq_phys_addr, cardrsp_phys_addr;
  221. struct net_device *netdev = adapter->netdev;
  222. u32 temp_intr_crb_mode, temp_rds_crb_mode;
  223. struct qlcnic_cardrsp_rds_ring *prsp_rds;
  224. struct qlcnic_cardrsp_sds_ring *prsp_sds;
  225. struct qlcnic_hostrq_rds_ring *prq_rds;
  226. struct qlcnic_hostrq_sds_ring *prq_sds;
  227. struct qlcnic_host_rds_ring *rds_ring;
  228. struct qlcnic_host_sds_ring *sds_ring;
  229. struct qlcnic_cardrsp_rx_ctx *prsp;
  230. struct qlcnic_hostrq_rx_ctx *prq;
  231. u8 i, nrds_rings, nsds_rings;
  232. struct qlcnic_cmd_args cmd;
  233. size_t rq_size, rsp_size;
  234. u32 cap, reg, val, reg2;
  235. u64 phys_addr;
  236. u16 temp_u16;
  237. void *addr;
  238. int err;
  239. nrds_rings = adapter->max_rds_rings;
  240. nsds_rings = adapter->max_sds_rings;
  241. rq_size = SIZEOF_HOSTRQ_RX(struct qlcnic_hostrq_rx_ctx, nrds_rings,
  242. nsds_rings);
  243. rsp_size = SIZEOF_CARDRSP_RX(struct qlcnic_cardrsp_rx_ctx, nrds_rings,
  244. nsds_rings);
  245. addr = dma_alloc_coherent(&adapter->pdev->dev, rq_size,
  246. &hostrq_phys_addr, GFP_KERNEL);
  247. if (addr == NULL)
  248. return -ENOMEM;
  249. prq = addr;
  250. addr = dma_alloc_coherent(&adapter->pdev->dev, rsp_size,
  251. &cardrsp_phys_addr, GFP_KERNEL);
  252. if (addr == NULL) {
  253. err = -ENOMEM;
  254. goto out_free_rq;
  255. }
  256. prsp = addr;
  257. prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr);
  258. cap = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN
  259. | QLCNIC_CAP0_VALIDOFF);
  260. cap |= (QLCNIC_CAP0_JUMBO_CONTIGUOUS | QLCNIC_CAP0_LRO_CONTIGUOUS);
  261. if (qlcnic_check_multi_tx(adapter) &&
  262. !adapter->ahw->diag_test) {
  263. cap |= QLCNIC_CAP0_TX_MULTI;
  264. } else {
  265. temp_u16 = offsetof(struct qlcnic_hostrq_rx_ctx, msix_handler);
  266. prq->valid_field_offset = cpu_to_le16(temp_u16);
  267. prq->txrx_sds_binding = nsds_rings - 1;
  268. temp_intr_crb_mode = QLCNIC_HOST_INT_CRB_MODE_SHARED;
  269. prq->host_int_crb_mode = cpu_to_le32(temp_intr_crb_mode);
  270. temp_rds_crb_mode = QLCNIC_HOST_RDS_CRB_MODE_UNIQUE;
  271. prq->host_rds_crb_mode = cpu_to_le32(temp_rds_crb_mode);
  272. }
  273. prq->capabilities[0] = cpu_to_le32(cap);
  274. prq->num_rds_rings = cpu_to_le16(nrds_rings);
  275. prq->num_sds_rings = cpu_to_le16(nsds_rings);
  276. prq->rds_ring_offset = 0;
  277. val = le32_to_cpu(prq->rds_ring_offset) +
  278. (sizeof(struct qlcnic_hostrq_rds_ring) * nrds_rings);
  279. prq->sds_ring_offset = cpu_to_le32(val);
  280. prq_rds = (struct qlcnic_hostrq_rds_ring *)(prq->data +
  281. le32_to_cpu(prq->rds_ring_offset));
  282. for (i = 0; i < nrds_rings; i++) {
  283. rds_ring = &recv_ctx->rds_rings[i];
  284. rds_ring->producer = 0;
  285. prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr);
  286. prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc);
  287. prq_rds[i].ring_kind = cpu_to_le32(i);
  288. prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size);
  289. }
  290. prq_sds = (struct qlcnic_hostrq_sds_ring *)(prq->data +
  291. le32_to_cpu(prq->sds_ring_offset));
  292. for (i = 0; i < nsds_rings; i++) {
  293. sds_ring = &recv_ctx->sds_rings[i];
  294. sds_ring->consumer = 0;
  295. memset(sds_ring->desc_head, 0, STATUS_DESC_RINGSIZE(sds_ring));
  296. prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr);
  297. prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc);
  298. if (qlcnic_check_multi_tx(adapter) &&
  299. !adapter->ahw->diag_test)
  300. prq_sds[i].msi_index = cpu_to_le16(ahw->intr_tbl[i].id);
  301. else
  302. prq_sds[i].msi_index = cpu_to_le16(i);
  303. }
  304. phys_addr = hostrq_phys_addr;
  305. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_RX_CTX);
  306. if (err)
  307. goto out_free_rsp;
  308. cmd.req.arg[1] = MSD(phys_addr);
  309. cmd.req.arg[2] = LSD(phys_addr);
  310. cmd.req.arg[3] = rq_size;
  311. err = qlcnic_issue_cmd(adapter, &cmd);
  312. if (err) {
  313. dev_err(&adapter->pdev->dev,
  314. "Failed to create rx ctx in firmware%d\n", err);
  315. goto out_free_rsp;
  316. }
  317. prsp_rds = ((struct qlcnic_cardrsp_rds_ring *)
  318. &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]);
  319. for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) {
  320. rds_ring = &recv_ctx->rds_rings[i];
  321. reg = le32_to_cpu(prsp_rds[i].host_producer_crb);
  322. rds_ring->crb_rcv_producer = ahw->pci_base0 + reg;
  323. }
  324. prsp_sds = ((struct qlcnic_cardrsp_sds_ring *)
  325. &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]);
  326. for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) {
  327. sds_ring = &recv_ctx->sds_rings[i];
  328. reg = le32_to_cpu(prsp_sds[i].host_consumer_crb);
  329. if (qlcnic_check_multi_tx(adapter) && !adapter->ahw->diag_test)
  330. reg2 = ahw->intr_tbl[i].src;
  331. else
  332. reg2 = le32_to_cpu(prsp_sds[i].interrupt_crb);
  333. sds_ring->crb_intr_mask = ahw->pci_base0 + reg2;
  334. sds_ring->crb_sts_consumer = ahw->pci_base0 + reg;
  335. }
  336. recv_ctx->state = le32_to_cpu(prsp->host_ctx_state);
  337. recv_ctx->context_id = le16_to_cpu(prsp->context_id);
  338. recv_ctx->virt_port = prsp->virt_port;
  339. netdev_info(netdev, "Rx Context[%d] Created, state 0x%x\n",
  340. recv_ctx->context_id, recv_ctx->state);
  341. qlcnic_free_mbx_args(&cmd);
  342. out_free_rsp:
  343. dma_free_coherent(&adapter->pdev->dev, rsp_size, prsp,
  344. cardrsp_phys_addr);
  345. out_free_rq:
  346. dma_free_coherent(&adapter->pdev->dev, rq_size, prq, hostrq_phys_addr);
  347. return err;
  348. }
  349. void qlcnic_82xx_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter)
  350. {
  351. int err;
  352. struct qlcnic_cmd_args cmd;
  353. struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
  354. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX);
  355. if (err)
  356. return;
  357. cmd.req.arg[1] = recv_ctx->context_id;
  358. err = qlcnic_issue_cmd(adapter, &cmd);
  359. if (err)
  360. dev_err(&adapter->pdev->dev,
  361. "Failed to destroy rx ctx in firmware\n");
  362. recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
  363. qlcnic_free_mbx_args(&cmd);
  364. }
  365. int qlcnic_82xx_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter,
  366. struct qlcnic_host_tx_ring *tx_ring,
  367. int ring)
  368. {
  369. struct qlcnic_hardware_context *ahw = adapter->ahw;
  370. struct net_device *netdev = adapter->netdev;
  371. struct qlcnic_hostrq_tx_ctx *prq;
  372. struct qlcnic_hostrq_cds_ring *prq_cds;
  373. struct qlcnic_cardrsp_tx_ctx *prsp;
  374. struct qlcnic_cmd_args cmd;
  375. u32 temp, intr_mask, temp_int_crb_mode;
  376. dma_addr_t rq_phys_addr, rsp_phys_addr;
  377. int temp_nsds_rings, index, err;
  378. void *rq_addr, *rsp_addr;
  379. size_t rq_size, rsp_size;
  380. u64 phys_addr;
  381. u16 msix_id;
  382. /* reset host resources */
  383. tx_ring->producer = 0;
  384. tx_ring->sw_consumer = 0;
  385. *(tx_ring->hw_consumer) = 0;
  386. rq_size = SIZEOF_HOSTRQ_TX(struct qlcnic_hostrq_tx_ctx);
  387. rq_addr = dma_zalloc_coherent(&adapter->pdev->dev, rq_size,
  388. &rq_phys_addr, GFP_KERNEL);
  389. if (!rq_addr)
  390. return -ENOMEM;
  391. rsp_size = SIZEOF_CARDRSP_TX(struct qlcnic_cardrsp_tx_ctx);
  392. rsp_addr = dma_zalloc_coherent(&adapter->pdev->dev, rsp_size,
  393. &rsp_phys_addr, GFP_KERNEL);
  394. if (!rsp_addr) {
  395. err = -ENOMEM;
  396. goto out_free_rq;
  397. }
  398. prq = rq_addr;
  399. prsp = rsp_addr;
  400. prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr);
  401. temp = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN |
  402. QLCNIC_CAP0_LSO);
  403. if (qlcnic_check_multi_tx(adapter) && !adapter->ahw->diag_test)
  404. temp |= QLCNIC_CAP0_TX_MULTI;
  405. prq->capabilities[0] = cpu_to_le32(temp);
  406. if (qlcnic_check_multi_tx(adapter) &&
  407. !adapter->ahw->diag_test) {
  408. temp_nsds_rings = adapter->max_sds_rings;
  409. index = temp_nsds_rings + ring;
  410. msix_id = ahw->intr_tbl[index].id;
  411. prq->msi_index = cpu_to_le16(msix_id);
  412. } else {
  413. temp_int_crb_mode = QLCNIC_HOST_INT_CRB_MODE_SHARED;
  414. prq->host_int_crb_mode = cpu_to_le32(temp_int_crb_mode);
  415. prq->msi_index = 0;
  416. }
  417. prq->interrupt_ctl = 0;
  418. prq->cmd_cons_dma_addr = cpu_to_le64(tx_ring->hw_cons_phys_addr);
  419. prq_cds = &prq->cds_ring;
  420. prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr);
  421. prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc);
  422. phys_addr = rq_phys_addr;
  423. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
  424. if (err)
  425. goto out_free_rsp;
  426. cmd.req.arg[1] = MSD(phys_addr);
  427. cmd.req.arg[2] = LSD(phys_addr);
  428. cmd.req.arg[3] = rq_size;
  429. err = qlcnic_issue_cmd(adapter, &cmd);
  430. if (err == QLCNIC_RCODE_SUCCESS) {
  431. tx_ring->state = le32_to_cpu(prsp->host_ctx_state);
  432. temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
  433. tx_ring->crb_cmd_producer = adapter->ahw->pci_base0 + temp;
  434. tx_ring->ctx_id = le16_to_cpu(prsp->context_id);
  435. if (qlcnic_check_multi_tx(adapter) &&
  436. !adapter->ahw->diag_test &&
  437. (adapter->flags & QLCNIC_MSIX_ENABLED)) {
  438. index = adapter->max_sds_rings + ring;
  439. intr_mask = ahw->intr_tbl[index].src;
  440. tx_ring->crb_intr_mask = ahw->pci_base0 + intr_mask;
  441. }
  442. netdev_info(netdev, "Tx Context[0x%x] Created, state 0x%x\n",
  443. tx_ring->ctx_id, tx_ring->state);
  444. } else {
  445. netdev_err(netdev, "Failed to create tx ctx in firmware%d\n",
  446. err);
  447. err = -EIO;
  448. }
  449. qlcnic_free_mbx_args(&cmd);
  450. out_free_rsp:
  451. dma_free_coherent(&adapter->pdev->dev, rsp_size, rsp_addr,
  452. rsp_phys_addr);
  453. out_free_rq:
  454. dma_free_coherent(&adapter->pdev->dev, rq_size, rq_addr, rq_phys_addr);
  455. return err;
  456. }
  457. void qlcnic_82xx_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter,
  458. struct qlcnic_host_tx_ring *tx_ring)
  459. {
  460. struct qlcnic_cmd_args cmd;
  461. int ret;
  462. ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX);
  463. if (ret)
  464. return;
  465. cmd.req.arg[1] = tx_ring->ctx_id;
  466. if (qlcnic_issue_cmd(adapter, &cmd))
  467. dev_err(&adapter->pdev->dev,
  468. "Failed to destroy tx ctx in firmware\n");
  469. qlcnic_free_mbx_args(&cmd);
  470. }
  471. int
  472. qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config)
  473. {
  474. int err;
  475. struct qlcnic_cmd_args cmd;
  476. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_PORT);
  477. if (err)
  478. return err;
  479. cmd.req.arg[1] = config;
  480. err = qlcnic_issue_cmd(adapter, &cmd);
  481. qlcnic_free_mbx_args(&cmd);
  482. return err;
  483. }
  484. int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter)
  485. {
  486. void *addr;
  487. int err, ring;
  488. struct qlcnic_recv_context *recv_ctx;
  489. struct qlcnic_host_rds_ring *rds_ring;
  490. struct qlcnic_host_sds_ring *sds_ring;
  491. struct qlcnic_host_tx_ring *tx_ring;
  492. __le32 *ptr;
  493. struct pci_dev *pdev = adapter->pdev;
  494. recv_ctx = adapter->recv_ctx;
  495. for (ring = 0; ring < adapter->max_drv_tx_rings; ring++) {
  496. tx_ring = &adapter->tx_ring[ring];
  497. ptr = (__le32 *)dma_alloc_coherent(&pdev->dev, sizeof(u32),
  498. &tx_ring->hw_cons_phys_addr,
  499. GFP_KERNEL);
  500. if (ptr == NULL)
  501. return -ENOMEM;
  502. tx_ring->hw_consumer = ptr;
  503. /* cmd desc ring */
  504. addr = dma_alloc_coherent(&pdev->dev, TX_DESC_RINGSIZE(tx_ring),
  505. &tx_ring->phys_addr,
  506. GFP_KERNEL);
  507. if (addr == NULL) {
  508. err = -ENOMEM;
  509. goto err_out_free;
  510. }
  511. tx_ring->desc_head = addr;
  512. }
  513. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  514. rds_ring = &recv_ctx->rds_rings[ring];
  515. addr = dma_alloc_coherent(&adapter->pdev->dev,
  516. RCV_DESC_RINGSIZE(rds_ring),
  517. &rds_ring->phys_addr, GFP_KERNEL);
  518. if (addr == NULL) {
  519. err = -ENOMEM;
  520. goto err_out_free;
  521. }
  522. rds_ring->desc_head = addr;
  523. }
  524. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  525. sds_ring = &recv_ctx->sds_rings[ring];
  526. addr = dma_alloc_coherent(&adapter->pdev->dev,
  527. STATUS_DESC_RINGSIZE(sds_ring),
  528. &sds_ring->phys_addr, GFP_KERNEL);
  529. if (addr == NULL) {
  530. err = -ENOMEM;
  531. goto err_out_free;
  532. }
  533. sds_ring->desc_head = addr;
  534. }
  535. return 0;
  536. err_out_free:
  537. qlcnic_free_hw_resources(adapter);
  538. return err;
  539. }
  540. int qlcnic_fw_create_ctx(struct qlcnic_adapter *dev)
  541. {
  542. int i, err, ring;
  543. if (dev->flags & QLCNIC_NEED_FLR) {
  544. pci_reset_function(dev->pdev);
  545. dev->flags &= ~QLCNIC_NEED_FLR;
  546. }
  547. if (qlcnic_83xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED)) {
  548. if (dev->ahw->diag_test != QLCNIC_LOOPBACK_TEST) {
  549. err = qlcnic_83xx_config_intrpt(dev, 1);
  550. if (err)
  551. return err;
  552. }
  553. }
  554. if (qlcnic_82xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED) &&
  555. qlcnic_check_multi_tx(dev) && !dev->ahw->diag_test) {
  556. err = qlcnic_82xx_mq_intrpt(dev, 1);
  557. if (err)
  558. return err;
  559. }
  560. err = qlcnic_fw_cmd_create_rx_ctx(dev);
  561. if (err)
  562. goto err_out;
  563. for (ring = 0; ring < dev->max_drv_tx_rings; ring++) {
  564. err = qlcnic_fw_cmd_create_tx_ctx(dev,
  565. &dev->tx_ring[ring],
  566. ring);
  567. if (err) {
  568. qlcnic_fw_cmd_del_rx_ctx(dev);
  569. if (ring == 0)
  570. goto err_out;
  571. for (i = 0; i < ring; i++)
  572. qlcnic_fw_cmd_del_tx_ctx(dev, &dev->tx_ring[i]);
  573. goto err_out;
  574. }
  575. }
  576. set_bit(__QLCNIC_FW_ATTACHED, &dev->state);
  577. return 0;
  578. err_out:
  579. if (qlcnic_82xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED) &&
  580. qlcnic_check_multi_tx(dev) && !dev->ahw->diag_test)
  581. qlcnic_82xx_config_intrpt(dev, 0);
  582. if (qlcnic_83xx_check(dev) && (dev->flags & QLCNIC_MSIX_ENABLED)) {
  583. if (dev->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
  584. qlcnic_83xx_config_intrpt(dev, 0);
  585. }
  586. return err;
  587. }
  588. void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter)
  589. {
  590. int ring;
  591. if (test_and_clear_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) {
  592. qlcnic_fw_cmd_del_rx_ctx(adapter);
  593. for (ring = 0; ring < adapter->max_drv_tx_rings; ring++)
  594. qlcnic_fw_cmd_del_tx_ctx(adapter,
  595. &adapter->tx_ring[ring]);
  596. if (qlcnic_82xx_check(adapter) &&
  597. (adapter->flags & QLCNIC_MSIX_ENABLED) &&
  598. qlcnic_check_multi_tx(adapter) &&
  599. !adapter->ahw->diag_test)
  600. qlcnic_82xx_config_intrpt(adapter, 0);
  601. if (qlcnic_83xx_check(adapter) &&
  602. (adapter->flags & QLCNIC_MSIX_ENABLED)) {
  603. if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
  604. qlcnic_83xx_config_intrpt(adapter, 0);
  605. }
  606. /* Allow dma queues to drain after context reset */
  607. mdelay(20);
  608. }
  609. }
  610. void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter)
  611. {
  612. struct qlcnic_recv_context *recv_ctx;
  613. struct qlcnic_host_rds_ring *rds_ring;
  614. struct qlcnic_host_sds_ring *sds_ring;
  615. struct qlcnic_host_tx_ring *tx_ring;
  616. int ring;
  617. recv_ctx = adapter->recv_ctx;
  618. for (ring = 0; ring < adapter->max_drv_tx_rings; ring++) {
  619. tx_ring = &adapter->tx_ring[ring];
  620. if (tx_ring->hw_consumer != NULL) {
  621. dma_free_coherent(&adapter->pdev->dev, sizeof(u32),
  622. tx_ring->hw_consumer,
  623. tx_ring->hw_cons_phys_addr);
  624. tx_ring->hw_consumer = NULL;
  625. }
  626. if (tx_ring->desc_head != NULL) {
  627. dma_free_coherent(&adapter->pdev->dev,
  628. TX_DESC_RINGSIZE(tx_ring),
  629. tx_ring->desc_head,
  630. tx_ring->phys_addr);
  631. tx_ring->desc_head = NULL;
  632. }
  633. }
  634. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  635. rds_ring = &recv_ctx->rds_rings[ring];
  636. if (rds_ring->desc_head != NULL) {
  637. dma_free_coherent(&adapter->pdev->dev,
  638. RCV_DESC_RINGSIZE(rds_ring),
  639. rds_ring->desc_head,
  640. rds_ring->phys_addr);
  641. rds_ring->desc_head = NULL;
  642. }
  643. }
  644. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  645. sds_ring = &recv_ctx->sds_rings[ring];
  646. if (sds_ring->desc_head != NULL) {
  647. dma_free_coherent(&adapter->pdev->dev,
  648. STATUS_DESC_RINGSIZE(sds_ring),
  649. sds_ring->desc_head,
  650. sds_ring->phys_addr);
  651. sds_ring->desc_head = NULL;
  652. }
  653. }
  654. }
  655. int qlcnic_82xx_config_intrpt(struct qlcnic_adapter *adapter, u8 op_type)
  656. {
  657. struct qlcnic_hardware_context *ahw = adapter->ahw;
  658. struct net_device *netdev = adapter->netdev;
  659. struct qlcnic_cmd_args cmd;
  660. u32 type, val;
  661. int i, err = 0;
  662. for (i = 0; i < ahw->num_msix; i++) {
  663. qlcnic_alloc_mbx_args(&cmd, adapter,
  664. QLCNIC_CMD_MQ_TX_CONFIG_INTR);
  665. type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
  666. val = type | (ahw->intr_tbl[i].type << 4);
  667. if (ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
  668. val |= (ahw->intr_tbl[i].id << 16);
  669. cmd.req.arg[1] = val;
  670. err = qlcnic_issue_cmd(adapter, &cmd);
  671. if (err) {
  672. netdev_err(netdev, "Failed to %s interrupts %d\n",
  673. op_type == QLCNIC_INTRPT_ADD ? "Add" :
  674. "Delete", err);
  675. qlcnic_free_mbx_args(&cmd);
  676. return err;
  677. }
  678. val = cmd.rsp.arg[1];
  679. if (LSB(val)) {
  680. netdev_info(netdev,
  681. "failed to configure interrupt for %d\n",
  682. ahw->intr_tbl[i].id);
  683. continue;
  684. }
  685. if (op_type) {
  686. ahw->intr_tbl[i].id = MSW(val);
  687. ahw->intr_tbl[i].enabled = 1;
  688. ahw->intr_tbl[i].src = cmd.rsp.arg[2];
  689. } else {
  690. ahw->intr_tbl[i].id = i;
  691. ahw->intr_tbl[i].enabled = 0;
  692. ahw->intr_tbl[i].src = 0;
  693. }
  694. qlcnic_free_mbx_args(&cmd);
  695. }
  696. return err;
  697. }
  698. int qlcnic_82xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
  699. u8 function)
  700. {
  701. int err, i;
  702. struct qlcnic_cmd_args cmd;
  703. u32 mac_low, mac_high;
  704. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
  705. if (err)
  706. return err;
  707. cmd.req.arg[1] = function | BIT_8;
  708. err = qlcnic_issue_cmd(adapter, &cmd);
  709. if (err == QLCNIC_RCODE_SUCCESS) {
  710. mac_low = cmd.rsp.arg[1];
  711. mac_high = cmd.rsp.arg[2];
  712. for (i = 0; i < 2; i++)
  713. mac[i] = (u8) (mac_high >> ((1 - i) * 8));
  714. for (i = 2; i < 6; i++)
  715. mac[i] = (u8) (mac_low >> ((5 - i) * 8));
  716. } else {
  717. dev_err(&adapter->pdev->dev,
  718. "Failed to get mac address%d\n", err);
  719. err = -EIO;
  720. }
  721. qlcnic_free_mbx_args(&cmd);
  722. return err;
  723. }
  724. /* Get info of a NIC partition */
  725. int qlcnic_82xx_get_nic_info(struct qlcnic_adapter *adapter,
  726. struct qlcnic_info *npar_info, u8 func_id)
  727. {
  728. int err;
  729. dma_addr_t nic_dma_t;
  730. const struct qlcnic_info_le *nic_info;
  731. void *nic_info_addr;
  732. struct qlcnic_cmd_args cmd;
  733. size_t nic_size = sizeof(struct qlcnic_info_le);
  734. nic_info_addr = dma_zalloc_coherent(&adapter->pdev->dev, nic_size,
  735. &nic_dma_t, GFP_KERNEL);
  736. if (!nic_info_addr)
  737. return -ENOMEM;
  738. nic_info = nic_info_addr;
  739. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
  740. if (err)
  741. goto out_free_dma;
  742. cmd.req.arg[1] = MSD(nic_dma_t);
  743. cmd.req.arg[2] = LSD(nic_dma_t);
  744. cmd.req.arg[3] = (func_id << 16 | nic_size);
  745. err = qlcnic_issue_cmd(adapter, &cmd);
  746. if (err != QLCNIC_RCODE_SUCCESS) {
  747. dev_err(&adapter->pdev->dev,
  748. "Failed to get nic info%d\n", err);
  749. err = -EIO;
  750. } else {
  751. npar_info->pci_func = le16_to_cpu(nic_info->pci_func);
  752. npar_info->op_mode = le16_to_cpu(nic_info->op_mode);
  753. npar_info->min_tx_bw = le16_to_cpu(nic_info->min_tx_bw);
  754. npar_info->max_tx_bw = le16_to_cpu(nic_info->max_tx_bw);
  755. npar_info->phys_port = le16_to_cpu(nic_info->phys_port);
  756. npar_info->switch_mode = le16_to_cpu(nic_info->switch_mode);
  757. npar_info->max_tx_ques = le16_to_cpu(nic_info->max_tx_ques);
  758. npar_info->max_rx_ques = le16_to_cpu(nic_info->max_rx_ques);
  759. npar_info->capabilities = le32_to_cpu(nic_info->capabilities);
  760. npar_info->max_mtu = le16_to_cpu(nic_info->max_mtu);
  761. }
  762. qlcnic_free_mbx_args(&cmd);
  763. out_free_dma:
  764. dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
  765. nic_dma_t);
  766. return err;
  767. }
  768. /* Configure a NIC partition */
  769. int qlcnic_82xx_set_nic_info(struct qlcnic_adapter *adapter,
  770. struct qlcnic_info *nic)
  771. {
  772. int err = -EIO;
  773. dma_addr_t nic_dma_t;
  774. void *nic_info_addr;
  775. struct qlcnic_cmd_args cmd;
  776. struct qlcnic_info_le *nic_info;
  777. size_t nic_size = sizeof(struct qlcnic_info_le);
  778. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  779. return err;
  780. nic_info_addr = dma_zalloc_coherent(&adapter->pdev->dev, nic_size,
  781. &nic_dma_t, GFP_KERNEL);
  782. if (!nic_info_addr)
  783. return -ENOMEM;
  784. nic_info = nic_info_addr;
  785. nic_info->pci_func = cpu_to_le16(nic->pci_func);
  786. nic_info->op_mode = cpu_to_le16(nic->op_mode);
  787. nic_info->phys_port = cpu_to_le16(nic->phys_port);
  788. nic_info->switch_mode = cpu_to_le16(nic->switch_mode);
  789. nic_info->capabilities = cpu_to_le32(nic->capabilities);
  790. nic_info->max_mac_filters = nic->max_mac_filters;
  791. nic_info->max_tx_ques = cpu_to_le16(nic->max_tx_ques);
  792. nic_info->max_rx_ques = cpu_to_le16(nic->max_rx_ques);
  793. nic_info->min_tx_bw = cpu_to_le16(nic->min_tx_bw);
  794. nic_info->max_tx_bw = cpu_to_le16(nic->max_tx_bw);
  795. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
  796. if (err)
  797. goto out_free_dma;
  798. cmd.req.arg[1] = MSD(nic_dma_t);
  799. cmd.req.arg[2] = LSD(nic_dma_t);
  800. cmd.req.arg[3] = ((nic->pci_func << 16) | nic_size);
  801. err = qlcnic_issue_cmd(adapter, &cmd);
  802. if (err != QLCNIC_RCODE_SUCCESS) {
  803. dev_err(&adapter->pdev->dev,
  804. "Failed to set nic info%d\n", err);
  805. err = -EIO;
  806. }
  807. qlcnic_free_mbx_args(&cmd);
  808. out_free_dma:
  809. dma_free_coherent(&adapter->pdev->dev, nic_size, nic_info_addr,
  810. nic_dma_t);
  811. return err;
  812. }
  813. /* Get PCI Info of a partition */
  814. int qlcnic_82xx_get_pci_info(struct qlcnic_adapter *adapter,
  815. struct qlcnic_pci_info *pci_info)
  816. {
  817. int err = 0, i;
  818. struct qlcnic_cmd_args cmd;
  819. dma_addr_t pci_info_dma_t;
  820. struct qlcnic_pci_info_le *npar;
  821. void *pci_info_addr;
  822. size_t npar_size = sizeof(struct qlcnic_pci_info_le);
  823. size_t pci_size = npar_size * QLCNIC_MAX_PCI_FUNC;
  824. pci_info_addr = dma_zalloc_coherent(&adapter->pdev->dev, pci_size,
  825. &pci_info_dma_t, GFP_KERNEL);
  826. if (!pci_info_addr)
  827. return -ENOMEM;
  828. npar = pci_info_addr;
  829. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
  830. if (err)
  831. goto out_free_dma;
  832. cmd.req.arg[1] = MSD(pci_info_dma_t);
  833. cmd.req.arg[2] = LSD(pci_info_dma_t);
  834. cmd.req.arg[3] = pci_size;
  835. err = qlcnic_issue_cmd(adapter, &cmd);
  836. adapter->ahw->act_pci_func = 0;
  837. if (err == QLCNIC_RCODE_SUCCESS) {
  838. for (i = 0; i < QLCNIC_MAX_PCI_FUNC; i++, npar++, pci_info++) {
  839. pci_info->id = le16_to_cpu(npar->id);
  840. pci_info->active = le16_to_cpu(npar->active);
  841. pci_info->type = le16_to_cpu(npar->type);
  842. if (pci_info->type == QLCNIC_TYPE_NIC)
  843. adapter->ahw->act_pci_func++;
  844. pci_info->default_port =
  845. le16_to_cpu(npar->default_port);
  846. pci_info->tx_min_bw =
  847. le16_to_cpu(npar->tx_min_bw);
  848. pci_info->tx_max_bw =
  849. le16_to_cpu(npar->tx_max_bw);
  850. memcpy(pci_info->mac, npar->mac, ETH_ALEN);
  851. }
  852. } else {
  853. dev_err(&adapter->pdev->dev,
  854. "Failed to get PCI Info%d\n", err);
  855. err = -EIO;
  856. }
  857. qlcnic_free_mbx_args(&cmd);
  858. out_free_dma:
  859. dma_free_coherent(&adapter->pdev->dev, pci_size, pci_info_addr,
  860. pci_info_dma_t);
  861. return err;
  862. }
  863. /* Configure eSwitch for port mirroring */
  864. int qlcnic_config_port_mirroring(struct qlcnic_adapter *adapter, u8 id,
  865. u8 enable_mirroring, u8 pci_func)
  866. {
  867. struct device *dev = &adapter->pdev->dev;
  868. struct qlcnic_cmd_args cmd;
  869. int err = -EIO;
  870. u32 arg1;
  871. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC ||
  872. !(adapter->eswitch[id].flags & QLCNIC_SWITCH_ENABLE))
  873. return err;
  874. arg1 = id | (enable_mirroring ? BIT_4 : 0);
  875. arg1 |= pci_func << 8;
  876. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  877. QLCNIC_CMD_SET_PORTMIRRORING);
  878. if (err)
  879. return err;
  880. cmd.req.arg[1] = arg1;
  881. err = qlcnic_issue_cmd(adapter, &cmd);
  882. if (err != QLCNIC_RCODE_SUCCESS)
  883. dev_err(dev, "Failed to configure port mirroring for vNIC function %d on eSwitch %d\n",
  884. pci_func, id);
  885. else
  886. dev_info(dev, "Configured port mirroring for vNIC function %d on eSwitch %d\n",
  887. pci_func, id);
  888. qlcnic_free_mbx_args(&cmd);
  889. return err;
  890. }
  891. int qlcnic_get_port_stats(struct qlcnic_adapter *adapter, const u8 func,
  892. const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
  893. size_t stats_size = sizeof(struct qlcnic_esw_stats_le);
  894. struct qlcnic_esw_stats_le *stats;
  895. dma_addr_t stats_dma_t;
  896. void *stats_addr;
  897. u32 arg1;
  898. struct qlcnic_cmd_args cmd;
  899. int err;
  900. if (esw_stats == NULL)
  901. return -ENOMEM;
  902. if ((adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) &&
  903. (func != adapter->ahw->pci_func)) {
  904. dev_err(&adapter->pdev->dev,
  905. "Not privilege to query stats for func=%d", func);
  906. return -EIO;
  907. }
  908. stats_addr = dma_zalloc_coherent(&adapter->pdev->dev, stats_size,
  909. &stats_dma_t, GFP_KERNEL);
  910. if (!stats_addr)
  911. return -ENOMEM;
  912. arg1 = func | QLCNIC_STATS_VERSION << 8 | QLCNIC_STATS_PORT << 12;
  913. arg1 |= rx_tx << 15 | stats_size << 16;
  914. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  915. QLCNIC_CMD_GET_ESWITCH_STATS);
  916. if (err)
  917. goto out_free_dma;
  918. cmd.req.arg[1] = arg1;
  919. cmd.req.arg[2] = MSD(stats_dma_t);
  920. cmd.req.arg[3] = LSD(stats_dma_t);
  921. err = qlcnic_issue_cmd(adapter, &cmd);
  922. if (!err) {
  923. stats = stats_addr;
  924. esw_stats->context_id = le16_to_cpu(stats->context_id);
  925. esw_stats->version = le16_to_cpu(stats->version);
  926. esw_stats->size = le16_to_cpu(stats->size);
  927. esw_stats->multicast_frames =
  928. le64_to_cpu(stats->multicast_frames);
  929. esw_stats->broadcast_frames =
  930. le64_to_cpu(stats->broadcast_frames);
  931. esw_stats->unicast_frames = le64_to_cpu(stats->unicast_frames);
  932. esw_stats->dropped_frames = le64_to_cpu(stats->dropped_frames);
  933. esw_stats->local_frames = le64_to_cpu(stats->local_frames);
  934. esw_stats->errors = le64_to_cpu(stats->errors);
  935. esw_stats->numbytes = le64_to_cpu(stats->numbytes);
  936. }
  937. qlcnic_free_mbx_args(&cmd);
  938. out_free_dma:
  939. dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
  940. stats_dma_t);
  941. return err;
  942. }
  943. /* This routine will retrieve the MAC statistics from firmware */
  944. int qlcnic_get_mac_stats(struct qlcnic_adapter *adapter,
  945. struct qlcnic_mac_statistics *mac_stats)
  946. {
  947. struct qlcnic_mac_statistics_le *stats;
  948. struct qlcnic_cmd_args cmd;
  949. size_t stats_size = sizeof(struct qlcnic_mac_statistics_le);
  950. dma_addr_t stats_dma_t;
  951. void *stats_addr;
  952. int err;
  953. if (mac_stats == NULL)
  954. return -ENOMEM;
  955. stats_addr = dma_zalloc_coherent(&adapter->pdev->dev, stats_size,
  956. &stats_dma_t, GFP_KERNEL);
  957. if (!stats_addr)
  958. return -ENOMEM;
  959. err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_MAC_STATS);
  960. if (err)
  961. goto out_free_dma;
  962. cmd.req.arg[1] = stats_size << 16;
  963. cmd.req.arg[2] = MSD(stats_dma_t);
  964. cmd.req.arg[3] = LSD(stats_dma_t);
  965. err = qlcnic_issue_cmd(adapter, &cmd);
  966. if (!err) {
  967. stats = stats_addr;
  968. mac_stats->mac_tx_frames = le64_to_cpu(stats->mac_tx_frames);
  969. mac_stats->mac_tx_bytes = le64_to_cpu(stats->mac_tx_bytes);
  970. mac_stats->mac_tx_mcast_pkts =
  971. le64_to_cpu(stats->mac_tx_mcast_pkts);
  972. mac_stats->mac_tx_bcast_pkts =
  973. le64_to_cpu(stats->mac_tx_bcast_pkts);
  974. mac_stats->mac_rx_frames = le64_to_cpu(stats->mac_rx_frames);
  975. mac_stats->mac_rx_bytes = le64_to_cpu(stats->mac_rx_bytes);
  976. mac_stats->mac_rx_mcast_pkts =
  977. le64_to_cpu(stats->mac_rx_mcast_pkts);
  978. mac_stats->mac_rx_length_error =
  979. le64_to_cpu(stats->mac_rx_length_error);
  980. mac_stats->mac_rx_length_small =
  981. le64_to_cpu(stats->mac_rx_length_small);
  982. mac_stats->mac_rx_length_large =
  983. le64_to_cpu(stats->mac_rx_length_large);
  984. mac_stats->mac_rx_jabber = le64_to_cpu(stats->mac_rx_jabber);
  985. mac_stats->mac_rx_dropped = le64_to_cpu(stats->mac_rx_dropped);
  986. mac_stats->mac_rx_crc_error = le64_to_cpu(stats->mac_rx_crc_error);
  987. } else {
  988. dev_err(&adapter->pdev->dev,
  989. "%s: Get mac stats failed, err=%d.\n", __func__, err);
  990. }
  991. qlcnic_free_mbx_args(&cmd);
  992. out_free_dma:
  993. dma_free_coherent(&adapter->pdev->dev, stats_size, stats_addr,
  994. stats_dma_t);
  995. return err;
  996. }
  997. int qlcnic_get_eswitch_stats(struct qlcnic_adapter *adapter, const u8 eswitch,
  998. const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) {
  999. struct __qlcnic_esw_statistics port_stats;
  1000. u8 i;
  1001. int ret = -EIO;
  1002. if (esw_stats == NULL)
  1003. return -ENOMEM;
  1004. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  1005. return -EIO;
  1006. if (adapter->npars == NULL)
  1007. return -EIO;
  1008. memset(esw_stats, 0, sizeof(u64));
  1009. esw_stats->unicast_frames = QLCNIC_STATS_NOT_AVAIL;
  1010. esw_stats->multicast_frames = QLCNIC_STATS_NOT_AVAIL;
  1011. esw_stats->broadcast_frames = QLCNIC_STATS_NOT_AVAIL;
  1012. esw_stats->dropped_frames = QLCNIC_STATS_NOT_AVAIL;
  1013. esw_stats->errors = QLCNIC_STATS_NOT_AVAIL;
  1014. esw_stats->local_frames = QLCNIC_STATS_NOT_AVAIL;
  1015. esw_stats->numbytes = QLCNIC_STATS_NOT_AVAIL;
  1016. esw_stats->context_id = eswitch;
  1017. for (i = 0; i < adapter->ahw->act_pci_func; i++) {
  1018. if (adapter->npars[i].phy_port != eswitch)
  1019. continue;
  1020. memset(&port_stats, 0, sizeof(struct __qlcnic_esw_statistics));
  1021. if (qlcnic_get_port_stats(adapter, adapter->npars[i].pci_func,
  1022. rx_tx, &port_stats))
  1023. continue;
  1024. esw_stats->size = port_stats.size;
  1025. esw_stats->version = port_stats.version;
  1026. QLCNIC_ADD_ESW_STATS(esw_stats->unicast_frames,
  1027. port_stats.unicast_frames);
  1028. QLCNIC_ADD_ESW_STATS(esw_stats->multicast_frames,
  1029. port_stats.multicast_frames);
  1030. QLCNIC_ADD_ESW_STATS(esw_stats->broadcast_frames,
  1031. port_stats.broadcast_frames);
  1032. QLCNIC_ADD_ESW_STATS(esw_stats->dropped_frames,
  1033. port_stats.dropped_frames);
  1034. QLCNIC_ADD_ESW_STATS(esw_stats->errors,
  1035. port_stats.errors);
  1036. QLCNIC_ADD_ESW_STATS(esw_stats->local_frames,
  1037. port_stats.local_frames);
  1038. QLCNIC_ADD_ESW_STATS(esw_stats->numbytes,
  1039. port_stats.numbytes);
  1040. ret = 0;
  1041. }
  1042. return ret;
  1043. }
  1044. int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, const u8 func_esw,
  1045. const u8 port, const u8 rx_tx)
  1046. {
  1047. int err;
  1048. u32 arg1;
  1049. struct qlcnic_cmd_args cmd;
  1050. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  1051. return -EIO;
  1052. if (func_esw == QLCNIC_STATS_PORT) {
  1053. if (port >= QLCNIC_MAX_PCI_FUNC)
  1054. goto err_ret;
  1055. } else if (func_esw == QLCNIC_STATS_ESWITCH) {
  1056. if (port >= QLCNIC_NIU_MAX_XG_PORTS)
  1057. goto err_ret;
  1058. } else {
  1059. goto err_ret;
  1060. }
  1061. if (rx_tx > QLCNIC_QUERY_TX_COUNTER)
  1062. goto err_ret;
  1063. arg1 = port | QLCNIC_STATS_VERSION << 8 | func_esw << 12;
  1064. arg1 |= BIT_14 | rx_tx << 15;
  1065. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  1066. QLCNIC_CMD_GET_ESWITCH_STATS);
  1067. if (err)
  1068. return err;
  1069. cmd.req.arg[1] = arg1;
  1070. err = qlcnic_issue_cmd(adapter, &cmd);
  1071. qlcnic_free_mbx_args(&cmd);
  1072. return err;
  1073. err_ret:
  1074. dev_err(&adapter->pdev->dev,
  1075. "Invalid args func_esw %d port %d rx_ctx %d\n",
  1076. func_esw, port, rx_tx);
  1077. return -EIO;
  1078. }
  1079. static int __qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
  1080. u32 *arg1, u32 *arg2)
  1081. {
  1082. struct device *dev = &adapter->pdev->dev;
  1083. struct qlcnic_cmd_args cmd;
  1084. u8 pci_func = *arg1 >> 8;
  1085. int err;
  1086. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  1087. QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG);
  1088. if (err)
  1089. return err;
  1090. cmd.req.arg[1] = *arg1;
  1091. err = qlcnic_issue_cmd(adapter, &cmd);
  1092. *arg1 = cmd.rsp.arg[1];
  1093. *arg2 = cmd.rsp.arg[2];
  1094. qlcnic_free_mbx_args(&cmd);
  1095. if (err == QLCNIC_RCODE_SUCCESS)
  1096. dev_info(dev, "Get eSwitch port config for vNIC function %d\n",
  1097. pci_func);
  1098. else
  1099. dev_err(dev, "Failed to get eswitch port config for vNIC function %d\n",
  1100. pci_func);
  1101. return err;
  1102. }
  1103. /* Configure eSwitch port
  1104. op_mode = 0 for setting default port behavior
  1105. op_mode = 1 for setting vlan id
  1106. op_mode = 2 for deleting vlan id
  1107. op_type = 0 for vlan_id
  1108. op_type = 1 for port vlan_id
  1109. */
  1110. int qlcnic_config_switch_port(struct qlcnic_adapter *adapter,
  1111. struct qlcnic_esw_func_cfg *esw_cfg)
  1112. {
  1113. struct device *dev = &adapter->pdev->dev;
  1114. struct qlcnic_cmd_args cmd;
  1115. int err = -EIO, index;
  1116. u32 arg1, arg2 = 0;
  1117. u8 pci_func;
  1118. if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC)
  1119. return err;
  1120. pci_func = esw_cfg->pci_func;
  1121. index = qlcnic_is_valid_nic_func(adapter, pci_func);
  1122. if (index < 0)
  1123. return err;
  1124. arg1 = (adapter->npars[index].phy_port & BIT_0);
  1125. arg1 |= (pci_func << 8);
  1126. if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
  1127. return err;
  1128. arg1 &= ~(0x0ff << 8);
  1129. arg1 |= (pci_func << 8);
  1130. arg1 &= ~(BIT_2 | BIT_3);
  1131. switch (esw_cfg->op_mode) {
  1132. case QLCNIC_PORT_DEFAULTS:
  1133. arg1 |= (BIT_4 | BIT_6 | BIT_7);
  1134. arg2 |= (BIT_0 | BIT_1);
  1135. if (adapter->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO)
  1136. arg2 |= (BIT_2 | BIT_3);
  1137. if (!(esw_cfg->discard_tagged))
  1138. arg1 &= ~BIT_4;
  1139. if (!(esw_cfg->promisc_mode))
  1140. arg1 &= ~BIT_6;
  1141. if (!(esw_cfg->mac_override))
  1142. arg1 &= ~BIT_7;
  1143. if (!(esw_cfg->mac_anti_spoof))
  1144. arg2 &= ~BIT_0;
  1145. if (!(esw_cfg->offload_flags & BIT_0))
  1146. arg2 &= ~(BIT_1 | BIT_2 | BIT_3);
  1147. if (!(esw_cfg->offload_flags & BIT_1))
  1148. arg2 &= ~BIT_2;
  1149. if (!(esw_cfg->offload_flags & BIT_2))
  1150. arg2 &= ~BIT_3;
  1151. break;
  1152. case QLCNIC_ADD_VLAN:
  1153. arg1 |= (BIT_2 | BIT_5);
  1154. arg1 |= (esw_cfg->vlan_id << 16);
  1155. break;
  1156. case QLCNIC_DEL_VLAN:
  1157. arg1 |= (BIT_3 | BIT_5);
  1158. arg1 &= ~(0x0ffff << 16);
  1159. break;
  1160. default:
  1161. return err;
  1162. }
  1163. err = qlcnic_alloc_mbx_args(&cmd, adapter,
  1164. QLCNIC_CMD_CONFIGURE_ESWITCH);
  1165. if (err)
  1166. return err;
  1167. cmd.req.arg[1] = arg1;
  1168. cmd.req.arg[2] = arg2;
  1169. err = qlcnic_issue_cmd(adapter, &cmd);
  1170. qlcnic_free_mbx_args(&cmd);
  1171. if (err != QLCNIC_RCODE_SUCCESS)
  1172. dev_err(dev, "Failed to configure eswitch for vNIC function %d\n",
  1173. pci_func);
  1174. else
  1175. dev_info(dev, "Configured eSwitch for vNIC function %d\n",
  1176. pci_func);
  1177. return err;
  1178. }
  1179. int
  1180. qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter,
  1181. struct qlcnic_esw_func_cfg *esw_cfg)
  1182. {
  1183. u32 arg1, arg2;
  1184. int index;
  1185. u8 phy_port;
  1186. if (adapter->ahw->op_mode == QLCNIC_MGMT_FUNC) {
  1187. index = qlcnic_is_valid_nic_func(adapter, esw_cfg->pci_func);
  1188. if (index < 0)
  1189. return -EIO;
  1190. phy_port = adapter->npars[index].phy_port;
  1191. } else {
  1192. phy_port = adapter->ahw->physical_port;
  1193. }
  1194. arg1 = phy_port;
  1195. arg1 |= (esw_cfg->pci_func << 8);
  1196. if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2))
  1197. return -EIO;
  1198. esw_cfg->discard_tagged = !!(arg1 & BIT_4);
  1199. esw_cfg->host_vlan_tag = !!(arg1 & BIT_5);
  1200. esw_cfg->promisc_mode = !!(arg1 & BIT_6);
  1201. esw_cfg->mac_override = !!(arg1 & BIT_7);
  1202. esw_cfg->vlan_id = LSW(arg1 >> 16);
  1203. esw_cfg->mac_anti_spoof = (arg2 & 0x1);
  1204. esw_cfg->offload_flags = ((arg2 >> 1) & 0x7);
  1205. return 0;
  1206. }