bna_tx_rx.c 92 KB

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  1. /*
  2. * Linux network driver for Brocade Converged Network Adapter.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License (GPL) Version 2 as
  6. * published by the Free Software Foundation
  7. *
  8. * This program is distributed in the hope that it will be useful, but
  9. * WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  11. * General Public License for more details.
  12. */
  13. /*
  14. * Copyright (c) 2005-2011 Brocade Communications Systems, Inc.
  15. * All rights reserved
  16. * www.brocade.com
  17. */
  18. #include "bna.h"
  19. #include "bfi.h"
  20. /* IB */
  21. static void
  22. bna_ib_coalescing_timeo_set(struct bna_ib *ib, u8 coalescing_timeo)
  23. {
  24. ib->coalescing_timeo = coalescing_timeo;
  25. ib->door_bell.doorbell_ack = BNA_DOORBELL_IB_INT_ACK(
  26. (u32)ib->coalescing_timeo, 0);
  27. }
  28. /* RXF */
  29. #define bna_rxf_vlan_cfg_soft_reset(rxf) \
  30. do { \
  31. (rxf)->vlan_pending_bitmask = (u8)BFI_VLAN_BMASK_ALL; \
  32. (rxf)->vlan_strip_pending = true; \
  33. } while (0)
  34. #define bna_rxf_rss_cfg_soft_reset(rxf) \
  35. do { \
  36. if ((rxf)->rss_status == BNA_STATUS_T_ENABLED) \
  37. (rxf)->rss_pending = (BNA_RSS_F_RIT_PENDING | \
  38. BNA_RSS_F_CFG_PENDING | \
  39. BNA_RSS_F_STATUS_PENDING); \
  40. } while (0)
  41. static int bna_rxf_cfg_apply(struct bna_rxf *rxf);
  42. static void bna_rxf_cfg_reset(struct bna_rxf *rxf);
  43. static int bna_rxf_fltr_clear(struct bna_rxf *rxf);
  44. static int bna_rxf_ucast_cfg_apply(struct bna_rxf *rxf);
  45. static int bna_rxf_promisc_cfg_apply(struct bna_rxf *rxf);
  46. static int bna_rxf_allmulti_cfg_apply(struct bna_rxf *rxf);
  47. static int bna_rxf_vlan_strip_cfg_apply(struct bna_rxf *rxf);
  48. static int bna_rxf_ucast_cfg_reset(struct bna_rxf *rxf,
  49. enum bna_cleanup_type cleanup);
  50. static int bna_rxf_promisc_cfg_reset(struct bna_rxf *rxf,
  51. enum bna_cleanup_type cleanup);
  52. static int bna_rxf_allmulti_cfg_reset(struct bna_rxf *rxf,
  53. enum bna_cleanup_type cleanup);
  54. bfa_fsm_state_decl(bna_rxf, stopped, struct bna_rxf,
  55. enum bna_rxf_event);
  56. bfa_fsm_state_decl(bna_rxf, paused, struct bna_rxf,
  57. enum bna_rxf_event);
  58. bfa_fsm_state_decl(bna_rxf, cfg_wait, struct bna_rxf,
  59. enum bna_rxf_event);
  60. bfa_fsm_state_decl(bna_rxf, started, struct bna_rxf,
  61. enum bna_rxf_event);
  62. bfa_fsm_state_decl(bna_rxf, fltr_clr_wait, struct bna_rxf,
  63. enum bna_rxf_event);
  64. bfa_fsm_state_decl(bna_rxf, last_resp_wait, struct bna_rxf,
  65. enum bna_rxf_event);
  66. static void
  67. bna_rxf_sm_stopped_entry(struct bna_rxf *rxf)
  68. {
  69. call_rxf_stop_cbfn(rxf);
  70. }
  71. static void
  72. bna_rxf_sm_stopped(struct bna_rxf *rxf, enum bna_rxf_event event)
  73. {
  74. switch (event) {
  75. case RXF_E_START:
  76. if (rxf->flags & BNA_RXF_F_PAUSED) {
  77. bfa_fsm_set_state(rxf, bna_rxf_sm_paused);
  78. call_rxf_start_cbfn(rxf);
  79. } else
  80. bfa_fsm_set_state(rxf, bna_rxf_sm_cfg_wait);
  81. break;
  82. case RXF_E_STOP:
  83. call_rxf_stop_cbfn(rxf);
  84. break;
  85. case RXF_E_FAIL:
  86. /* No-op */
  87. break;
  88. case RXF_E_CONFIG:
  89. call_rxf_cam_fltr_cbfn(rxf);
  90. break;
  91. case RXF_E_PAUSE:
  92. rxf->flags |= BNA_RXF_F_PAUSED;
  93. call_rxf_pause_cbfn(rxf);
  94. break;
  95. case RXF_E_RESUME:
  96. rxf->flags &= ~BNA_RXF_F_PAUSED;
  97. call_rxf_resume_cbfn(rxf);
  98. break;
  99. default:
  100. bfa_sm_fault(event);
  101. }
  102. }
  103. static void
  104. bna_rxf_sm_paused_entry(struct bna_rxf *rxf)
  105. {
  106. call_rxf_pause_cbfn(rxf);
  107. }
  108. static void
  109. bna_rxf_sm_paused(struct bna_rxf *rxf, enum bna_rxf_event event)
  110. {
  111. switch (event) {
  112. case RXF_E_STOP:
  113. case RXF_E_FAIL:
  114. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  115. break;
  116. case RXF_E_CONFIG:
  117. call_rxf_cam_fltr_cbfn(rxf);
  118. break;
  119. case RXF_E_RESUME:
  120. rxf->flags &= ~BNA_RXF_F_PAUSED;
  121. bfa_fsm_set_state(rxf, bna_rxf_sm_cfg_wait);
  122. break;
  123. default:
  124. bfa_sm_fault(event);
  125. }
  126. }
  127. static void
  128. bna_rxf_sm_cfg_wait_entry(struct bna_rxf *rxf)
  129. {
  130. if (!bna_rxf_cfg_apply(rxf)) {
  131. /* No more pending config updates */
  132. bfa_fsm_set_state(rxf, bna_rxf_sm_started);
  133. }
  134. }
  135. static void
  136. bna_rxf_sm_cfg_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  137. {
  138. switch (event) {
  139. case RXF_E_STOP:
  140. bfa_fsm_set_state(rxf, bna_rxf_sm_last_resp_wait);
  141. break;
  142. case RXF_E_FAIL:
  143. bna_rxf_cfg_reset(rxf);
  144. call_rxf_start_cbfn(rxf);
  145. call_rxf_cam_fltr_cbfn(rxf);
  146. call_rxf_resume_cbfn(rxf);
  147. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  148. break;
  149. case RXF_E_CONFIG:
  150. /* No-op */
  151. break;
  152. case RXF_E_PAUSE:
  153. rxf->flags |= BNA_RXF_F_PAUSED;
  154. call_rxf_start_cbfn(rxf);
  155. bfa_fsm_set_state(rxf, bna_rxf_sm_fltr_clr_wait);
  156. break;
  157. case RXF_E_FW_RESP:
  158. if (!bna_rxf_cfg_apply(rxf)) {
  159. /* No more pending config updates */
  160. bfa_fsm_set_state(rxf, bna_rxf_sm_started);
  161. }
  162. break;
  163. default:
  164. bfa_sm_fault(event);
  165. }
  166. }
  167. static void
  168. bna_rxf_sm_started_entry(struct bna_rxf *rxf)
  169. {
  170. call_rxf_start_cbfn(rxf);
  171. call_rxf_cam_fltr_cbfn(rxf);
  172. call_rxf_resume_cbfn(rxf);
  173. }
  174. static void
  175. bna_rxf_sm_started(struct bna_rxf *rxf, enum bna_rxf_event event)
  176. {
  177. switch (event) {
  178. case RXF_E_STOP:
  179. case RXF_E_FAIL:
  180. bna_rxf_cfg_reset(rxf);
  181. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  182. break;
  183. case RXF_E_CONFIG:
  184. bfa_fsm_set_state(rxf, bna_rxf_sm_cfg_wait);
  185. break;
  186. case RXF_E_PAUSE:
  187. rxf->flags |= BNA_RXF_F_PAUSED;
  188. if (!bna_rxf_fltr_clear(rxf))
  189. bfa_fsm_set_state(rxf, bna_rxf_sm_paused);
  190. else
  191. bfa_fsm_set_state(rxf, bna_rxf_sm_fltr_clr_wait);
  192. break;
  193. default:
  194. bfa_sm_fault(event);
  195. }
  196. }
  197. static void
  198. bna_rxf_sm_fltr_clr_wait_entry(struct bna_rxf *rxf)
  199. {
  200. }
  201. static void
  202. bna_rxf_sm_fltr_clr_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  203. {
  204. switch (event) {
  205. case RXF_E_FAIL:
  206. bna_rxf_cfg_reset(rxf);
  207. call_rxf_pause_cbfn(rxf);
  208. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  209. break;
  210. case RXF_E_FW_RESP:
  211. if (!bna_rxf_fltr_clear(rxf)) {
  212. /* No more pending CAM entries to clear */
  213. bfa_fsm_set_state(rxf, bna_rxf_sm_paused);
  214. }
  215. break;
  216. default:
  217. bfa_sm_fault(event);
  218. }
  219. }
  220. static void
  221. bna_rxf_sm_last_resp_wait_entry(struct bna_rxf *rxf)
  222. {
  223. }
  224. static void
  225. bna_rxf_sm_last_resp_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  226. {
  227. switch (event) {
  228. case RXF_E_FAIL:
  229. case RXF_E_FW_RESP:
  230. bna_rxf_cfg_reset(rxf);
  231. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  232. break;
  233. default:
  234. bfa_sm_fault(event);
  235. }
  236. }
  237. static void
  238. bna_bfi_ucast_req(struct bna_rxf *rxf, struct bna_mac *mac,
  239. enum bfi_enet_h2i_msgs req_type)
  240. {
  241. struct bfi_enet_ucast_req *req = &rxf->bfi_enet_cmd.ucast_req;
  242. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET, req_type, 0, rxf->rx->rid);
  243. req->mh.num_entries = htons(
  244. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_ucast_req)));
  245. memcpy(&req->mac_addr, &mac->addr, sizeof(mac_t));
  246. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  247. sizeof(struct bfi_enet_ucast_req), &req->mh);
  248. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  249. }
  250. static void
  251. bna_bfi_mcast_add_req(struct bna_rxf *rxf, struct bna_mac *mac)
  252. {
  253. struct bfi_enet_mcast_add_req *req =
  254. &rxf->bfi_enet_cmd.mcast_add_req;
  255. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET, BFI_ENET_H2I_MAC_MCAST_ADD_REQ,
  256. 0, rxf->rx->rid);
  257. req->mh.num_entries = htons(
  258. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_mcast_add_req)));
  259. memcpy(&req->mac_addr, &mac->addr, sizeof(mac_t));
  260. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  261. sizeof(struct bfi_enet_mcast_add_req), &req->mh);
  262. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  263. }
  264. static void
  265. bna_bfi_mcast_del_req(struct bna_rxf *rxf, u16 handle)
  266. {
  267. struct bfi_enet_mcast_del_req *req =
  268. &rxf->bfi_enet_cmd.mcast_del_req;
  269. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET, BFI_ENET_H2I_MAC_MCAST_DEL_REQ,
  270. 0, rxf->rx->rid);
  271. req->mh.num_entries = htons(
  272. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_mcast_del_req)));
  273. req->handle = htons(handle);
  274. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  275. sizeof(struct bfi_enet_mcast_del_req), &req->mh);
  276. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  277. }
  278. static void
  279. bna_bfi_mcast_filter_req(struct bna_rxf *rxf, enum bna_status status)
  280. {
  281. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  282. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  283. BFI_ENET_H2I_MAC_MCAST_FILTER_REQ, 0, rxf->rx->rid);
  284. req->mh.num_entries = htons(
  285. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  286. req->enable = status;
  287. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  288. sizeof(struct bfi_enet_enable_req), &req->mh);
  289. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  290. }
  291. static void
  292. bna_bfi_rx_promisc_req(struct bna_rxf *rxf, enum bna_status status)
  293. {
  294. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  295. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  296. BFI_ENET_H2I_RX_PROMISCUOUS_REQ, 0, rxf->rx->rid);
  297. req->mh.num_entries = htons(
  298. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  299. req->enable = status;
  300. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  301. sizeof(struct bfi_enet_enable_req), &req->mh);
  302. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  303. }
  304. static void
  305. bna_bfi_rx_vlan_filter_set(struct bna_rxf *rxf, u8 block_idx)
  306. {
  307. struct bfi_enet_rx_vlan_req *req = &rxf->bfi_enet_cmd.vlan_req;
  308. int i;
  309. int j;
  310. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  311. BFI_ENET_H2I_RX_VLAN_SET_REQ, 0, rxf->rx->rid);
  312. req->mh.num_entries = htons(
  313. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rx_vlan_req)));
  314. req->block_idx = block_idx;
  315. for (i = 0; i < (BFI_ENET_VLAN_BLOCK_SIZE / 32); i++) {
  316. j = (block_idx * (BFI_ENET_VLAN_BLOCK_SIZE / 32)) + i;
  317. if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED)
  318. req->bit_mask[i] =
  319. htonl(rxf->vlan_filter_table[j]);
  320. else
  321. req->bit_mask[i] = 0xFFFFFFFF;
  322. }
  323. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  324. sizeof(struct bfi_enet_rx_vlan_req), &req->mh);
  325. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  326. }
  327. static void
  328. bna_bfi_vlan_strip_enable(struct bna_rxf *rxf)
  329. {
  330. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  331. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  332. BFI_ENET_H2I_RX_VLAN_STRIP_ENABLE_REQ, 0, rxf->rx->rid);
  333. req->mh.num_entries = htons(
  334. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  335. req->enable = rxf->vlan_strip_status;
  336. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  337. sizeof(struct bfi_enet_enable_req), &req->mh);
  338. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  339. }
  340. static void
  341. bna_bfi_rit_cfg(struct bna_rxf *rxf)
  342. {
  343. struct bfi_enet_rit_req *req = &rxf->bfi_enet_cmd.rit_req;
  344. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  345. BFI_ENET_H2I_RIT_CFG_REQ, 0, rxf->rx->rid);
  346. req->mh.num_entries = htons(
  347. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rit_req)));
  348. req->size = htons(rxf->rit_size);
  349. memcpy(&req->table[0], rxf->rit, rxf->rit_size);
  350. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  351. sizeof(struct bfi_enet_rit_req), &req->mh);
  352. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  353. }
  354. static void
  355. bna_bfi_rss_cfg(struct bna_rxf *rxf)
  356. {
  357. struct bfi_enet_rss_cfg_req *req = &rxf->bfi_enet_cmd.rss_req;
  358. int i;
  359. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  360. BFI_ENET_H2I_RSS_CFG_REQ, 0, rxf->rx->rid);
  361. req->mh.num_entries = htons(
  362. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rss_cfg_req)));
  363. req->cfg.type = rxf->rss_cfg.hash_type;
  364. req->cfg.mask = rxf->rss_cfg.hash_mask;
  365. for (i = 0; i < BFI_ENET_RSS_KEY_LEN; i++)
  366. req->cfg.key[i] =
  367. htonl(rxf->rss_cfg.toeplitz_hash_key[i]);
  368. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  369. sizeof(struct bfi_enet_rss_cfg_req), &req->mh);
  370. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  371. }
  372. static void
  373. bna_bfi_rss_enable(struct bna_rxf *rxf)
  374. {
  375. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  376. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  377. BFI_ENET_H2I_RSS_ENABLE_REQ, 0, rxf->rx->rid);
  378. req->mh.num_entries = htons(
  379. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  380. req->enable = rxf->rss_status;
  381. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  382. sizeof(struct bfi_enet_enable_req), &req->mh);
  383. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  384. }
  385. /* This function gets the multicast MAC that has already been added to CAM */
  386. static struct bna_mac *
  387. bna_rxf_mcmac_get(struct bna_rxf *rxf, u8 *mac_addr)
  388. {
  389. struct bna_mac *mac;
  390. struct list_head *qe;
  391. list_for_each(qe, &rxf->mcast_active_q) {
  392. mac = (struct bna_mac *)qe;
  393. if (BNA_MAC_IS_EQUAL(&mac->addr, mac_addr))
  394. return mac;
  395. }
  396. list_for_each(qe, &rxf->mcast_pending_del_q) {
  397. mac = (struct bna_mac *)qe;
  398. if (BNA_MAC_IS_EQUAL(&mac->addr, mac_addr))
  399. return mac;
  400. }
  401. return NULL;
  402. }
  403. static struct bna_mcam_handle *
  404. bna_rxf_mchandle_get(struct bna_rxf *rxf, int handle)
  405. {
  406. struct bna_mcam_handle *mchandle;
  407. struct list_head *qe;
  408. list_for_each(qe, &rxf->mcast_handle_q) {
  409. mchandle = (struct bna_mcam_handle *)qe;
  410. if (mchandle->handle == handle)
  411. return mchandle;
  412. }
  413. return NULL;
  414. }
  415. static void
  416. bna_rxf_mchandle_attach(struct bna_rxf *rxf, u8 *mac_addr, int handle)
  417. {
  418. struct bna_mac *mcmac;
  419. struct bna_mcam_handle *mchandle;
  420. mcmac = bna_rxf_mcmac_get(rxf, mac_addr);
  421. mchandle = bna_rxf_mchandle_get(rxf, handle);
  422. if (mchandle == NULL) {
  423. mchandle = bna_mcam_mod_handle_get(&rxf->rx->bna->mcam_mod);
  424. mchandle->handle = handle;
  425. mchandle->refcnt = 0;
  426. list_add_tail(&mchandle->qe, &rxf->mcast_handle_q);
  427. }
  428. mchandle->refcnt++;
  429. mcmac->handle = mchandle;
  430. }
  431. static int
  432. bna_rxf_mcast_del(struct bna_rxf *rxf, struct bna_mac *mac,
  433. enum bna_cleanup_type cleanup)
  434. {
  435. struct bna_mcam_handle *mchandle;
  436. int ret = 0;
  437. mchandle = mac->handle;
  438. if (mchandle == NULL)
  439. return ret;
  440. mchandle->refcnt--;
  441. if (mchandle->refcnt == 0) {
  442. if (cleanup == BNA_HARD_CLEANUP) {
  443. bna_bfi_mcast_del_req(rxf, mchandle->handle);
  444. ret = 1;
  445. }
  446. list_del(&mchandle->qe);
  447. bfa_q_qe_init(&mchandle->qe);
  448. bna_mcam_mod_handle_put(&rxf->rx->bna->mcam_mod, mchandle);
  449. }
  450. mac->handle = NULL;
  451. return ret;
  452. }
  453. static int
  454. bna_rxf_mcast_cfg_apply(struct bna_rxf *rxf)
  455. {
  456. struct bna_mac *mac = NULL;
  457. struct list_head *qe;
  458. int ret;
  459. /* Delete multicast entries previousely added */
  460. while (!list_empty(&rxf->mcast_pending_del_q)) {
  461. bfa_q_deq(&rxf->mcast_pending_del_q, &qe);
  462. bfa_q_qe_init(qe);
  463. mac = (struct bna_mac *)qe;
  464. ret = bna_rxf_mcast_del(rxf, mac, BNA_HARD_CLEANUP);
  465. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  466. if (ret)
  467. return ret;
  468. }
  469. /* Add multicast entries */
  470. if (!list_empty(&rxf->mcast_pending_add_q)) {
  471. bfa_q_deq(&rxf->mcast_pending_add_q, &qe);
  472. bfa_q_qe_init(qe);
  473. mac = (struct bna_mac *)qe;
  474. list_add_tail(&mac->qe, &rxf->mcast_active_q);
  475. bna_bfi_mcast_add_req(rxf, mac);
  476. return 1;
  477. }
  478. return 0;
  479. }
  480. static int
  481. bna_rxf_vlan_cfg_apply(struct bna_rxf *rxf)
  482. {
  483. u8 vlan_pending_bitmask;
  484. int block_idx = 0;
  485. if (rxf->vlan_pending_bitmask) {
  486. vlan_pending_bitmask = rxf->vlan_pending_bitmask;
  487. while (!(vlan_pending_bitmask & 0x1)) {
  488. block_idx++;
  489. vlan_pending_bitmask >>= 1;
  490. }
  491. rxf->vlan_pending_bitmask &= ~(1 << block_idx);
  492. bna_bfi_rx_vlan_filter_set(rxf, block_idx);
  493. return 1;
  494. }
  495. return 0;
  496. }
  497. static int
  498. bna_rxf_mcast_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  499. {
  500. struct list_head *qe;
  501. struct bna_mac *mac;
  502. int ret;
  503. /* Throw away delete pending mcast entries */
  504. while (!list_empty(&rxf->mcast_pending_del_q)) {
  505. bfa_q_deq(&rxf->mcast_pending_del_q, &qe);
  506. bfa_q_qe_init(qe);
  507. mac = (struct bna_mac *)qe;
  508. ret = bna_rxf_mcast_del(rxf, mac, cleanup);
  509. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  510. if (ret)
  511. return ret;
  512. }
  513. /* Move active mcast entries to pending_add_q */
  514. while (!list_empty(&rxf->mcast_active_q)) {
  515. bfa_q_deq(&rxf->mcast_active_q, &qe);
  516. bfa_q_qe_init(qe);
  517. list_add_tail(qe, &rxf->mcast_pending_add_q);
  518. mac = (struct bna_mac *)qe;
  519. if (bna_rxf_mcast_del(rxf, mac, cleanup))
  520. return 1;
  521. }
  522. return 0;
  523. }
  524. static int
  525. bna_rxf_rss_cfg_apply(struct bna_rxf *rxf)
  526. {
  527. if (rxf->rss_pending) {
  528. if (rxf->rss_pending & BNA_RSS_F_RIT_PENDING) {
  529. rxf->rss_pending &= ~BNA_RSS_F_RIT_PENDING;
  530. bna_bfi_rit_cfg(rxf);
  531. return 1;
  532. }
  533. if (rxf->rss_pending & BNA_RSS_F_CFG_PENDING) {
  534. rxf->rss_pending &= ~BNA_RSS_F_CFG_PENDING;
  535. bna_bfi_rss_cfg(rxf);
  536. return 1;
  537. }
  538. if (rxf->rss_pending & BNA_RSS_F_STATUS_PENDING) {
  539. rxf->rss_pending &= ~BNA_RSS_F_STATUS_PENDING;
  540. bna_bfi_rss_enable(rxf);
  541. return 1;
  542. }
  543. }
  544. return 0;
  545. }
  546. static int
  547. bna_rxf_cfg_apply(struct bna_rxf *rxf)
  548. {
  549. if (bna_rxf_ucast_cfg_apply(rxf))
  550. return 1;
  551. if (bna_rxf_mcast_cfg_apply(rxf))
  552. return 1;
  553. if (bna_rxf_promisc_cfg_apply(rxf))
  554. return 1;
  555. if (bna_rxf_allmulti_cfg_apply(rxf))
  556. return 1;
  557. if (bna_rxf_vlan_cfg_apply(rxf))
  558. return 1;
  559. if (bna_rxf_vlan_strip_cfg_apply(rxf))
  560. return 1;
  561. if (bna_rxf_rss_cfg_apply(rxf))
  562. return 1;
  563. return 0;
  564. }
  565. /* Only software reset */
  566. static int
  567. bna_rxf_fltr_clear(struct bna_rxf *rxf)
  568. {
  569. if (bna_rxf_ucast_cfg_reset(rxf, BNA_HARD_CLEANUP))
  570. return 1;
  571. if (bna_rxf_mcast_cfg_reset(rxf, BNA_HARD_CLEANUP))
  572. return 1;
  573. if (bna_rxf_promisc_cfg_reset(rxf, BNA_HARD_CLEANUP))
  574. return 1;
  575. if (bna_rxf_allmulti_cfg_reset(rxf, BNA_HARD_CLEANUP))
  576. return 1;
  577. return 0;
  578. }
  579. static void
  580. bna_rxf_cfg_reset(struct bna_rxf *rxf)
  581. {
  582. bna_rxf_ucast_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  583. bna_rxf_mcast_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  584. bna_rxf_promisc_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  585. bna_rxf_allmulti_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  586. bna_rxf_vlan_cfg_soft_reset(rxf);
  587. bna_rxf_rss_cfg_soft_reset(rxf);
  588. }
  589. static void
  590. bna_rit_init(struct bna_rxf *rxf, int rit_size)
  591. {
  592. struct bna_rx *rx = rxf->rx;
  593. struct bna_rxp *rxp;
  594. struct list_head *qe;
  595. int offset = 0;
  596. rxf->rit_size = rit_size;
  597. list_for_each(qe, &rx->rxp_q) {
  598. rxp = (struct bna_rxp *)qe;
  599. rxf->rit[offset] = rxp->cq.ccb->id;
  600. offset++;
  601. }
  602. }
  603. void
  604. bna_bfi_rxf_cfg_rsp(struct bna_rxf *rxf, struct bfi_msgq_mhdr *msghdr)
  605. {
  606. bfa_fsm_send_event(rxf, RXF_E_FW_RESP);
  607. }
  608. void
  609. bna_bfi_rxf_ucast_set_rsp(struct bna_rxf *rxf,
  610. struct bfi_msgq_mhdr *msghdr)
  611. {
  612. struct bfi_enet_rsp *rsp =
  613. (struct bfi_enet_rsp *)msghdr;
  614. if (rsp->error) {
  615. /* Clear ucast from cache */
  616. rxf->ucast_active_set = 0;
  617. }
  618. bfa_fsm_send_event(rxf, RXF_E_FW_RESP);
  619. }
  620. void
  621. bna_bfi_rxf_mcast_add_rsp(struct bna_rxf *rxf,
  622. struct bfi_msgq_mhdr *msghdr)
  623. {
  624. struct bfi_enet_mcast_add_req *req =
  625. &rxf->bfi_enet_cmd.mcast_add_req;
  626. struct bfi_enet_mcast_add_rsp *rsp =
  627. (struct bfi_enet_mcast_add_rsp *)msghdr;
  628. bna_rxf_mchandle_attach(rxf, (u8 *)&req->mac_addr,
  629. ntohs(rsp->handle));
  630. bfa_fsm_send_event(rxf, RXF_E_FW_RESP);
  631. }
  632. static void
  633. bna_rxf_init(struct bna_rxf *rxf,
  634. struct bna_rx *rx,
  635. struct bna_rx_config *q_config,
  636. struct bna_res_info *res_info)
  637. {
  638. rxf->rx = rx;
  639. INIT_LIST_HEAD(&rxf->ucast_pending_add_q);
  640. INIT_LIST_HEAD(&rxf->ucast_pending_del_q);
  641. rxf->ucast_pending_set = 0;
  642. rxf->ucast_active_set = 0;
  643. INIT_LIST_HEAD(&rxf->ucast_active_q);
  644. rxf->ucast_pending_mac = NULL;
  645. INIT_LIST_HEAD(&rxf->mcast_pending_add_q);
  646. INIT_LIST_HEAD(&rxf->mcast_pending_del_q);
  647. INIT_LIST_HEAD(&rxf->mcast_active_q);
  648. INIT_LIST_HEAD(&rxf->mcast_handle_q);
  649. if (q_config->paused)
  650. rxf->flags |= BNA_RXF_F_PAUSED;
  651. rxf->rit = (u8 *)
  652. res_info[BNA_RX_RES_MEM_T_RIT].res_u.mem_info.mdl[0].kva;
  653. bna_rit_init(rxf, q_config->num_paths);
  654. rxf->rss_status = q_config->rss_status;
  655. if (rxf->rss_status == BNA_STATUS_T_ENABLED) {
  656. rxf->rss_cfg = q_config->rss_config;
  657. rxf->rss_pending |= BNA_RSS_F_CFG_PENDING;
  658. rxf->rss_pending |= BNA_RSS_F_RIT_PENDING;
  659. rxf->rss_pending |= BNA_RSS_F_STATUS_PENDING;
  660. }
  661. rxf->vlan_filter_status = BNA_STATUS_T_DISABLED;
  662. memset(rxf->vlan_filter_table, 0,
  663. (sizeof(u32) * (BFI_ENET_VLAN_ID_MAX / 32)));
  664. rxf->vlan_filter_table[0] |= 1; /* for pure priority tagged frames */
  665. rxf->vlan_pending_bitmask = (u8)BFI_VLAN_BMASK_ALL;
  666. rxf->vlan_strip_status = q_config->vlan_strip_status;
  667. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  668. }
  669. static void
  670. bna_rxf_uninit(struct bna_rxf *rxf)
  671. {
  672. struct bna_mac *mac;
  673. rxf->ucast_pending_set = 0;
  674. rxf->ucast_active_set = 0;
  675. while (!list_empty(&rxf->ucast_pending_add_q)) {
  676. bfa_q_deq(&rxf->ucast_pending_add_q, &mac);
  677. bfa_q_qe_init(&mac->qe);
  678. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  679. }
  680. if (rxf->ucast_pending_mac) {
  681. bfa_q_qe_init(&rxf->ucast_pending_mac->qe);
  682. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod,
  683. rxf->ucast_pending_mac);
  684. rxf->ucast_pending_mac = NULL;
  685. }
  686. while (!list_empty(&rxf->mcast_pending_add_q)) {
  687. bfa_q_deq(&rxf->mcast_pending_add_q, &mac);
  688. bfa_q_qe_init(&mac->qe);
  689. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  690. }
  691. rxf->rxmode_pending = 0;
  692. rxf->rxmode_pending_bitmask = 0;
  693. if (rxf->rx->bna->promisc_rid == rxf->rx->rid)
  694. rxf->rx->bna->promisc_rid = BFI_INVALID_RID;
  695. if (rxf->rx->bna->default_mode_rid == rxf->rx->rid)
  696. rxf->rx->bna->default_mode_rid = BFI_INVALID_RID;
  697. rxf->rss_pending = 0;
  698. rxf->vlan_strip_pending = false;
  699. rxf->flags = 0;
  700. rxf->rx = NULL;
  701. }
  702. static void
  703. bna_rx_cb_rxf_started(struct bna_rx *rx)
  704. {
  705. bfa_fsm_send_event(rx, RX_E_RXF_STARTED);
  706. }
  707. static void
  708. bna_rxf_start(struct bna_rxf *rxf)
  709. {
  710. rxf->start_cbfn = bna_rx_cb_rxf_started;
  711. rxf->start_cbarg = rxf->rx;
  712. bfa_fsm_send_event(rxf, RXF_E_START);
  713. }
  714. static void
  715. bna_rx_cb_rxf_stopped(struct bna_rx *rx)
  716. {
  717. bfa_fsm_send_event(rx, RX_E_RXF_STOPPED);
  718. }
  719. static void
  720. bna_rxf_stop(struct bna_rxf *rxf)
  721. {
  722. rxf->stop_cbfn = bna_rx_cb_rxf_stopped;
  723. rxf->stop_cbarg = rxf->rx;
  724. bfa_fsm_send_event(rxf, RXF_E_STOP);
  725. }
  726. static void
  727. bna_rxf_fail(struct bna_rxf *rxf)
  728. {
  729. bfa_fsm_send_event(rxf, RXF_E_FAIL);
  730. }
  731. enum bna_cb_status
  732. bna_rx_ucast_set(struct bna_rx *rx, u8 *ucmac,
  733. void (*cbfn)(struct bnad *, struct bna_rx *))
  734. {
  735. struct bna_rxf *rxf = &rx->rxf;
  736. if (rxf->ucast_pending_mac == NULL) {
  737. rxf->ucast_pending_mac =
  738. bna_ucam_mod_mac_get(&rxf->rx->bna->ucam_mod);
  739. if (rxf->ucast_pending_mac == NULL)
  740. return BNA_CB_UCAST_CAM_FULL;
  741. bfa_q_qe_init(&rxf->ucast_pending_mac->qe);
  742. }
  743. memcpy(rxf->ucast_pending_mac->addr, ucmac, ETH_ALEN);
  744. rxf->ucast_pending_set = 1;
  745. rxf->cam_fltr_cbfn = cbfn;
  746. rxf->cam_fltr_cbarg = rx->bna->bnad;
  747. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  748. return BNA_CB_SUCCESS;
  749. }
  750. enum bna_cb_status
  751. bna_rx_mcast_add(struct bna_rx *rx, u8 *addr,
  752. void (*cbfn)(struct bnad *, struct bna_rx *))
  753. {
  754. struct bna_rxf *rxf = &rx->rxf;
  755. struct bna_mac *mac;
  756. /* Check if already added or pending addition */
  757. if (bna_mac_find(&rxf->mcast_active_q, addr) ||
  758. bna_mac_find(&rxf->mcast_pending_add_q, addr)) {
  759. if (cbfn)
  760. cbfn(rx->bna->bnad, rx);
  761. return BNA_CB_SUCCESS;
  762. }
  763. mac = bna_mcam_mod_mac_get(&rxf->rx->bna->mcam_mod);
  764. if (mac == NULL)
  765. return BNA_CB_MCAST_LIST_FULL;
  766. bfa_q_qe_init(&mac->qe);
  767. memcpy(mac->addr, addr, ETH_ALEN);
  768. list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
  769. rxf->cam_fltr_cbfn = cbfn;
  770. rxf->cam_fltr_cbarg = rx->bna->bnad;
  771. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  772. return BNA_CB_SUCCESS;
  773. }
  774. enum bna_cb_status
  775. bna_rx_mcast_listset(struct bna_rx *rx, int count, u8 *mclist,
  776. void (*cbfn)(struct bnad *, struct bna_rx *))
  777. {
  778. struct bna_rxf *rxf = &rx->rxf;
  779. struct list_head list_head;
  780. struct list_head *qe;
  781. u8 *mcaddr;
  782. struct bna_mac *mac;
  783. int i;
  784. /* Allocate nodes */
  785. INIT_LIST_HEAD(&list_head);
  786. for (i = 0, mcaddr = mclist; i < count; i++) {
  787. mac = bna_mcam_mod_mac_get(&rxf->rx->bna->mcam_mod);
  788. if (mac == NULL)
  789. goto err_return;
  790. bfa_q_qe_init(&mac->qe);
  791. memcpy(mac->addr, mcaddr, ETH_ALEN);
  792. list_add_tail(&mac->qe, &list_head);
  793. mcaddr += ETH_ALEN;
  794. }
  795. /* Purge the pending_add_q */
  796. while (!list_empty(&rxf->mcast_pending_add_q)) {
  797. bfa_q_deq(&rxf->mcast_pending_add_q, &qe);
  798. bfa_q_qe_init(qe);
  799. mac = (struct bna_mac *)qe;
  800. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  801. }
  802. /* Schedule active_q entries for deletion */
  803. while (!list_empty(&rxf->mcast_active_q)) {
  804. bfa_q_deq(&rxf->mcast_active_q, &qe);
  805. mac = (struct bna_mac *)qe;
  806. bfa_q_qe_init(&mac->qe);
  807. list_add_tail(&mac->qe, &rxf->mcast_pending_del_q);
  808. }
  809. /* Add the new entries */
  810. while (!list_empty(&list_head)) {
  811. bfa_q_deq(&list_head, &qe);
  812. mac = (struct bna_mac *)qe;
  813. bfa_q_qe_init(&mac->qe);
  814. list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
  815. }
  816. rxf->cam_fltr_cbfn = cbfn;
  817. rxf->cam_fltr_cbarg = rx->bna->bnad;
  818. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  819. return BNA_CB_SUCCESS;
  820. err_return:
  821. while (!list_empty(&list_head)) {
  822. bfa_q_deq(&list_head, &qe);
  823. mac = (struct bna_mac *)qe;
  824. bfa_q_qe_init(&mac->qe);
  825. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  826. }
  827. return BNA_CB_MCAST_LIST_FULL;
  828. }
  829. void
  830. bna_rx_vlan_add(struct bna_rx *rx, int vlan_id)
  831. {
  832. struct bna_rxf *rxf = &rx->rxf;
  833. int index = (vlan_id >> BFI_VLAN_WORD_SHIFT);
  834. int bit = (1 << (vlan_id & BFI_VLAN_WORD_MASK));
  835. int group_id = (vlan_id >> BFI_VLAN_BLOCK_SHIFT);
  836. rxf->vlan_filter_table[index] |= bit;
  837. if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) {
  838. rxf->vlan_pending_bitmask |= (1 << group_id);
  839. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  840. }
  841. }
  842. void
  843. bna_rx_vlan_del(struct bna_rx *rx, int vlan_id)
  844. {
  845. struct bna_rxf *rxf = &rx->rxf;
  846. int index = (vlan_id >> BFI_VLAN_WORD_SHIFT);
  847. int bit = (1 << (vlan_id & BFI_VLAN_WORD_MASK));
  848. int group_id = (vlan_id >> BFI_VLAN_BLOCK_SHIFT);
  849. rxf->vlan_filter_table[index] &= ~bit;
  850. if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) {
  851. rxf->vlan_pending_bitmask |= (1 << group_id);
  852. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  853. }
  854. }
  855. static int
  856. bna_rxf_ucast_cfg_apply(struct bna_rxf *rxf)
  857. {
  858. struct bna_mac *mac = NULL;
  859. struct list_head *qe;
  860. /* Delete MAC addresses previousely added */
  861. if (!list_empty(&rxf->ucast_pending_del_q)) {
  862. bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
  863. bfa_q_qe_init(qe);
  864. mac = (struct bna_mac *)qe;
  865. bna_bfi_ucast_req(rxf, mac, BFI_ENET_H2I_MAC_UCAST_DEL_REQ);
  866. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  867. return 1;
  868. }
  869. /* Set default unicast MAC */
  870. if (rxf->ucast_pending_set) {
  871. rxf->ucast_pending_set = 0;
  872. memcpy(rxf->ucast_active_mac.addr,
  873. rxf->ucast_pending_mac->addr, ETH_ALEN);
  874. rxf->ucast_active_set = 1;
  875. bna_bfi_ucast_req(rxf, &rxf->ucast_active_mac,
  876. BFI_ENET_H2I_MAC_UCAST_SET_REQ);
  877. return 1;
  878. }
  879. /* Add additional MAC entries */
  880. if (!list_empty(&rxf->ucast_pending_add_q)) {
  881. bfa_q_deq(&rxf->ucast_pending_add_q, &qe);
  882. bfa_q_qe_init(qe);
  883. mac = (struct bna_mac *)qe;
  884. list_add_tail(&mac->qe, &rxf->ucast_active_q);
  885. bna_bfi_ucast_req(rxf, mac, BFI_ENET_H2I_MAC_UCAST_ADD_REQ);
  886. return 1;
  887. }
  888. return 0;
  889. }
  890. static int
  891. bna_rxf_ucast_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  892. {
  893. struct list_head *qe;
  894. struct bna_mac *mac;
  895. /* Throw away delete pending ucast entries */
  896. while (!list_empty(&rxf->ucast_pending_del_q)) {
  897. bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
  898. bfa_q_qe_init(qe);
  899. mac = (struct bna_mac *)qe;
  900. if (cleanup == BNA_SOFT_CLEANUP)
  901. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  902. else {
  903. bna_bfi_ucast_req(rxf, mac,
  904. BFI_ENET_H2I_MAC_UCAST_DEL_REQ);
  905. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  906. return 1;
  907. }
  908. }
  909. /* Move active ucast entries to pending_add_q */
  910. while (!list_empty(&rxf->ucast_active_q)) {
  911. bfa_q_deq(&rxf->ucast_active_q, &qe);
  912. bfa_q_qe_init(qe);
  913. list_add_tail(qe, &rxf->ucast_pending_add_q);
  914. if (cleanup == BNA_HARD_CLEANUP) {
  915. mac = (struct bna_mac *)qe;
  916. bna_bfi_ucast_req(rxf, mac,
  917. BFI_ENET_H2I_MAC_UCAST_DEL_REQ);
  918. return 1;
  919. }
  920. }
  921. if (rxf->ucast_active_set) {
  922. rxf->ucast_pending_set = 1;
  923. rxf->ucast_active_set = 0;
  924. if (cleanup == BNA_HARD_CLEANUP) {
  925. bna_bfi_ucast_req(rxf, &rxf->ucast_active_mac,
  926. BFI_ENET_H2I_MAC_UCAST_CLR_REQ);
  927. return 1;
  928. }
  929. }
  930. return 0;
  931. }
  932. static int
  933. bna_rxf_promisc_cfg_apply(struct bna_rxf *rxf)
  934. {
  935. struct bna *bna = rxf->rx->bna;
  936. /* Enable/disable promiscuous mode */
  937. if (is_promisc_enable(rxf->rxmode_pending,
  938. rxf->rxmode_pending_bitmask)) {
  939. /* move promisc configuration from pending -> active */
  940. promisc_inactive(rxf->rxmode_pending,
  941. rxf->rxmode_pending_bitmask);
  942. rxf->rxmode_active |= BNA_RXMODE_PROMISC;
  943. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_ENABLED);
  944. return 1;
  945. } else if (is_promisc_disable(rxf->rxmode_pending,
  946. rxf->rxmode_pending_bitmask)) {
  947. /* move promisc configuration from pending -> active */
  948. promisc_inactive(rxf->rxmode_pending,
  949. rxf->rxmode_pending_bitmask);
  950. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  951. bna->promisc_rid = BFI_INVALID_RID;
  952. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_DISABLED);
  953. return 1;
  954. }
  955. return 0;
  956. }
  957. static int
  958. bna_rxf_promisc_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  959. {
  960. struct bna *bna = rxf->rx->bna;
  961. /* Clear pending promisc mode disable */
  962. if (is_promisc_disable(rxf->rxmode_pending,
  963. rxf->rxmode_pending_bitmask)) {
  964. promisc_inactive(rxf->rxmode_pending,
  965. rxf->rxmode_pending_bitmask);
  966. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  967. bna->promisc_rid = BFI_INVALID_RID;
  968. if (cleanup == BNA_HARD_CLEANUP) {
  969. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_DISABLED);
  970. return 1;
  971. }
  972. }
  973. /* Move promisc mode config from active -> pending */
  974. if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
  975. promisc_enable(rxf->rxmode_pending,
  976. rxf->rxmode_pending_bitmask);
  977. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  978. if (cleanup == BNA_HARD_CLEANUP) {
  979. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_DISABLED);
  980. return 1;
  981. }
  982. }
  983. return 0;
  984. }
  985. static int
  986. bna_rxf_allmulti_cfg_apply(struct bna_rxf *rxf)
  987. {
  988. /* Enable/disable allmulti mode */
  989. if (is_allmulti_enable(rxf->rxmode_pending,
  990. rxf->rxmode_pending_bitmask)) {
  991. /* move allmulti configuration from pending -> active */
  992. allmulti_inactive(rxf->rxmode_pending,
  993. rxf->rxmode_pending_bitmask);
  994. rxf->rxmode_active |= BNA_RXMODE_ALLMULTI;
  995. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_DISABLED);
  996. return 1;
  997. } else if (is_allmulti_disable(rxf->rxmode_pending,
  998. rxf->rxmode_pending_bitmask)) {
  999. /* move allmulti configuration from pending -> active */
  1000. allmulti_inactive(rxf->rxmode_pending,
  1001. rxf->rxmode_pending_bitmask);
  1002. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1003. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_ENABLED);
  1004. return 1;
  1005. }
  1006. return 0;
  1007. }
  1008. static int
  1009. bna_rxf_allmulti_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  1010. {
  1011. /* Clear pending allmulti mode disable */
  1012. if (is_allmulti_disable(rxf->rxmode_pending,
  1013. rxf->rxmode_pending_bitmask)) {
  1014. allmulti_inactive(rxf->rxmode_pending,
  1015. rxf->rxmode_pending_bitmask);
  1016. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1017. if (cleanup == BNA_HARD_CLEANUP) {
  1018. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_ENABLED);
  1019. return 1;
  1020. }
  1021. }
  1022. /* Move allmulti mode config from active -> pending */
  1023. if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
  1024. allmulti_enable(rxf->rxmode_pending,
  1025. rxf->rxmode_pending_bitmask);
  1026. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1027. if (cleanup == BNA_HARD_CLEANUP) {
  1028. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_ENABLED);
  1029. return 1;
  1030. }
  1031. }
  1032. return 0;
  1033. }
  1034. static int
  1035. bna_rxf_promisc_enable(struct bna_rxf *rxf)
  1036. {
  1037. struct bna *bna = rxf->rx->bna;
  1038. int ret = 0;
  1039. if (is_promisc_enable(rxf->rxmode_pending,
  1040. rxf->rxmode_pending_bitmask) ||
  1041. (rxf->rxmode_active & BNA_RXMODE_PROMISC)) {
  1042. /* Do nothing if pending enable or already enabled */
  1043. } else if (is_promisc_disable(rxf->rxmode_pending,
  1044. rxf->rxmode_pending_bitmask)) {
  1045. /* Turn off pending disable command */
  1046. promisc_inactive(rxf->rxmode_pending,
  1047. rxf->rxmode_pending_bitmask);
  1048. } else {
  1049. /* Schedule enable */
  1050. promisc_enable(rxf->rxmode_pending,
  1051. rxf->rxmode_pending_bitmask);
  1052. bna->promisc_rid = rxf->rx->rid;
  1053. ret = 1;
  1054. }
  1055. return ret;
  1056. }
  1057. static int
  1058. bna_rxf_promisc_disable(struct bna_rxf *rxf)
  1059. {
  1060. struct bna *bna = rxf->rx->bna;
  1061. int ret = 0;
  1062. if (is_promisc_disable(rxf->rxmode_pending,
  1063. rxf->rxmode_pending_bitmask) ||
  1064. (!(rxf->rxmode_active & BNA_RXMODE_PROMISC))) {
  1065. /* Do nothing if pending disable or already disabled */
  1066. } else if (is_promisc_enable(rxf->rxmode_pending,
  1067. rxf->rxmode_pending_bitmask)) {
  1068. /* Turn off pending enable command */
  1069. promisc_inactive(rxf->rxmode_pending,
  1070. rxf->rxmode_pending_bitmask);
  1071. bna->promisc_rid = BFI_INVALID_RID;
  1072. } else if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
  1073. /* Schedule disable */
  1074. promisc_disable(rxf->rxmode_pending,
  1075. rxf->rxmode_pending_bitmask);
  1076. ret = 1;
  1077. }
  1078. return ret;
  1079. }
  1080. static int
  1081. bna_rxf_allmulti_enable(struct bna_rxf *rxf)
  1082. {
  1083. int ret = 0;
  1084. if (is_allmulti_enable(rxf->rxmode_pending,
  1085. rxf->rxmode_pending_bitmask) ||
  1086. (rxf->rxmode_active & BNA_RXMODE_ALLMULTI)) {
  1087. /* Do nothing if pending enable or already enabled */
  1088. } else if (is_allmulti_disable(rxf->rxmode_pending,
  1089. rxf->rxmode_pending_bitmask)) {
  1090. /* Turn off pending disable command */
  1091. allmulti_inactive(rxf->rxmode_pending,
  1092. rxf->rxmode_pending_bitmask);
  1093. } else {
  1094. /* Schedule enable */
  1095. allmulti_enable(rxf->rxmode_pending,
  1096. rxf->rxmode_pending_bitmask);
  1097. ret = 1;
  1098. }
  1099. return ret;
  1100. }
  1101. static int
  1102. bna_rxf_allmulti_disable(struct bna_rxf *rxf)
  1103. {
  1104. int ret = 0;
  1105. if (is_allmulti_disable(rxf->rxmode_pending,
  1106. rxf->rxmode_pending_bitmask) ||
  1107. (!(rxf->rxmode_active & BNA_RXMODE_ALLMULTI))) {
  1108. /* Do nothing if pending disable or already disabled */
  1109. } else if (is_allmulti_enable(rxf->rxmode_pending,
  1110. rxf->rxmode_pending_bitmask)) {
  1111. /* Turn off pending enable command */
  1112. allmulti_inactive(rxf->rxmode_pending,
  1113. rxf->rxmode_pending_bitmask);
  1114. } else if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
  1115. /* Schedule disable */
  1116. allmulti_disable(rxf->rxmode_pending,
  1117. rxf->rxmode_pending_bitmask);
  1118. ret = 1;
  1119. }
  1120. return ret;
  1121. }
  1122. static int
  1123. bna_rxf_vlan_strip_cfg_apply(struct bna_rxf *rxf)
  1124. {
  1125. if (rxf->vlan_strip_pending) {
  1126. rxf->vlan_strip_pending = false;
  1127. bna_bfi_vlan_strip_enable(rxf);
  1128. return 1;
  1129. }
  1130. return 0;
  1131. }
  1132. /* RX */
  1133. #define BNA_GET_RXQS(qcfg) (((qcfg)->rxp_type == BNA_RXP_SINGLE) ? \
  1134. (qcfg)->num_paths : ((qcfg)->num_paths * 2))
  1135. #define SIZE_TO_PAGES(size) (((size) >> PAGE_SHIFT) + ((((size) &\
  1136. (PAGE_SIZE - 1)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT))
  1137. #define call_rx_stop_cbfn(rx) \
  1138. do { \
  1139. if ((rx)->stop_cbfn) { \
  1140. void (*cbfn)(void *, struct bna_rx *); \
  1141. void *cbarg; \
  1142. cbfn = (rx)->stop_cbfn; \
  1143. cbarg = (rx)->stop_cbarg; \
  1144. (rx)->stop_cbfn = NULL; \
  1145. (rx)->stop_cbarg = NULL; \
  1146. cbfn(cbarg, rx); \
  1147. } \
  1148. } while (0)
  1149. #define call_rx_stall_cbfn(rx) \
  1150. do { \
  1151. if ((rx)->rx_stall_cbfn) \
  1152. (rx)->rx_stall_cbfn((rx)->bna->bnad, (rx)); \
  1153. } while (0)
  1154. #define bfi_enet_datapath_q_init(bfi_q, bna_qpt) \
  1155. do { \
  1156. struct bna_dma_addr cur_q_addr = \
  1157. *((struct bna_dma_addr *)((bna_qpt)->kv_qpt_ptr)); \
  1158. (bfi_q)->pg_tbl.a32.addr_lo = (bna_qpt)->hw_qpt_ptr.lsb; \
  1159. (bfi_q)->pg_tbl.a32.addr_hi = (bna_qpt)->hw_qpt_ptr.msb; \
  1160. (bfi_q)->first_entry.a32.addr_lo = cur_q_addr.lsb; \
  1161. (bfi_q)->first_entry.a32.addr_hi = cur_q_addr.msb; \
  1162. (bfi_q)->pages = htons((u16)(bna_qpt)->page_count); \
  1163. (bfi_q)->page_sz = htons((u16)(bna_qpt)->page_size);\
  1164. } while (0)
  1165. static void bna_bfi_rx_enet_start(struct bna_rx *rx);
  1166. static void bna_rx_enet_stop(struct bna_rx *rx);
  1167. static void bna_rx_mod_cb_rx_stopped(void *arg, struct bna_rx *rx);
  1168. bfa_fsm_state_decl(bna_rx, stopped,
  1169. struct bna_rx, enum bna_rx_event);
  1170. bfa_fsm_state_decl(bna_rx, start_wait,
  1171. struct bna_rx, enum bna_rx_event);
  1172. bfa_fsm_state_decl(bna_rx, start_stop_wait,
  1173. struct bna_rx, enum bna_rx_event);
  1174. bfa_fsm_state_decl(bna_rx, rxf_start_wait,
  1175. struct bna_rx, enum bna_rx_event);
  1176. bfa_fsm_state_decl(bna_rx, started,
  1177. struct bna_rx, enum bna_rx_event);
  1178. bfa_fsm_state_decl(bna_rx, rxf_stop_wait,
  1179. struct bna_rx, enum bna_rx_event);
  1180. bfa_fsm_state_decl(bna_rx, stop_wait,
  1181. struct bna_rx, enum bna_rx_event);
  1182. bfa_fsm_state_decl(bna_rx, cleanup_wait,
  1183. struct bna_rx, enum bna_rx_event);
  1184. bfa_fsm_state_decl(bna_rx, failed,
  1185. struct bna_rx, enum bna_rx_event);
  1186. bfa_fsm_state_decl(bna_rx, quiesce_wait,
  1187. struct bna_rx, enum bna_rx_event);
  1188. static void bna_rx_sm_stopped_entry(struct bna_rx *rx)
  1189. {
  1190. call_rx_stop_cbfn(rx);
  1191. }
  1192. static void bna_rx_sm_stopped(struct bna_rx *rx,
  1193. enum bna_rx_event event)
  1194. {
  1195. switch (event) {
  1196. case RX_E_START:
  1197. bfa_fsm_set_state(rx, bna_rx_sm_start_wait);
  1198. break;
  1199. case RX_E_STOP:
  1200. call_rx_stop_cbfn(rx);
  1201. break;
  1202. case RX_E_FAIL:
  1203. /* no-op */
  1204. break;
  1205. default:
  1206. bfa_sm_fault(event);
  1207. break;
  1208. }
  1209. }
  1210. static void bna_rx_sm_start_wait_entry(struct bna_rx *rx)
  1211. {
  1212. bna_bfi_rx_enet_start(rx);
  1213. }
  1214. static void
  1215. bna_rx_sm_stop_wait_entry(struct bna_rx *rx)
  1216. {
  1217. }
  1218. static void
  1219. bna_rx_sm_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
  1220. {
  1221. switch (event) {
  1222. case RX_E_FAIL:
  1223. case RX_E_STOPPED:
  1224. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1225. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1226. break;
  1227. case RX_E_STARTED:
  1228. bna_rx_enet_stop(rx);
  1229. break;
  1230. default:
  1231. bfa_sm_fault(event);
  1232. break;
  1233. }
  1234. }
  1235. static void bna_rx_sm_start_wait(struct bna_rx *rx,
  1236. enum bna_rx_event event)
  1237. {
  1238. switch (event) {
  1239. case RX_E_STOP:
  1240. bfa_fsm_set_state(rx, bna_rx_sm_start_stop_wait);
  1241. break;
  1242. case RX_E_FAIL:
  1243. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1244. break;
  1245. case RX_E_STARTED:
  1246. bfa_fsm_set_state(rx, bna_rx_sm_rxf_start_wait);
  1247. break;
  1248. default:
  1249. bfa_sm_fault(event);
  1250. break;
  1251. }
  1252. }
  1253. static void bna_rx_sm_rxf_start_wait_entry(struct bna_rx *rx)
  1254. {
  1255. rx->rx_post_cbfn(rx->bna->bnad, rx);
  1256. bna_rxf_start(&rx->rxf);
  1257. }
  1258. static void
  1259. bna_rx_sm_rxf_stop_wait_entry(struct bna_rx *rx)
  1260. {
  1261. }
  1262. static void
  1263. bna_rx_sm_rxf_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
  1264. {
  1265. switch (event) {
  1266. case RX_E_FAIL:
  1267. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1268. bna_rxf_fail(&rx->rxf);
  1269. call_rx_stall_cbfn(rx);
  1270. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1271. break;
  1272. case RX_E_RXF_STARTED:
  1273. bna_rxf_stop(&rx->rxf);
  1274. break;
  1275. case RX_E_RXF_STOPPED:
  1276. bfa_fsm_set_state(rx, bna_rx_sm_stop_wait);
  1277. call_rx_stall_cbfn(rx);
  1278. bna_rx_enet_stop(rx);
  1279. break;
  1280. default:
  1281. bfa_sm_fault(event);
  1282. break;
  1283. }
  1284. }
  1285. static void
  1286. bna_rx_sm_start_stop_wait_entry(struct bna_rx *rx)
  1287. {
  1288. }
  1289. static void
  1290. bna_rx_sm_start_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
  1291. {
  1292. switch (event) {
  1293. case RX_E_FAIL:
  1294. case RX_E_STOPPED:
  1295. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1296. break;
  1297. case RX_E_STARTED:
  1298. bna_rx_enet_stop(rx);
  1299. break;
  1300. default:
  1301. bfa_sm_fault(event);
  1302. }
  1303. }
  1304. static void
  1305. bna_rx_sm_started_entry(struct bna_rx *rx)
  1306. {
  1307. struct bna_rxp *rxp;
  1308. struct list_head *qe_rxp;
  1309. int is_regular = (rx->type == BNA_RX_T_REGULAR);
  1310. /* Start IB */
  1311. list_for_each(qe_rxp, &rx->rxp_q) {
  1312. rxp = (struct bna_rxp *)qe_rxp;
  1313. bna_ib_start(rx->bna, &rxp->cq.ib, is_regular);
  1314. }
  1315. bna_ethport_cb_rx_started(&rx->bna->ethport);
  1316. }
  1317. static void
  1318. bna_rx_sm_started(struct bna_rx *rx, enum bna_rx_event event)
  1319. {
  1320. switch (event) {
  1321. case RX_E_STOP:
  1322. bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait);
  1323. bna_ethport_cb_rx_stopped(&rx->bna->ethport);
  1324. bna_rxf_stop(&rx->rxf);
  1325. break;
  1326. case RX_E_FAIL:
  1327. bfa_fsm_set_state(rx, bna_rx_sm_failed);
  1328. bna_ethport_cb_rx_stopped(&rx->bna->ethport);
  1329. bna_rxf_fail(&rx->rxf);
  1330. call_rx_stall_cbfn(rx);
  1331. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1332. break;
  1333. default:
  1334. bfa_sm_fault(event);
  1335. break;
  1336. }
  1337. }
  1338. static void bna_rx_sm_rxf_start_wait(struct bna_rx *rx,
  1339. enum bna_rx_event event)
  1340. {
  1341. switch (event) {
  1342. case RX_E_STOP:
  1343. bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait);
  1344. break;
  1345. case RX_E_FAIL:
  1346. bfa_fsm_set_state(rx, bna_rx_sm_failed);
  1347. bna_rxf_fail(&rx->rxf);
  1348. call_rx_stall_cbfn(rx);
  1349. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1350. break;
  1351. case RX_E_RXF_STARTED:
  1352. bfa_fsm_set_state(rx, bna_rx_sm_started);
  1353. break;
  1354. default:
  1355. bfa_sm_fault(event);
  1356. break;
  1357. }
  1358. }
  1359. static void
  1360. bna_rx_sm_cleanup_wait_entry(struct bna_rx *rx)
  1361. {
  1362. }
  1363. static void
  1364. bna_rx_sm_cleanup_wait(struct bna_rx *rx, enum bna_rx_event event)
  1365. {
  1366. switch (event) {
  1367. case RX_E_FAIL:
  1368. case RX_E_RXF_STOPPED:
  1369. /* No-op */
  1370. break;
  1371. case RX_E_CLEANUP_DONE:
  1372. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1373. break;
  1374. default:
  1375. bfa_sm_fault(event);
  1376. break;
  1377. }
  1378. }
  1379. static void
  1380. bna_rx_sm_failed_entry(struct bna_rx *rx)
  1381. {
  1382. }
  1383. static void
  1384. bna_rx_sm_failed(struct bna_rx *rx, enum bna_rx_event event)
  1385. {
  1386. switch (event) {
  1387. case RX_E_START:
  1388. bfa_fsm_set_state(rx, bna_rx_sm_quiesce_wait);
  1389. break;
  1390. case RX_E_STOP:
  1391. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1392. break;
  1393. case RX_E_FAIL:
  1394. case RX_E_RXF_STARTED:
  1395. case RX_E_RXF_STOPPED:
  1396. /* No-op */
  1397. break;
  1398. case RX_E_CLEANUP_DONE:
  1399. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1400. break;
  1401. default:
  1402. bfa_sm_fault(event);
  1403. break;
  1404. } }
  1405. static void
  1406. bna_rx_sm_quiesce_wait_entry(struct bna_rx *rx)
  1407. {
  1408. }
  1409. static void
  1410. bna_rx_sm_quiesce_wait(struct bna_rx *rx, enum bna_rx_event event)
  1411. {
  1412. switch (event) {
  1413. case RX_E_STOP:
  1414. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1415. break;
  1416. case RX_E_FAIL:
  1417. bfa_fsm_set_state(rx, bna_rx_sm_failed);
  1418. break;
  1419. case RX_E_CLEANUP_DONE:
  1420. bfa_fsm_set_state(rx, bna_rx_sm_start_wait);
  1421. break;
  1422. default:
  1423. bfa_sm_fault(event);
  1424. break;
  1425. }
  1426. }
  1427. static void
  1428. bna_bfi_rx_enet_start(struct bna_rx *rx)
  1429. {
  1430. struct bfi_enet_rx_cfg_req *cfg_req = &rx->bfi_enet_cmd.cfg_req;
  1431. struct bna_rxp *rxp = NULL;
  1432. struct bna_rxq *q0 = NULL, *q1 = NULL;
  1433. struct list_head *rxp_qe;
  1434. int i;
  1435. bfi_msgq_mhdr_set(cfg_req->mh, BFI_MC_ENET,
  1436. BFI_ENET_H2I_RX_CFG_SET_REQ, 0, rx->rid);
  1437. cfg_req->mh.num_entries = htons(
  1438. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rx_cfg_req)));
  1439. cfg_req->num_queue_sets = rx->num_paths;
  1440. for (i = 0, rxp_qe = bfa_q_first(&rx->rxp_q);
  1441. i < rx->num_paths;
  1442. i++, rxp_qe = bfa_q_next(rxp_qe)) {
  1443. rxp = (struct bna_rxp *)rxp_qe;
  1444. GET_RXQS(rxp, q0, q1);
  1445. switch (rxp->type) {
  1446. case BNA_RXP_SLR:
  1447. case BNA_RXP_HDS:
  1448. /* Small RxQ */
  1449. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].qs.q,
  1450. &q1->qpt);
  1451. cfg_req->q_cfg[i].qs.rx_buffer_size =
  1452. htons((u16)q1->buffer_size);
  1453. /* Fall through */
  1454. case BNA_RXP_SINGLE:
  1455. /* Large/Single RxQ */
  1456. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].ql.q,
  1457. &q0->qpt);
  1458. q0->buffer_size =
  1459. bna_enet_mtu_get(&rx->bna->enet);
  1460. cfg_req->q_cfg[i].ql.rx_buffer_size =
  1461. htons((u16)q0->buffer_size);
  1462. break;
  1463. default:
  1464. BUG_ON(1);
  1465. }
  1466. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].cq.q,
  1467. &rxp->cq.qpt);
  1468. cfg_req->q_cfg[i].ib.index_addr.a32.addr_lo =
  1469. rxp->cq.ib.ib_seg_host_addr.lsb;
  1470. cfg_req->q_cfg[i].ib.index_addr.a32.addr_hi =
  1471. rxp->cq.ib.ib_seg_host_addr.msb;
  1472. cfg_req->q_cfg[i].ib.intr.msix_index =
  1473. htons((u16)rxp->cq.ib.intr_vector);
  1474. }
  1475. cfg_req->ib_cfg.int_pkt_dma = BNA_STATUS_T_DISABLED;
  1476. cfg_req->ib_cfg.int_enabled = BNA_STATUS_T_ENABLED;
  1477. cfg_req->ib_cfg.int_pkt_enabled = BNA_STATUS_T_DISABLED;
  1478. cfg_req->ib_cfg.continuous_coalescing = BNA_STATUS_T_DISABLED;
  1479. cfg_req->ib_cfg.msix = (rxp->cq.ib.intr_type == BNA_INTR_T_MSIX)
  1480. ? BNA_STATUS_T_ENABLED :
  1481. BNA_STATUS_T_DISABLED;
  1482. cfg_req->ib_cfg.coalescing_timeout =
  1483. htonl((u32)rxp->cq.ib.coalescing_timeo);
  1484. cfg_req->ib_cfg.inter_pkt_timeout =
  1485. htonl((u32)rxp->cq.ib.interpkt_timeo);
  1486. cfg_req->ib_cfg.inter_pkt_count = (u8)rxp->cq.ib.interpkt_count;
  1487. switch (rxp->type) {
  1488. case BNA_RXP_SLR:
  1489. cfg_req->rx_cfg.rxq_type = BFI_ENET_RXQ_LARGE_SMALL;
  1490. break;
  1491. case BNA_RXP_HDS:
  1492. cfg_req->rx_cfg.rxq_type = BFI_ENET_RXQ_HDS;
  1493. cfg_req->rx_cfg.hds.type = rx->hds_cfg.hdr_type;
  1494. cfg_req->rx_cfg.hds.force_offset = rx->hds_cfg.forced_offset;
  1495. cfg_req->rx_cfg.hds.max_header_size = rx->hds_cfg.forced_offset;
  1496. break;
  1497. case BNA_RXP_SINGLE:
  1498. cfg_req->rx_cfg.rxq_type = BFI_ENET_RXQ_SINGLE;
  1499. break;
  1500. default:
  1501. BUG_ON(1);
  1502. }
  1503. cfg_req->rx_cfg.strip_vlan = rx->rxf.vlan_strip_status;
  1504. bfa_msgq_cmd_set(&rx->msgq_cmd, NULL, NULL,
  1505. sizeof(struct bfi_enet_rx_cfg_req), &cfg_req->mh);
  1506. bfa_msgq_cmd_post(&rx->bna->msgq, &rx->msgq_cmd);
  1507. }
  1508. static void
  1509. bna_bfi_rx_enet_stop(struct bna_rx *rx)
  1510. {
  1511. struct bfi_enet_req *req = &rx->bfi_enet_cmd.req;
  1512. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  1513. BFI_ENET_H2I_RX_CFG_CLR_REQ, 0, rx->rid);
  1514. req->mh.num_entries = htons(
  1515. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_req)));
  1516. bfa_msgq_cmd_set(&rx->msgq_cmd, NULL, NULL, sizeof(struct bfi_enet_req),
  1517. &req->mh);
  1518. bfa_msgq_cmd_post(&rx->bna->msgq, &rx->msgq_cmd);
  1519. }
  1520. static void
  1521. bna_rx_enet_stop(struct bna_rx *rx)
  1522. {
  1523. struct bna_rxp *rxp;
  1524. struct list_head *qe_rxp;
  1525. /* Stop IB */
  1526. list_for_each(qe_rxp, &rx->rxp_q) {
  1527. rxp = (struct bna_rxp *)qe_rxp;
  1528. bna_ib_stop(rx->bna, &rxp->cq.ib);
  1529. }
  1530. bna_bfi_rx_enet_stop(rx);
  1531. }
  1532. static int
  1533. bna_rx_res_check(struct bna_rx_mod *rx_mod, struct bna_rx_config *rx_cfg)
  1534. {
  1535. if ((rx_mod->rx_free_count == 0) ||
  1536. (rx_mod->rxp_free_count == 0) ||
  1537. (rx_mod->rxq_free_count == 0))
  1538. return 0;
  1539. if (rx_cfg->rxp_type == BNA_RXP_SINGLE) {
  1540. if ((rx_mod->rxp_free_count < rx_cfg->num_paths) ||
  1541. (rx_mod->rxq_free_count < rx_cfg->num_paths))
  1542. return 0;
  1543. } else {
  1544. if ((rx_mod->rxp_free_count < rx_cfg->num_paths) ||
  1545. (rx_mod->rxq_free_count < (2 * rx_cfg->num_paths)))
  1546. return 0;
  1547. }
  1548. return 1;
  1549. }
  1550. static struct bna_rxq *
  1551. bna_rxq_get(struct bna_rx_mod *rx_mod)
  1552. {
  1553. struct bna_rxq *rxq = NULL;
  1554. struct list_head *qe = NULL;
  1555. bfa_q_deq(&rx_mod->rxq_free_q, &qe);
  1556. rx_mod->rxq_free_count--;
  1557. rxq = (struct bna_rxq *)qe;
  1558. bfa_q_qe_init(&rxq->qe);
  1559. return rxq;
  1560. }
  1561. static void
  1562. bna_rxq_put(struct bna_rx_mod *rx_mod, struct bna_rxq *rxq)
  1563. {
  1564. bfa_q_qe_init(&rxq->qe);
  1565. list_add_tail(&rxq->qe, &rx_mod->rxq_free_q);
  1566. rx_mod->rxq_free_count++;
  1567. }
  1568. static struct bna_rxp *
  1569. bna_rxp_get(struct bna_rx_mod *rx_mod)
  1570. {
  1571. struct list_head *qe = NULL;
  1572. struct bna_rxp *rxp = NULL;
  1573. bfa_q_deq(&rx_mod->rxp_free_q, &qe);
  1574. rx_mod->rxp_free_count--;
  1575. rxp = (struct bna_rxp *)qe;
  1576. bfa_q_qe_init(&rxp->qe);
  1577. return rxp;
  1578. }
  1579. static void
  1580. bna_rxp_put(struct bna_rx_mod *rx_mod, struct bna_rxp *rxp)
  1581. {
  1582. bfa_q_qe_init(&rxp->qe);
  1583. list_add_tail(&rxp->qe, &rx_mod->rxp_free_q);
  1584. rx_mod->rxp_free_count++;
  1585. }
  1586. static struct bna_rx *
  1587. bna_rx_get(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
  1588. {
  1589. struct list_head *qe = NULL;
  1590. struct bna_rx *rx = NULL;
  1591. if (type == BNA_RX_T_REGULAR) {
  1592. bfa_q_deq(&rx_mod->rx_free_q, &qe);
  1593. } else
  1594. bfa_q_deq_tail(&rx_mod->rx_free_q, &qe);
  1595. rx_mod->rx_free_count--;
  1596. rx = (struct bna_rx *)qe;
  1597. bfa_q_qe_init(&rx->qe);
  1598. list_add_tail(&rx->qe, &rx_mod->rx_active_q);
  1599. rx->type = type;
  1600. return rx;
  1601. }
  1602. static void
  1603. bna_rx_put(struct bna_rx_mod *rx_mod, struct bna_rx *rx)
  1604. {
  1605. struct list_head *prev_qe = NULL;
  1606. struct list_head *qe;
  1607. bfa_q_qe_init(&rx->qe);
  1608. list_for_each(qe, &rx_mod->rx_free_q) {
  1609. if (((struct bna_rx *)qe)->rid < rx->rid)
  1610. prev_qe = qe;
  1611. else
  1612. break;
  1613. }
  1614. if (prev_qe == NULL) {
  1615. /* This is the first entry */
  1616. bfa_q_enq_head(&rx_mod->rx_free_q, &rx->qe);
  1617. } else if (bfa_q_next(prev_qe) == &rx_mod->rx_free_q) {
  1618. /* This is the last entry */
  1619. list_add_tail(&rx->qe, &rx_mod->rx_free_q);
  1620. } else {
  1621. /* Somewhere in the middle */
  1622. bfa_q_next(&rx->qe) = bfa_q_next(prev_qe);
  1623. bfa_q_prev(&rx->qe) = prev_qe;
  1624. bfa_q_next(prev_qe) = &rx->qe;
  1625. bfa_q_prev(bfa_q_next(&rx->qe)) = &rx->qe;
  1626. }
  1627. rx_mod->rx_free_count++;
  1628. }
  1629. static void
  1630. bna_rxp_add_rxqs(struct bna_rxp *rxp, struct bna_rxq *q0,
  1631. struct bna_rxq *q1)
  1632. {
  1633. switch (rxp->type) {
  1634. case BNA_RXP_SINGLE:
  1635. rxp->rxq.single.only = q0;
  1636. rxp->rxq.single.reserved = NULL;
  1637. break;
  1638. case BNA_RXP_SLR:
  1639. rxp->rxq.slr.large = q0;
  1640. rxp->rxq.slr.small = q1;
  1641. break;
  1642. case BNA_RXP_HDS:
  1643. rxp->rxq.hds.data = q0;
  1644. rxp->rxq.hds.hdr = q1;
  1645. break;
  1646. default:
  1647. break;
  1648. }
  1649. }
  1650. static void
  1651. bna_rxq_qpt_setup(struct bna_rxq *rxq,
  1652. struct bna_rxp *rxp,
  1653. u32 page_count,
  1654. u32 page_size,
  1655. struct bna_mem_descr *qpt_mem,
  1656. struct bna_mem_descr *swqpt_mem,
  1657. struct bna_mem_descr *page_mem)
  1658. {
  1659. u8 *kva;
  1660. u64 dma;
  1661. struct bna_dma_addr bna_dma;
  1662. int i;
  1663. rxq->qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
  1664. rxq->qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
  1665. rxq->qpt.kv_qpt_ptr = qpt_mem->kva;
  1666. rxq->qpt.page_count = page_count;
  1667. rxq->qpt.page_size = page_size;
  1668. rxq->rcb->sw_qpt = (void **) swqpt_mem->kva;
  1669. rxq->rcb->sw_q = page_mem->kva;
  1670. kva = page_mem->kva;
  1671. BNA_GET_DMA_ADDR(&page_mem->dma, dma);
  1672. for (i = 0; i < rxq->qpt.page_count; i++) {
  1673. rxq->rcb->sw_qpt[i] = kva;
  1674. kva += PAGE_SIZE;
  1675. BNA_SET_DMA_ADDR(dma, &bna_dma);
  1676. ((struct bna_dma_addr *)rxq->qpt.kv_qpt_ptr)[i].lsb =
  1677. bna_dma.lsb;
  1678. ((struct bna_dma_addr *)rxq->qpt.kv_qpt_ptr)[i].msb =
  1679. bna_dma.msb;
  1680. dma += PAGE_SIZE;
  1681. }
  1682. }
  1683. static void
  1684. bna_rxp_cqpt_setup(struct bna_rxp *rxp,
  1685. u32 page_count,
  1686. u32 page_size,
  1687. struct bna_mem_descr *qpt_mem,
  1688. struct bna_mem_descr *swqpt_mem,
  1689. struct bna_mem_descr *page_mem)
  1690. {
  1691. u8 *kva;
  1692. u64 dma;
  1693. struct bna_dma_addr bna_dma;
  1694. int i;
  1695. rxp->cq.qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
  1696. rxp->cq.qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
  1697. rxp->cq.qpt.kv_qpt_ptr = qpt_mem->kva;
  1698. rxp->cq.qpt.page_count = page_count;
  1699. rxp->cq.qpt.page_size = page_size;
  1700. rxp->cq.ccb->sw_qpt = (void **) swqpt_mem->kva;
  1701. rxp->cq.ccb->sw_q = page_mem->kva;
  1702. kva = page_mem->kva;
  1703. BNA_GET_DMA_ADDR(&page_mem->dma, dma);
  1704. for (i = 0; i < rxp->cq.qpt.page_count; i++) {
  1705. rxp->cq.ccb->sw_qpt[i] = kva;
  1706. kva += PAGE_SIZE;
  1707. BNA_SET_DMA_ADDR(dma, &bna_dma);
  1708. ((struct bna_dma_addr *)rxp->cq.qpt.kv_qpt_ptr)[i].lsb =
  1709. bna_dma.lsb;
  1710. ((struct bna_dma_addr *)rxp->cq.qpt.kv_qpt_ptr)[i].msb =
  1711. bna_dma.msb;
  1712. dma += PAGE_SIZE;
  1713. }
  1714. }
  1715. static void
  1716. bna_rx_mod_cb_rx_stopped(void *arg, struct bna_rx *rx)
  1717. {
  1718. struct bna_rx_mod *rx_mod = (struct bna_rx_mod *)arg;
  1719. bfa_wc_down(&rx_mod->rx_stop_wc);
  1720. }
  1721. static void
  1722. bna_rx_mod_cb_rx_stopped_all(void *arg)
  1723. {
  1724. struct bna_rx_mod *rx_mod = (struct bna_rx_mod *)arg;
  1725. if (rx_mod->stop_cbfn)
  1726. rx_mod->stop_cbfn(&rx_mod->bna->enet);
  1727. rx_mod->stop_cbfn = NULL;
  1728. }
  1729. static void
  1730. bna_rx_start(struct bna_rx *rx)
  1731. {
  1732. rx->rx_flags |= BNA_RX_F_ENET_STARTED;
  1733. if (rx->rx_flags & BNA_RX_F_ENABLED)
  1734. bfa_fsm_send_event(rx, RX_E_START);
  1735. }
  1736. static void
  1737. bna_rx_stop(struct bna_rx *rx)
  1738. {
  1739. rx->rx_flags &= ~BNA_RX_F_ENET_STARTED;
  1740. if (rx->fsm == (bfa_fsm_t) bna_rx_sm_stopped)
  1741. bna_rx_mod_cb_rx_stopped(&rx->bna->rx_mod, rx);
  1742. else {
  1743. rx->stop_cbfn = bna_rx_mod_cb_rx_stopped;
  1744. rx->stop_cbarg = &rx->bna->rx_mod;
  1745. bfa_fsm_send_event(rx, RX_E_STOP);
  1746. }
  1747. }
  1748. static void
  1749. bna_rx_fail(struct bna_rx *rx)
  1750. {
  1751. /* Indicate Enet is not enabled, and failed */
  1752. rx->rx_flags &= ~BNA_RX_F_ENET_STARTED;
  1753. bfa_fsm_send_event(rx, RX_E_FAIL);
  1754. }
  1755. void
  1756. bna_rx_mod_start(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
  1757. {
  1758. struct bna_rx *rx;
  1759. struct list_head *qe;
  1760. rx_mod->flags |= BNA_RX_MOD_F_ENET_STARTED;
  1761. if (type == BNA_RX_T_LOOPBACK)
  1762. rx_mod->flags |= BNA_RX_MOD_F_ENET_LOOPBACK;
  1763. list_for_each(qe, &rx_mod->rx_active_q) {
  1764. rx = (struct bna_rx *)qe;
  1765. if (rx->type == type)
  1766. bna_rx_start(rx);
  1767. }
  1768. }
  1769. void
  1770. bna_rx_mod_stop(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
  1771. {
  1772. struct bna_rx *rx;
  1773. struct list_head *qe;
  1774. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_STARTED;
  1775. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_LOOPBACK;
  1776. rx_mod->stop_cbfn = bna_enet_cb_rx_stopped;
  1777. bfa_wc_init(&rx_mod->rx_stop_wc, bna_rx_mod_cb_rx_stopped_all, rx_mod);
  1778. list_for_each(qe, &rx_mod->rx_active_q) {
  1779. rx = (struct bna_rx *)qe;
  1780. if (rx->type == type) {
  1781. bfa_wc_up(&rx_mod->rx_stop_wc);
  1782. bna_rx_stop(rx);
  1783. }
  1784. }
  1785. bfa_wc_wait(&rx_mod->rx_stop_wc);
  1786. }
  1787. void
  1788. bna_rx_mod_fail(struct bna_rx_mod *rx_mod)
  1789. {
  1790. struct bna_rx *rx;
  1791. struct list_head *qe;
  1792. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_STARTED;
  1793. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_LOOPBACK;
  1794. list_for_each(qe, &rx_mod->rx_active_q) {
  1795. rx = (struct bna_rx *)qe;
  1796. bna_rx_fail(rx);
  1797. }
  1798. }
  1799. void bna_rx_mod_init(struct bna_rx_mod *rx_mod, struct bna *bna,
  1800. struct bna_res_info *res_info)
  1801. {
  1802. int index;
  1803. struct bna_rx *rx_ptr;
  1804. struct bna_rxp *rxp_ptr;
  1805. struct bna_rxq *rxq_ptr;
  1806. rx_mod->bna = bna;
  1807. rx_mod->flags = 0;
  1808. rx_mod->rx = (struct bna_rx *)
  1809. res_info[BNA_MOD_RES_MEM_T_RX_ARRAY].res_u.mem_info.mdl[0].kva;
  1810. rx_mod->rxp = (struct bna_rxp *)
  1811. res_info[BNA_MOD_RES_MEM_T_RXP_ARRAY].res_u.mem_info.mdl[0].kva;
  1812. rx_mod->rxq = (struct bna_rxq *)
  1813. res_info[BNA_MOD_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.mdl[0].kva;
  1814. /* Initialize the queues */
  1815. INIT_LIST_HEAD(&rx_mod->rx_free_q);
  1816. rx_mod->rx_free_count = 0;
  1817. INIT_LIST_HEAD(&rx_mod->rxq_free_q);
  1818. rx_mod->rxq_free_count = 0;
  1819. INIT_LIST_HEAD(&rx_mod->rxp_free_q);
  1820. rx_mod->rxp_free_count = 0;
  1821. INIT_LIST_HEAD(&rx_mod->rx_active_q);
  1822. /* Build RX queues */
  1823. for (index = 0; index < bna->ioceth.attr.num_rxp; index++) {
  1824. rx_ptr = &rx_mod->rx[index];
  1825. bfa_q_qe_init(&rx_ptr->qe);
  1826. INIT_LIST_HEAD(&rx_ptr->rxp_q);
  1827. rx_ptr->bna = NULL;
  1828. rx_ptr->rid = index;
  1829. rx_ptr->stop_cbfn = NULL;
  1830. rx_ptr->stop_cbarg = NULL;
  1831. list_add_tail(&rx_ptr->qe, &rx_mod->rx_free_q);
  1832. rx_mod->rx_free_count++;
  1833. }
  1834. /* build RX-path queue */
  1835. for (index = 0; index < bna->ioceth.attr.num_rxp; index++) {
  1836. rxp_ptr = &rx_mod->rxp[index];
  1837. bfa_q_qe_init(&rxp_ptr->qe);
  1838. list_add_tail(&rxp_ptr->qe, &rx_mod->rxp_free_q);
  1839. rx_mod->rxp_free_count++;
  1840. }
  1841. /* build RXQ queue */
  1842. for (index = 0; index < (bna->ioceth.attr.num_rxp * 2); index++) {
  1843. rxq_ptr = &rx_mod->rxq[index];
  1844. bfa_q_qe_init(&rxq_ptr->qe);
  1845. list_add_tail(&rxq_ptr->qe, &rx_mod->rxq_free_q);
  1846. rx_mod->rxq_free_count++;
  1847. }
  1848. }
  1849. void
  1850. bna_rx_mod_uninit(struct bna_rx_mod *rx_mod)
  1851. {
  1852. struct list_head *qe;
  1853. int i;
  1854. i = 0;
  1855. list_for_each(qe, &rx_mod->rx_free_q)
  1856. i++;
  1857. i = 0;
  1858. list_for_each(qe, &rx_mod->rxp_free_q)
  1859. i++;
  1860. i = 0;
  1861. list_for_each(qe, &rx_mod->rxq_free_q)
  1862. i++;
  1863. rx_mod->bna = NULL;
  1864. }
  1865. void
  1866. bna_bfi_rx_enet_start_rsp(struct bna_rx *rx, struct bfi_msgq_mhdr *msghdr)
  1867. {
  1868. struct bfi_enet_rx_cfg_rsp *cfg_rsp = &rx->bfi_enet_cmd.cfg_rsp;
  1869. struct bna_rxp *rxp = NULL;
  1870. struct bna_rxq *q0 = NULL, *q1 = NULL;
  1871. struct list_head *rxp_qe;
  1872. int i;
  1873. bfa_msgq_rsp_copy(&rx->bna->msgq, (u8 *)cfg_rsp,
  1874. sizeof(struct bfi_enet_rx_cfg_rsp));
  1875. rx->hw_id = cfg_rsp->hw_id;
  1876. for (i = 0, rxp_qe = bfa_q_first(&rx->rxp_q);
  1877. i < rx->num_paths;
  1878. i++, rxp_qe = bfa_q_next(rxp_qe)) {
  1879. rxp = (struct bna_rxp *)rxp_qe;
  1880. GET_RXQS(rxp, q0, q1);
  1881. /* Setup doorbells */
  1882. rxp->cq.ccb->i_dbell->doorbell_addr =
  1883. rx->bna->pcidev.pci_bar_kva
  1884. + ntohl(cfg_rsp->q_handles[i].i_dbell);
  1885. rxp->hw_id = cfg_rsp->q_handles[i].hw_cqid;
  1886. q0->rcb->q_dbell =
  1887. rx->bna->pcidev.pci_bar_kva
  1888. + ntohl(cfg_rsp->q_handles[i].ql_dbell);
  1889. q0->hw_id = cfg_rsp->q_handles[i].hw_lqid;
  1890. if (q1) {
  1891. q1->rcb->q_dbell =
  1892. rx->bna->pcidev.pci_bar_kva
  1893. + ntohl(cfg_rsp->q_handles[i].qs_dbell);
  1894. q1->hw_id = cfg_rsp->q_handles[i].hw_sqid;
  1895. }
  1896. /* Initialize producer/consumer indexes */
  1897. (*rxp->cq.ccb->hw_producer_index) = 0;
  1898. rxp->cq.ccb->producer_index = 0;
  1899. q0->rcb->producer_index = q0->rcb->consumer_index = 0;
  1900. if (q1)
  1901. q1->rcb->producer_index = q1->rcb->consumer_index = 0;
  1902. }
  1903. bfa_fsm_send_event(rx, RX_E_STARTED);
  1904. }
  1905. void
  1906. bna_bfi_rx_enet_stop_rsp(struct bna_rx *rx, struct bfi_msgq_mhdr *msghdr)
  1907. {
  1908. bfa_fsm_send_event(rx, RX_E_STOPPED);
  1909. }
  1910. void
  1911. bna_rx_res_req(struct bna_rx_config *q_cfg, struct bna_res_info *res_info)
  1912. {
  1913. u32 cq_size, hq_size, dq_size;
  1914. u32 cpage_count, hpage_count, dpage_count;
  1915. struct bna_mem_info *mem_info;
  1916. u32 cq_depth;
  1917. u32 hq_depth;
  1918. u32 dq_depth;
  1919. dq_depth = q_cfg->q_depth;
  1920. hq_depth = ((q_cfg->rxp_type == BNA_RXP_SINGLE) ? 0 : q_cfg->q_depth);
  1921. cq_depth = dq_depth + hq_depth;
  1922. BNA_TO_POWER_OF_2_HIGH(cq_depth);
  1923. cq_size = cq_depth * BFI_CQ_WI_SIZE;
  1924. cq_size = ALIGN(cq_size, PAGE_SIZE);
  1925. cpage_count = SIZE_TO_PAGES(cq_size);
  1926. BNA_TO_POWER_OF_2_HIGH(dq_depth);
  1927. dq_size = dq_depth * BFI_RXQ_WI_SIZE;
  1928. dq_size = ALIGN(dq_size, PAGE_SIZE);
  1929. dpage_count = SIZE_TO_PAGES(dq_size);
  1930. if (BNA_RXP_SINGLE != q_cfg->rxp_type) {
  1931. BNA_TO_POWER_OF_2_HIGH(hq_depth);
  1932. hq_size = hq_depth * BFI_RXQ_WI_SIZE;
  1933. hq_size = ALIGN(hq_size, PAGE_SIZE);
  1934. hpage_count = SIZE_TO_PAGES(hq_size);
  1935. } else
  1936. hpage_count = 0;
  1937. res_info[BNA_RX_RES_MEM_T_CCB].res_type = BNA_RES_T_MEM;
  1938. mem_info = &res_info[BNA_RX_RES_MEM_T_CCB].res_u.mem_info;
  1939. mem_info->mem_type = BNA_MEM_T_KVA;
  1940. mem_info->len = sizeof(struct bna_ccb);
  1941. mem_info->num = q_cfg->num_paths;
  1942. res_info[BNA_RX_RES_MEM_T_RCB].res_type = BNA_RES_T_MEM;
  1943. mem_info = &res_info[BNA_RX_RES_MEM_T_RCB].res_u.mem_info;
  1944. mem_info->mem_type = BNA_MEM_T_KVA;
  1945. mem_info->len = sizeof(struct bna_rcb);
  1946. mem_info->num = BNA_GET_RXQS(q_cfg);
  1947. res_info[BNA_RX_RES_MEM_T_CQPT].res_type = BNA_RES_T_MEM;
  1948. mem_info = &res_info[BNA_RX_RES_MEM_T_CQPT].res_u.mem_info;
  1949. mem_info->mem_type = BNA_MEM_T_DMA;
  1950. mem_info->len = cpage_count * sizeof(struct bna_dma_addr);
  1951. mem_info->num = q_cfg->num_paths;
  1952. res_info[BNA_RX_RES_MEM_T_CSWQPT].res_type = BNA_RES_T_MEM;
  1953. mem_info = &res_info[BNA_RX_RES_MEM_T_CSWQPT].res_u.mem_info;
  1954. mem_info->mem_type = BNA_MEM_T_KVA;
  1955. mem_info->len = cpage_count * sizeof(void *);
  1956. mem_info->num = q_cfg->num_paths;
  1957. res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_type = BNA_RES_T_MEM;
  1958. mem_info = &res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info;
  1959. mem_info->mem_type = BNA_MEM_T_DMA;
  1960. mem_info->len = PAGE_SIZE * cpage_count;
  1961. mem_info->num = q_cfg->num_paths;
  1962. res_info[BNA_RX_RES_MEM_T_DQPT].res_type = BNA_RES_T_MEM;
  1963. mem_info = &res_info[BNA_RX_RES_MEM_T_DQPT].res_u.mem_info;
  1964. mem_info->mem_type = BNA_MEM_T_DMA;
  1965. mem_info->len = dpage_count * sizeof(struct bna_dma_addr);
  1966. mem_info->num = q_cfg->num_paths;
  1967. res_info[BNA_RX_RES_MEM_T_DSWQPT].res_type = BNA_RES_T_MEM;
  1968. mem_info = &res_info[BNA_RX_RES_MEM_T_DSWQPT].res_u.mem_info;
  1969. mem_info->mem_type = BNA_MEM_T_KVA;
  1970. mem_info->len = dpage_count * sizeof(void *);
  1971. mem_info->num = q_cfg->num_paths;
  1972. res_info[BNA_RX_RES_MEM_T_DPAGE].res_type = BNA_RES_T_MEM;
  1973. mem_info = &res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info;
  1974. mem_info->mem_type = BNA_MEM_T_DMA;
  1975. mem_info->len = PAGE_SIZE * dpage_count;
  1976. mem_info->num = q_cfg->num_paths;
  1977. res_info[BNA_RX_RES_MEM_T_HQPT].res_type = BNA_RES_T_MEM;
  1978. mem_info = &res_info[BNA_RX_RES_MEM_T_HQPT].res_u.mem_info;
  1979. mem_info->mem_type = BNA_MEM_T_DMA;
  1980. mem_info->len = hpage_count * sizeof(struct bna_dma_addr);
  1981. mem_info->num = (hpage_count ? q_cfg->num_paths : 0);
  1982. res_info[BNA_RX_RES_MEM_T_HSWQPT].res_type = BNA_RES_T_MEM;
  1983. mem_info = &res_info[BNA_RX_RES_MEM_T_HSWQPT].res_u.mem_info;
  1984. mem_info->mem_type = BNA_MEM_T_KVA;
  1985. mem_info->len = hpage_count * sizeof(void *);
  1986. mem_info->num = (hpage_count ? q_cfg->num_paths : 0);
  1987. res_info[BNA_RX_RES_MEM_T_HPAGE].res_type = BNA_RES_T_MEM;
  1988. mem_info = &res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info;
  1989. mem_info->mem_type = BNA_MEM_T_DMA;
  1990. mem_info->len = PAGE_SIZE * hpage_count;
  1991. mem_info->num = (hpage_count ? q_cfg->num_paths : 0);
  1992. res_info[BNA_RX_RES_MEM_T_IBIDX].res_type = BNA_RES_T_MEM;
  1993. mem_info = &res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info;
  1994. mem_info->mem_type = BNA_MEM_T_DMA;
  1995. mem_info->len = BFI_IBIDX_SIZE;
  1996. mem_info->num = q_cfg->num_paths;
  1997. res_info[BNA_RX_RES_MEM_T_RIT].res_type = BNA_RES_T_MEM;
  1998. mem_info = &res_info[BNA_RX_RES_MEM_T_RIT].res_u.mem_info;
  1999. mem_info->mem_type = BNA_MEM_T_KVA;
  2000. mem_info->len = BFI_ENET_RSS_RIT_MAX;
  2001. mem_info->num = 1;
  2002. res_info[BNA_RX_RES_T_INTR].res_type = BNA_RES_T_INTR;
  2003. res_info[BNA_RX_RES_T_INTR].res_u.intr_info.intr_type = BNA_INTR_T_MSIX;
  2004. res_info[BNA_RX_RES_T_INTR].res_u.intr_info.num = q_cfg->num_paths;
  2005. }
  2006. struct bna_rx *
  2007. bna_rx_create(struct bna *bna, struct bnad *bnad,
  2008. struct bna_rx_config *rx_cfg,
  2009. const struct bna_rx_event_cbfn *rx_cbfn,
  2010. struct bna_res_info *res_info,
  2011. void *priv)
  2012. {
  2013. struct bna_rx_mod *rx_mod = &bna->rx_mod;
  2014. struct bna_rx *rx;
  2015. struct bna_rxp *rxp;
  2016. struct bna_rxq *q0;
  2017. struct bna_rxq *q1;
  2018. struct bna_intr_info *intr_info;
  2019. u32 page_count;
  2020. struct bna_mem_descr *ccb_mem;
  2021. struct bna_mem_descr *rcb_mem;
  2022. struct bna_mem_descr *unmapq_mem;
  2023. struct bna_mem_descr *cqpt_mem;
  2024. struct bna_mem_descr *cswqpt_mem;
  2025. struct bna_mem_descr *cpage_mem;
  2026. struct bna_mem_descr *hqpt_mem;
  2027. struct bna_mem_descr *dqpt_mem;
  2028. struct bna_mem_descr *hsqpt_mem;
  2029. struct bna_mem_descr *dsqpt_mem;
  2030. struct bna_mem_descr *hpage_mem;
  2031. struct bna_mem_descr *dpage_mem;
  2032. int i;
  2033. int dpage_count, hpage_count, rcb_idx;
  2034. if (!bna_rx_res_check(rx_mod, rx_cfg))
  2035. return NULL;
  2036. intr_info = &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
  2037. ccb_mem = &res_info[BNA_RX_RES_MEM_T_CCB].res_u.mem_info.mdl[0];
  2038. rcb_mem = &res_info[BNA_RX_RES_MEM_T_RCB].res_u.mem_info.mdl[0];
  2039. unmapq_mem = &res_info[BNA_RX_RES_MEM_T_UNMAPQ].res_u.mem_info.mdl[0];
  2040. cqpt_mem = &res_info[BNA_RX_RES_MEM_T_CQPT].res_u.mem_info.mdl[0];
  2041. cswqpt_mem = &res_info[BNA_RX_RES_MEM_T_CSWQPT].res_u.mem_info.mdl[0];
  2042. cpage_mem = &res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info.mdl[0];
  2043. hqpt_mem = &res_info[BNA_RX_RES_MEM_T_HQPT].res_u.mem_info.mdl[0];
  2044. dqpt_mem = &res_info[BNA_RX_RES_MEM_T_DQPT].res_u.mem_info.mdl[0];
  2045. hsqpt_mem = &res_info[BNA_RX_RES_MEM_T_HSWQPT].res_u.mem_info.mdl[0];
  2046. dsqpt_mem = &res_info[BNA_RX_RES_MEM_T_DSWQPT].res_u.mem_info.mdl[0];
  2047. hpage_mem = &res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info.mdl[0];
  2048. dpage_mem = &res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info.mdl[0];
  2049. page_count = res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info.len /
  2050. PAGE_SIZE;
  2051. dpage_count = res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info.len /
  2052. PAGE_SIZE;
  2053. hpage_count = res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info.len /
  2054. PAGE_SIZE;
  2055. rx = bna_rx_get(rx_mod, rx_cfg->rx_type);
  2056. rx->bna = bna;
  2057. rx->rx_flags = 0;
  2058. INIT_LIST_HEAD(&rx->rxp_q);
  2059. rx->stop_cbfn = NULL;
  2060. rx->stop_cbarg = NULL;
  2061. rx->priv = priv;
  2062. rx->rcb_setup_cbfn = rx_cbfn->rcb_setup_cbfn;
  2063. rx->rcb_destroy_cbfn = rx_cbfn->rcb_destroy_cbfn;
  2064. rx->ccb_setup_cbfn = rx_cbfn->ccb_setup_cbfn;
  2065. rx->ccb_destroy_cbfn = rx_cbfn->ccb_destroy_cbfn;
  2066. rx->rx_stall_cbfn = rx_cbfn->rx_stall_cbfn;
  2067. /* Following callbacks are mandatory */
  2068. rx->rx_cleanup_cbfn = rx_cbfn->rx_cleanup_cbfn;
  2069. rx->rx_post_cbfn = rx_cbfn->rx_post_cbfn;
  2070. if (rx->bna->rx_mod.flags & BNA_RX_MOD_F_ENET_STARTED) {
  2071. switch (rx->type) {
  2072. case BNA_RX_T_REGULAR:
  2073. if (!(rx->bna->rx_mod.flags &
  2074. BNA_RX_MOD_F_ENET_LOOPBACK))
  2075. rx->rx_flags |= BNA_RX_F_ENET_STARTED;
  2076. break;
  2077. case BNA_RX_T_LOOPBACK:
  2078. if (rx->bna->rx_mod.flags & BNA_RX_MOD_F_ENET_LOOPBACK)
  2079. rx->rx_flags |= BNA_RX_F_ENET_STARTED;
  2080. break;
  2081. }
  2082. }
  2083. rx->num_paths = rx_cfg->num_paths;
  2084. for (i = 0, rcb_idx = 0; i < rx->num_paths; i++) {
  2085. rxp = bna_rxp_get(rx_mod);
  2086. list_add_tail(&rxp->qe, &rx->rxp_q);
  2087. rxp->type = rx_cfg->rxp_type;
  2088. rxp->rx = rx;
  2089. rxp->cq.rx = rx;
  2090. q0 = bna_rxq_get(rx_mod);
  2091. if (BNA_RXP_SINGLE == rx_cfg->rxp_type)
  2092. q1 = NULL;
  2093. else
  2094. q1 = bna_rxq_get(rx_mod);
  2095. if (1 == intr_info->num)
  2096. rxp->vector = intr_info->idl[0].vector;
  2097. else
  2098. rxp->vector = intr_info->idl[i].vector;
  2099. /* Setup IB */
  2100. rxp->cq.ib.ib_seg_host_addr.lsb =
  2101. res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.lsb;
  2102. rxp->cq.ib.ib_seg_host_addr.msb =
  2103. res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.msb;
  2104. rxp->cq.ib.ib_seg_host_addr_kva =
  2105. res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].kva;
  2106. rxp->cq.ib.intr_type = intr_info->intr_type;
  2107. if (intr_info->intr_type == BNA_INTR_T_MSIX)
  2108. rxp->cq.ib.intr_vector = rxp->vector;
  2109. else
  2110. rxp->cq.ib.intr_vector = (1 << rxp->vector);
  2111. rxp->cq.ib.coalescing_timeo = rx_cfg->coalescing_timeo;
  2112. rxp->cq.ib.interpkt_count = BFI_RX_INTERPKT_COUNT;
  2113. rxp->cq.ib.interpkt_timeo = BFI_RX_INTERPKT_TIMEO;
  2114. bna_rxp_add_rxqs(rxp, q0, q1);
  2115. /* Setup large Q */
  2116. q0->rx = rx;
  2117. q0->rxp = rxp;
  2118. q0->rcb = (struct bna_rcb *) rcb_mem[rcb_idx].kva;
  2119. q0->rcb->unmap_q = (void *)unmapq_mem[rcb_idx].kva;
  2120. rcb_idx++;
  2121. q0->rcb->q_depth = rx_cfg->q_depth;
  2122. q0->rcb->rxq = q0;
  2123. q0->rcb->bnad = bna->bnad;
  2124. q0->rcb->id = 0;
  2125. q0->rx_packets = q0->rx_bytes = 0;
  2126. q0->rx_packets_with_error = q0->rxbuf_alloc_failed = 0;
  2127. bna_rxq_qpt_setup(q0, rxp, dpage_count, PAGE_SIZE,
  2128. &dqpt_mem[i], &dsqpt_mem[i], &dpage_mem[i]);
  2129. if (rx->rcb_setup_cbfn)
  2130. rx->rcb_setup_cbfn(bnad, q0->rcb);
  2131. /* Setup small Q */
  2132. if (q1) {
  2133. q1->rx = rx;
  2134. q1->rxp = rxp;
  2135. q1->rcb = (struct bna_rcb *) rcb_mem[rcb_idx].kva;
  2136. q1->rcb->unmap_q = (void *)unmapq_mem[rcb_idx].kva;
  2137. rcb_idx++;
  2138. q1->rcb->q_depth = rx_cfg->q_depth;
  2139. q1->rcb->rxq = q1;
  2140. q1->rcb->bnad = bna->bnad;
  2141. q1->rcb->id = 1;
  2142. q1->buffer_size = (rx_cfg->rxp_type == BNA_RXP_HDS) ?
  2143. rx_cfg->hds_config.forced_offset
  2144. : rx_cfg->small_buff_size;
  2145. q1->rx_packets = q1->rx_bytes = 0;
  2146. q1->rx_packets_with_error = q1->rxbuf_alloc_failed = 0;
  2147. bna_rxq_qpt_setup(q1, rxp, hpage_count, PAGE_SIZE,
  2148. &hqpt_mem[i], &hsqpt_mem[i],
  2149. &hpage_mem[i]);
  2150. if (rx->rcb_setup_cbfn)
  2151. rx->rcb_setup_cbfn(bnad, q1->rcb);
  2152. }
  2153. /* Setup CQ */
  2154. rxp->cq.ccb = (struct bna_ccb *) ccb_mem[i].kva;
  2155. rxp->cq.ccb->q_depth = rx_cfg->q_depth +
  2156. ((rx_cfg->rxp_type == BNA_RXP_SINGLE) ?
  2157. 0 : rx_cfg->q_depth);
  2158. rxp->cq.ccb->cq = &rxp->cq;
  2159. rxp->cq.ccb->rcb[0] = q0->rcb;
  2160. q0->rcb->ccb = rxp->cq.ccb;
  2161. if (q1) {
  2162. rxp->cq.ccb->rcb[1] = q1->rcb;
  2163. q1->rcb->ccb = rxp->cq.ccb;
  2164. }
  2165. rxp->cq.ccb->hw_producer_index =
  2166. (u32 *)rxp->cq.ib.ib_seg_host_addr_kva;
  2167. rxp->cq.ccb->i_dbell = &rxp->cq.ib.door_bell;
  2168. rxp->cq.ccb->intr_type = rxp->cq.ib.intr_type;
  2169. rxp->cq.ccb->intr_vector = rxp->cq.ib.intr_vector;
  2170. rxp->cq.ccb->rx_coalescing_timeo =
  2171. rxp->cq.ib.coalescing_timeo;
  2172. rxp->cq.ccb->pkt_rate.small_pkt_cnt = 0;
  2173. rxp->cq.ccb->pkt_rate.large_pkt_cnt = 0;
  2174. rxp->cq.ccb->bnad = bna->bnad;
  2175. rxp->cq.ccb->id = i;
  2176. bna_rxp_cqpt_setup(rxp, page_count, PAGE_SIZE,
  2177. &cqpt_mem[i], &cswqpt_mem[i], &cpage_mem[i]);
  2178. if (rx->ccb_setup_cbfn)
  2179. rx->ccb_setup_cbfn(bnad, rxp->cq.ccb);
  2180. }
  2181. rx->hds_cfg = rx_cfg->hds_config;
  2182. bna_rxf_init(&rx->rxf, rx, rx_cfg, res_info);
  2183. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  2184. rx_mod->rid_mask |= (1 << rx->rid);
  2185. return rx;
  2186. }
  2187. void
  2188. bna_rx_destroy(struct bna_rx *rx)
  2189. {
  2190. struct bna_rx_mod *rx_mod = &rx->bna->rx_mod;
  2191. struct bna_rxq *q0 = NULL;
  2192. struct bna_rxq *q1 = NULL;
  2193. struct bna_rxp *rxp;
  2194. struct list_head *qe;
  2195. bna_rxf_uninit(&rx->rxf);
  2196. while (!list_empty(&rx->rxp_q)) {
  2197. bfa_q_deq(&rx->rxp_q, &rxp);
  2198. GET_RXQS(rxp, q0, q1);
  2199. if (rx->rcb_destroy_cbfn)
  2200. rx->rcb_destroy_cbfn(rx->bna->bnad, q0->rcb);
  2201. q0->rcb = NULL;
  2202. q0->rxp = NULL;
  2203. q0->rx = NULL;
  2204. bna_rxq_put(rx_mod, q0);
  2205. if (q1) {
  2206. if (rx->rcb_destroy_cbfn)
  2207. rx->rcb_destroy_cbfn(rx->bna->bnad, q1->rcb);
  2208. q1->rcb = NULL;
  2209. q1->rxp = NULL;
  2210. q1->rx = NULL;
  2211. bna_rxq_put(rx_mod, q1);
  2212. }
  2213. rxp->rxq.slr.large = NULL;
  2214. rxp->rxq.slr.small = NULL;
  2215. if (rx->ccb_destroy_cbfn)
  2216. rx->ccb_destroy_cbfn(rx->bna->bnad, rxp->cq.ccb);
  2217. rxp->cq.ccb = NULL;
  2218. rxp->rx = NULL;
  2219. bna_rxp_put(rx_mod, rxp);
  2220. }
  2221. list_for_each(qe, &rx_mod->rx_active_q) {
  2222. if (qe == &rx->qe) {
  2223. list_del(&rx->qe);
  2224. bfa_q_qe_init(&rx->qe);
  2225. break;
  2226. }
  2227. }
  2228. rx_mod->rid_mask &= ~(1 << rx->rid);
  2229. rx->bna = NULL;
  2230. rx->priv = NULL;
  2231. bna_rx_put(rx_mod, rx);
  2232. }
  2233. void
  2234. bna_rx_enable(struct bna_rx *rx)
  2235. {
  2236. if (rx->fsm != (bfa_sm_t)bna_rx_sm_stopped)
  2237. return;
  2238. rx->rx_flags |= BNA_RX_F_ENABLED;
  2239. if (rx->rx_flags & BNA_RX_F_ENET_STARTED)
  2240. bfa_fsm_send_event(rx, RX_E_START);
  2241. }
  2242. void
  2243. bna_rx_disable(struct bna_rx *rx, enum bna_cleanup_type type,
  2244. void (*cbfn)(void *, struct bna_rx *))
  2245. {
  2246. if (type == BNA_SOFT_CLEANUP) {
  2247. /* h/w should not be accessed. Treat we're stopped */
  2248. (*cbfn)(rx->bna->bnad, rx);
  2249. } else {
  2250. rx->stop_cbfn = cbfn;
  2251. rx->stop_cbarg = rx->bna->bnad;
  2252. rx->rx_flags &= ~BNA_RX_F_ENABLED;
  2253. bfa_fsm_send_event(rx, RX_E_STOP);
  2254. }
  2255. }
  2256. void
  2257. bna_rx_cleanup_complete(struct bna_rx *rx)
  2258. {
  2259. bfa_fsm_send_event(rx, RX_E_CLEANUP_DONE);
  2260. }
  2261. enum bna_cb_status
  2262. bna_rx_mode_set(struct bna_rx *rx, enum bna_rxmode new_mode,
  2263. enum bna_rxmode bitmask,
  2264. void (*cbfn)(struct bnad *, struct bna_rx *))
  2265. {
  2266. struct bna_rxf *rxf = &rx->rxf;
  2267. int need_hw_config = 0;
  2268. /* Error checks */
  2269. if (is_promisc_enable(new_mode, bitmask)) {
  2270. /* If promisc mode is already enabled elsewhere in the system */
  2271. if ((rx->bna->promisc_rid != BFI_INVALID_RID) &&
  2272. (rx->bna->promisc_rid != rxf->rx->rid))
  2273. goto err_return;
  2274. /* If default mode is already enabled in the system */
  2275. if (rx->bna->default_mode_rid != BFI_INVALID_RID)
  2276. goto err_return;
  2277. /* Trying to enable promiscuous and default mode together */
  2278. if (is_default_enable(new_mode, bitmask))
  2279. goto err_return;
  2280. }
  2281. if (is_default_enable(new_mode, bitmask)) {
  2282. /* If default mode is already enabled elsewhere in the system */
  2283. if ((rx->bna->default_mode_rid != BFI_INVALID_RID) &&
  2284. (rx->bna->default_mode_rid != rxf->rx->rid)) {
  2285. goto err_return;
  2286. }
  2287. /* If promiscuous mode is already enabled in the system */
  2288. if (rx->bna->promisc_rid != BFI_INVALID_RID)
  2289. goto err_return;
  2290. }
  2291. /* Process the commands */
  2292. if (is_promisc_enable(new_mode, bitmask)) {
  2293. if (bna_rxf_promisc_enable(rxf))
  2294. need_hw_config = 1;
  2295. } else if (is_promisc_disable(new_mode, bitmask)) {
  2296. if (bna_rxf_promisc_disable(rxf))
  2297. need_hw_config = 1;
  2298. }
  2299. if (is_allmulti_enable(new_mode, bitmask)) {
  2300. if (bna_rxf_allmulti_enable(rxf))
  2301. need_hw_config = 1;
  2302. } else if (is_allmulti_disable(new_mode, bitmask)) {
  2303. if (bna_rxf_allmulti_disable(rxf))
  2304. need_hw_config = 1;
  2305. }
  2306. /* Trigger h/w if needed */
  2307. if (need_hw_config) {
  2308. rxf->cam_fltr_cbfn = cbfn;
  2309. rxf->cam_fltr_cbarg = rx->bna->bnad;
  2310. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  2311. } else if (cbfn)
  2312. (*cbfn)(rx->bna->bnad, rx);
  2313. return BNA_CB_SUCCESS;
  2314. err_return:
  2315. return BNA_CB_FAIL;
  2316. }
  2317. void
  2318. bna_rx_vlanfilter_enable(struct bna_rx *rx)
  2319. {
  2320. struct bna_rxf *rxf = &rx->rxf;
  2321. if (rxf->vlan_filter_status == BNA_STATUS_T_DISABLED) {
  2322. rxf->vlan_filter_status = BNA_STATUS_T_ENABLED;
  2323. rxf->vlan_pending_bitmask = (u8)BFI_VLAN_BMASK_ALL;
  2324. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  2325. }
  2326. }
  2327. void
  2328. bna_rx_coalescing_timeo_set(struct bna_rx *rx, int coalescing_timeo)
  2329. {
  2330. struct bna_rxp *rxp;
  2331. struct list_head *qe;
  2332. list_for_each(qe, &rx->rxp_q) {
  2333. rxp = (struct bna_rxp *)qe;
  2334. rxp->cq.ccb->rx_coalescing_timeo = coalescing_timeo;
  2335. bna_ib_coalescing_timeo_set(&rxp->cq.ib, coalescing_timeo);
  2336. }
  2337. }
  2338. void
  2339. bna_rx_dim_reconfig(struct bna *bna, const u32 vector[][BNA_BIAS_T_MAX])
  2340. {
  2341. int i, j;
  2342. for (i = 0; i < BNA_LOAD_T_MAX; i++)
  2343. for (j = 0; j < BNA_BIAS_T_MAX; j++)
  2344. bna->rx_mod.dim_vector[i][j] = vector[i][j];
  2345. }
  2346. void
  2347. bna_rx_dim_update(struct bna_ccb *ccb)
  2348. {
  2349. struct bna *bna = ccb->cq->rx->bna;
  2350. u32 load, bias;
  2351. u32 pkt_rt, small_rt, large_rt;
  2352. u8 coalescing_timeo;
  2353. if ((ccb->pkt_rate.small_pkt_cnt == 0) &&
  2354. (ccb->pkt_rate.large_pkt_cnt == 0))
  2355. return;
  2356. /* Arrive at preconfigured coalescing timeo value based on pkt rate */
  2357. small_rt = ccb->pkt_rate.small_pkt_cnt;
  2358. large_rt = ccb->pkt_rate.large_pkt_cnt;
  2359. pkt_rt = small_rt + large_rt;
  2360. if (pkt_rt < BNA_PKT_RATE_10K)
  2361. load = BNA_LOAD_T_LOW_4;
  2362. else if (pkt_rt < BNA_PKT_RATE_20K)
  2363. load = BNA_LOAD_T_LOW_3;
  2364. else if (pkt_rt < BNA_PKT_RATE_30K)
  2365. load = BNA_LOAD_T_LOW_2;
  2366. else if (pkt_rt < BNA_PKT_RATE_40K)
  2367. load = BNA_LOAD_T_LOW_1;
  2368. else if (pkt_rt < BNA_PKT_RATE_50K)
  2369. load = BNA_LOAD_T_HIGH_1;
  2370. else if (pkt_rt < BNA_PKT_RATE_60K)
  2371. load = BNA_LOAD_T_HIGH_2;
  2372. else if (pkt_rt < BNA_PKT_RATE_80K)
  2373. load = BNA_LOAD_T_HIGH_3;
  2374. else
  2375. load = BNA_LOAD_T_HIGH_4;
  2376. if (small_rt > (large_rt << 1))
  2377. bias = 0;
  2378. else
  2379. bias = 1;
  2380. ccb->pkt_rate.small_pkt_cnt = 0;
  2381. ccb->pkt_rate.large_pkt_cnt = 0;
  2382. coalescing_timeo = bna->rx_mod.dim_vector[load][bias];
  2383. ccb->rx_coalescing_timeo = coalescing_timeo;
  2384. /* Set it to IB */
  2385. bna_ib_coalescing_timeo_set(&ccb->cq->ib, coalescing_timeo);
  2386. }
  2387. const u32 bna_napi_dim_vector[BNA_LOAD_T_MAX][BNA_BIAS_T_MAX] = {
  2388. {12, 12},
  2389. {6, 10},
  2390. {5, 10},
  2391. {4, 8},
  2392. {3, 6},
  2393. {3, 6},
  2394. {2, 4},
  2395. {1, 2},
  2396. };
  2397. /* TX */
  2398. #define call_tx_stop_cbfn(tx) \
  2399. do { \
  2400. if ((tx)->stop_cbfn) { \
  2401. void (*cbfn)(void *, struct bna_tx *); \
  2402. void *cbarg; \
  2403. cbfn = (tx)->stop_cbfn; \
  2404. cbarg = (tx)->stop_cbarg; \
  2405. (tx)->stop_cbfn = NULL; \
  2406. (tx)->stop_cbarg = NULL; \
  2407. cbfn(cbarg, (tx)); \
  2408. } \
  2409. } while (0)
  2410. #define call_tx_prio_change_cbfn(tx) \
  2411. do { \
  2412. if ((tx)->prio_change_cbfn) { \
  2413. void (*cbfn)(struct bnad *, struct bna_tx *); \
  2414. cbfn = (tx)->prio_change_cbfn; \
  2415. (tx)->prio_change_cbfn = NULL; \
  2416. cbfn((tx)->bna->bnad, (tx)); \
  2417. } \
  2418. } while (0)
  2419. static void bna_tx_mod_cb_tx_stopped(void *tx_mod, struct bna_tx *tx);
  2420. static void bna_bfi_tx_enet_start(struct bna_tx *tx);
  2421. static void bna_tx_enet_stop(struct bna_tx *tx);
  2422. enum bna_tx_event {
  2423. TX_E_START = 1,
  2424. TX_E_STOP = 2,
  2425. TX_E_FAIL = 3,
  2426. TX_E_STARTED = 4,
  2427. TX_E_STOPPED = 5,
  2428. TX_E_PRIO_CHANGE = 6,
  2429. TX_E_CLEANUP_DONE = 7,
  2430. TX_E_BW_UPDATE = 8,
  2431. };
  2432. bfa_fsm_state_decl(bna_tx, stopped, struct bna_tx, enum bna_tx_event);
  2433. bfa_fsm_state_decl(bna_tx, start_wait, struct bna_tx, enum bna_tx_event);
  2434. bfa_fsm_state_decl(bna_tx, started, struct bna_tx, enum bna_tx_event);
  2435. bfa_fsm_state_decl(bna_tx, stop_wait, struct bna_tx, enum bna_tx_event);
  2436. bfa_fsm_state_decl(bna_tx, cleanup_wait, struct bna_tx,
  2437. enum bna_tx_event);
  2438. bfa_fsm_state_decl(bna_tx, prio_stop_wait, struct bna_tx,
  2439. enum bna_tx_event);
  2440. bfa_fsm_state_decl(bna_tx, prio_cleanup_wait, struct bna_tx,
  2441. enum bna_tx_event);
  2442. bfa_fsm_state_decl(bna_tx, failed, struct bna_tx, enum bna_tx_event);
  2443. bfa_fsm_state_decl(bna_tx, quiesce_wait, struct bna_tx,
  2444. enum bna_tx_event);
  2445. static void
  2446. bna_tx_sm_stopped_entry(struct bna_tx *tx)
  2447. {
  2448. call_tx_stop_cbfn(tx);
  2449. }
  2450. static void
  2451. bna_tx_sm_stopped(struct bna_tx *tx, enum bna_tx_event event)
  2452. {
  2453. switch (event) {
  2454. case TX_E_START:
  2455. bfa_fsm_set_state(tx, bna_tx_sm_start_wait);
  2456. break;
  2457. case TX_E_STOP:
  2458. call_tx_stop_cbfn(tx);
  2459. break;
  2460. case TX_E_FAIL:
  2461. /* No-op */
  2462. break;
  2463. case TX_E_PRIO_CHANGE:
  2464. call_tx_prio_change_cbfn(tx);
  2465. break;
  2466. case TX_E_BW_UPDATE:
  2467. /* No-op */
  2468. break;
  2469. default:
  2470. bfa_sm_fault(event);
  2471. }
  2472. }
  2473. static void
  2474. bna_tx_sm_start_wait_entry(struct bna_tx *tx)
  2475. {
  2476. bna_bfi_tx_enet_start(tx);
  2477. }
  2478. static void
  2479. bna_tx_sm_start_wait(struct bna_tx *tx, enum bna_tx_event event)
  2480. {
  2481. switch (event) {
  2482. case TX_E_STOP:
  2483. tx->flags &= ~(BNA_TX_F_PRIO_CHANGED | BNA_TX_F_BW_UPDATED);
  2484. bfa_fsm_set_state(tx, bna_tx_sm_stop_wait);
  2485. break;
  2486. case TX_E_FAIL:
  2487. tx->flags &= ~(BNA_TX_F_PRIO_CHANGED | BNA_TX_F_BW_UPDATED);
  2488. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  2489. break;
  2490. case TX_E_STARTED:
  2491. if (tx->flags & (BNA_TX_F_PRIO_CHANGED | BNA_TX_F_BW_UPDATED)) {
  2492. tx->flags &= ~(BNA_TX_F_PRIO_CHANGED |
  2493. BNA_TX_F_BW_UPDATED);
  2494. bfa_fsm_set_state(tx, bna_tx_sm_prio_stop_wait);
  2495. } else
  2496. bfa_fsm_set_state(tx, bna_tx_sm_started);
  2497. break;
  2498. case TX_E_PRIO_CHANGE:
  2499. tx->flags |= BNA_TX_F_PRIO_CHANGED;
  2500. break;
  2501. case TX_E_BW_UPDATE:
  2502. tx->flags |= BNA_TX_F_BW_UPDATED;
  2503. break;
  2504. default:
  2505. bfa_sm_fault(event);
  2506. }
  2507. }
  2508. static void
  2509. bna_tx_sm_started_entry(struct bna_tx *tx)
  2510. {
  2511. struct bna_txq *txq;
  2512. struct list_head *qe;
  2513. int is_regular = (tx->type == BNA_TX_T_REGULAR);
  2514. list_for_each(qe, &tx->txq_q) {
  2515. txq = (struct bna_txq *)qe;
  2516. txq->tcb->priority = txq->priority;
  2517. /* Start IB */
  2518. bna_ib_start(tx->bna, &txq->ib, is_regular);
  2519. }
  2520. tx->tx_resume_cbfn(tx->bna->bnad, tx);
  2521. }
  2522. static void
  2523. bna_tx_sm_started(struct bna_tx *tx, enum bna_tx_event event)
  2524. {
  2525. switch (event) {
  2526. case TX_E_STOP:
  2527. bfa_fsm_set_state(tx, bna_tx_sm_stop_wait);
  2528. tx->tx_stall_cbfn(tx->bna->bnad, tx);
  2529. bna_tx_enet_stop(tx);
  2530. break;
  2531. case TX_E_FAIL:
  2532. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2533. tx->tx_stall_cbfn(tx->bna->bnad, tx);
  2534. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2535. break;
  2536. case TX_E_PRIO_CHANGE:
  2537. case TX_E_BW_UPDATE:
  2538. bfa_fsm_set_state(tx, bna_tx_sm_prio_stop_wait);
  2539. break;
  2540. default:
  2541. bfa_sm_fault(event);
  2542. }
  2543. }
  2544. static void
  2545. bna_tx_sm_stop_wait_entry(struct bna_tx *tx)
  2546. {
  2547. }
  2548. static void
  2549. bna_tx_sm_stop_wait(struct bna_tx *tx, enum bna_tx_event event)
  2550. {
  2551. switch (event) {
  2552. case TX_E_FAIL:
  2553. case TX_E_STOPPED:
  2554. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2555. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2556. break;
  2557. case TX_E_STARTED:
  2558. /**
  2559. * We are here due to start_wait -> stop_wait transition on
  2560. * TX_E_STOP event
  2561. */
  2562. bna_tx_enet_stop(tx);
  2563. break;
  2564. case TX_E_PRIO_CHANGE:
  2565. case TX_E_BW_UPDATE:
  2566. /* No-op */
  2567. break;
  2568. default:
  2569. bfa_sm_fault(event);
  2570. }
  2571. }
  2572. static void
  2573. bna_tx_sm_cleanup_wait_entry(struct bna_tx *tx)
  2574. {
  2575. }
  2576. static void
  2577. bna_tx_sm_cleanup_wait(struct bna_tx *tx, enum bna_tx_event event)
  2578. {
  2579. switch (event) {
  2580. case TX_E_FAIL:
  2581. case TX_E_PRIO_CHANGE:
  2582. case TX_E_BW_UPDATE:
  2583. /* No-op */
  2584. break;
  2585. case TX_E_CLEANUP_DONE:
  2586. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  2587. break;
  2588. default:
  2589. bfa_sm_fault(event);
  2590. }
  2591. }
  2592. static void
  2593. bna_tx_sm_prio_stop_wait_entry(struct bna_tx *tx)
  2594. {
  2595. tx->tx_stall_cbfn(tx->bna->bnad, tx);
  2596. bna_tx_enet_stop(tx);
  2597. }
  2598. static void
  2599. bna_tx_sm_prio_stop_wait(struct bna_tx *tx, enum bna_tx_event event)
  2600. {
  2601. switch (event) {
  2602. case TX_E_STOP:
  2603. bfa_fsm_set_state(tx, bna_tx_sm_stop_wait);
  2604. break;
  2605. case TX_E_FAIL:
  2606. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2607. call_tx_prio_change_cbfn(tx);
  2608. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2609. break;
  2610. case TX_E_STOPPED:
  2611. bfa_fsm_set_state(tx, bna_tx_sm_prio_cleanup_wait);
  2612. break;
  2613. case TX_E_PRIO_CHANGE:
  2614. case TX_E_BW_UPDATE:
  2615. /* No-op */
  2616. break;
  2617. default:
  2618. bfa_sm_fault(event);
  2619. }
  2620. }
  2621. static void
  2622. bna_tx_sm_prio_cleanup_wait_entry(struct bna_tx *tx)
  2623. {
  2624. call_tx_prio_change_cbfn(tx);
  2625. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2626. }
  2627. static void
  2628. bna_tx_sm_prio_cleanup_wait(struct bna_tx *tx, enum bna_tx_event event)
  2629. {
  2630. switch (event) {
  2631. case TX_E_STOP:
  2632. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2633. break;
  2634. case TX_E_FAIL:
  2635. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2636. break;
  2637. case TX_E_PRIO_CHANGE:
  2638. case TX_E_BW_UPDATE:
  2639. /* No-op */
  2640. break;
  2641. case TX_E_CLEANUP_DONE:
  2642. bfa_fsm_set_state(tx, bna_tx_sm_start_wait);
  2643. break;
  2644. default:
  2645. bfa_sm_fault(event);
  2646. }
  2647. }
  2648. static void
  2649. bna_tx_sm_failed_entry(struct bna_tx *tx)
  2650. {
  2651. }
  2652. static void
  2653. bna_tx_sm_failed(struct bna_tx *tx, enum bna_tx_event event)
  2654. {
  2655. switch (event) {
  2656. case TX_E_START:
  2657. bfa_fsm_set_state(tx, bna_tx_sm_quiesce_wait);
  2658. break;
  2659. case TX_E_STOP:
  2660. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2661. break;
  2662. case TX_E_FAIL:
  2663. /* No-op */
  2664. break;
  2665. case TX_E_CLEANUP_DONE:
  2666. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  2667. break;
  2668. default:
  2669. bfa_sm_fault(event);
  2670. }
  2671. }
  2672. static void
  2673. bna_tx_sm_quiesce_wait_entry(struct bna_tx *tx)
  2674. {
  2675. }
  2676. static void
  2677. bna_tx_sm_quiesce_wait(struct bna_tx *tx, enum bna_tx_event event)
  2678. {
  2679. switch (event) {
  2680. case TX_E_STOP:
  2681. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2682. break;
  2683. case TX_E_FAIL:
  2684. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2685. break;
  2686. case TX_E_CLEANUP_DONE:
  2687. bfa_fsm_set_state(tx, bna_tx_sm_start_wait);
  2688. break;
  2689. case TX_E_BW_UPDATE:
  2690. /* No-op */
  2691. break;
  2692. default:
  2693. bfa_sm_fault(event);
  2694. }
  2695. }
  2696. static void
  2697. bna_bfi_tx_enet_start(struct bna_tx *tx)
  2698. {
  2699. struct bfi_enet_tx_cfg_req *cfg_req = &tx->bfi_enet_cmd.cfg_req;
  2700. struct bna_txq *txq = NULL;
  2701. struct list_head *qe;
  2702. int i;
  2703. bfi_msgq_mhdr_set(cfg_req->mh, BFI_MC_ENET,
  2704. BFI_ENET_H2I_TX_CFG_SET_REQ, 0, tx->rid);
  2705. cfg_req->mh.num_entries = htons(
  2706. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_tx_cfg_req)));
  2707. cfg_req->num_queues = tx->num_txq;
  2708. for (i = 0, qe = bfa_q_first(&tx->txq_q);
  2709. i < tx->num_txq;
  2710. i++, qe = bfa_q_next(qe)) {
  2711. txq = (struct bna_txq *)qe;
  2712. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].q.q, &txq->qpt);
  2713. cfg_req->q_cfg[i].q.priority = txq->priority;
  2714. cfg_req->q_cfg[i].ib.index_addr.a32.addr_lo =
  2715. txq->ib.ib_seg_host_addr.lsb;
  2716. cfg_req->q_cfg[i].ib.index_addr.a32.addr_hi =
  2717. txq->ib.ib_seg_host_addr.msb;
  2718. cfg_req->q_cfg[i].ib.intr.msix_index =
  2719. htons((u16)txq->ib.intr_vector);
  2720. }
  2721. cfg_req->ib_cfg.int_pkt_dma = BNA_STATUS_T_ENABLED;
  2722. cfg_req->ib_cfg.int_enabled = BNA_STATUS_T_ENABLED;
  2723. cfg_req->ib_cfg.int_pkt_enabled = BNA_STATUS_T_DISABLED;
  2724. cfg_req->ib_cfg.continuous_coalescing = BNA_STATUS_T_ENABLED;
  2725. cfg_req->ib_cfg.msix = (txq->ib.intr_type == BNA_INTR_T_MSIX)
  2726. ? BNA_STATUS_T_ENABLED : BNA_STATUS_T_DISABLED;
  2727. cfg_req->ib_cfg.coalescing_timeout =
  2728. htonl((u32)txq->ib.coalescing_timeo);
  2729. cfg_req->ib_cfg.inter_pkt_timeout =
  2730. htonl((u32)txq->ib.interpkt_timeo);
  2731. cfg_req->ib_cfg.inter_pkt_count = (u8)txq->ib.interpkt_count;
  2732. cfg_req->tx_cfg.vlan_mode = BFI_ENET_TX_VLAN_WI;
  2733. cfg_req->tx_cfg.vlan_id = htons((u16)tx->txf_vlan_id);
  2734. cfg_req->tx_cfg.admit_tagged_frame = BNA_STATUS_T_DISABLED;
  2735. cfg_req->tx_cfg.apply_vlan_filter = BNA_STATUS_T_DISABLED;
  2736. bfa_msgq_cmd_set(&tx->msgq_cmd, NULL, NULL,
  2737. sizeof(struct bfi_enet_tx_cfg_req), &cfg_req->mh);
  2738. bfa_msgq_cmd_post(&tx->bna->msgq, &tx->msgq_cmd);
  2739. }
  2740. static void
  2741. bna_bfi_tx_enet_stop(struct bna_tx *tx)
  2742. {
  2743. struct bfi_enet_req *req = &tx->bfi_enet_cmd.req;
  2744. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  2745. BFI_ENET_H2I_TX_CFG_CLR_REQ, 0, tx->rid);
  2746. req->mh.num_entries = htons(
  2747. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_req)));
  2748. bfa_msgq_cmd_set(&tx->msgq_cmd, NULL, NULL, sizeof(struct bfi_enet_req),
  2749. &req->mh);
  2750. bfa_msgq_cmd_post(&tx->bna->msgq, &tx->msgq_cmd);
  2751. }
  2752. static void
  2753. bna_tx_enet_stop(struct bna_tx *tx)
  2754. {
  2755. struct bna_txq *txq;
  2756. struct list_head *qe;
  2757. /* Stop IB */
  2758. list_for_each(qe, &tx->txq_q) {
  2759. txq = (struct bna_txq *)qe;
  2760. bna_ib_stop(tx->bna, &txq->ib);
  2761. }
  2762. bna_bfi_tx_enet_stop(tx);
  2763. }
  2764. static void
  2765. bna_txq_qpt_setup(struct bna_txq *txq, int page_count, int page_size,
  2766. struct bna_mem_descr *qpt_mem,
  2767. struct bna_mem_descr *swqpt_mem,
  2768. struct bna_mem_descr *page_mem)
  2769. {
  2770. u8 *kva;
  2771. u64 dma;
  2772. struct bna_dma_addr bna_dma;
  2773. int i;
  2774. txq->qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
  2775. txq->qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
  2776. txq->qpt.kv_qpt_ptr = qpt_mem->kva;
  2777. txq->qpt.page_count = page_count;
  2778. txq->qpt.page_size = page_size;
  2779. txq->tcb->sw_qpt = (void **) swqpt_mem->kva;
  2780. txq->tcb->sw_q = page_mem->kva;
  2781. kva = page_mem->kva;
  2782. BNA_GET_DMA_ADDR(&page_mem->dma, dma);
  2783. for (i = 0; i < page_count; i++) {
  2784. txq->tcb->sw_qpt[i] = kva;
  2785. kva += PAGE_SIZE;
  2786. BNA_SET_DMA_ADDR(dma, &bna_dma);
  2787. ((struct bna_dma_addr *)txq->qpt.kv_qpt_ptr)[i].lsb =
  2788. bna_dma.lsb;
  2789. ((struct bna_dma_addr *)txq->qpt.kv_qpt_ptr)[i].msb =
  2790. bna_dma.msb;
  2791. dma += PAGE_SIZE;
  2792. }
  2793. }
  2794. static struct bna_tx *
  2795. bna_tx_get(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
  2796. {
  2797. struct list_head *qe = NULL;
  2798. struct bna_tx *tx = NULL;
  2799. if (list_empty(&tx_mod->tx_free_q))
  2800. return NULL;
  2801. if (type == BNA_TX_T_REGULAR) {
  2802. bfa_q_deq(&tx_mod->tx_free_q, &qe);
  2803. } else {
  2804. bfa_q_deq_tail(&tx_mod->tx_free_q, &qe);
  2805. }
  2806. tx = (struct bna_tx *)qe;
  2807. bfa_q_qe_init(&tx->qe);
  2808. tx->type = type;
  2809. return tx;
  2810. }
  2811. static void
  2812. bna_tx_free(struct bna_tx *tx)
  2813. {
  2814. struct bna_tx_mod *tx_mod = &tx->bna->tx_mod;
  2815. struct bna_txq *txq;
  2816. struct list_head *prev_qe;
  2817. struct list_head *qe;
  2818. while (!list_empty(&tx->txq_q)) {
  2819. bfa_q_deq(&tx->txq_q, &txq);
  2820. bfa_q_qe_init(&txq->qe);
  2821. txq->tcb = NULL;
  2822. txq->tx = NULL;
  2823. list_add_tail(&txq->qe, &tx_mod->txq_free_q);
  2824. }
  2825. list_for_each(qe, &tx_mod->tx_active_q) {
  2826. if (qe == &tx->qe) {
  2827. list_del(&tx->qe);
  2828. bfa_q_qe_init(&tx->qe);
  2829. break;
  2830. }
  2831. }
  2832. tx->bna = NULL;
  2833. tx->priv = NULL;
  2834. prev_qe = NULL;
  2835. list_for_each(qe, &tx_mod->tx_free_q) {
  2836. if (((struct bna_tx *)qe)->rid < tx->rid)
  2837. prev_qe = qe;
  2838. else {
  2839. break;
  2840. }
  2841. }
  2842. if (prev_qe == NULL) {
  2843. /* This is the first entry */
  2844. bfa_q_enq_head(&tx_mod->tx_free_q, &tx->qe);
  2845. } else if (bfa_q_next(prev_qe) == &tx_mod->tx_free_q) {
  2846. /* This is the last entry */
  2847. list_add_tail(&tx->qe, &tx_mod->tx_free_q);
  2848. } else {
  2849. /* Somewhere in the middle */
  2850. bfa_q_next(&tx->qe) = bfa_q_next(prev_qe);
  2851. bfa_q_prev(&tx->qe) = prev_qe;
  2852. bfa_q_next(prev_qe) = &tx->qe;
  2853. bfa_q_prev(bfa_q_next(&tx->qe)) = &tx->qe;
  2854. }
  2855. }
  2856. static void
  2857. bna_tx_start(struct bna_tx *tx)
  2858. {
  2859. tx->flags |= BNA_TX_F_ENET_STARTED;
  2860. if (tx->flags & BNA_TX_F_ENABLED)
  2861. bfa_fsm_send_event(tx, TX_E_START);
  2862. }
  2863. static void
  2864. bna_tx_stop(struct bna_tx *tx)
  2865. {
  2866. tx->stop_cbfn = bna_tx_mod_cb_tx_stopped;
  2867. tx->stop_cbarg = &tx->bna->tx_mod;
  2868. tx->flags &= ~BNA_TX_F_ENET_STARTED;
  2869. bfa_fsm_send_event(tx, TX_E_STOP);
  2870. }
  2871. static void
  2872. bna_tx_fail(struct bna_tx *tx)
  2873. {
  2874. tx->flags &= ~BNA_TX_F_ENET_STARTED;
  2875. bfa_fsm_send_event(tx, TX_E_FAIL);
  2876. }
  2877. void
  2878. bna_bfi_tx_enet_start_rsp(struct bna_tx *tx, struct bfi_msgq_mhdr *msghdr)
  2879. {
  2880. struct bfi_enet_tx_cfg_rsp *cfg_rsp = &tx->bfi_enet_cmd.cfg_rsp;
  2881. struct bna_txq *txq = NULL;
  2882. struct list_head *qe;
  2883. int i;
  2884. bfa_msgq_rsp_copy(&tx->bna->msgq, (u8 *)cfg_rsp,
  2885. sizeof(struct bfi_enet_tx_cfg_rsp));
  2886. tx->hw_id = cfg_rsp->hw_id;
  2887. for (i = 0, qe = bfa_q_first(&tx->txq_q);
  2888. i < tx->num_txq; i++, qe = bfa_q_next(qe)) {
  2889. txq = (struct bna_txq *)qe;
  2890. /* Setup doorbells */
  2891. txq->tcb->i_dbell->doorbell_addr =
  2892. tx->bna->pcidev.pci_bar_kva
  2893. + ntohl(cfg_rsp->q_handles[i].i_dbell);
  2894. txq->tcb->q_dbell =
  2895. tx->bna->pcidev.pci_bar_kva
  2896. + ntohl(cfg_rsp->q_handles[i].q_dbell);
  2897. txq->hw_id = cfg_rsp->q_handles[i].hw_qid;
  2898. /* Initialize producer/consumer indexes */
  2899. (*txq->tcb->hw_consumer_index) = 0;
  2900. txq->tcb->producer_index = txq->tcb->consumer_index = 0;
  2901. }
  2902. bfa_fsm_send_event(tx, TX_E_STARTED);
  2903. }
  2904. void
  2905. bna_bfi_tx_enet_stop_rsp(struct bna_tx *tx, struct bfi_msgq_mhdr *msghdr)
  2906. {
  2907. bfa_fsm_send_event(tx, TX_E_STOPPED);
  2908. }
  2909. void
  2910. bna_bfi_bw_update_aen(struct bna_tx_mod *tx_mod)
  2911. {
  2912. struct bna_tx *tx;
  2913. struct list_head *qe;
  2914. list_for_each(qe, &tx_mod->tx_active_q) {
  2915. tx = (struct bna_tx *)qe;
  2916. bfa_fsm_send_event(tx, TX_E_BW_UPDATE);
  2917. }
  2918. }
  2919. void
  2920. bna_tx_res_req(int num_txq, int txq_depth, struct bna_res_info *res_info)
  2921. {
  2922. u32 q_size;
  2923. u32 page_count;
  2924. struct bna_mem_info *mem_info;
  2925. res_info[BNA_TX_RES_MEM_T_TCB].res_type = BNA_RES_T_MEM;
  2926. mem_info = &res_info[BNA_TX_RES_MEM_T_TCB].res_u.mem_info;
  2927. mem_info->mem_type = BNA_MEM_T_KVA;
  2928. mem_info->len = sizeof(struct bna_tcb);
  2929. mem_info->num = num_txq;
  2930. q_size = txq_depth * BFI_TXQ_WI_SIZE;
  2931. q_size = ALIGN(q_size, PAGE_SIZE);
  2932. page_count = q_size >> PAGE_SHIFT;
  2933. res_info[BNA_TX_RES_MEM_T_QPT].res_type = BNA_RES_T_MEM;
  2934. mem_info = &res_info[BNA_TX_RES_MEM_T_QPT].res_u.mem_info;
  2935. mem_info->mem_type = BNA_MEM_T_DMA;
  2936. mem_info->len = page_count * sizeof(struct bna_dma_addr);
  2937. mem_info->num = num_txq;
  2938. res_info[BNA_TX_RES_MEM_T_SWQPT].res_type = BNA_RES_T_MEM;
  2939. mem_info = &res_info[BNA_TX_RES_MEM_T_SWQPT].res_u.mem_info;
  2940. mem_info->mem_type = BNA_MEM_T_KVA;
  2941. mem_info->len = page_count * sizeof(void *);
  2942. mem_info->num = num_txq;
  2943. res_info[BNA_TX_RES_MEM_T_PAGE].res_type = BNA_RES_T_MEM;
  2944. mem_info = &res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info;
  2945. mem_info->mem_type = BNA_MEM_T_DMA;
  2946. mem_info->len = PAGE_SIZE * page_count;
  2947. mem_info->num = num_txq;
  2948. res_info[BNA_TX_RES_MEM_T_IBIDX].res_type = BNA_RES_T_MEM;
  2949. mem_info = &res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info;
  2950. mem_info->mem_type = BNA_MEM_T_DMA;
  2951. mem_info->len = BFI_IBIDX_SIZE;
  2952. mem_info->num = num_txq;
  2953. res_info[BNA_TX_RES_INTR_T_TXCMPL].res_type = BNA_RES_T_INTR;
  2954. res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info.intr_type =
  2955. BNA_INTR_T_MSIX;
  2956. res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info.num = num_txq;
  2957. }
  2958. struct bna_tx *
  2959. bna_tx_create(struct bna *bna, struct bnad *bnad,
  2960. struct bna_tx_config *tx_cfg,
  2961. const struct bna_tx_event_cbfn *tx_cbfn,
  2962. struct bna_res_info *res_info, void *priv)
  2963. {
  2964. struct bna_intr_info *intr_info;
  2965. struct bna_tx_mod *tx_mod = &bna->tx_mod;
  2966. struct bna_tx *tx;
  2967. struct bna_txq *txq;
  2968. struct list_head *qe;
  2969. int page_count;
  2970. int i;
  2971. intr_info = &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
  2972. page_count = (res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info.len) /
  2973. PAGE_SIZE;
  2974. /**
  2975. * Get resources
  2976. */
  2977. if ((intr_info->num != 1) && (intr_info->num != tx_cfg->num_txq))
  2978. return NULL;
  2979. /* Tx */
  2980. tx = bna_tx_get(tx_mod, tx_cfg->tx_type);
  2981. if (!tx)
  2982. return NULL;
  2983. tx->bna = bna;
  2984. tx->priv = priv;
  2985. /* TxQs */
  2986. INIT_LIST_HEAD(&tx->txq_q);
  2987. for (i = 0; i < tx_cfg->num_txq; i++) {
  2988. if (list_empty(&tx_mod->txq_free_q))
  2989. goto err_return;
  2990. bfa_q_deq(&tx_mod->txq_free_q, &txq);
  2991. bfa_q_qe_init(&txq->qe);
  2992. list_add_tail(&txq->qe, &tx->txq_q);
  2993. txq->tx = tx;
  2994. }
  2995. /*
  2996. * Initialize
  2997. */
  2998. /* Tx */
  2999. tx->tcb_setup_cbfn = tx_cbfn->tcb_setup_cbfn;
  3000. tx->tcb_destroy_cbfn = tx_cbfn->tcb_destroy_cbfn;
  3001. /* Following callbacks are mandatory */
  3002. tx->tx_stall_cbfn = tx_cbfn->tx_stall_cbfn;
  3003. tx->tx_resume_cbfn = tx_cbfn->tx_resume_cbfn;
  3004. tx->tx_cleanup_cbfn = tx_cbfn->tx_cleanup_cbfn;
  3005. list_add_tail(&tx->qe, &tx_mod->tx_active_q);
  3006. tx->num_txq = tx_cfg->num_txq;
  3007. tx->flags = 0;
  3008. if (tx->bna->tx_mod.flags & BNA_TX_MOD_F_ENET_STARTED) {
  3009. switch (tx->type) {
  3010. case BNA_TX_T_REGULAR:
  3011. if (!(tx->bna->tx_mod.flags &
  3012. BNA_TX_MOD_F_ENET_LOOPBACK))
  3013. tx->flags |= BNA_TX_F_ENET_STARTED;
  3014. break;
  3015. case BNA_TX_T_LOOPBACK:
  3016. if (tx->bna->tx_mod.flags & BNA_TX_MOD_F_ENET_LOOPBACK)
  3017. tx->flags |= BNA_TX_F_ENET_STARTED;
  3018. break;
  3019. }
  3020. }
  3021. /* TxQ */
  3022. i = 0;
  3023. list_for_each(qe, &tx->txq_q) {
  3024. txq = (struct bna_txq *)qe;
  3025. txq->tcb = (struct bna_tcb *)
  3026. res_info[BNA_TX_RES_MEM_T_TCB].res_u.mem_info.mdl[i].kva;
  3027. txq->tx_packets = 0;
  3028. txq->tx_bytes = 0;
  3029. /* IB */
  3030. txq->ib.ib_seg_host_addr.lsb =
  3031. res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.lsb;
  3032. txq->ib.ib_seg_host_addr.msb =
  3033. res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.msb;
  3034. txq->ib.ib_seg_host_addr_kva =
  3035. res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].kva;
  3036. txq->ib.intr_type = intr_info->intr_type;
  3037. txq->ib.intr_vector = (intr_info->num == 1) ?
  3038. intr_info->idl[0].vector :
  3039. intr_info->idl[i].vector;
  3040. if (intr_info->intr_type == BNA_INTR_T_INTX)
  3041. txq->ib.intr_vector = (1 << txq->ib.intr_vector);
  3042. txq->ib.coalescing_timeo = tx_cfg->coalescing_timeo;
  3043. txq->ib.interpkt_timeo = BFI_TX_INTERPKT_TIMEO;
  3044. txq->ib.interpkt_count = BFI_TX_INTERPKT_COUNT;
  3045. /* TCB */
  3046. txq->tcb->q_depth = tx_cfg->txq_depth;
  3047. txq->tcb->unmap_q = (void *)
  3048. res_info[BNA_TX_RES_MEM_T_UNMAPQ].res_u.mem_info.mdl[i].kva;
  3049. txq->tcb->hw_consumer_index =
  3050. (u32 *)txq->ib.ib_seg_host_addr_kva;
  3051. txq->tcb->i_dbell = &txq->ib.door_bell;
  3052. txq->tcb->intr_type = txq->ib.intr_type;
  3053. txq->tcb->intr_vector = txq->ib.intr_vector;
  3054. txq->tcb->txq = txq;
  3055. txq->tcb->bnad = bnad;
  3056. txq->tcb->id = i;
  3057. /* QPT, SWQPT, Pages */
  3058. bna_txq_qpt_setup(txq, page_count, PAGE_SIZE,
  3059. &res_info[BNA_TX_RES_MEM_T_QPT].res_u.mem_info.mdl[i],
  3060. &res_info[BNA_TX_RES_MEM_T_SWQPT].res_u.mem_info.mdl[i],
  3061. &res_info[BNA_TX_RES_MEM_T_PAGE].
  3062. res_u.mem_info.mdl[i]);
  3063. /* Callback to bnad for setting up TCB */
  3064. if (tx->tcb_setup_cbfn)
  3065. (tx->tcb_setup_cbfn)(bna->bnad, txq->tcb);
  3066. if (tx_cfg->num_txq == BFI_TX_MAX_PRIO)
  3067. txq->priority = txq->tcb->id;
  3068. else
  3069. txq->priority = tx_mod->default_prio;
  3070. i++;
  3071. }
  3072. tx->txf_vlan_id = 0;
  3073. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  3074. tx_mod->rid_mask |= (1 << tx->rid);
  3075. return tx;
  3076. err_return:
  3077. bna_tx_free(tx);
  3078. return NULL;
  3079. }
  3080. void
  3081. bna_tx_destroy(struct bna_tx *tx)
  3082. {
  3083. struct bna_txq *txq;
  3084. struct list_head *qe;
  3085. list_for_each(qe, &tx->txq_q) {
  3086. txq = (struct bna_txq *)qe;
  3087. if (tx->tcb_destroy_cbfn)
  3088. (tx->tcb_destroy_cbfn)(tx->bna->bnad, txq->tcb);
  3089. }
  3090. tx->bna->tx_mod.rid_mask &= ~(1 << tx->rid);
  3091. bna_tx_free(tx);
  3092. }
  3093. void
  3094. bna_tx_enable(struct bna_tx *tx)
  3095. {
  3096. if (tx->fsm != (bfa_sm_t)bna_tx_sm_stopped)
  3097. return;
  3098. tx->flags |= BNA_TX_F_ENABLED;
  3099. if (tx->flags & BNA_TX_F_ENET_STARTED)
  3100. bfa_fsm_send_event(tx, TX_E_START);
  3101. }
  3102. void
  3103. bna_tx_disable(struct bna_tx *tx, enum bna_cleanup_type type,
  3104. void (*cbfn)(void *, struct bna_tx *))
  3105. {
  3106. if (type == BNA_SOFT_CLEANUP) {
  3107. (*cbfn)(tx->bna->bnad, tx);
  3108. return;
  3109. }
  3110. tx->stop_cbfn = cbfn;
  3111. tx->stop_cbarg = tx->bna->bnad;
  3112. tx->flags &= ~BNA_TX_F_ENABLED;
  3113. bfa_fsm_send_event(tx, TX_E_STOP);
  3114. }
  3115. void
  3116. bna_tx_cleanup_complete(struct bna_tx *tx)
  3117. {
  3118. bfa_fsm_send_event(tx, TX_E_CLEANUP_DONE);
  3119. }
  3120. static void
  3121. bna_tx_mod_cb_tx_stopped(void *arg, struct bna_tx *tx)
  3122. {
  3123. struct bna_tx_mod *tx_mod = (struct bna_tx_mod *)arg;
  3124. bfa_wc_down(&tx_mod->tx_stop_wc);
  3125. }
  3126. static void
  3127. bna_tx_mod_cb_tx_stopped_all(void *arg)
  3128. {
  3129. struct bna_tx_mod *tx_mod = (struct bna_tx_mod *)arg;
  3130. if (tx_mod->stop_cbfn)
  3131. tx_mod->stop_cbfn(&tx_mod->bna->enet);
  3132. tx_mod->stop_cbfn = NULL;
  3133. }
  3134. void
  3135. bna_tx_mod_init(struct bna_tx_mod *tx_mod, struct bna *bna,
  3136. struct bna_res_info *res_info)
  3137. {
  3138. int i;
  3139. tx_mod->bna = bna;
  3140. tx_mod->flags = 0;
  3141. tx_mod->tx = (struct bna_tx *)
  3142. res_info[BNA_MOD_RES_MEM_T_TX_ARRAY].res_u.mem_info.mdl[0].kva;
  3143. tx_mod->txq = (struct bna_txq *)
  3144. res_info[BNA_MOD_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.mdl[0].kva;
  3145. INIT_LIST_HEAD(&tx_mod->tx_free_q);
  3146. INIT_LIST_HEAD(&tx_mod->tx_active_q);
  3147. INIT_LIST_HEAD(&tx_mod->txq_free_q);
  3148. for (i = 0; i < bna->ioceth.attr.num_txq; i++) {
  3149. tx_mod->tx[i].rid = i;
  3150. bfa_q_qe_init(&tx_mod->tx[i].qe);
  3151. list_add_tail(&tx_mod->tx[i].qe, &tx_mod->tx_free_q);
  3152. bfa_q_qe_init(&tx_mod->txq[i].qe);
  3153. list_add_tail(&tx_mod->txq[i].qe, &tx_mod->txq_free_q);
  3154. }
  3155. tx_mod->prio_map = BFI_TX_PRIO_MAP_ALL;
  3156. tx_mod->default_prio = 0;
  3157. tx_mod->iscsi_over_cee = BNA_STATUS_T_DISABLED;
  3158. tx_mod->iscsi_prio = -1;
  3159. }
  3160. void
  3161. bna_tx_mod_uninit(struct bna_tx_mod *tx_mod)
  3162. {
  3163. struct list_head *qe;
  3164. int i;
  3165. i = 0;
  3166. list_for_each(qe, &tx_mod->tx_free_q)
  3167. i++;
  3168. i = 0;
  3169. list_for_each(qe, &tx_mod->txq_free_q)
  3170. i++;
  3171. tx_mod->bna = NULL;
  3172. }
  3173. void
  3174. bna_tx_mod_start(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
  3175. {
  3176. struct bna_tx *tx;
  3177. struct list_head *qe;
  3178. tx_mod->flags |= BNA_TX_MOD_F_ENET_STARTED;
  3179. if (type == BNA_TX_T_LOOPBACK)
  3180. tx_mod->flags |= BNA_TX_MOD_F_ENET_LOOPBACK;
  3181. list_for_each(qe, &tx_mod->tx_active_q) {
  3182. tx = (struct bna_tx *)qe;
  3183. if (tx->type == type)
  3184. bna_tx_start(tx);
  3185. }
  3186. }
  3187. void
  3188. bna_tx_mod_stop(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
  3189. {
  3190. struct bna_tx *tx;
  3191. struct list_head *qe;
  3192. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_STARTED;
  3193. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_LOOPBACK;
  3194. tx_mod->stop_cbfn = bna_enet_cb_tx_stopped;
  3195. bfa_wc_init(&tx_mod->tx_stop_wc, bna_tx_mod_cb_tx_stopped_all, tx_mod);
  3196. list_for_each(qe, &tx_mod->tx_active_q) {
  3197. tx = (struct bna_tx *)qe;
  3198. if (tx->type == type) {
  3199. bfa_wc_up(&tx_mod->tx_stop_wc);
  3200. bna_tx_stop(tx);
  3201. }
  3202. }
  3203. bfa_wc_wait(&tx_mod->tx_stop_wc);
  3204. }
  3205. void
  3206. bna_tx_mod_fail(struct bna_tx_mod *tx_mod)
  3207. {
  3208. struct bna_tx *tx;
  3209. struct list_head *qe;
  3210. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_STARTED;
  3211. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_LOOPBACK;
  3212. list_for_each(qe, &tx_mod->tx_active_q) {
  3213. tx = (struct bna_tx *)qe;
  3214. bna_tx_fail(tx);
  3215. }
  3216. }
  3217. void
  3218. bna_tx_coalescing_timeo_set(struct bna_tx *tx, int coalescing_timeo)
  3219. {
  3220. struct bna_txq *txq;
  3221. struct list_head *qe;
  3222. list_for_each(qe, &tx->txq_q) {
  3223. txq = (struct bna_txq *)qe;
  3224. bna_ib_coalescing_timeo_set(&txq->ib, coalescing_timeo);
  3225. }
  3226. }