bnx2x_sriov.c 99 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678
  1. /* bnx2x_sriov.c: Broadcom Everest network driver.
  2. *
  3. * Copyright 2009-2013 Broadcom Corporation
  4. *
  5. * Unless you and Broadcom execute a separate written software license
  6. * agreement governing use of this software, this software is licensed to you
  7. * under the terms of the GNU General Public License version 2, available
  8. * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
  9. *
  10. * Notwithstanding the above, under no circumstances may you combine this
  11. * software in any way with any other Broadcom software provided under a
  12. * license other than the GPL, without Broadcom's express prior written
  13. * consent.
  14. *
  15. * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  16. * Written by: Shmulik Ravid <shmulikr@broadcom.com>
  17. * Ariel Elior <ariele@broadcom.com>
  18. *
  19. */
  20. #include "bnx2x.h"
  21. #include "bnx2x_init.h"
  22. #include "bnx2x_cmn.h"
  23. #include "bnx2x_sp.h"
  24. #include <linux/crc32.h>
  25. #include <linux/if_vlan.h>
  26. /* General service functions */
  27. static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
  28. u16 pf_id)
  29. {
  30. REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
  31. pf_id);
  32. REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
  33. pf_id);
  34. REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
  35. pf_id);
  36. REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
  37. pf_id);
  38. }
  39. static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
  40. u8 enable)
  41. {
  42. REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
  43. enable);
  44. REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
  45. enable);
  46. REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
  47. enable);
  48. REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
  49. enable);
  50. }
  51. int bnx2x_vf_idx_by_abs_fid(struct bnx2x *bp, u16 abs_vfid)
  52. {
  53. int idx;
  54. for_each_vf(bp, idx)
  55. if (bnx2x_vf(bp, idx, abs_vfid) == abs_vfid)
  56. break;
  57. return idx;
  58. }
  59. static
  60. struct bnx2x_virtf *bnx2x_vf_by_abs_fid(struct bnx2x *bp, u16 abs_vfid)
  61. {
  62. u16 idx = (u16)bnx2x_vf_idx_by_abs_fid(bp, abs_vfid);
  63. return (idx < BNX2X_NR_VIRTFN(bp)) ? BP_VF(bp, idx) : NULL;
  64. }
  65. static void bnx2x_vf_igu_ack_sb(struct bnx2x *bp, struct bnx2x_virtf *vf,
  66. u8 igu_sb_id, u8 segment, u16 index, u8 op,
  67. u8 update)
  68. {
  69. /* acking a VF sb through the PF - use the GRC */
  70. u32 ctl;
  71. u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
  72. u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
  73. u32 func_encode = vf->abs_vfid;
  74. u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + igu_sb_id;
  75. struct igu_regular cmd_data = {0};
  76. cmd_data.sb_id_and_flags =
  77. ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
  78. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  79. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  80. (op << IGU_REGULAR_ENABLE_INT_SHIFT));
  81. ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
  82. func_encode << IGU_CTRL_REG_FID_SHIFT |
  83. IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
  84. DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
  85. cmd_data.sb_id_and_flags, igu_addr_data);
  86. REG_WR(bp, igu_addr_data, cmd_data.sb_id_and_flags);
  87. mmiowb();
  88. barrier();
  89. DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
  90. ctl, igu_addr_ctl);
  91. REG_WR(bp, igu_addr_ctl, ctl);
  92. mmiowb();
  93. barrier();
  94. }
  95. /* VFOP - VF slow-path operation support */
  96. #define BNX2X_VFOP_FILTER_ADD_CNT_MAX 0x10000
  97. /* VFOP operations states */
  98. enum bnx2x_vfop_qctor_state {
  99. BNX2X_VFOP_QCTOR_INIT,
  100. BNX2X_VFOP_QCTOR_SETUP,
  101. BNX2X_VFOP_QCTOR_INT_EN
  102. };
  103. enum bnx2x_vfop_qdtor_state {
  104. BNX2X_VFOP_QDTOR_HALT,
  105. BNX2X_VFOP_QDTOR_TERMINATE,
  106. BNX2X_VFOP_QDTOR_CFCDEL,
  107. BNX2X_VFOP_QDTOR_DONE
  108. };
  109. enum bnx2x_vfop_vlan_mac_state {
  110. BNX2X_VFOP_VLAN_MAC_CONFIG_SINGLE,
  111. BNX2X_VFOP_VLAN_MAC_CLEAR,
  112. BNX2X_VFOP_VLAN_MAC_CHK_DONE,
  113. BNX2X_VFOP_MAC_CONFIG_LIST,
  114. BNX2X_VFOP_VLAN_CONFIG_LIST,
  115. BNX2X_VFOP_VLAN_CONFIG_LIST_0
  116. };
  117. enum bnx2x_vfop_qsetup_state {
  118. BNX2X_VFOP_QSETUP_CTOR,
  119. BNX2X_VFOP_QSETUP_VLAN0,
  120. BNX2X_VFOP_QSETUP_DONE
  121. };
  122. enum bnx2x_vfop_mcast_state {
  123. BNX2X_VFOP_MCAST_DEL,
  124. BNX2X_VFOP_MCAST_ADD,
  125. BNX2X_VFOP_MCAST_CHK_DONE
  126. };
  127. enum bnx2x_vfop_qflr_state {
  128. BNX2X_VFOP_QFLR_CLR_VLAN,
  129. BNX2X_VFOP_QFLR_CLR_MAC,
  130. BNX2X_VFOP_QFLR_TERMINATE,
  131. BNX2X_VFOP_QFLR_DONE
  132. };
  133. enum bnx2x_vfop_flr_state {
  134. BNX2X_VFOP_FLR_QUEUES,
  135. BNX2X_VFOP_FLR_HW
  136. };
  137. enum bnx2x_vfop_close_state {
  138. BNX2X_VFOP_CLOSE_QUEUES,
  139. BNX2X_VFOP_CLOSE_HW
  140. };
  141. enum bnx2x_vfop_rxmode_state {
  142. BNX2X_VFOP_RXMODE_CONFIG,
  143. BNX2X_VFOP_RXMODE_DONE
  144. };
  145. enum bnx2x_vfop_qteardown_state {
  146. BNX2X_VFOP_QTEARDOWN_RXMODE,
  147. BNX2X_VFOP_QTEARDOWN_CLR_VLAN,
  148. BNX2X_VFOP_QTEARDOWN_CLR_MAC,
  149. BNX2X_VFOP_QTEARDOWN_QDTOR,
  150. BNX2X_VFOP_QTEARDOWN_DONE
  151. };
  152. enum bnx2x_vfop_rss_state {
  153. BNX2X_VFOP_RSS_CONFIG,
  154. BNX2X_VFOP_RSS_DONE
  155. };
  156. #define bnx2x_vfop_reset_wq(vf) atomic_set(&vf->op_in_progress, 0)
  157. void bnx2x_vfop_qctor_dump_tx(struct bnx2x *bp, struct bnx2x_virtf *vf,
  158. struct bnx2x_queue_init_params *init_params,
  159. struct bnx2x_queue_setup_params *setup_params,
  160. u16 q_idx, u16 sb_idx)
  161. {
  162. DP(BNX2X_MSG_IOV,
  163. "VF[%d] Q_SETUP: txq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, flags=0x%lx, traffic-type=%d",
  164. vf->abs_vfid,
  165. q_idx,
  166. sb_idx,
  167. init_params->tx.sb_cq_index,
  168. init_params->tx.hc_rate,
  169. setup_params->flags,
  170. setup_params->txq_params.traffic_type);
  171. }
  172. void bnx2x_vfop_qctor_dump_rx(struct bnx2x *bp, struct bnx2x_virtf *vf,
  173. struct bnx2x_queue_init_params *init_params,
  174. struct bnx2x_queue_setup_params *setup_params,
  175. u16 q_idx, u16 sb_idx)
  176. {
  177. struct bnx2x_rxq_setup_params *rxq_params = &setup_params->rxq_params;
  178. DP(BNX2X_MSG_IOV, "VF[%d] Q_SETUP: rxq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, mtu=%d, buf-size=%d\n"
  179. "sge-size=%d, max_sge_pkt=%d, tpa-agg-size=%d, flags=0x%lx, drop-flags=0x%x, cache-log=%d\n",
  180. vf->abs_vfid,
  181. q_idx,
  182. sb_idx,
  183. init_params->rx.sb_cq_index,
  184. init_params->rx.hc_rate,
  185. setup_params->gen_params.mtu,
  186. rxq_params->buf_sz,
  187. rxq_params->sge_buf_sz,
  188. rxq_params->max_sges_pkt,
  189. rxq_params->tpa_agg_sz,
  190. setup_params->flags,
  191. rxq_params->drop_flags,
  192. rxq_params->cache_line_log);
  193. }
  194. void bnx2x_vfop_qctor_prep(struct bnx2x *bp,
  195. struct bnx2x_virtf *vf,
  196. struct bnx2x_vf_queue *q,
  197. struct bnx2x_vfop_qctor_params *p,
  198. unsigned long q_type)
  199. {
  200. struct bnx2x_queue_init_params *init_p = &p->qstate.params.init;
  201. struct bnx2x_queue_setup_params *setup_p = &p->prep_qsetup;
  202. /* INIT */
  203. /* Enable host coalescing in the transition to INIT state */
  204. if (test_bit(BNX2X_Q_FLG_HC, &init_p->rx.flags))
  205. __set_bit(BNX2X_Q_FLG_HC_EN, &init_p->rx.flags);
  206. if (test_bit(BNX2X_Q_FLG_HC, &init_p->tx.flags))
  207. __set_bit(BNX2X_Q_FLG_HC_EN, &init_p->tx.flags);
  208. /* FW SB ID */
  209. init_p->rx.fw_sb_id = vf_igu_sb(vf, q->sb_idx);
  210. init_p->tx.fw_sb_id = vf_igu_sb(vf, q->sb_idx);
  211. /* context */
  212. init_p->cxts[0] = q->cxt;
  213. /* SETUP */
  214. /* Setup-op general parameters */
  215. setup_p->gen_params.spcl_id = vf->sp_cl_id;
  216. setup_p->gen_params.stat_id = vfq_stat_id(vf, q);
  217. /* Setup-op pause params:
  218. * Nothing to do, the pause thresholds are set by default to 0 which
  219. * effectively turns off the feature for this queue. We don't want
  220. * one queue (VF) to interfering with another queue (another VF)
  221. */
  222. if (vf->cfg_flags & VF_CFG_FW_FC)
  223. BNX2X_ERR("No support for pause to VFs (abs_vfid: %d)\n",
  224. vf->abs_vfid);
  225. /* Setup-op flags:
  226. * collect statistics, zero statistics, local-switching, security,
  227. * OV for Flex10, RSS and MCAST for leading
  228. */
  229. if (test_bit(BNX2X_Q_FLG_STATS, &setup_p->flags))
  230. __set_bit(BNX2X_Q_FLG_ZERO_STATS, &setup_p->flags);
  231. /* for VFs, enable tx switching, bd coherency, and mac address
  232. * anti-spoofing
  233. */
  234. __set_bit(BNX2X_Q_FLG_TX_SWITCH, &setup_p->flags);
  235. __set_bit(BNX2X_Q_FLG_TX_SEC, &setup_p->flags);
  236. __set_bit(BNX2X_Q_FLG_ANTI_SPOOF, &setup_p->flags);
  237. /* Setup-op rx parameters */
  238. if (test_bit(BNX2X_Q_TYPE_HAS_RX, &q_type)) {
  239. struct bnx2x_rxq_setup_params *rxq_p = &setup_p->rxq_params;
  240. rxq_p->cl_qzone_id = vfq_qzone_id(vf, q);
  241. rxq_p->fw_sb_id = vf_igu_sb(vf, q->sb_idx);
  242. rxq_p->rss_engine_id = FW_VF_HANDLE(vf->abs_vfid);
  243. if (test_bit(BNX2X_Q_FLG_TPA, &setup_p->flags))
  244. rxq_p->max_tpa_queues = BNX2X_VF_MAX_TPA_AGG_QUEUES;
  245. }
  246. /* Setup-op tx parameters */
  247. if (test_bit(BNX2X_Q_TYPE_HAS_TX, &q_type)) {
  248. setup_p->txq_params.tss_leading_cl_id = vf->leading_rss;
  249. setup_p->txq_params.fw_sb_id = vf_igu_sb(vf, q->sb_idx);
  250. }
  251. }
  252. /* VFOP queue construction */
  253. static void bnx2x_vfop_qctor(struct bnx2x *bp, struct bnx2x_virtf *vf)
  254. {
  255. struct bnx2x_vfop *vfop = bnx2x_vfop_cur(bp, vf);
  256. struct bnx2x_vfop_args_qctor *args = &vfop->args.qctor;
  257. struct bnx2x_queue_state_params *q_params = &vfop->op_p->qctor.qstate;
  258. enum bnx2x_vfop_qctor_state state = vfop->state;
  259. bnx2x_vfop_reset_wq(vf);
  260. if (vfop->rc < 0)
  261. goto op_err;
  262. DP(BNX2X_MSG_IOV, "vf[%d] STATE: %d\n", vf->abs_vfid, state);
  263. switch (state) {
  264. case BNX2X_VFOP_QCTOR_INIT:
  265. /* has this queue already been opened? */
  266. if (bnx2x_get_q_logical_state(bp, q_params->q_obj) ==
  267. BNX2X_Q_LOGICAL_STATE_ACTIVE) {
  268. DP(BNX2X_MSG_IOV,
  269. "Entered qctor but queue was already up. Aborting gracefully\n");
  270. goto op_done;
  271. }
  272. /* next state */
  273. vfop->state = BNX2X_VFOP_QCTOR_SETUP;
  274. q_params->cmd = BNX2X_Q_CMD_INIT;
  275. vfop->rc = bnx2x_queue_state_change(bp, q_params);
  276. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_CONT);
  277. case BNX2X_VFOP_QCTOR_SETUP:
  278. /* next state */
  279. vfop->state = BNX2X_VFOP_QCTOR_INT_EN;
  280. /* copy pre-prepared setup params to the queue-state params */
  281. vfop->op_p->qctor.qstate.params.setup =
  282. vfop->op_p->qctor.prep_qsetup;
  283. q_params->cmd = BNX2X_Q_CMD_SETUP;
  284. vfop->rc = bnx2x_queue_state_change(bp, q_params);
  285. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_CONT);
  286. case BNX2X_VFOP_QCTOR_INT_EN:
  287. /* enable interrupts */
  288. bnx2x_vf_igu_ack_sb(bp, vf, vf_igu_sb(vf, args->sb_idx),
  289. USTORM_ID, 0, IGU_INT_ENABLE, 0);
  290. goto op_done;
  291. default:
  292. bnx2x_vfop_default(state);
  293. }
  294. op_err:
  295. BNX2X_ERR("QCTOR[%d:%d] error: cmd %d, rc %d\n",
  296. vf->abs_vfid, args->qid, q_params->cmd, vfop->rc);
  297. op_done:
  298. bnx2x_vfop_end(bp, vf, vfop);
  299. op_pending:
  300. return;
  301. }
  302. static int bnx2x_vfop_qctor_cmd(struct bnx2x *bp,
  303. struct bnx2x_virtf *vf,
  304. struct bnx2x_vfop_cmd *cmd,
  305. int qid)
  306. {
  307. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  308. if (vfop) {
  309. vf->op_params.qctor.qstate.q_obj = &bnx2x_vfq(vf, qid, sp_obj);
  310. vfop->args.qctor.qid = qid;
  311. vfop->args.qctor.sb_idx = bnx2x_vfq(vf, qid, sb_idx);
  312. bnx2x_vfop_opset(BNX2X_VFOP_QCTOR_INIT,
  313. bnx2x_vfop_qctor, cmd->done);
  314. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_qctor,
  315. cmd->block);
  316. }
  317. return -ENOMEM;
  318. }
  319. /* VFOP queue destruction */
  320. static void bnx2x_vfop_qdtor(struct bnx2x *bp, struct bnx2x_virtf *vf)
  321. {
  322. struct bnx2x_vfop *vfop = bnx2x_vfop_cur(bp, vf);
  323. struct bnx2x_vfop_args_qdtor *qdtor = &vfop->args.qdtor;
  324. struct bnx2x_queue_state_params *q_params = &vfop->op_p->qctor.qstate;
  325. enum bnx2x_vfop_qdtor_state state = vfop->state;
  326. bnx2x_vfop_reset_wq(vf);
  327. if (vfop->rc < 0)
  328. goto op_err;
  329. DP(BNX2X_MSG_IOV, "vf[%d] STATE: %d\n", vf->abs_vfid, state);
  330. switch (state) {
  331. case BNX2X_VFOP_QDTOR_HALT:
  332. /* has this queue already been stopped? */
  333. if (bnx2x_get_q_logical_state(bp, q_params->q_obj) ==
  334. BNX2X_Q_LOGICAL_STATE_STOPPED) {
  335. DP(BNX2X_MSG_IOV,
  336. "Entered qdtor but queue was already stopped. Aborting gracefully\n");
  337. /* next state */
  338. vfop->state = BNX2X_VFOP_QDTOR_DONE;
  339. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_CONT);
  340. }
  341. /* next state */
  342. vfop->state = BNX2X_VFOP_QDTOR_TERMINATE;
  343. q_params->cmd = BNX2X_Q_CMD_HALT;
  344. vfop->rc = bnx2x_queue_state_change(bp, q_params);
  345. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_CONT);
  346. case BNX2X_VFOP_QDTOR_TERMINATE:
  347. /* next state */
  348. vfop->state = BNX2X_VFOP_QDTOR_CFCDEL;
  349. q_params->cmd = BNX2X_Q_CMD_TERMINATE;
  350. vfop->rc = bnx2x_queue_state_change(bp, q_params);
  351. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_CONT);
  352. case BNX2X_VFOP_QDTOR_CFCDEL:
  353. /* next state */
  354. vfop->state = BNX2X_VFOP_QDTOR_DONE;
  355. q_params->cmd = BNX2X_Q_CMD_CFC_DEL;
  356. vfop->rc = bnx2x_queue_state_change(bp, q_params);
  357. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_DONE);
  358. op_err:
  359. BNX2X_ERR("QDTOR[%d:%d] error: cmd %d, rc %d\n",
  360. vf->abs_vfid, qdtor->qid, q_params->cmd, vfop->rc);
  361. op_done:
  362. case BNX2X_VFOP_QDTOR_DONE:
  363. /* invalidate the context */
  364. if (qdtor->cxt) {
  365. qdtor->cxt->ustorm_ag_context.cdu_usage = 0;
  366. qdtor->cxt->xstorm_ag_context.cdu_reserved = 0;
  367. }
  368. bnx2x_vfop_end(bp, vf, vfop);
  369. return;
  370. default:
  371. bnx2x_vfop_default(state);
  372. }
  373. op_pending:
  374. return;
  375. }
  376. static int bnx2x_vfop_qdtor_cmd(struct bnx2x *bp,
  377. struct bnx2x_virtf *vf,
  378. struct bnx2x_vfop_cmd *cmd,
  379. int qid)
  380. {
  381. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  382. if (vfop) {
  383. struct bnx2x_queue_state_params *qstate =
  384. &vf->op_params.qctor.qstate;
  385. memset(qstate, 0, sizeof(*qstate));
  386. qstate->q_obj = &bnx2x_vfq(vf, qid, sp_obj);
  387. vfop->args.qdtor.qid = qid;
  388. vfop->args.qdtor.cxt = bnx2x_vfq(vf, qid, cxt);
  389. bnx2x_vfop_opset(BNX2X_VFOP_QDTOR_HALT,
  390. bnx2x_vfop_qdtor, cmd->done);
  391. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_qdtor,
  392. cmd->block);
  393. }
  394. DP(BNX2X_MSG_IOV, "VF[%d] failed to add a vfop. rc %d\n",
  395. vf->abs_vfid, vfop->rc);
  396. return -ENOMEM;
  397. }
  398. static void
  399. bnx2x_vf_set_igu_info(struct bnx2x *bp, u8 igu_sb_id, u8 abs_vfid)
  400. {
  401. struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid);
  402. if (vf) {
  403. /* the first igu entry belonging to VFs of this PF */
  404. if (!BP_VFDB(bp)->first_vf_igu_entry)
  405. BP_VFDB(bp)->first_vf_igu_entry = igu_sb_id;
  406. /* the first igu entry belonging to this VF */
  407. if (!vf_sb_count(vf))
  408. vf->igu_base_id = igu_sb_id;
  409. ++vf_sb_count(vf);
  410. ++vf->sb_count;
  411. }
  412. BP_VFDB(bp)->vf_sbs_pool++;
  413. }
  414. /* VFOP MAC/VLAN helpers */
  415. static inline void bnx2x_vfop_credit(struct bnx2x *bp,
  416. struct bnx2x_vfop *vfop,
  417. struct bnx2x_vlan_mac_obj *obj)
  418. {
  419. struct bnx2x_vfop_args_filters *args = &vfop->args.filters;
  420. /* update credit only if there is no error
  421. * and a valid credit counter
  422. */
  423. if (!vfop->rc && args->credit) {
  424. struct list_head *pos;
  425. int read_lock;
  426. int cnt = 0;
  427. read_lock = bnx2x_vlan_mac_h_read_lock(bp, obj);
  428. if (read_lock)
  429. DP(BNX2X_MSG_SP, "Failed to take vlan mac read head; continuing anyway\n");
  430. list_for_each(pos, &obj->head)
  431. cnt++;
  432. if (!read_lock)
  433. bnx2x_vlan_mac_h_read_unlock(bp, obj);
  434. atomic_set(args->credit, cnt);
  435. }
  436. }
  437. static int bnx2x_vfop_set_user_req(struct bnx2x *bp,
  438. struct bnx2x_vfop_filter *pos,
  439. struct bnx2x_vlan_mac_data *user_req)
  440. {
  441. user_req->cmd = pos->add ? BNX2X_VLAN_MAC_ADD :
  442. BNX2X_VLAN_MAC_DEL;
  443. switch (pos->type) {
  444. case BNX2X_VFOP_FILTER_MAC:
  445. memcpy(user_req->u.mac.mac, pos->mac, ETH_ALEN);
  446. break;
  447. case BNX2X_VFOP_FILTER_VLAN:
  448. user_req->u.vlan.vlan = pos->vid;
  449. break;
  450. default:
  451. BNX2X_ERR("Invalid filter type, skipping\n");
  452. return 1;
  453. }
  454. return 0;
  455. }
  456. static int bnx2x_vfop_config_list(struct bnx2x *bp,
  457. struct bnx2x_vfop_filters *filters,
  458. struct bnx2x_vlan_mac_ramrod_params *vlan_mac)
  459. {
  460. struct bnx2x_vfop_filter *pos, *tmp;
  461. struct list_head rollback_list, *filters_list = &filters->head;
  462. struct bnx2x_vlan_mac_data *user_req = &vlan_mac->user_req;
  463. int rc = 0, cnt = 0;
  464. INIT_LIST_HEAD(&rollback_list);
  465. list_for_each_entry_safe(pos, tmp, filters_list, link) {
  466. if (bnx2x_vfop_set_user_req(bp, pos, user_req))
  467. continue;
  468. rc = bnx2x_config_vlan_mac(bp, vlan_mac);
  469. if (rc >= 0) {
  470. cnt += pos->add ? 1 : -1;
  471. list_move(&pos->link, &rollback_list);
  472. rc = 0;
  473. } else if (rc == -EEXIST) {
  474. rc = 0;
  475. } else {
  476. BNX2X_ERR("Failed to add a new vlan_mac command\n");
  477. break;
  478. }
  479. }
  480. /* rollback if error or too many rules added */
  481. if (rc || cnt > filters->add_cnt) {
  482. BNX2X_ERR("error or too many rules added. Performing rollback\n");
  483. list_for_each_entry_safe(pos, tmp, &rollback_list, link) {
  484. pos->add = !pos->add; /* reverse op */
  485. bnx2x_vfop_set_user_req(bp, pos, user_req);
  486. bnx2x_config_vlan_mac(bp, vlan_mac);
  487. list_del(&pos->link);
  488. }
  489. cnt = 0;
  490. if (!rc)
  491. rc = -EINVAL;
  492. }
  493. filters->add_cnt = cnt;
  494. return rc;
  495. }
  496. /* VFOP set VLAN/MAC */
  497. static void bnx2x_vfop_vlan_mac(struct bnx2x *bp, struct bnx2x_virtf *vf)
  498. {
  499. struct bnx2x_vfop *vfop = bnx2x_vfop_cur(bp, vf);
  500. struct bnx2x_vlan_mac_ramrod_params *vlan_mac = &vfop->op_p->vlan_mac;
  501. struct bnx2x_vlan_mac_obj *obj = vlan_mac->vlan_mac_obj;
  502. struct bnx2x_vfop_filters *filters = vfop->args.filters.multi_filter;
  503. enum bnx2x_vfop_vlan_mac_state state = vfop->state;
  504. if (vfop->rc < 0)
  505. goto op_err;
  506. DP(BNX2X_MSG_IOV, "vf[%d] STATE: %d\n", vf->abs_vfid, state);
  507. bnx2x_vfop_reset_wq(vf);
  508. switch (state) {
  509. case BNX2X_VFOP_VLAN_MAC_CLEAR:
  510. /* next state */
  511. vfop->state = BNX2X_VFOP_VLAN_MAC_CHK_DONE;
  512. /* do delete */
  513. vfop->rc = obj->delete_all(bp, obj,
  514. &vlan_mac->user_req.vlan_mac_flags,
  515. &vlan_mac->ramrod_flags);
  516. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_DONE);
  517. case BNX2X_VFOP_VLAN_MAC_CONFIG_SINGLE:
  518. /* next state */
  519. vfop->state = BNX2X_VFOP_VLAN_MAC_CHK_DONE;
  520. /* do config */
  521. vfop->rc = bnx2x_config_vlan_mac(bp, vlan_mac);
  522. if (vfop->rc == -EEXIST)
  523. vfop->rc = 0;
  524. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_DONE);
  525. case BNX2X_VFOP_VLAN_MAC_CHK_DONE:
  526. vfop->rc = !!obj->raw.check_pending(&obj->raw);
  527. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_DONE);
  528. case BNX2X_VFOP_MAC_CONFIG_LIST:
  529. /* next state */
  530. vfop->state = BNX2X_VFOP_VLAN_MAC_CHK_DONE;
  531. /* do list config */
  532. vfop->rc = bnx2x_vfop_config_list(bp, filters, vlan_mac);
  533. if (vfop->rc)
  534. goto op_err;
  535. set_bit(RAMROD_CONT, &vlan_mac->ramrod_flags);
  536. vfop->rc = bnx2x_config_vlan_mac(bp, vlan_mac);
  537. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_DONE);
  538. case BNX2X_VFOP_VLAN_CONFIG_LIST:
  539. /* next state */
  540. vfop->state = BNX2X_VFOP_VLAN_MAC_CHK_DONE;
  541. /* do list config */
  542. vfop->rc = bnx2x_vfop_config_list(bp, filters, vlan_mac);
  543. if (!vfop->rc) {
  544. set_bit(RAMROD_CONT, &vlan_mac->ramrod_flags);
  545. vfop->rc = bnx2x_config_vlan_mac(bp, vlan_mac);
  546. }
  547. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_DONE);
  548. default:
  549. bnx2x_vfop_default(state);
  550. }
  551. op_err:
  552. BNX2X_ERR("VLAN-MAC error: rc %d\n", vfop->rc);
  553. op_done:
  554. kfree(filters);
  555. bnx2x_vfop_credit(bp, vfop, obj);
  556. bnx2x_vfop_end(bp, vf, vfop);
  557. op_pending:
  558. return;
  559. }
  560. struct bnx2x_vfop_vlan_mac_flags {
  561. bool drv_only;
  562. bool dont_consume;
  563. bool single_cmd;
  564. bool add;
  565. };
  566. static void
  567. bnx2x_vfop_vlan_mac_prep_ramrod(struct bnx2x_vlan_mac_ramrod_params *ramrod,
  568. struct bnx2x_vfop_vlan_mac_flags *flags)
  569. {
  570. struct bnx2x_vlan_mac_data *ureq = &ramrod->user_req;
  571. memset(ramrod, 0, sizeof(*ramrod));
  572. /* ramrod flags */
  573. if (flags->drv_only)
  574. set_bit(RAMROD_DRV_CLR_ONLY, &ramrod->ramrod_flags);
  575. if (flags->single_cmd)
  576. set_bit(RAMROD_EXEC, &ramrod->ramrod_flags);
  577. /* mac_vlan flags */
  578. if (flags->dont_consume)
  579. set_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, &ureq->vlan_mac_flags);
  580. /* cmd */
  581. ureq->cmd = flags->add ? BNX2X_VLAN_MAC_ADD : BNX2X_VLAN_MAC_DEL;
  582. }
  583. static inline void
  584. bnx2x_vfop_mac_prep_ramrod(struct bnx2x_vlan_mac_ramrod_params *ramrod,
  585. struct bnx2x_vfop_vlan_mac_flags *flags)
  586. {
  587. bnx2x_vfop_vlan_mac_prep_ramrod(ramrod, flags);
  588. set_bit(BNX2X_ETH_MAC, &ramrod->user_req.vlan_mac_flags);
  589. }
  590. static int bnx2x_vfop_mac_delall_cmd(struct bnx2x *bp,
  591. struct bnx2x_virtf *vf,
  592. struct bnx2x_vfop_cmd *cmd,
  593. int qid, bool drv_only)
  594. {
  595. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  596. int rc;
  597. if (vfop) {
  598. struct bnx2x_vfop_args_filters filters = {
  599. .multi_filter = NULL, /* single */
  600. .credit = NULL, /* consume credit */
  601. };
  602. struct bnx2x_vfop_vlan_mac_flags flags = {
  603. .drv_only = drv_only,
  604. .dont_consume = (filters.credit != NULL),
  605. .single_cmd = true,
  606. .add = false /* don't care */,
  607. };
  608. struct bnx2x_vlan_mac_ramrod_params *ramrod =
  609. &vf->op_params.vlan_mac;
  610. /* set ramrod params */
  611. bnx2x_vfop_mac_prep_ramrod(ramrod, &flags);
  612. /* set object */
  613. rc = validate_vlan_mac(bp, &bnx2x_vfq(vf, qid, mac_obj));
  614. if (rc)
  615. return rc;
  616. ramrod->vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj);
  617. /* set extra args */
  618. vfop->args.filters = filters;
  619. bnx2x_vfop_opset(BNX2X_VFOP_VLAN_MAC_CLEAR,
  620. bnx2x_vfop_vlan_mac, cmd->done);
  621. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_vlan_mac,
  622. cmd->block);
  623. }
  624. return -ENOMEM;
  625. }
  626. int bnx2x_vfop_mac_list_cmd(struct bnx2x *bp,
  627. struct bnx2x_virtf *vf,
  628. struct bnx2x_vfop_cmd *cmd,
  629. struct bnx2x_vfop_filters *macs,
  630. int qid, bool drv_only)
  631. {
  632. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  633. int rc;
  634. if (vfop) {
  635. struct bnx2x_vfop_args_filters filters = {
  636. .multi_filter = macs,
  637. .credit = NULL, /* consume credit */
  638. };
  639. struct bnx2x_vfop_vlan_mac_flags flags = {
  640. .drv_only = drv_only,
  641. .dont_consume = (filters.credit != NULL),
  642. .single_cmd = false,
  643. .add = false, /* don't care since only the items in the
  644. * filters list affect the sp operation,
  645. * not the list itself
  646. */
  647. };
  648. struct bnx2x_vlan_mac_ramrod_params *ramrod =
  649. &vf->op_params.vlan_mac;
  650. /* set ramrod params */
  651. bnx2x_vfop_mac_prep_ramrod(ramrod, &flags);
  652. /* set object */
  653. rc = validate_vlan_mac(bp, &bnx2x_vfq(vf, qid, mac_obj));
  654. if (rc)
  655. return rc;
  656. ramrod->vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj);
  657. /* set extra args */
  658. filters.multi_filter->add_cnt = BNX2X_VFOP_FILTER_ADD_CNT_MAX;
  659. vfop->args.filters = filters;
  660. bnx2x_vfop_opset(BNX2X_VFOP_MAC_CONFIG_LIST,
  661. bnx2x_vfop_vlan_mac, cmd->done);
  662. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_vlan_mac,
  663. cmd->block);
  664. }
  665. return -ENOMEM;
  666. }
  667. int bnx2x_vfop_vlan_set_cmd(struct bnx2x *bp,
  668. struct bnx2x_virtf *vf,
  669. struct bnx2x_vfop_cmd *cmd,
  670. int qid, u16 vid, bool add)
  671. {
  672. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  673. int rc;
  674. if (vfop) {
  675. struct bnx2x_vfop_args_filters filters = {
  676. .multi_filter = NULL, /* single command */
  677. .credit = &bnx2x_vfq(vf, qid, vlan_count),
  678. };
  679. struct bnx2x_vfop_vlan_mac_flags flags = {
  680. .drv_only = false,
  681. .dont_consume = (filters.credit != NULL),
  682. .single_cmd = true,
  683. .add = add,
  684. };
  685. struct bnx2x_vlan_mac_ramrod_params *ramrod =
  686. &vf->op_params.vlan_mac;
  687. /* set ramrod params */
  688. bnx2x_vfop_vlan_mac_prep_ramrod(ramrod, &flags);
  689. ramrod->user_req.u.vlan.vlan = vid;
  690. /* set object */
  691. rc = validate_vlan_mac(bp, &bnx2x_vfq(vf, qid, vlan_obj));
  692. if (rc)
  693. return rc;
  694. ramrod->vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj);
  695. /* set extra args */
  696. vfop->args.filters = filters;
  697. bnx2x_vfop_opset(BNX2X_VFOP_VLAN_MAC_CONFIG_SINGLE,
  698. bnx2x_vfop_vlan_mac, cmd->done);
  699. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_vlan_mac,
  700. cmd->block);
  701. }
  702. return -ENOMEM;
  703. }
  704. static int bnx2x_vfop_vlan_delall_cmd(struct bnx2x *bp,
  705. struct bnx2x_virtf *vf,
  706. struct bnx2x_vfop_cmd *cmd,
  707. int qid, bool drv_only)
  708. {
  709. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  710. int rc;
  711. if (vfop) {
  712. struct bnx2x_vfop_args_filters filters = {
  713. .multi_filter = NULL, /* single command */
  714. .credit = &bnx2x_vfq(vf, qid, vlan_count),
  715. };
  716. struct bnx2x_vfop_vlan_mac_flags flags = {
  717. .drv_only = drv_only,
  718. .dont_consume = (filters.credit != NULL),
  719. .single_cmd = true,
  720. .add = false, /* don't care */
  721. };
  722. struct bnx2x_vlan_mac_ramrod_params *ramrod =
  723. &vf->op_params.vlan_mac;
  724. /* set ramrod params */
  725. bnx2x_vfop_vlan_mac_prep_ramrod(ramrod, &flags);
  726. /* set object */
  727. rc = validate_vlan_mac(bp, &bnx2x_vfq(vf, qid, vlan_obj));
  728. if (rc)
  729. return rc;
  730. ramrod->vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj);
  731. /* set extra args */
  732. vfop->args.filters = filters;
  733. bnx2x_vfop_opset(BNX2X_VFOP_VLAN_MAC_CLEAR,
  734. bnx2x_vfop_vlan_mac, cmd->done);
  735. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_vlan_mac,
  736. cmd->block);
  737. }
  738. return -ENOMEM;
  739. }
  740. int bnx2x_vfop_vlan_list_cmd(struct bnx2x *bp,
  741. struct bnx2x_virtf *vf,
  742. struct bnx2x_vfop_cmd *cmd,
  743. struct bnx2x_vfop_filters *vlans,
  744. int qid, bool drv_only)
  745. {
  746. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  747. int rc;
  748. if (vfop) {
  749. struct bnx2x_vfop_args_filters filters = {
  750. .multi_filter = vlans,
  751. .credit = &bnx2x_vfq(vf, qid, vlan_count),
  752. };
  753. struct bnx2x_vfop_vlan_mac_flags flags = {
  754. .drv_only = drv_only,
  755. .dont_consume = (filters.credit != NULL),
  756. .single_cmd = false,
  757. .add = false, /* don't care */
  758. };
  759. struct bnx2x_vlan_mac_ramrod_params *ramrod =
  760. &vf->op_params.vlan_mac;
  761. /* set ramrod params */
  762. bnx2x_vfop_vlan_mac_prep_ramrod(ramrod, &flags);
  763. /* set object */
  764. rc = validate_vlan_mac(bp, &bnx2x_vfq(vf, qid, vlan_obj));
  765. if (rc)
  766. return rc;
  767. ramrod->vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj);
  768. /* set extra args */
  769. filters.multi_filter->add_cnt = vf_vlan_rules_cnt(vf) -
  770. atomic_read(filters.credit);
  771. vfop->args.filters = filters;
  772. bnx2x_vfop_opset(BNX2X_VFOP_VLAN_CONFIG_LIST,
  773. bnx2x_vfop_vlan_mac, cmd->done);
  774. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_vlan_mac,
  775. cmd->block);
  776. }
  777. return -ENOMEM;
  778. }
  779. /* VFOP queue setup (queue constructor + set vlan 0) */
  780. static void bnx2x_vfop_qsetup(struct bnx2x *bp, struct bnx2x_virtf *vf)
  781. {
  782. struct bnx2x_vfop *vfop = bnx2x_vfop_cur(bp, vf);
  783. int qid = vfop->args.qctor.qid;
  784. enum bnx2x_vfop_qsetup_state state = vfop->state;
  785. struct bnx2x_vfop_cmd cmd = {
  786. .done = bnx2x_vfop_qsetup,
  787. .block = false,
  788. };
  789. if (vfop->rc < 0)
  790. goto op_err;
  791. DP(BNX2X_MSG_IOV, "vf[%d] STATE: %d\n", vf->abs_vfid, state);
  792. switch (state) {
  793. case BNX2X_VFOP_QSETUP_CTOR:
  794. /* init the queue ctor command */
  795. vfop->state = BNX2X_VFOP_QSETUP_VLAN0;
  796. vfop->rc = bnx2x_vfop_qctor_cmd(bp, vf, &cmd, qid);
  797. if (vfop->rc)
  798. goto op_err;
  799. return;
  800. case BNX2X_VFOP_QSETUP_VLAN0:
  801. /* skip if non-leading or FPGA/EMU*/
  802. if (qid)
  803. goto op_done;
  804. /* init the queue set-vlan command (for vlan 0) */
  805. vfop->state = BNX2X_VFOP_QSETUP_DONE;
  806. vfop->rc = bnx2x_vfop_vlan_set_cmd(bp, vf, &cmd, qid, 0, true);
  807. if (vfop->rc)
  808. goto op_err;
  809. return;
  810. op_err:
  811. BNX2X_ERR("QSETUP[%d:%d] error: rc %d\n", vf->abs_vfid, qid, vfop->rc);
  812. op_done:
  813. case BNX2X_VFOP_QSETUP_DONE:
  814. vf->cfg_flags |= VF_CFG_VLAN;
  815. smp_mb__before_clear_bit();
  816. set_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
  817. &bp->sp_rtnl_state);
  818. smp_mb__after_clear_bit();
  819. schedule_delayed_work(&bp->sp_rtnl_task, 0);
  820. bnx2x_vfop_end(bp, vf, vfop);
  821. return;
  822. default:
  823. bnx2x_vfop_default(state);
  824. }
  825. }
  826. int bnx2x_vfop_qsetup_cmd(struct bnx2x *bp,
  827. struct bnx2x_virtf *vf,
  828. struct bnx2x_vfop_cmd *cmd,
  829. int qid)
  830. {
  831. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  832. if (vfop) {
  833. vfop->args.qctor.qid = qid;
  834. bnx2x_vfop_opset(BNX2X_VFOP_QSETUP_CTOR,
  835. bnx2x_vfop_qsetup, cmd->done);
  836. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_qsetup,
  837. cmd->block);
  838. }
  839. return -ENOMEM;
  840. }
  841. /* VFOP queue FLR handling (clear vlans, clear macs, queue destructor) */
  842. static void bnx2x_vfop_qflr(struct bnx2x *bp, struct bnx2x_virtf *vf)
  843. {
  844. struct bnx2x_vfop *vfop = bnx2x_vfop_cur(bp, vf);
  845. int qid = vfop->args.qx.qid;
  846. enum bnx2x_vfop_qflr_state state = vfop->state;
  847. struct bnx2x_queue_state_params *qstate;
  848. struct bnx2x_vfop_cmd cmd;
  849. bnx2x_vfop_reset_wq(vf);
  850. if (vfop->rc < 0)
  851. goto op_err;
  852. DP(BNX2X_MSG_IOV, "VF[%d] STATE: %d\n", vf->abs_vfid, state);
  853. cmd.done = bnx2x_vfop_qflr;
  854. cmd.block = false;
  855. switch (state) {
  856. case BNX2X_VFOP_QFLR_CLR_VLAN:
  857. /* vlan-clear-all: driver-only, don't consume credit */
  858. vfop->state = BNX2X_VFOP_QFLR_CLR_MAC;
  859. if (!validate_vlan_mac(bp, &bnx2x_vfq(vf, qid, vlan_obj)))
  860. vfop->rc = bnx2x_vfop_vlan_delall_cmd(bp, vf, &cmd, qid,
  861. true);
  862. if (vfop->rc)
  863. goto op_err;
  864. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_CONT);
  865. case BNX2X_VFOP_QFLR_CLR_MAC:
  866. /* mac-clear-all: driver only consume credit */
  867. vfop->state = BNX2X_VFOP_QFLR_TERMINATE;
  868. if (!validate_vlan_mac(bp, &bnx2x_vfq(vf, qid, mac_obj)))
  869. vfop->rc = bnx2x_vfop_mac_delall_cmd(bp, vf, &cmd, qid,
  870. true);
  871. DP(BNX2X_MSG_IOV,
  872. "VF[%d] vfop->rc after bnx2x_vfop_mac_delall_cmd was %d",
  873. vf->abs_vfid, vfop->rc);
  874. if (vfop->rc)
  875. goto op_err;
  876. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_CONT);
  877. case BNX2X_VFOP_QFLR_TERMINATE:
  878. qstate = &vfop->op_p->qctor.qstate;
  879. memset(qstate , 0, sizeof(*qstate));
  880. qstate->q_obj = &bnx2x_vfq(vf, qid, sp_obj);
  881. vfop->state = BNX2X_VFOP_QFLR_DONE;
  882. DP(BNX2X_MSG_IOV, "VF[%d] qstate during flr was %d\n",
  883. vf->abs_vfid, qstate->q_obj->state);
  884. if (qstate->q_obj->state != BNX2X_Q_STATE_RESET) {
  885. qstate->q_obj->state = BNX2X_Q_STATE_STOPPED;
  886. qstate->cmd = BNX2X_Q_CMD_TERMINATE;
  887. vfop->rc = bnx2x_queue_state_change(bp, qstate);
  888. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_VERIFY_PEND);
  889. } else {
  890. goto op_done;
  891. }
  892. op_err:
  893. BNX2X_ERR("QFLR[%d:%d] error: rc %d\n",
  894. vf->abs_vfid, qid, vfop->rc);
  895. op_done:
  896. case BNX2X_VFOP_QFLR_DONE:
  897. bnx2x_vfop_end(bp, vf, vfop);
  898. return;
  899. default:
  900. bnx2x_vfop_default(state);
  901. }
  902. op_pending:
  903. return;
  904. }
  905. static int bnx2x_vfop_qflr_cmd(struct bnx2x *bp,
  906. struct bnx2x_virtf *vf,
  907. struct bnx2x_vfop_cmd *cmd,
  908. int qid)
  909. {
  910. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  911. if (vfop) {
  912. vfop->args.qx.qid = qid;
  913. bnx2x_vfop_opset(BNX2X_VFOP_QFLR_CLR_VLAN,
  914. bnx2x_vfop_qflr, cmd->done);
  915. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_qflr,
  916. cmd->block);
  917. }
  918. return -ENOMEM;
  919. }
  920. /* VFOP multi-casts */
  921. static void bnx2x_vfop_mcast(struct bnx2x *bp, struct bnx2x_virtf *vf)
  922. {
  923. struct bnx2x_vfop *vfop = bnx2x_vfop_cur(bp, vf);
  924. struct bnx2x_mcast_ramrod_params *mcast = &vfop->op_p->mcast;
  925. struct bnx2x_raw_obj *raw = &mcast->mcast_obj->raw;
  926. struct bnx2x_vfop_args_mcast *args = &vfop->args.mc_list;
  927. enum bnx2x_vfop_mcast_state state = vfop->state;
  928. int i;
  929. bnx2x_vfop_reset_wq(vf);
  930. if (vfop->rc < 0)
  931. goto op_err;
  932. DP(BNX2X_MSG_IOV, "vf[%d] STATE: %d\n", vf->abs_vfid, state);
  933. switch (state) {
  934. case BNX2X_VFOP_MCAST_DEL:
  935. /* clear existing mcasts */
  936. vfop->state = BNX2X_VFOP_MCAST_ADD;
  937. vfop->rc = bnx2x_config_mcast(bp, mcast, BNX2X_MCAST_CMD_DEL);
  938. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_CONT);
  939. case BNX2X_VFOP_MCAST_ADD:
  940. if (raw->check_pending(raw))
  941. goto op_pending;
  942. if (args->mc_num) {
  943. /* update mcast list on the ramrod params */
  944. INIT_LIST_HEAD(&mcast->mcast_list);
  945. for (i = 0; i < args->mc_num; i++)
  946. list_add_tail(&(args->mc[i].link),
  947. &mcast->mcast_list);
  948. /* add new mcasts */
  949. vfop->state = BNX2X_VFOP_MCAST_CHK_DONE;
  950. vfop->rc = bnx2x_config_mcast(bp, mcast,
  951. BNX2X_MCAST_CMD_ADD);
  952. }
  953. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_DONE);
  954. case BNX2X_VFOP_MCAST_CHK_DONE:
  955. vfop->rc = raw->check_pending(raw) ? 1 : 0;
  956. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_DONE);
  957. default:
  958. bnx2x_vfop_default(state);
  959. }
  960. op_err:
  961. BNX2X_ERR("MCAST CONFIG error: rc %d\n", vfop->rc);
  962. op_done:
  963. kfree(args->mc);
  964. bnx2x_vfop_end(bp, vf, vfop);
  965. op_pending:
  966. return;
  967. }
  968. int bnx2x_vfop_mcast_cmd(struct bnx2x *bp,
  969. struct bnx2x_virtf *vf,
  970. struct bnx2x_vfop_cmd *cmd,
  971. bnx2x_mac_addr_t *mcasts,
  972. int mcast_num, bool drv_only)
  973. {
  974. struct bnx2x_vfop *vfop = NULL;
  975. size_t mc_sz = mcast_num * sizeof(struct bnx2x_mcast_list_elem);
  976. struct bnx2x_mcast_list_elem *mc = mc_sz ? kzalloc(mc_sz, GFP_KERNEL) :
  977. NULL;
  978. if (!mc_sz || mc) {
  979. vfop = bnx2x_vfop_add(bp, vf);
  980. if (vfop) {
  981. int i;
  982. struct bnx2x_mcast_ramrod_params *ramrod =
  983. &vf->op_params.mcast;
  984. /* set ramrod params */
  985. memset(ramrod, 0, sizeof(*ramrod));
  986. ramrod->mcast_obj = &vf->mcast_obj;
  987. if (drv_only)
  988. set_bit(RAMROD_DRV_CLR_ONLY,
  989. &ramrod->ramrod_flags);
  990. /* copy mcasts pointers */
  991. vfop->args.mc_list.mc_num = mcast_num;
  992. vfop->args.mc_list.mc = mc;
  993. for (i = 0; i < mcast_num; i++)
  994. mc[i].mac = mcasts[i];
  995. bnx2x_vfop_opset(BNX2X_VFOP_MCAST_DEL,
  996. bnx2x_vfop_mcast, cmd->done);
  997. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_mcast,
  998. cmd->block);
  999. } else {
  1000. kfree(mc);
  1001. }
  1002. }
  1003. return -ENOMEM;
  1004. }
  1005. /* VFOP rx-mode */
  1006. static void bnx2x_vfop_rxmode(struct bnx2x *bp, struct bnx2x_virtf *vf)
  1007. {
  1008. struct bnx2x_vfop *vfop = bnx2x_vfop_cur(bp, vf);
  1009. struct bnx2x_rx_mode_ramrod_params *ramrod = &vfop->op_p->rx_mode;
  1010. enum bnx2x_vfop_rxmode_state state = vfop->state;
  1011. bnx2x_vfop_reset_wq(vf);
  1012. if (vfop->rc < 0)
  1013. goto op_err;
  1014. DP(BNX2X_MSG_IOV, "vf[%d] STATE: %d\n", vf->abs_vfid, state);
  1015. switch (state) {
  1016. case BNX2X_VFOP_RXMODE_CONFIG:
  1017. /* next state */
  1018. vfop->state = BNX2X_VFOP_RXMODE_DONE;
  1019. vfop->rc = bnx2x_config_rx_mode(bp, ramrod);
  1020. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_DONE);
  1021. op_err:
  1022. BNX2X_ERR("RXMODE error: rc %d\n", vfop->rc);
  1023. op_done:
  1024. case BNX2X_VFOP_RXMODE_DONE:
  1025. bnx2x_vfop_end(bp, vf, vfop);
  1026. return;
  1027. default:
  1028. bnx2x_vfop_default(state);
  1029. }
  1030. op_pending:
  1031. return;
  1032. }
  1033. int bnx2x_vfop_rxmode_cmd(struct bnx2x *bp,
  1034. struct bnx2x_virtf *vf,
  1035. struct bnx2x_vfop_cmd *cmd,
  1036. int qid, unsigned long accept_flags)
  1037. {
  1038. struct bnx2x_vf_queue *vfq = vfq_get(vf, qid);
  1039. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  1040. if (vfop) {
  1041. struct bnx2x_rx_mode_ramrod_params *ramrod =
  1042. &vf->op_params.rx_mode;
  1043. memset(ramrod, 0, sizeof(*ramrod));
  1044. /* Prepare ramrod parameters */
  1045. ramrod->cid = vfq->cid;
  1046. ramrod->cl_id = vfq_cl_id(vf, vfq);
  1047. ramrod->rx_mode_obj = &bp->rx_mode_obj;
  1048. ramrod->func_id = FW_VF_HANDLE(vf->abs_vfid);
  1049. ramrod->rx_accept_flags = accept_flags;
  1050. ramrod->tx_accept_flags = accept_flags;
  1051. ramrod->pstate = &vf->filter_state;
  1052. ramrod->state = BNX2X_FILTER_RX_MODE_PENDING;
  1053. set_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state);
  1054. set_bit(RAMROD_RX, &ramrod->ramrod_flags);
  1055. set_bit(RAMROD_TX, &ramrod->ramrod_flags);
  1056. ramrod->rdata =
  1057. bnx2x_vf_sp(bp, vf, rx_mode_rdata.e2);
  1058. ramrod->rdata_mapping =
  1059. bnx2x_vf_sp_map(bp, vf, rx_mode_rdata.e2);
  1060. bnx2x_vfop_opset(BNX2X_VFOP_RXMODE_CONFIG,
  1061. bnx2x_vfop_rxmode, cmd->done);
  1062. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_rxmode,
  1063. cmd->block);
  1064. }
  1065. return -ENOMEM;
  1066. }
  1067. /* VFOP queue tear-down ('drop all' rx-mode, clear vlans, clear macs,
  1068. * queue destructor)
  1069. */
  1070. static void bnx2x_vfop_qdown(struct bnx2x *bp, struct bnx2x_virtf *vf)
  1071. {
  1072. struct bnx2x_vfop *vfop = bnx2x_vfop_cur(bp, vf);
  1073. int qid = vfop->args.qx.qid;
  1074. enum bnx2x_vfop_qteardown_state state = vfop->state;
  1075. struct bnx2x_vfop_cmd cmd;
  1076. if (vfop->rc < 0)
  1077. goto op_err;
  1078. DP(BNX2X_MSG_IOV, "vf[%d] STATE: %d\n", vf->abs_vfid, state);
  1079. cmd.done = bnx2x_vfop_qdown;
  1080. cmd.block = false;
  1081. switch (state) {
  1082. case BNX2X_VFOP_QTEARDOWN_RXMODE:
  1083. /* Drop all */
  1084. vfop->state = BNX2X_VFOP_QTEARDOWN_CLR_VLAN;
  1085. vfop->rc = bnx2x_vfop_rxmode_cmd(bp, vf, &cmd, qid, 0);
  1086. if (vfop->rc)
  1087. goto op_err;
  1088. return;
  1089. case BNX2X_VFOP_QTEARDOWN_CLR_VLAN:
  1090. /* vlan-clear-all: don't consume credit */
  1091. vfop->state = BNX2X_VFOP_QTEARDOWN_CLR_MAC;
  1092. vfop->rc = bnx2x_vfop_vlan_delall_cmd(bp, vf, &cmd, qid, false);
  1093. if (vfop->rc)
  1094. goto op_err;
  1095. return;
  1096. case BNX2X_VFOP_QTEARDOWN_CLR_MAC:
  1097. /* mac-clear-all: consume credit */
  1098. vfop->state = BNX2X_VFOP_QTEARDOWN_QDTOR;
  1099. vfop->rc = bnx2x_vfop_mac_delall_cmd(bp, vf, &cmd, qid, false);
  1100. if (vfop->rc)
  1101. goto op_err;
  1102. return;
  1103. case BNX2X_VFOP_QTEARDOWN_QDTOR:
  1104. /* run the queue destruction flow */
  1105. DP(BNX2X_MSG_IOV, "case: BNX2X_VFOP_QTEARDOWN_QDTOR\n");
  1106. vfop->state = BNX2X_VFOP_QTEARDOWN_DONE;
  1107. DP(BNX2X_MSG_IOV, "new state: BNX2X_VFOP_QTEARDOWN_DONE\n");
  1108. vfop->rc = bnx2x_vfop_qdtor_cmd(bp, vf, &cmd, qid);
  1109. DP(BNX2X_MSG_IOV, "returned from cmd\n");
  1110. if (vfop->rc)
  1111. goto op_err;
  1112. return;
  1113. op_err:
  1114. BNX2X_ERR("QTEARDOWN[%d:%d] error: rc %d\n",
  1115. vf->abs_vfid, qid, vfop->rc);
  1116. case BNX2X_VFOP_QTEARDOWN_DONE:
  1117. bnx2x_vfop_end(bp, vf, vfop);
  1118. return;
  1119. default:
  1120. bnx2x_vfop_default(state);
  1121. }
  1122. }
  1123. int bnx2x_vfop_qdown_cmd(struct bnx2x *bp,
  1124. struct bnx2x_virtf *vf,
  1125. struct bnx2x_vfop_cmd *cmd,
  1126. int qid)
  1127. {
  1128. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  1129. /* for non leading queues skip directly to qdown sate */
  1130. if (vfop) {
  1131. vfop->args.qx.qid = qid;
  1132. bnx2x_vfop_opset(qid == LEADING_IDX ?
  1133. BNX2X_VFOP_QTEARDOWN_RXMODE :
  1134. BNX2X_VFOP_QTEARDOWN_QDTOR, bnx2x_vfop_qdown,
  1135. cmd->done);
  1136. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_qdown,
  1137. cmd->block);
  1138. }
  1139. return -ENOMEM;
  1140. }
  1141. /* VF enable primitives
  1142. * when pretend is required the caller is responsible
  1143. * for calling pretend prior to calling these routines
  1144. */
  1145. /* internal vf enable - until vf is enabled internally all transactions
  1146. * are blocked. This routine should always be called last with pretend.
  1147. */
  1148. static void bnx2x_vf_enable_internal(struct bnx2x *bp, u8 enable)
  1149. {
  1150. REG_WR(bp, PGLUE_B_REG_INTERNAL_VFID_ENABLE, enable ? 1 : 0);
  1151. }
  1152. /* clears vf error in all semi blocks */
  1153. static void bnx2x_vf_semi_clear_err(struct bnx2x *bp, u8 abs_vfid)
  1154. {
  1155. REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, abs_vfid);
  1156. REG_WR(bp, USEM_REG_VFPF_ERR_NUM, abs_vfid);
  1157. REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, abs_vfid);
  1158. REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, abs_vfid);
  1159. }
  1160. static void bnx2x_vf_pglue_clear_err(struct bnx2x *bp, u8 abs_vfid)
  1161. {
  1162. u32 was_err_group = (2 * BP_PATH(bp) + abs_vfid) >> 5;
  1163. u32 was_err_reg = 0;
  1164. switch (was_err_group) {
  1165. case 0:
  1166. was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR;
  1167. break;
  1168. case 1:
  1169. was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR;
  1170. break;
  1171. case 2:
  1172. was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR;
  1173. break;
  1174. case 3:
  1175. was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR;
  1176. break;
  1177. }
  1178. REG_WR(bp, was_err_reg, 1 << (abs_vfid & 0x1f));
  1179. }
  1180. static void bnx2x_vf_igu_reset(struct bnx2x *bp, struct bnx2x_virtf *vf)
  1181. {
  1182. int i;
  1183. u32 val;
  1184. /* Set VF masks and configuration - pretend */
  1185. bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid));
  1186. REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
  1187. REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
  1188. REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
  1189. REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
  1190. REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
  1191. REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
  1192. val = REG_RD(bp, IGU_REG_VF_CONFIGURATION);
  1193. val |= (IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_MSI_MSIX_EN);
  1194. if (vf->cfg_flags & VF_CFG_INT_SIMD)
  1195. val |= IGU_VF_CONF_SINGLE_ISR_EN;
  1196. val &= ~IGU_VF_CONF_PARENT_MASK;
  1197. val |= BP_FUNC(bp) << IGU_VF_CONF_PARENT_SHIFT; /* parent PF */
  1198. REG_WR(bp, IGU_REG_VF_CONFIGURATION, val);
  1199. DP(BNX2X_MSG_IOV,
  1200. "value in IGU_REG_VF_CONFIGURATION of vf %d after write %x\n",
  1201. vf->abs_vfid, REG_RD(bp, IGU_REG_VF_CONFIGURATION));
  1202. bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
  1203. /* iterate over all queues, clear sb consumer */
  1204. for (i = 0; i < vf_sb_count(vf); i++) {
  1205. u8 igu_sb_id = vf_igu_sb(vf, i);
  1206. /* zero prod memory */
  1207. REG_WR(bp, IGU_REG_PROD_CONS_MEMORY + igu_sb_id * 4, 0);
  1208. /* clear sb state machine */
  1209. bnx2x_igu_clear_sb_gen(bp, vf->abs_vfid, igu_sb_id,
  1210. false /* VF */);
  1211. /* disable + update */
  1212. bnx2x_vf_igu_ack_sb(bp, vf, igu_sb_id, USTORM_ID, 0,
  1213. IGU_INT_DISABLE, 1);
  1214. }
  1215. }
  1216. void bnx2x_vf_enable_access(struct bnx2x *bp, u8 abs_vfid)
  1217. {
  1218. /* set the VF-PF association in the FW */
  1219. storm_memset_vf_to_pf(bp, FW_VF_HANDLE(abs_vfid), BP_FUNC(bp));
  1220. storm_memset_func_en(bp, FW_VF_HANDLE(abs_vfid), 1);
  1221. /* clear vf errors*/
  1222. bnx2x_vf_semi_clear_err(bp, abs_vfid);
  1223. bnx2x_vf_pglue_clear_err(bp, abs_vfid);
  1224. /* internal vf-enable - pretend */
  1225. bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, abs_vfid));
  1226. DP(BNX2X_MSG_IOV, "enabling internal access for vf %x\n", abs_vfid);
  1227. bnx2x_vf_enable_internal(bp, true);
  1228. bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
  1229. }
  1230. static void bnx2x_vf_enable_traffic(struct bnx2x *bp, struct bnx2x_virtf *vf)
  1231. {
  1232. /* Reset vf in IGU interrupts are still disabled */
  1233. bnx2x_vf_igu_reset(bp, vf);
  1234. /* pretend to enable the vf with the PBF */
  1235. bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid));
  1236. REG_WR(bp, PBF_REG_DISABLE_VF, 0);
  1237. bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
  1238. }
  1239. static u8 bnx2x_vf_is_pcie_pending(struct bnx2x *bp, u8 abs_vfid)
  1240. {
  1241. struct pci_dev *dev;
  1242. struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid);
  1243. if (!vf)
  1244. return false;
  1245. dev = pci_get_bus_and_slot(vf->bus, vf->devfn);
  1246. if (dev)
  1247. return bnx2x_is_pcie_pending(dev);
  1248. return false;
  1249. }
  1250. int bnx2x_vf_flr_clnup_epilog(struct bnx2x *bp, u8 abs_vfid)
  1251. {
  1252. /* Verify no pending pci transactions */
  1253. if (bnx2x_vf_is_pcie_pending(bp, abs_vfid))
  1254. BNX2X_ERR("PCIE Transactions still pending\n");
  1255. return 0;
  1256. }
  1257. /* must be called after the number of PF queues and the number of VFs are
  1258. * both known
  1259. */
  1260. static void
  1261. bnx2x_iov_static_resc(struct bnx2x *bp, struct bnx2x_virtf *vf)
  1262. {
  1263. struct vf_pf_resc_request *resc = &vf->alloc_resc;
  1264. u16 vlan_count = 0;
  1265. /* will be set only during VF-ACQUIRE */
  1266. resc->num_rxqs = 0;
  1267. resc->num_txqs = 0;
  1268. /* no credit calculations for macs (just yet) */
  1269. resc->num_mac_filters = 1;
  1270. /* divvy up vlan rules */
  1271. vlan_count = bp->vlans_pool.check(&bp->vlans_pool);
  1272. vlan_count = 1 << ilog2(vlan_count);
  1273. resc->num_vlan_filters = vlan_count / BNX2X_NR_VIRTFN(bp);
  1274. /* no real limitation */
  1275. resc->num_mc_filters = 0;
  1276. /* num_sbs already set */
  1277. resc->num_sbs = vf->sb_count;
  1278. }
  1279. /* FLR routines: */
  1280. static void bnx2x_vf_free_resc(struct bnx2x *bp, struct bnx2x_virtf *vf)
  1281. {
  1282. /* reset the state variables */
  1283. bnx2x_iov_static_resc(bp, vf);
  1284. vf->state = VF_FREE;
  1285. }
  1286. static void bnx2x_vf_flr_clnup_hw(struct bnx2x *bp, struct bnx2x_virtf *vf)
  1287. {
  1288. u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
  1289. /* DQ usage counter */
  1290. bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid));
  1291. bnx2x_flr_clnup_poll_hw_counter(bp, DORQ_REG_VF_USAGE_CNT,
  1292. "DQ VF usage counter timed out",
  1293. poll_cnt);
  1294. bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
  1295. /* FW cleanup command - poll for the results */
  1296. if (bnx2x_send_final_clnup(bp, (u8)FW_VF_HANDLE(vf->abs_vfid),
  1297. poll_cnt))
  1298. BNX2X_ERR("VF[%d] Final cleanup timed-out\n", vf->abs_vfid);
  1299. /* verify TX hw is flushed */
  1300. bnx2x_tx_hw_flushed(bp, poll_cnt);
  1301. }
  1302. static void bnx2x_vfop_flr(struct bnx2x *bp, struct bnx2x_virtf *vf)
  1303. {
  1304. struct bnx2x_vfop *vfop = bnx2x_vfop_cur(bp, vf);
  1305. struct bnx2x_vfop_args_qx *qx = &vfop->args.qx;
  1306. enum bnx2x_vfop_flr_state state = vfop->state;
  1307. struct bnx2x_vfop_cmd cmd = {
  1308. .done = bnx2x_vfop_flr,
  1309. .block = false,
  1310. };
  1311. if (vfop->rc < 0)
  1312. goto op_err;
  1313. DP(BNX2X_MSG_IOV, "vf[%d] STATE: %d\n", vf->abs_vfid, state);
  1314. switch (state) {
  1315. case BNX2X_VFOP_FLR_QUEUES:
  1316. /* the cleanup operations are valid if and only if the VF
  1317. * was first acquired.
  1318. */
  1319. if (++(qx->qid) < vf_rxq_count(vf)) {
  1320. vfop->rc = bnx2x_vfop_qflr_cmd(bp, vf, &cmd,
  1321. qx->qid);
  1322. if (vfop->rc)
  1323. goto op_err;
  1324. return;
  1325. }
  1326. /* remove multicasts */
  1327. vfop->state = BNX2X_VFOP_FLR_HW;
  1328. vfop->rc = bnx2x_vfop_mcast_cmd(bp, vf, &cmd, NULL,
  1329. 0, true);
  1330. if (vfop->rc)
  1331. goto op_err;
  1332. return;
  1333. case BNX2X_VFOP_FLR_HW:
  1334. /* dispatch final cleanup and wait for HW queues to flush */
  1335. bnx2x_vf_flr_clnup_hw(bp, vf);
  1336. /* release VF resources */
  1337. bnx2x_vf_free_resc(bp, vf);
  1338. /* re-open the mailbox */
  1339. bnx2x_vf_enable_mbx(bp, vf->abs_vfid);
  1340. goto op_done;
  1341. default:
  1342. bnx2x_vfop_default(state);
  1343. }
  1344. op_err:
  1345. BNX2X_ERR("VF[%d] FLR error: rc %d\n", vf->abs_vfid, vfop->rc);
  1346. op_done:
  1347. vf->flr_clnup_stage = VF_FLR_ACK;
  1348. bnx2x_vfop_end(bp, vf, vfop);
  1349. bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_FLR);
  1350. }
  1351. static int bnx2x_vfop_flr_cmd(struct bnx2x *bp,
  1352. struct bnx2x_virtf *vf,
  1353. vfop_handler_t done)
  1354. {
  1355. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  1356. if (vfop) {
  1357. vfop->args.qx.qid = -1; /* loop */
  1358. bnx2x_vfop_opset(BNX2X_VFOP_FLR_QUEUES,
  1359. bnx2x_vfop_flr, done);
  1360. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_flr, false);
  1361. }
  1362. return -ENOMEM;
  1363. }
  1364. static void bnx2x_vf_flr_clnup(struct bnx2x *bp, struct bnx2x_virtf *prev_vf)
  1365. {
  1366. int i = prev_vf ? prev_vf->index + 1 : 0;
  1367. struct bnx2x_virtf *vf;
  1368. /* find next VF to cleanup */
  1369. next_vf_to_clean:
  1370. for (;
  1371. i < BNX2X_NR_VIRTFN(bp) &&
  1372. (bnx2x_vf(bp, i, state) != VF_RESET ||
  1373. bnx2x_vf(bp, i, flr_clnup_stage) != VF_FLR_CLN);
  1374. i++)
  1375. ;
  1376. DP(BNX2X_MSG_IOV, "next vf to cleanup: %d. Num of vfs: %d\n", i,
  1377. BNX2X_NR_VIRTFN(bp));
  1378. if (i < BNX2X_NR_VIRTFN(bp)) {
  1379. vf = BP_VF(bp, i);
  1380. /* lock the vf pf channel */
  1381. bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_FLR);
  1382. /* invoke the VF FLR SM */
  1383. if (bnx2x_vfop_flr_cmd(bp, vf, bnx2x_vf_flr_clnup)) {
  1384. BNX2X_ERR("VF[%d]: FLR cleanup failed -ENOMEM\n",
  1385. vf->abs_vfid);
  1386. /* mark the VF to be ACKED and continue */
  1387. vf->flr_clnup_stage = VF_FLR_ACK;
  1388. goto next_vf_to_clean;
  1389. }
  1390. return;
  1391. }
  1392. /* we are done, update vf records */
  1393. for_each_vf(bp, i) {
  1394. vf = BP_VF(bp, i);
  1395. if (vf->flr_clnup_stage != VF_FLR_ACK)
  1396. continue;
  1397. vf->flr_clnup_stage = VF_FLR_EPILOG;
  1398. }
  1399. /* Acknowledge the handled VFs.
  1400. * we are acknowledge all the vfs which an flr was requested for, even
  1401. * if amongst them there are such that we never opened, since the mcp
  1402. * will interrupt us immediately again if we only ack some of the bits,
  1403. * resulting in an endless loop. This can happen for example in KVM
  1404. * where an 'all ones' flr request is sometimes given by hyper visor
  1405. */
  1406. DP(BNX2X_MSG_MCP, "DRV_STATUS_VF_DISABLED ACK for vfs 0x%x 0x%x\n",
  1407. bp->vfdb->flrd_vfs[0], bp->vfdb->flrd_vfs[1]);
  1408. for (i = 0; i < FLRD_VFS_DWORDS; i++)
  1409. SHMEM2_WR(bp, drv_ack_vf_disabled[BP_FW_MB_IDX(bp)][i],
  1410. bp->vfdb->flrd_vfs[i]);
  1411. bnx2x_fw_command(bp, DRV_MSG_CODE_VF_DISABLED_DONE, 0);
  1412. /* clear the acked bits - better yet if the MCP implemented
  1413. * write to clear semantics
  1414. */
  1415. for (i = 0; i < FLRD_VFS_DWORDS; i++)
  1416. SHMEM2_WR(bp, drv_ack_vf_disabled[BP_FW_MB_IDX(bp)][i], 0);
  1417. }
  1418. void bnx2x_vf_handle_flr_event(struct bnx2x *bp)
  1419. {
  1420. int i;
  1421. /* Read FLR'd VFs */
  1422. for (i = 0; i < FLRD_VFS_DWORDS; i++)
  1423. bp->vfdb->flrd_vfs[i] = SHMEM2_RD(bp, mcp_vf_disabled[i]);
  1424. DP(BNX2X_MSG_MCP,
  1425. "DRV_STATUS_VF_DISABLED received for vfs 0x%x 0x%x\n",
  1426. bp->vfdb->flrd_vfs[0], bp->vfdb->flrd_vfs[1]);
  1427. for_each_vf(bp, i) {
  1428. struct bnx2x_virtf *vf = BP_VF(bp, i);
  1429. u32 reset = 0;
  1430. if (vf->abs_vfid < 32)
  1431. reset = bp->vfdb->flrd_vfs[0] & (1 << vf->abs_vfid);
  1432. else
  1433. reset = bp->vfdb->flrd_vfs[1] &
  1434. (1 << (vf->abs_vfid - 32));
  1435. if (reset) {
  1436. /* set as reset and ready for cleanup */
  1437. vf->state = VF_RESET;
  1438. vf->flr_clnup_stage = VF_FLR_CLN;
  1439. DP(BNX2X_MSG_IOV,
  1440. "Initiating Final cleanup for VF %d\n",
  1441. vf->abs_vfid);
  1442. }
  1443. }
  1444. /* do the FLR cleanup for all marked VFs*/
  1445. bnx2x_vf_flr_clnup(bp, NULL);
  1446. }
  1447. /* IOV global initialization routines */
  1448. void bnx2x_iov_init_dq(struct bnx2x *bp)
  1449. {
  1450. if (!IS_SRIOV(bp))
  1451. return;
  1452. /* Set the DQ such that the CID reflect the abs_vfid */
  1453. REG_WR(bp, DORQ_REG_VF_NORM_VF_BASE, 0);
  1454. REG_WR(bp, DORQ_REG_MAX_RVFID_SIZE, ilog2(BNX2X_MAX_NUM_OF_VFS));
  1455. /* Set VFs starting CID. If its > 0 the preceding CIDs are belong to
  1456. * the PF L2 queues
  1457. */
  1458. REG_WR(bp, DORQ_REG_VF_NORM_CID_BASE, BNX2X_FIRST_VF_CID);
  1459. /* The VF window size is the log2 of the max number of CIDs per VF */
  1460. REG_WR(bp, DORQ_REG_VF_NORM_CID_WND_SIZE, BNX2X_VF_CID_WND);
  1461. /* The VF doorbell size 0 - *B, 4 - 128B. We set it here to match
  1462. * the Pf doorbell size although the 2 are independent.
  1463. */
  1464. REG_WR(bp, DORQ_REG_VF_NORM_CID_OFST, 3);
  1465. /* No security checks for now -
  1466. * configure single rule (out of 16) mask = 0x1, value = 0x0,
  1467. * CID range 0 - 0x1ffff
  1468. */
  1469. REG_WR(bp, DORQ_REG_VF_TYPE_MASK_0, 1);
  1470. REG_WR(bp, DORQ_REG_VF_TYPE_VALUE_0, 0);
  1471. REG_WR(bp, DORQ_REG_VF_TYPE_MIN_MCID_0, 0);
  1472. REG_WR(bp, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff);
  1473. /* set the VF doorbell threshold */
  1474. REG_WR(bp, DORQ_REG_VF_USAGE_CT_LIMIT, 4);
  1475. }
  1476. void bnx2x_iov_init_dmae(struct bnx2x *bp)
  1477. {
  1478. if (pci_find_ext_capability(bp->pdev, PCI_EXT_CAP_ID_SRIOV))
  1479. REG_WR(bp, DMAE_REG_BACKWARD_COMP_EN, 0);
  1480. }
  1481. static int bnx2x_vf_bus(struct bnx2x *bp, int vfid)
  1482. {
  1483. struct pci_dev *dev = bp->pdev;
  1484. struct bnx2x_sriov *iov = &bp->vfdb->sriov;
  1485. return dev->bus->number + ((dev->devfn + iov->offset +
  1486. iov->stride * vfid) >> 8);
  1487. }
  1488. static int bnx2x_vf_devfn(struct bnx2x *bp, int vfid)
  1489. {
  1490. struct pci_dev *dev = bp->pdev;
  1491. struct bnx2x_sriov *iov = &bp->vfdb->sriov;
  1492. return (dev->devfn + iov->offset + iov->stride * vfid) & 0xff;
  1493. }
  1494. static void bnx2x_vf_set_bars(struct bnx2x *bp, struct bnx2x_virtf *vf)
  1495. {
  1496. int i, n;
  1497. struct pci_dev *dev = bp->pdev;
  1498. struct bnx2x_sriov *iov = &bp->vfdb->sriov;
  1499. for (i = 0, n = 0; i < PCI_SRIOV_NUM_BARS; i += 2, n++) {
  1500. u64 start = pci_resource_start(dev, PCI_IOV_RESOURCES + i);
  1501. u32 size = pci_resource_len(dev, PCI_IOV_RESOURCES + i);
  1502. size /= iov->total;
  1503. vf->bars[n].bar = start + size * vf->abs_vfid;
  1504. vf->bars[n].size = size;
  1505. }
  1506. }
  1507. static int bnx2x_ari_enabled(struct pci_dev *dev)
  1508. {
  1509. return dev->bus->self && dev->bus->self->ari_enabled;
  1510. }
  1511. static void
  1512. bnx2x_get_vf_igu_cam_info(struct bnx2x *bp)
  1513. {
  1514. int sb_id;
  1515. u32 val;
  1516. u8 fid, current_pf = 0;
  1517. /* IGU in normal mode - read CAM */
  1518. for (sb_id = 0; sb_id < IGU_REG_MAPPING_MEMORY_SIZE; sb_id++) {
  1519. val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + sb_id * 4);
  1520. if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
  1521. continue;
  1522. fid = GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID);
  1523. if (fid & IGU_FID_ENCODE_IS_PF)
  1524. current_pf = fid & IGU_FID_PF_NUM_MASK;
  1525. else if (current_pf == BP_ABS_FUNC(bp))
  1526. bnx2x_vf_set_igu_info(bp, sb_id,
  1527. (fid & IGU_FID_VF_NUM_MASK));
  1528. DP(BNX2X_MSG_IOV, "%s[%d], igu_sb_id=%d, msix=%d\n",
  1529. ((fid & IGU_FID_ENCODE_IS_PF) ? "PF" : "VF"),
  1530. ((fid & IGU_FID_ENCODE_IS_PF) ? (fid & IGU_FID_PF_NUM_MASK) :
  1531. (fid & IGU_FID_VF_NUM_MASK)), sb_id,
  1532. GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR));
  1533. }
  1534. DP(BNX2X_MSG_IOV, "vf_sbs_pool is %d\n", BP_VFDB(bp)->vf_sbs_pool);
  1535. }
  1536. static void __bnx2x_iov_free_vfdb(struct bnx2x *bp)
  1537. {
  1538. if (bp->vfdb) {
  1539. kfree(bp->vfdb->vfqs);
  1540. kfree(bp->vfdb->vfs);
  1541. kfree(bp->vfdb);
  1542. }
  1543. bp->vfdb = NULL;
  1544. }
  1545. static int bnx2x_sriov_pci_cfg_info(struct bnx2x *bp, struct bnx2x_sriov *iov)
  1546. {
  1547. int pos;
  1548. struct pci_dev *dev = bp->pdev;
  1549. pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
  1550. if (!pos) {
  1551. BNX2X_ERR("failed to find SRIOV capability in device\n");
  1552. return -ENODEV;
  1553. }
  1554. iov->pos = pos;
  1555. DP(BNX2X_MSG_IOV, "sriov ext pos %d\n", pos);
  1556. pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &iov->ctrl);
  1557. pci_read_config_word(dev, pos + PCI_SRIOV_TOTAL_VF, &iov->total);
  1558. pci_read_config_word(dev, pos + PCI_SRIOV_INITIAL_VF, &iov->initial);
  1559. pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &iov->offset);
  1560. pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &iov->stride);
  1561. pci_read_config_dword(dev, pos + PCI_SRIOV_SUP_PGSIZE, &iov->pgsz);
  1562. pci_read_config_dword(dev, pos + PCI_SRIOV_CAP, &iov->cap);
  1563. pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link);
  1564. return 0;
  1565. }
  1566. static int bnx2x_sriov_info(struct bnx2x *bp, struct bnx2x_sriov *iov)
  1567. {
  1568. u32 val;
  1569. /* read the SRIOV capability structure
  1570. * The fields can be read via configuration read or
  1571. * directly from the device (starting at offset PCICFG_OFFSET)
  1572. */
  1573. if (bnx2x_sriov_pci_cfg_info(bp, iov))
  1574. return -ENODEV;
  1575. /* get the number of SRIOV bars */
  1576. iov->nres = 0;
  1577. /* read the first_vfid */
  1578. val = REG_RD(bp, PCICFG_OFFSET + GRC_CONFIG_REG_PF_INIT_VF);
  1579. iov->first_vf_in_pf = ((val & GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK)
  1580. * 8) - (BNX2X_MAX_NUM_OF_VFS * BP_PATH(bp));
  1581. DP(BNX2X_MSG_IOV,
  1582. "IOV info[%d]: first vf %d, nres %d, cap 0x%x, ctrl 0x%x, total %d, initial %d, num vfs %d, offset %d, stride %d, page size 0x%x\n",
  1583. BP_FUNC(bp),
  1584. iov->first_vf_in_pf, iov->nres, iov->cap, iov->ctrl, iov->total,
  1585. iov->initial, iov->nr_virtfn, iov->offset, iov->stride, iov->pgsz);
  1586. return 0;
  1587. }
  1588. /* must be called after PF bars are mapped */
  1589. int bnx2x_iov_init_one(struct bnx2x *bp, int int_mode_param,
  1590. int num_vfs_param)
  1591. {
  1592. int err, i;
  1593. struct bnx2x_sriov *iov;
  1594. struct pci_dev *dev = bp->pdev;
  1595. bp->vfdb = NULL;
  1596. /* verify is pf */
  1597. if (IS_VF(bp))
  1598. return 0;
  1599. /* verify sriov capability is present in configuration space */
  1600. if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV))
  1601. return 0;
  1602. /* verify chip revision */
  1603. if (CHIP_IS_E1x(bp))
  1604. return 0;
  1605. /* check if SRIOV support is turned off */
  1606. if (!num_vfs_param)
  1607. return 0;
  1608. /* SRIOV assumes that num of PF CIDs < BNX2X_FIRST_VF_CID */
  1609. if (BNX2X_L2_MAX_CID(bp) >= BNX2X_FIRST_VF_CID) {
  1610. BNX2X_ERR("PF cids %d are overspilling into vf space (starts at %d). Abort SRIOV\n",
  1611. BNX2X_L2_MAX_CID(bp), BNX2X_FIRST_VF_CID);
  1612. return 0;
  1613. }
  1614. /* SRIOV can be enabled only with MSIX */
  1615. if (int_mode_param == BNX2X_INT_MODE_MSI ||
  1616. int_mode_param == BNX2X_INT_MODE_INTX) {
  1617. BNX2X_ERR("Forced MSI/INTx mode is incompatible with SRIOV\n");
  1618. return 0;
  1619. }
  1620. err = -EIO;
  1621. /* verify ari is enabled */
  1622. if (!bnx2x_ari_enabled(bp->pdev)) {
  1623. BNX2X_ERR("ARI not supported (check pci bridge ARI forwarding), SRIOV can not be enabled\n");
  1624. return 0;
  1625. }
  1626. /* verify igu is in normal mode */
  1627. if (CHIP_INT_MODE_IS_BC(bp)) {
  1628. BNX2X_ERR("IGU not normal mode, SRIOV can not be enabled\n");
  1629. return 0;
  1630. }
  1631. /* allocate the vfs database */
  1632. bp->vfdb = kzalloc(sizeof(*(bp->vfdb)), GFP_KERNEL);
  1633. if (!bp->vfdb) {
  1634. BNX2X_ERR("failed to allocate vf database\n");
  1635. err = -ENOMEM;
  1636. goto failed;
  1637. }
  1638. /* get the sriov info - Linux already collected all the pertinent
  1639. * information, however the sriov structure is for the private use
  1640. * of the pci module. Also we want this information regardless
  1641. * of the hyper-visor.
  1642. */
  1643. iov = &(bp->vfdb->sriov);
  1644. err = bnx2x_sriov_info(bp, iov);
  1645. if (err)
  1646. goto failed;
  1647. /* SR-IOV capability was enabled but there are no VFs*/
  1648. if (iov->total == 0)
  1649. goto failed;
  1650. iov->nr_virtfn = min_t(u16, iov->total, num_vfs_param);
  1651. DP(BNX2X_MSG_IOV, "num_vfs_param was %d, nr_virtfn was %d\n",
  1652. num_vfs_param, iov->nr_virtfn);
  1653. /* allocate the vf array */
  1654. bp->vfdb->vfs = kzalloc(sizeof(struct bnx2x_virtf) *
  1655. BNX2X_NR_VIRTFN(bp), GFP_KERNEL);
  1656. if (!bp->vfdb->vfs) {
  1657. BNX2X_ERR("failed to allocate vf array\n");
  1658. err = -ENOMEM;
  1659. goto failed;
  1660. }
  1661. /* Initial VF init - index and abs_vfid - nr_virtfn must be set */
  1662. for_each_vf(bp, i) {
  1663. bnx2x_vf(bp, i, index) = i;
  1664. bnx2x_vf(bp, i, abs_vfid) = iov->first_vf_in_pf + i;
  1665. bnx2x_vf(bp, i, state) = VF_FREE;
  1666. INIT_LIST_HEAD(&bnx2x_vf(bp, i, op_list_head));
  1667. mutex_init(&bnx2x_vf(bp, i, op_mutex));
  1668. bnx2x_vf(bp, i, op_current) = CHANNEL_TLV_NONE;
  1669. }
  1670. /* re-read the IGU CAM for VFs - index and abs_vfid must be set */
  1671. bnx2x_get_vf_igu_cam_info(bp);
  1672. /* allocate the queue arrays for all VFs */
  1673. bp->vfdb->vfqs = kzalloc(
  1674. BNX2X_MAX_NUM_VF_QUEUES * sizeof(struct bnx2x_vf_queue),
  1675. GFP_KERNEL);
  1676. DP(BNX2X_MSG_IOV, "bp->vfdb->vfqs was %p\n", bp->vfdb->vfqs);
  1677. if (!bp->vfdb->vfqs) {
  1678. BNX2X_ERR("failed to allocate vf queue array\n");
  1679. err = -ENOMEM;
  1680. goto failed;
  1681. }
  1682. return 0;
  1683. failed:
  1684. DP(BNX2X_MSG_IOV, "Failed err=%d\n", err);
  1685. __bnx2x_iov_free_vfdb(bp);
  1686. return err;
  1687. }
  1688. void bnx2x_iov_remove_one(struct bnx2x *bp)
  1689. {
  1690. /* if SRIOV is not enabled there's nothing to do */
  1691. if (!IS_SRIOV(bp))
  1692. return;
  1693. DP(BNX2X_MSG_IOV, "about to call disable sriov\n");
  1694. pci_disable_sriov(bp->pdev);
  1695. DP(BNX2X_MSG_IOV, "sriov disabled\n");
  1696. /* free vf database */
  1697. __bnx2x_iov_free_vfdb(bp);
  1698. }
  1699. void bnx2x_iov_free_mem(struct bnx2x *bp)
  1700. {
  1701. int i;
  1702. if (!IS_SRIOV(bp))
  1703. return;
  1704. /* free vfs hw contexts */
  1705. for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) {
  1706. struct hw_dma *cxt = &bp->vfdb->context[i];
  1707. BNX2X_PCI_FREE(cxt->addr, cxt->mapping, cxt->size);
  1708. }
  1709. BNX2X_PCI_FREE(BP_VFDB(bp)->sp_dma.addr,
  1710. BP_VFDB(bp)->sp_dma.mapping,
  1711. BP_VFDB(bp)->sp_dma.size);
  1712. BNX2X_PCI_FREE(BP_VF_MBX_DMA(bp)->addr,
  1713. BP_VF_MBX_DMA(bp)->mapping,
  1714. BP_VF_MBX_DMA(bp)->size);
  1715. BNX2X_PCI_FREE(BP_VF_BULLETIN_DMA(bp)->addr,
  1716. BP_VF_BULLETIN_DMA(bp)->mapping,
  1717. BP_VF_BULLETIN_DMA(bp)->size);
  1718. }
  1719. int bnx2x_iov_alloc_mem(struct bnx2x *bp)
  1720. {
  1721. size_t tot_size;
  1722. int i, rc = 0;
  1723. if (!IS_SRIOV(bp))
  1724. return rc;
  1725. /* allocate vfs hw contexts */
  1726. tot_size = (BP_VFDB(bp)->sriov.first_vf_in_pf + BNX2X_NR_VIRTFN(bp)) *
  1727. BNX2X_CIDS_PER_VF * sizeof(union cdu_context);
  1728. for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) {
  1729. struct hw_dma *cxt = BP_VF_CXT_PAGE(bp, i);
  1730. cxt->size = min_t(size_t, tot_size, CDU_ILT_PAGE_SZ);
  1731. if (cxt->size) {
  1732. BNX2X_PCI_ALLOC(cxt->addr, &cxt->mapping, cxt->size);
  1733. } else {
  1734. cxt->addr = NULL;
  1735. cxt->mapping = 0;
  1736. }
  1737. tot_size -= cxt->size;
  1738. }
  1739. /* allocate vfs ramrods dma memory - client_init and set_mac */
  1740. tot_size = BNX2X_NR_VIRTFN(bp) * sizeof(struct bnx2x_vf_sp);
  1741. BNX2X_PCI_ALLOC(BP_VFDB(bp)->sp_dma.addr, &BP_VFDB(bp)->sp_dma.mapping,
  1742. tot_size);
  1743. BP_VFDB(bp)->sp_dma.size = tot_size;
  1744. /* allocate mailboxes */
  1745. tot_size = BNX2X_NR_VIRTFN(bp) * MBX_MSG_ALIGNED_SIZE;
  1746. BNX2X_PCI_ALLOC(BP_VF_MBX_DMA(bp)->addr, &BP_VF_MBX_DMA(bp)->mapping,
  1747. tot_size);
  1748. BP_VF_MBX_DMA(bp)->size = tot_size;
  1749. /* allocate local bulletin boards */
  1750. tot_size = BNX2X_NR_VIRTFN(bp) * BULLETIN_CONTENT_SIZE;
  1751. BNX2X_PCI_ALLOC(BP_VF_BULLETIN_DMA(bp)->addr,
  1752. &BP_VF_BULLETIN_DMA(bp)->mapping, tot_size);
  1753. BP_VF_BULLETIN_DMA(bp)->size = tot_size;
  1754. return 0;
  1755. alloc_mem_err:
  1756. return -ENOMEM;
  1757. }
  1758. static void bnx2x_vfq_init(struct bnx2x *bp, struct bnx2x_virtf *vf,
  1759. struct bnx2x_vf_queue *q)
  1760. {
  1761. u8 cl_id = vfq_cl_id(vf, q);
  1762. u8 func_id = FW_VF_HANDLE(vf->abs_vfid);
  1763. unsigned long q_type = 0;
  1764. set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
  1765. set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
  1766. /* Queue State object */
  1767. bnx2x_init_queue_obj(bp, &q->sp_obj,
  1768. cl_id, &q->cid, 1, func_id,
  1769. bnx2x_vf_sp(bp, vf, q_data),
  1770. bnx2x_vf_sp_map(bp, vf, q_data),
  1771. q_type);
  1772. DP(BNX2X_MSG_IOV,
  1773. "initialized vf %d's queue object. func id set to %d. cid set to 0x%x\n",
  1774. vf->abs_vfid, q->sp_obj.func_id, q->cid);
  1775. }
  1776. /* called by bnx2x_nic_load */
  1777. int bnx2x_iov_nic_init(struct bnx2x *bp)
  1778. {
  1779. int vfid;
  1780. if (!IS_SRIOV(bp)) {
  1781. DP(BNX2X_MSG_IOV, "vfdb was not allocated\n");
  1782. return 0;
  1783. }
  1784. DP(BNX2X_MSG_IOV, "num of vfs: %d\n", (bp)->vfdb->sriov.nr_virtfn);
  1785. /* let FLR complete ... */
  1786. msleep(100);
  1787. /* initialize vf database */
  1788. for_each_vf(bp, vfid) {
  1789. struct bnx2x_virtf *vf = BP_VF(bp, vfid);
  1790. int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vfid) *
  1791. BNX2X_CIDS_PER_VF;
  1792. union cdu_context *base_cxt = (union cdu_context *)
  1793. BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr +
  1794. (base_vf_cid & (ILT_PAGE_CIDS-1));
  1795. DP(BNX2X_MSG_IOV,
  1796. "VF[%d] Max IGU SBs: %d, base vf cid 0x%x, base cid 0x%x, base cxt %p\n",
  1797. vf->abs_vfid, vf_sb_count(vf), base_vf_cid,
  1798. BNX2X_FIRST_VF_CID + base_vf_cid, base_cxt);
  1799. /* init statically provisioned resources */
  1800. bnx2x_iov_static_resc(bp, vf);
  1801. /* queues are initialized during VF-ACQUIRE */
  1802. /* reserve the vf vlan credit */
  1803. bp->vlans_pool.get(&bp->vlans_pool, vf_vlan_rules_cnt(vf));
  1804. vf->filter_state = 0;
  1805. vf->sp_cl_id = bnx2x_fp(bp, 0, cl_id);
  1806. /* init mcast object - This object will be re-initialized
  1807. * during VF-ACQUIRE with the proper cl_id and cid.
  1808. * It needs to be initialized here so that it can be safely
  1809. * handled by a subsequent FLR flow.
  1810. */
  1811. bnx2x_init_mcast_obj(bp, &vf->mcast_obj, 0xFF,
  1812. 0xFF, 0xFF, 0xFF,
  1813. bnx2x_vf_sp(bp, vf, mcast_rdata),
  1814. bnx2x_vf_sp_map(bp, vf, mcast_rdata),
  1815. BNX2X_FILTER_MCAST_PENDING,
  1816. &vf->filter_state,
  1817. BNX2X_OBJ_TYPE_RX_TX);
  1818. /* set the mailbox message addresses */
  1819. BP_VF_MBX(bp, vfid)->msg = (struct bnx2x_vf_mbx_msg *)
  1820. (((u8 *)BP_VF_MBX_DMA(bp)->addr) + vfid *
  1821. MBX_MSG_ALIGNED_SIZE);
  1822. BP_VF_MBX(bp, vfid)->msg_mapping = BP_VF_MBX_DMA(bp)->mapping +
  1823. vfid * MBX_MSG_ALIGNED_SIZE;
  1824. /* Enable vf mailbox */
  1825. bnx2x_vf_enable_mbx(bp, vf->abs_vfid);
  1826. }
  1827. /* Final VF init */
  1828. for_each_vf(bp, vfid) {
  1829. struct bnx2x_virtf *vf = BP_VF(bp, vfid);
  1830. /* fill in the BDF and bars */
  1831. vf->bus = bnx2x_vf_bus(bp, vfid);
  1832. vf->devfn = bnx2x_vf_devfn(bp, vfid);
  1833. bnx2x_vf_set_bars(bp, vf);
  1834. DP(BNX2X_MSG_IOV,
  1835. "VF info[%d]: bus 0x%x, devfn 0x%x, bar0 [0x%x, %d], bar1 [0x%x, %d], bar2 [0x%x, %d]\n",
  1836. vf->abs_vfid, vf->bus, vf->devfn,
  1837. (unsigned)vf->bars[0].bar, vf->bars[0].size,
  1838. (unsigned)vf->bars[1].bar, vf->bars[1].size,
  1839. (unsigned)vf->bars[2].bar, vf->bars[2].size);
  1840. }
  1841. return 0;
  1842. }
  1843. /* called by bnx2x_chip_cleanup */
  1844. int bnx2x_iov_chip_cleanup(struct bnx2x *bp)
  1845. {
  1846. int i;
  1847. if (!IS_SRIOV(bp))
  1848. return 0;
  1849. /* release all the VFs */
  1850. for_each_vf(bp, i)
  1851. bnx2x_vf_release(bp, BP_VF(bp, i), true); /* blocking */
  1852. return 0;
  1853. }
  1854. /* called by bnx2x_init_hw_func, returns the next ilt line */
  1855. int bnx2x_iov_init_ilt(struct bnx2x *bp, u16 line)
  1856. {
  1857. int i;
  1858. struct bnx2x_ilt *ilt = BP_ILT(bp);
  1859. if (!IS_SRIOV(bp))
  1860. return line;
  1861. /* set vfs ilt lines */
  1862. for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) {
  1863. struct hw_dma *hw_cxt = BP_VF_CXT_PAGE(bp, i);
  1864. ilt->lines[line+i].page = hw_cxt->addr;
  1865. ilt->lines[line+i].page_mapping = hw_cxt->mapping;
  1866. ilt->lines[line+i].size = hw_cxt->size; /* doesn't matter */
  1867. }
  1868. return line + i;
  1869. }
  1870. static u8 bnx2x_iov_is_vf_cid(struct bnx2x *bp, u16 cid)
  1871. {
  1872. return ((cid >= BNX2X_FIRST_VF_CID) &&
  1873. ((cid - BNX2X_FIRST_VF_CID) < BNX2X_VF_CIDS));
  1874. }
  1875. static
  1876. void bnx2x_vf_handle_classification_eqe(struct bnx2x *bp,
  1877. struct bnx2x_vf_queue *vfq,
  1878. union event_ring_elem *elem)
  1879. {
  1880. unsigned long ramrod_flags = 0;
  1881. int rc = 0;
  1882. /* Always push next commands out, don't wait here */
  1883. set_bit(RAMROD_CONT, &ramrod_flags);
  1884. switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
  1885. case BNX2X_FILTER_MAC_PENDING:
  1886. rc = vfq->mac_obj.complete(bp, &vfq->mac_obj, elem,
  1887. &ramrod_flags);
  1888. break;
  1889. case BNX2X_FILTER_VLAN_PENDING:
  1890. rc = vfq->vlan_obj.complete(bp, &vfq->vlan_obj, elem,
  1891. &ramrod_flags);
  1892. break;
  1893. default:
  1894. BNX2X_ERR("Unsupported classification command: %d\n",
  1895. elem->message.data.eth_event.echo);
  1896. return;
  1897. }
  1898. if (rc < 0)
  1899. BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
  1900. else if (rc > 0)
  1901. DP(BNX2X_MSG_IOV, "Scheduled next pending commands...\n");
  1902. }
  1903. static
  1904. void bnx2x_vf_handle_mcast_eqe(struct bnx2x *bp,
  1905. struct bnx2x_virtf *vf)
  1906. {
  1907. struct bnx2x_mcast_ramrod_params rparam = {NULL};
  1908. int rc;
  1909. rparam.mcast_obj = &vf->mcast_obj;
  1910. vf->mcast_obj.raw.clear_pending(&vf->mcast_obj.raw);
  1911. /* If there are pending mcast commands - send them */
  1912. if (vf->mcast_obj.check_pending(&vf->mcast_obj)) {
  1913. rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
  1914. if (rc < 0)
  1915. BNX2X_ERR("Failed to send pending mcast commands: %d\n",
  1916. rc);
  1917. }
  1918. }
  1919. static
  1920. void bnx2x_vf_handle_filters_eqe(struct bnx2x *bp,
  1921. struct bnx2x_virtf *vf)
  1922. {
  1923. smp_mb__before_clear_bit();
  1924. clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state);
  1925. smp_mb__after_clear_bit();
  1926. }
  1927. int bnx2x_iov_eq_sp_event(struct bnx2x *bp, union event_ring_elem *elem)
  1928. {
  1929. struct bnx2x_virtf *vf;
  1930. int qidx = 0, abs_vfid;
  1931. u8 opcode;
  1932. u16 cid = 0xffff;
  1933. if (!IS_SRIOV(bp))
  1934. return 1;
  1935. /* first get the cid - the only events we handle here are cfc-delete
  1936. * and set-mac completion
  1937. */
  1938. opcode = elem->message.opcode;
  1939. switch (opcode) {
  1940. case EVENT_RING_OPCODE_CFC_DEL:
  1941. cid = SW_CID((__force __le32)
  1942. elem->message.data.cfc_del_event.cid);
  1943. DP(BNX2X_MSG_IOV, "checking cfc-del comp cid=%d\n", cid);
  1944. break;
  1945. case EVENT_RING_OPCODE_CLASSIFICATION_RULES:
  1946. case EVENT_RING_OPCODE_MULTICAST_RULES:
  1947. case EVENT_RING_OPCODE_FILTERS_RULES:
  1948. cid = (elem->message.data.eth_event.echo &
  1949. BNX2X_SWCID_MASK);
  1950. DP(BNX2X_MSG_IOV, "checking filtering comp cid=%d\n", cid);
  1951. break;
  1952. case EVENT_RING_OPCODE_VF_FLR:
  1953. abs_vfid = elem->message.data.vf_flr_event.vf_id;
  1954. DP(BNX2X_MSG_IOV, "Got VF FLR notification abs_vfid=%d\n",
  1955. abs_vfid);
  1956. goto get_vf;
  1957. case EVENT_RING_OPCODE_MALICIOUS_VF:
  1958. abs_vfid = elem->message.data.malicious_vf_event.vf_id;
  1959. DP(BNX2X_MSG_IOV, "Got VF MALICIOUS notification abs_vfid=%d err_id=0x%x\n",
  1960. abs_vfid, elem->message.data.malicious_vf_event.err_id);
  1961. goto get_vf;
  1962. default:
  1963. return 1;
  1964. }
  1965. /* check if the cid is the VF range */
  1966. if (!bnx2x_iov_is_vf_cid(bp, cid)) {
  1967. DP(BNX2X_MSG_IOV, "cid is outside vf range: %d\n", cid);
  1968. return 1;
  1969. }
  1970. /* extract vf and rxq index from vf_cid - relies on the following:
  1971. * 1. vfid on cid reflects the true abs_vfid
  1972. * 2. The max number of VFs (per path) is 64
  1973. */
  1974. qidx = cid & ((1 << BNX2X_VF_CID_WND)-1);
  1975. abs_vfid = (cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1);
  1976. get_vf:
  1977. vf = bnx2x_vf_by_abs_fid(bp, abs_vfid);
  1978. if (!vf) {
  1979. BNX2X_ERR("EQ completion for unknown VF, cid %d, abs_vfid %d\n",
  1980. cid, abs_vfid);
  1981. return 0;
  1982. }
  1983. switch (opcode) {
  1984. case EVENT_RING_OPCODE_CFC_DEL:
  1985. DP(BNX2X_MSG_IOV, "got VF [%d:%d] cfc delete ramrod\n",
  1986. vf->abs_vfid, qidx);
  1987. vfq_get(vf, qidx)->sp_obj.complete_cmd(bp,
  1988. &vfq_get(vf,
  1989. qidx)->sp_obj,
  1990. BNX2X_Q_CMD_CFC_DEL);
  1991. break;
  1992. case EVENT_RING_OPCODE_CLASSIFICATION_RULES:
  1993. DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mac/vlan ramrod\n",
  1994. vf->abs_vfid, qidx);
  1995. bnx2x_vf_handle_classification_eqe(bp, vfq_get(vf, qidx), elem);
  1996. break;
  1997. case EVENT_RING_OPCODE_MULTICAST_RULES:
  1998. DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mcast ramrod\n",
  1999. vf->abs_vfid, qidx);
  2000. bnx2x_vf_handle_mcast_eqe(bp, vf);
  2001. break;
  2002. case EVENT_RING_OPCODE_FILTERS_RULES:
  2003. DP(BNX2X_MSG_IOV, "got VF [%d:%d] set rx-mode ramrod\n",
  2004. vf->abs_vfid, qidx);
  2005. bnx2x_vf_handle_filters_eqe(bp, vf);
  2006. break;
  2007. case EVENT_RING_OPCODE_VF_FLR:
  2008. DP(BNX2X_MSG_IOV, "got VF [%d] FLR notification\n",
  2009. vf->abs_vfid);
  2010. /* Do nothing for now */
  2011. break;
  2012. case EVENT_RING_OPCODE_MALICIOUS_VF:
  2013. DP(BNX2X_MSG_IOV, "Got VF MALICIOUS notification abs_vfid=%d error id %x\n",
  2014. abs_vfid, elem->message.data.malicious_vf_event.err_id);
  2015. /* Do nothing for now */
  2016. break;
  2017. }
  2018. /* SRIOV: reschedule any 'in_progress' operations */
  2019. bnx2x_iov_sp_event(bp, cid, false);
  2020. return 0;
  2021. }
  2022. static struct bnx2x_virtf *bnx2x_vf_by_cid(struct bnx2x *bp, int vf_cid)
  2023. {
  2024. /* extract the vf from vf_cid - relies on the following:
  2025. * 1. vfid on cid reflects the true abs_vfid
  2026. * 2. The max number of VFs (per path) is 64
  2027. */
  2028. int abs_vfid = (vf_cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1);
  2029. return bnx2x_vf_by_abs_fid(bp, abs_vfid);
  2030. }
  2031. void bnx2x_iov_set_queue_sp_obj(struct bnx2x *bp, int vf_cid,
  2032. struct bnx2x_queue_sp_obj **q_obj)
  2033. {
  2034. struct bnx2x_virtf *vf;
  2035. if (!IS_SRIOV(bp))
  2036. return;
  2037. vf = bnx2x_vf_by_cid(bp, vf_cid);
  2038. if (vf) {
  2039. /* extract queue index from vf_cid - relies on the following:
  2040. * 1. vfid on cid reflects the true abs_vfid
  2041. * 2. The max number of VFs (per path) is 64
  2042. */
  2043. int q_index = vf_cid & ((1 << BNX2X_VF_CID_WND)-1);
  2044. *q_obj = &bnx2x_vfq(vf, q_index, sp_obj);
  2045. } else {
  2046. BNX2X_ERR("No vf matching cid %d\n", vf_cid);
  2047. }
  2048. }
  2049. void bnx2x_iov_sp_event(struct bnx2x *bp, int vf_cid, bool queue_work)
  2050. {
  2051. struct bnx2x_virtf *vf;
  2052. /* check if the cid is the VF range */
  2053. if (!IS_SRIOV(bp) || !bnx2x_iov_is_vf_cid(bp, vf_cid))
  2054. return;
  2055. vf = bnx2x_vf_by_cid(bp, vf_cid);
  2056. if (vf) {
  2057. /* set in_progress flag */
  2058. atomic_set(&vf->op_in_progress, 1);
  2059. if (queue_work)
  2060. queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
  2061. }
  2062. }
  2063. void bnx2x_iov_adjust_stats_req(struct bnx2x *bp)
  2064. {
  2065. int i;
  2066. int first_queue_query_index, num_queues_req;
  2067. dma_addr_t cur_data_offset;
  2068. struct stats_query_entry *cur_query_entry;
  2069. u8 stats_count = 0;
  2070. bool is_fcoe = false;
  2071. if (!IS_SRIOV(bp))
  2072. return;
  2073. if (!NO_FCOE(bp))
  2074. is_fcoe = true;
  2075. /* fcoe adds one global request and one queue request */
  2076. num_queues_req = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe;
  2077. first_queue_query_index = BNX2X_FIRST_QUEUE_QUERY_IDX -
  2078. (is_fcoe ? 0 : 1);
  2079. DP(BNX2X_MSG_IOV,
  2080. "BNX2X_NUM_ETH_QUEUES %d, is_fcoe %d, first_queue_query_index %d => determined the last non virtual statistics query index is %d. Will add queries on top of that\n",
  2081. BNX2X_NUM_ETH_QUEUES(bp), is_fcoe, first_queue_query_index,
  2082. first_queue_query_index + num_queues_req);
  2083. cur_data_offset = bp->fw_stats_data_mapping +
  2084. offsetof(struct bnx2x_fw_stats_data, queue_stats) +
  2085. num_queues_req * sizeof(struct per_queue_stats);
  2086. cur_query_entry = &bp->fw_stats_req->
  2087. query[first_queue_query_index + num_queues_req];
  2088. for_each_vf(bp, i) {
  2089. int j;
  2090. struct bnx2x_virtf *vf = BP_VF(bp, i);
  2091. if (vf->state != VF_ENABLED) {
  2092. DP(BNX2X_MSG_IOV,
  2093. "vf %d not enabled so no stats for it\n",
  2094. vf->abs_vfid);
  2095. continue;
  2096. }
  2097. DP(BNX2X_MSG_IOV, "add addresses for vf %d\n", vf->abs_vfid);
  2098. for_each_vfq(vf, j) {
  2099. struct bnx2x_vf_queue *rxq = vfq_get(vf, j);
  2100. dma_addr_t q_stats_addr =
  2101. vf->fw_stat_map + j * vf->stats_stride;
  2102. /* collect stats fro active queues only */
  2103. if (bnx2x_get_q_logical_state(bp, &rxq->sp_obj) ==
  2104. BNX2X_Q_LOGICAL_STATE_STOPPED)
  2105. continue;
  2106. /* create stats query entry for this queue */
  2107. cur_query_entry->kind = STATS_TYPE_QUEUE;
  2108. cur_query_entry->index = vfq_stat_id(vf, rxq);
  2109. cur_query_entry->funcID =
  2110. cpu_to_le16(FW_VF_HANDLE(vf->abs_vfid));
  2111. cur_query_entry->address.hi =
  2112. cpu_to_le32(U64_HI(q_stats_addr));
  2113. cur_query_entry->address.lo =
  2114. cpu_to_le32(U64_LO(q_stats_addr));
  2115. DP(BNX2X_MSG_IOV,
  2116. "added address %x %x for vf %d queue %d client %d\n",
  2117. cur_query_entry->address.hi,
  2118. cur_query_entry->address.lo, cur_query_entry->funcID,
  2119. j, cur_query_entry->index);
  2120. cur_query_entry++;
  2121. cur_data_offset += sizeof(struct per_queue_stats);
  2122. stats_count++;
  2123. /* all stats are coalesced to the leading queue */
  2124. if (vf->cfg_flags & VF_CFG_STATS_COALESCE)
  2125. break;
  2126. }
  2127. }
  2128. bp->fw_stats_req->hdr.cmd_num = bp->fw_stats_num + stats_count;
  2129. }
  2130. void bnx2x_iov_sp_task(struct bnx2x *bp)
  2131. {
  2132. int i;
  2133. if (!IS_SRIOV(bp))
  2134. return;
  2135. /* Iterate over all VFs and invoke state transition for VFs with
  2136. * 'in-progress' slow-path operations
  2137. */
  2138. DP(BNX2X_MSG_IOV, "searching for pending vf operations\n");
  2139. for_each_vf(bp, i) {
  2140. struct bnx2x_virtf *vf = BP_VF(bp, i);
  2141. if (!vf) {
  2142. BNX2X_ERR("VF was null! skipping...\n");
  2143. continue;
  2144. }
  2145. if (!list_empty(&vf->op_list_head) &&
  2146. atomic_read(&vf->op_in_progress)) {
  2147. DP(BNX2X_MSG_IOV, "running pending op for vf %d\n", i);
  2148. bnx2x_vfop_cur(bp, vf)->transition(bp, vf);
  2149. }
  2150. }
  2151. }
  2152. static inline
  2153. struct bnx2x_virtf *__vf_from_stat_id(struct bnx2x *bp, u8 stat_id)
  2154. {
  2155. int i;
  2156. struct bnx2x_virtf *vf = NULL;
  2157. for_each_vf(bp, i) {
  2158. vf = BP_VF(bp, i);
  2159. if (stat_id >= vf->igu_base_id &&
  2160. stat_id < vf->igu_base_id + vf_sb_count(vf))
  2161. break;
  2162. }
  2163. return vf;
  2164. }
  2165. /* VF API helpers */
  2166. static void bnx2x_vf_qtbl_set_q(struct bnx2x *bp, u8 abs_vfid, u8 qid,
  2167. u8 enable)
  2168. {
  2169. u32 reg = PXP_REG_HST_ZONE_PERMISSION_TABLE + qid * 4;
  2170. u32 val = enable ? (abs_vfid | (1 << 6)) : 0;
  2171. REG_WR(bp, reg, val);
  2172. }
  2173. static void bnx2x_vf_clr_qtbl(struct bnx2x *bp, struct bnx2x_virtf *vf)
  2174. {
  2175. int i;
  2176. for_each_vfq(vf, i)
  2177. bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid,
  2178. vfq_qzone_id(vf, vfq_get(vf, i)), false);
  2179. }
  2180. static void bnx2x_vf_igu_disable(struct bnx2x *bp, struct bnx2x_virtf *vf)
  2181. {
  2182. u32 val;
  2183. /* clear the VF configuration - pretend */
  2184. bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid));
  2185. val = REG_RD(bp, IGU_REG_VF_CONFIGURATION);
  2186. val &= ~(IGU_VF_CONF_MSI_MSIX_EN | IGU_VF_CONF_SINGLE_ISR_EN |
  2187. IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_PARENT_MASK);
  2188. REG_WR(bp, IGU_REG_VF_CONFIGURATION, val);
  2189. bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
  2190. }
  2191. u8 bnx2x_vf_max_queue_cnt(struct bnx2x *bp, struct bnx2x_virtf *vf)
  2192. {
  2193. return min_t(u8, min_t(u8, vf_sb_count(vf), BNX2X_CIDS_PER_VF),
  2194. BNX2X_VF_MAX_QUEUES);
  2195. }
  2196. static
  2197. int bnx2x_vf_chk_avail_resc(struct bnx2x *bp, struct bnx2x_virtf *vf,
  2198. struct vf_pf_resc_request *req_resc)
  2199. {
  2200. u8 rxq_cnt = vf_rxq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf);
  2201. u8 txq_cnt = vf_txq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf);
  2202. return ((req_resc->num_rxqs <= rxq_cnt) &&
  2203. (req_resc->num_txqs <= txq_cnt) &&
  2204. (req_resc->num_sbs <= vf_sb_count(vf)) &&
  2205. (req_resc->num_mac_filters <= vf_mac_rules_cnt(vf)) &&
  2206. (req_resc->num_vlan_filters <= vf_vlan_rules_cnt(vf)));
  2207. }
  2208. /* CORE VF API */
  2209. int bnx2x_vf_acquire(struct bnx2x *bp, struct bnx2x_virtf *vf,
  2210. struct vf_pf_resc_request *resc)
  2211. {
  2212. int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vf->index) *
  2213. BNX2X_CIDS_PER_VF;
  2214. union cdu_context *base_cxt = (union cdu_context *)
  2215. BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr +
  2216. (base_vf_cid & (ILT_PAGE_CIDS-1));
  2217. int i;
  2218. /* if state is 'acquired' the VF was not released or FLR'd, in
  2219. * this case the returned resources match the acquired already
  2220. * acquired resources. Verify that the requested numbers do
  2221. * not exceed the already acquired numbers.
  2222. */
  2223. if (vf->state == VF_ACQUIRED) {
  2224. DP(BNX2X_MSG_IOV, "VF[%d] Trying to re-acquire resources (VF was not released or FLR'd)\n",
  2225. vf->abs_vfid);
  2226. if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) {
  2227. BNX2X_ERR("VF[%d] When re-acquiring resources, requested numbers must be <= then previously acquired numbers\n",
  2228. vf->abs_vfid);
  2229. return -EINVAL;
  2230. }
  2231. return 0;
  2232. }
  2233. /* Otherwise vf state must be 'free' or 'reset' */
  2234. if (vf->state != VF_FREE && vf->state != VF_RESET) {
  2235. BNX2X_ERR("VF[%d] Can not acquire a VF with state %d\n",
  2236. vf->abs_vfid, vf->state);
  2237. return -EINVAL;
  2238. }
  2239. /* static allocation:
  2240. * the global maximum number are fixed per VF. Fail the request if
  2241. * requested number exceed these globals
  2242. */
  2243. if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) {
  2244. DP(BNX2X_MSG_IOV,
  2245. "cannot fulfill vf resource request. Placing maximal available values in response\n");
  2246. /* set the max resource in the vf */
  2247. return -ENOMEM;
  2248. }
  2249. /* Set resources counters - 0 request means max available */
  2250. vf_sb_count(vf) = resc->num_sbs;
  2251. vf_rxq_count(vf) = resc->num_rxqs ? : bnx2x_vf_max_queue_cnt(bp, vf);
  2252. vf_txq_count(vf) = resc->num_txqs ? : bnx2x_vf_max_queue_cnt(bp, vf);
  2253. if (resc->num_mac_filters)
  2254. vf_mac_rules_cnt(vf) = resc->num_mac_filters;
  2255. if (resc->num_vlan_filters)
  2256. vf_vlan_rules_cnt(vf) = resc->num_vlan_filters;
  2257. DP(BNX2X_MSG_IOV,
  2258. "Fulfilling vf request: sb count %d, tx_count %d, rx_count %d, mac_rules_count %d, vlan_rules_count %d\n",
  2259. vf_sb_count(vf), vf_rxq_count(vf),
  2260. vf_txq_count(vf), vf_mac_rules_cnt(vf),
  2261. vf_vlan_rules_cnt(vf));
  2262. /* Initialize the queues */
  2263. if (!vf->vfqs) {
  2264. DP(BNX2X_MSG_IOV, "vf->vfqs was not allocated\n");
  2265. return -EINVAL;
  2266. }
  2267. for_each_vfq(vf, i) {
  2268. struct bnx2x_vf_queue *q = vfq_get(vf, i);
  2269. if (!q) {
  2270. BNX2X_ERR("q number %d was not allocated\n", i);
  2271. return -EINVAL;
  2272. }
  2273. q->index = i;
  2274. q->cxt = &((base_cxt + i)->eth);
  2275. q->cid = BNX2X_FIRST_VF_CID + base_vf_cid + i;
  2276. DP(BNX2X_MSG_IOV, "VFQ[%d:%d]: index %d, cid 0x%x, cxt %p\n",
  2277. vf->abs_vfid, i, q->index, q->cid, q->cxt);
  2278. /* init SP objects */
  2279. bnx2x_vfq_init(bp, vf, q);
  2280. }
  2281. vf->state = VF_ACQUIRED;
  2282. return 0;
  2283. }
  2284. int bnx2x_vf_init(struct bnx2x *bp, struct bnx2x_virtf *vf, dma_addr_t *sb_map)
  2285. {
  2286. struct bnx2x_func_init_params func_init = {0};
  2287. u16 flags = 0;
  2288. int i;
  2289. /* the sb resources are initialized at this point, do the
  2290. * FW/HW initializations
  2291. */
  2292. for_each_vf_sb(vf, i)
  2293. bnx2x_init_sb(bp, (dma_addr_t)sb_map[i], vf->abs_vfid, true,
  2294. vf_igu_sb(vf, i), vf_igu_sb(vf, i));
  2295. /* Sanity checks */
  2296. if (vf->state != VF_ACQUIRED) {
  2297. DP(BNX2X_MSG_IOV, "VF[%d] is not in VF_ACQUIRED, but %d\n",
  2298. vf->abs_vfid, vf->state);
  2299. return -EINVAL;
  2300. }
  2301. /* let FLR complete ... */
  2302. msleep(100);
  2303. /* FLR cleanup epilogue */
  2304. if (bnx2x_vf_flr_clnup_epilog(bp, vf->abs_vfid))
  2305. return -EBUSY;
  2306. /* reset IGU VF statistics: MSIX */
  2307. REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + vf->abs_vfid * 4 , 0);
  2308. /* vf init */
  2309. if (vf->cfg_flags & VF_CFG_STATS)
  2310. flags |= (FUNC_FLG_STATS | FUNC_FLG_SPQ);
  2311. if (vf->cfg_flags & VF_CFG_TPA)
  2312. flags |= FUNC_FLG_TPA;
  2313. if (is_vf_multi(vf))
  2314. flags |= FUNC_FLG_RSS;
  2315. /* function setup */
  2316. func_init.func_flgs = flags;
  2317. func_init.pf_id = BP_FUNC(bp);
  2318. func_init.func_id = FW_VF_HANDLE(vf->abs_vfid);
  2319. func_init.fw_stat_map = vf->fw_stat_map;
  2320. func_init.spq_map = vf->spq_map;
  2321. func_init.spq_prod = 0;
  2322. bnx2x_func_init(bp, &func_init);
  2323. /* Enable the vf */
  2324. bnx2x_vf_enable_access(bp, vf->abs_vfid);
  2325. bnx2x_vf_enable_traffic(bp, vf);
  2326. /* queue protection table */
  2327. for_each_vfq(vf, i)
  2328. bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid,
  2329. vfq_qzone_id(vf, vfq_get(vf, i)), true);
  2330. vf->state = VF_ENABLED;
  2331. /* update vf bulletin board */
  2332. bnx2x_post_vf_bulletin(bp, vf->index);
  2333. return 0;
  2334. }
  2335. struct set_vf_state_cookie {
  2336. struct bnx2x_virtf *vf;
  2337. u8 state;
  2338. };
  2339. void bnx2x_set_vf_state(void *cookie)
  2340. {
  2341. struct set_vf_state_cookie *p = (struct set_vf_state_cookie *)cookie;
  2342. p->vf->state = p->state;
  2343. }
  2344. /* VFOP close (teardown the queues, delete mcasts and close HW) */
  2345. static void bnx2x_vfop_close(struct bnx2x *bp, struct bnx2x_virtf *vf)
  2346. {
  2347. struct bnx2x_vfop *vfop = bnx2x_vfop_cur(bp, vf);
  2348. struct bnx2x_vfop_args_qx *qx = &vfop->args.qx;
  2349. enum bnx2x_vfop_close_state state = vfop->state;
  2350. struct bnx2x_vfop_cmd cmd = {
  2351. .done = bnx2x_vfop_close,
  2352. .block = false,
  2353. };
  2354. if (vfop->rc < 0)
  2355. goto op_err;
  2356. DP(BNX2X_MSG_IOV, "vf[%d] STATE: %d\n", vf->abs_vfid, state);
  2357. switch (state) {
  2358. case BNX2X_VFOP_CLOSE_QUEUES:
  2359. if (++(qx->qid) < vf_rxq_count(vf)) {
  2360. vfop->rc = bnx2x_vfop_qdown_cmd(bp, vf, &cmd, qx->qid);
  2361. if (vfop->rc)
  2362. goto op_err;
  2363. return;
  2364. }
  2365. /* remove multicasts */
  2366. vfop->state = BNX2X_VFOP_CLOSE_HW;
  2367. vfop->rc = bnx2x_vfop_mcast_cmd(bp, vf, &cmd, NULL, 0, false);
  2368. if (vfop->rc)
  2369. goto op_err;
  2370. return;
  2371. case BNX2X_VFOP_CLOSE_HW:
  2372. /* disable the interrupts */
  2373. DP(BNX2X_MSG_IOV, "disabling igu\n");
  2374. bnx2x_vf_igu_disable(bp, vf);
  2375. /* disable the VF */
  2376. DP(BNX2X_MSG_IOV, "clearing qtbl\n");
  2377. bnx2x_vf_clr_qtbl(bp, vf);
  2378. goto op_done;
  2379. default:
  2380. bnx2x_vfop_default(state);
  2381. }
  2382. op_err:
  2383. BNX2X_ERR("VF[%d] CLOSE error: rc %d\n", vf->abs_vfid, vfop->rc);
  2384. op_done:
  2385. /* need to make sure there are no outstanding stats ramrods which may
  2386. * cause the device to access the VF's stats buffer which it will free
  2387. * as soon as we return from the close flow.
  2388. */
  2389. {
  2390. struct set_vf_state_cookie cookie;
  2391. cookie.vf = vf;
  2392. cookie.state = VF_ACQUIRED;
  2393. bnx2x_stats_safe_exec(bp, bnx2x_set_vf_state, &cookie);
  2394. }
  2395. DP(BNX2X_MSG_IOV, "set state to acquired\n");
  2396. bnx2x_vfop_end(bp, vf, vfop);
  2397. }
  2398. int bnx2x_vfop_close_cmd(struct bnx2x *bp,
  2399. struct bnx2x_virtf *vf,
  2400. struct bnx2x_vfop_cmd *cmd)
  2401. {
  2402. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  2403. if (vfop) {
  2404. vfop->args.qx.qid = -1; /* loop */
  2405. bnx2x_vfop_opset(BNX2X_VFOP_CLOSE_QUEUES,
  2406. bnx2x_vfop_close, cmd->done);
  2407. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_close,
  2408. cmd->block);
  2409. }
  2410. return -ENOMEM;
  2411. }
  2412. /* VF release can be called either: 1. The VF was acquired but
  2413. * not enabled 2. the vf was enabled or in the process of being
  2414. * enabled
  2415. */
  2416. static void bnx2x_vfop_release(struct bnx2x *bp, struct bnx2x_virtf *vf)
  2417. {
  2418. struct bnx2x_vfop *vfop = bnx2x_vfop_cur(bp, vf);
  2419. struct bnx2x_vfop_cmd cmd = {
  2420. .done = bnx2x_vfop_release,
  2421. .block = false,
  2422. };
  2423. DP(BNX2X_MSG_IOV, "vfop->rc %d\n", vfop->rc);
  2424. if (vfop->rc < 0)
  2425. goto op_err;
  2426. DP(BNX2X_MSG_IOV, "VF[%d] STATE: %s\n", vf->abs_vfid,
  2427. vf->state == VF_FREE ? "Free" :
  2428. vf->state == VF_ACQUIRED ? "Acquired" :
  2429. vf->state == VF_ENABLED ? "Enabled" :
  2430. vf->state == VF_RESET ? "Reset" :
  2431. "Unknown");
  2432. switch (vf->state) {
  2433. case VF_ENABLED:
  2434. vfop->rc = bnx2x_vfop_close_cmd(bp, vf, &cmd);
  2435. if (vfop->rc)
  2436. goto op_err;
  2437. return;
  2438. case VF_ACQUIRED:
  2439. DP(BNX2X_MSG_IOV, "about to free resources\n");
  2440. bnx2x_vf_free_resc(bp, vf);
  2441. DP(BNX2X_MSG_IOV, "vfop->rc %d\n", vfop->rc);
  2442. goto op_done;
  2443. case VF_FREE:
  2444. case VF_RESET:
  2445. /* do nothing */
  2446. goto op_done;
  2447. default:
  2448. bnx2x_vfop_default(vf->state);
  2449. }
  2450. op_err:
  2451. BNX2X_ERR("VF[%d] RELEASE error: rc %d\n", vf->abs_vfid, vfop->rc);
  2452. op_done:
  2453. bnx2x_vfop_end(bp, vf, vfop);
  2454. }
  2455. static void bnx2x_vfop_rss(struct bnx2x *bp, struct bnx2x_virtf *vf)
  2456. {
  2457. struct bnx2x_vfop *vfop = bnx2x_vfop_cur(bp, vf);
  2458. enum bnx2x_vfop_rss_state state;
  2459. if (!vfop) {
  2460. BNX2X_ERR("vfop was null\n");
  2461. return;
  2462. }
  2463. state = vfop->state;
  2464. bnx2x_vfop_reset_wq(vf);
  2465. if (vfop->rc < 0)
  2466. goto op_err;
  2467. DP(BNX2X_MSG_IOV, "vf[%d] STATE: %d\n", vf->abs_vfid, state);
  2468. switch (state) {
  2469. case BNX2X_VFOP_RSS_CONFIG:
  2470. /* next state */
  2471. vfop->state = BNX2X_VFOP_RSS_DONE;
  2472. bnx2x_config_rss(bp, &vfop->op_p->rss);
  2473. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_DONE);
  2474. op_err:
  2475. BNX2X_ERR("RSS error: rc %d\n", vfop->rc);
  2476. op_done:
  2477. case BNX2X_VFOP_RSS_DONE:
  2478. bnx2x_vfop_end(bp, vf, vfop);
  2479. return;
  2480. default:
  2481. bnx2x_vfop_default(state);
  2482. }
  2483. op_pending:
  2484. return;
  2485. }
  2486. int bnx2x_vfop_release_cmd(struct bnx2x *bp,
  2487. struct bnx2x_virtf *vf,
  2488. struct bnx2x_vfop_cmd *cmd)
  2489. {
  2490. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  2491. if (vfop) {
  2492. bnx2x_vfop_opset(-1, /* use vf->state */
  2493. bnx2x_vfop_release, cmd->done);
  2494. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_release,
  2495. cmd->block);
  2496. }
  2497. return -ENOMEM;
  2498. }
  2499. int bnx2x_vfop_rss_cmd(struct bnx2x *bp,
  2500. struct bnx2x_virtf *vf,
  2501. struct bnx2x_vfop_cmd *cmd)
  2502. {
  2503. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  2504. if (vfop) {
  2505. bnx2x_vfop_opset(BNX2X_VFOP_RSS_CONFIG, bnx2x_vfop_rss,
  2506. cmd->done);
  2507. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_rss,
  2508. cmd->block);
  2509. }
  2510. return -ENOMEM;
  2511. }
  2512. /* VF release ~ VF close + VF release-resources
  2513. * Release is the ultimate SW shutdown and is called whenever an
  2514. * irrecoverable error is encountered.
  2515. */
  2516. void bnx2x_vf_release(struct bnx2x *bp, struct bnx2x_virtf *vf, bool block)
  2517. {
  2518. struct bnx2x_vfop_cmd cmd = {
  2519. .done = NULL,
  2520. .block = block,
  2521. };
  2522. int rc;
  2523. DP(BNX2X_MSG_IOV, "PF releasing vf %d\n", vf->abs_vfid);
  2524. bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_RELEASE_VF);
  2525. rc = bnx2x_vfop_release_cmd(bp, vf, &cmd);
  2526. if (rc)
  2527. WARN(rc,
  2528. "VF[%d] Failed to allocate resources for release op- rc=%d\n",
  2529. vf->abs_vfid, rc);
  2530. }
  2531. static inline void bnx2x_vf_get_sbdf(struct bnx2x *bp,
  2532. struct bnx2x_virtf *vf, u32 *sbdf)
  2533. {
  2534. *sbdf = vf->devfn | (vf->bus << 8);
  2535. }
  2536. static inline void bnx2x_vf_get_bars(struct bnx2x *bp, struct bnx2x_virtf *vf,
  2537. struct bnx2x_vf_bar_info *bar_info)
  2538. {
  2539. int n;
  2540. bar_info->nr_bars = bp->vfdb->sriov.nres;
  2541. for (n = 0; n < bar_info->nr_bars; n++)
  2542. bar_info->bars[n] = vf->bars[n];
  2543. }
  2544. void bnx2x_lock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf,
  2545. enum channel_tlvs tlv)
  2546. {
  2547. /* we don't lock the channel for unsupported tlvs */
  2548. if (!bnx2x_tlv_supported(tlv)) {
  2549. BNX2X_ERR("attempting to lock with unsupported tlv. Aborting\n");
  2550. return;
  2551. }
  2552. /* lock the channel */
  2553. mutex_lock(&vf->op_mutex);
  2554. /* record the locking op */
  2555. vf->op_current = tlv;
  2556. /* log the lock */
  2557. DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel locked by %d\n",
  2558. vf->abs_vfid, tlv);
  2559. }
  2560. void bnx2x_unlock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf,
  2561. enum channel_tlvs expected_tlv)
  2562. {
  2563. enum channel_tlvs current_tlv;
  2564. if (!vf) {
  2565. BNX2X_ERR("VF was %p\n", vf);
  2566. return;
  2567. }
  2568. current_tlv = vf->op_current;
  2569. /* we don't unlock the channel for unsupported tlvs */
  2570. if (!bnx2x_tlv_supported(expected_tlv))
  2571. return;
  2572. WARN(expected_tlv != vf->op_current,
  2573. "lock mismatch: expected %d found %d", expected_tlv,
  2574. vf->op_current);
  2575. /* record the locking op */
  2576. vf->op_current = CHANNEL_TLV_NONE;
  2577. /* lock the channel */
  2578. mutex_unlock(&vf->op_mutex);
  2579. /* log the unlock */
  2580. DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel unlocked by %d\n",
  2581. vf->abs_vfid, vf->op_current);
  2582. }
  2583. int bnx2x_sriov_configure(struct pci_dev *dev, int num_vfs_param)
  2584. {
  2585. struct bnx2x *bp = netdev_priv(pci_get_drvdata(dev));
  2586. DP(BNX2X_MSG_IOV, "bnx2x_sriov_configure called with %d, BNX2X_NR_VIRTFN(bp) was %d\n",
  2587. num_vfs_param, BNX2X_NR_VIRTFN(bp));
  2588. /* HW channel is only operational when PF is up */
  2589. if (bp->state != BNX2X_STATE_OPEN) {
  2590. BNX2X_ERR("VF num configuration via sysfs not supported while PF is down\n");
  2591. return -EINVAL;
  2592. }
  2593. /* we are always bound by the total_vfs in the configuration space */
  2594. if (num_vfs_param > BNX2X_NR_VIRTFN(bp)) {
  2595. BNX2X_ERR("truncating requested number of VFs (%d) down to maximum allowed (%d)\n",
  2596. num_vfs_param, BNX2X_NR_VIRTFN(bp));
  2597. num_vfs_param = BNX2X_NR_VIRTFN(bp);
  2598. }
  2599. bp->requested_nr_virtfn = num_vfs_param;
  2600. if (num_vfs_param == 0) {
  2601. pci_disable_sriov(dev);
  2602. return 0;
  2603. } else {
  2604. return bnx2x_enable_sriov(bp);
  2605. }
  2606. }
  2607. #define IGU_ENTRY_SIZE 4
  2608. int bnx2x_enable_sriov(struct bnx2x *bp)
  2609. {
  2610. int rc = 0, req_vfs = bp->requested_nr_virtfn;
  2611. int vf_idx, sb_idx, vfq_idx, qcount, first_vf;
  2612. u32 igu_entry, address;
  2613. u16 num_vf_queues;
  2614. if (req_vfs == 0)
  2615. return 0;
  2616. first_vf = bp->vfdb->sriov.first_vf_in_pf;
  2617. /* statically distribute vf sb pool between VFs */
  2618. num_vf_queues = min_t(u16, BNX2X_VF_MAX_QUEUES,
  2619. BP_VFDB(bp)->vf_sbs_pool / req_vfs);
  2620. /* zero previous values learned from igu cam */
  2621. for (vf_idx = 0; vf_idx < req_vfs; vf_idx++) {
  2622. struct bnx2x_virtf *vf = BP_VF(bp, vf_idx);
  2623. vf->sb_count = 0;
  2624. vf_sb_count(BP_VF(bp, vf_idx)) = 0;
  2625. }
  2626. bp->vfdb->vf_sbs_pool = 0;
  2627. /* prepare IGU cam */
  2628. sb_idx = BP_VFDB(bp)->first_vf_igu_entry;
  2629. address = IGU_REG_MAPPING_MEMORY + sb_idx * IGU_ENTRY_SIZE;
  2630. for (vf_idx = first_vf; vf_idx < first_vf + req_vfs; vf_idx++) {
  2631. for (vfq_idx = 0; vfq_idx < num_vf_queues; vfq_idx++) {
  2632. igu_entry = vf_idx << IGU_REG_MAPPING_MEMORY_FID_SHIFT |
  2633. vfq_idx << IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT |
  2634. IGU_REG_MAPPING_MEMORY_VALID;
  2635. DP(BNX2X_MSG_IOV, "assigning sb %d to vf %d\n",
  2636. sb_idx, vf_idx);
  2637. REG_WR(bp, address, igu_entry);
  2638. sb_idx++;
  2639. address += IGU_ENTRY_SIZE;
  2640. }
  2641. }
  2642. /* Reinitialize vf database according to igu cam */
  2643. bnx2x_get_vf_igu_cam_info(bp);
  2644. DP(BNX2X_MSG_IOV, "vf_sbs_pool %d, num_vf_queues %d\n",
  2645. BP_VFDB(bp)->vf_sbs_pool, num_vf_queues);
  2646. qcount = 0;
  2647. for_each_vf(bp, vf_idx) {
  2648. struct bnx2x_virtf *vf = BP_VF(bp, vf_idx);
  2649. /* set local queue arrays */
  2650. vf->vfqs = &bp->vfdb->vfqs[qcount];
  2651. qcount += vf_sb_count(vf);
  2652. }
  2653. /* prepare msix vectors in VF configuration space */
  2654. for (vf_idx = first_vf; vf_idx < first_vf + req_vfs; vf_idx++) {
  2655. bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf_idx));
  2656. REG_WR(bp, PCICFG_OFFSET + GRC_CONFIG_REG_VF_MSIX_CONTROL,
  2657. num_vf_queues);
  2658. }
  2659. bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
  2660. /* enable sriov. This will probe all the VFs, and consequentially cause
  2661. * the "acquire" messages to appear on the VF PF channel.
  2662. */
  2663. DP(BNX2X_MSG_IOV, "about to call enable sriov\n");
  2664. pci_disable_sriov(bp->pdev);
  2665. rc = pci_enable_sriov(bp->pdev, req_vfs);
  2666. if (rc) {
  2667. BNX2X_ERR("pci_enable_sriov failed with %d\n", rc);
  2668. return rc;
  2669. }
  2670. DP(BNX2X_MSG_IOV, "sriov enabled (%d vfs)\n", req_vfs);
  2671. return req_vfs;
  2672. }
  2673. void bnx2x_pf_set_vfs_vlan(struct bnx2x *bp)
  2674. {
  2675. int vfidx;
  2676. struct pf_vf_bulletin_content *bulletin;
  2677. DP(BNX2X_MSG_IOV, "configuring vlan for VFs from sp-task\n");
  2678. for_each_vf(bp, vfidx) {
  2679. bulletin = BP_VF_BULLETIN(bp, vfidx);
  2680. if (BP_VF(bp, vfidx)->cfg_flags & VF_CFG_VLAN)
  2681. bnx2x_set_vf_vlan(bp->dev, vfidx, bulletin->vlan, 0);
  2682. }
  2683. }
  2684. void bnx2x_disable_sriov(struct bnx2x *bp)
  2685. {
  2686. pci_disable_sriov(bp->pdev);
  2687. }
  2688. int bnx2x_vf_ndo_prep(struct bnx2x *bp, int vfidx, struct bnx2x_virtf **vf,
  2689. struct pf_vf_bulletin_content **bulletin)
  2690. {
  2691. if (bp->state != BNX2X_STATE_OPEN) {
  2692. BNX2X_ERR("vf ndo called though PF is down\n");
  2693. return -EINVAL;
  2694. }
  2695. if (!IS_SRIOV(bp)) {
  2696. BNX2X_ERR("vf ndo called though sriov is disabled\n");
  2697. return -EINVAL;
  2698. }
  2699. if (vfidx >= BNX2X_NR_VIRTFN(bp)) {
  2700. BNX2X_ERR("vf ndo called for uninitialized VF. vfidx was %d BNX2X_NR_VIRTFN was %d\n",
  2701. vfidx, BNX2X_NR_VIRTFN(bp));
  2702. return -EINVAL;
  2703. }
  2704. /* init members */
  2705. *vf = BP_VF(bp, vfidx);
  2706. *bulletin = BP_VF_BULLETIN(bp, vfidx);
  2707. if (!*vf) {
  2708. BNX2X_ERR("vf ndo called but vf struct is null. vfidx was %d\n",
  2709. vfidx);
  2710. return -EINVAL;
  2711. }
  2712. if (!(*vf)->vfqs) {
  2713. BNX2X_ERR("vf ndo called but vfqs struct is null. Was ndo invoked before dynamically enabling SR-IOV? vfidx was %d\n",
  2714. vfidx);
  2715. return -EINVAL;
  2716. }
  2717. if (!*bulletin) {
  2718. BNX2X_ERR("vf ndo called but Bulletin Board struct is null. vfidx was %d\n",
  2719. vfidx);
  2720. return -EINVAL;
  2721. }
  2722. return 0;
  2723. }
  2724. int bnx2x_get_vf_config(struct net_device *dev, int vfidx,
  2725. struct ifla_vf_info *ivi)
  2726. {
  2727. struct bnx2x *bp = netdev_priv(dev);
  2728. struct bnx2x_virtf *vf = NULL;
  2729. struct pf_vf_bulletin_content *bulletin = NULL;
  2730. struct bnx2x_vlan_mac_obj *mac_obj;
  2731. struct bnx2x_vlan_mac_obj *vlan_obj;
  2732. int rc;
  2733. /* sanity and init */
  2734. rc = bnx2x_vf_ndo_prep(bp, vfidx, &vf, &bulletin);
  2735. if (rc)
  2736. return rc;
  2737. mac_obj = &bnx2x_leading_vfq(vf, mac_obj);
  2738. vlan_obj = &bnx2x_leading_vfq(vf, vlan_obj);
  2739. if (!mac_obj || !vlan_obj) {
  2740. BNX2X_ERR("VF partially initialized\n");
  2741. return -EINVAL;
  2742. }
  2743. ivi->vf = vfidx;
  2744. ivi->qos = 0;
  2745. ivi->tx_rate = 10000; /* always 10G. TBA take from link struct */
  2746. ivi->spoofchk = 1; /*always enabled */
  2747. if (vf->state == VF_ENABLED) {
  2748. /* mac and vlan are in vlan_mac objects */
  2749. if (validate_vlan_mac(bp, &bnx2x_leading_vfq(vf, mac_obj)))
  2750. mac_obj->get_n_elements(bp, mac_obj, 1, (u8 *)&ivi->mac,
  2751. 0, ETH_ALEN);
  2752. if (validate_vlan_mac(bp, &bnx2x_leading_vfq(vf, vlan_obj)))
  2753. vlan_obj->get_n_elements(bp, vlan_obj, 1,
  2754. (u8 *)&ivi->vlan, 0,
  2755. VLAN_HLEN);
  2756. } else {
  2757. /* mac */
  2758. if (bulletin->valid_bitmap & (1 << MAC_ADDR_VALID))
  2759. /* mac configured by ndo so its in bulletin board */
  2760. memcpy(&ivi->mac, bulletin->mac, ETH_ALEN);
  2761. else
  2762. /* function has not been loaded yet. Show mac as 0s */
  2763. memset(&ivi->mac, 0, ETH_ALEN);
  2764. /* vlan */
  2765. if (bulletin->valid_bitmap & (1 << VLAN_VALID))
  2766. /* vlan configured by ndo so its in bulletin board */
  2767. memcpy(&ivi->vlan, &bulletin->vlan, VLAN_HLEN);
  2768. else
  2769. /* function has not been loaded yet. Show vlans as 0s */
  2770. memset(&ivi->vlan, 0, VLAN_HLEN);
  2771. }
  2772. return 0;
  2773. }
  2774. /* New mac for VF. Consider these cases:
  2775. * 1. VF hasn't been acquired yet - save the mac in local bulletin board and
  2776. * supply at acquire.
  2777. * 2. VF has already been acquired but has not yet initialized - store in local
  2778. * bulletin board. mac will be posted on VF bulletin board after VF init. VF
  2779. * will configure this mac when it is ready.
  2780. * 3. VF has already initialized but has not yet setup a queue - post the new
  2781. * mac on VF's bulletin board right now. VF will configure this mac when it
  2782. * is ready.
  2783. * 4. VF has already set a queue - delete any macs already configured for this
  2784. * queue and manually config the new mac.
  2785. * In any event, once this function has been called refuse any attempts by the
  2786. * VF to configure any mac for itself except for this mac. In case of a race
  2787. * where the VF fails to see the new post on its bulletin board before sending a
  2788. * mac configuration request, the PF will simply fail the request and VF can try
  2789. * again after consulting its bulletin board.
  2790. */
  2791. int bnx2x_set_vf_mac(struct net_device *dev, int vfidx, u8 *mac)
  2792. {
  2793. struct bnx2x *bp = netdev_priv(dev);
  2794. int rc, q_logical_state;
  2795. struct bnx2x_virtf *vf = NULL;
  2796. struct pf_vf_bulletin_content *bulletin = NULL;
  2797. /* sanity and init */
  2798. rc = bnx2x_vf_ndo_prep(bp, vfidx, &vf, &bulletin);
  2799. if (rc)
  2800. return rc;
  2801. if (!is_valid_ether_addr(mac)) {
  2802. BNX2X_ERR("mac address invalid\n");
  2803. return -EINVAL;
  2804. }
  2805. /* update PF's copy of the VF's bulletin. Will no longer accept mac
  2806. * configuration requests from vf unless match this mac
  2807. */
  2808. bulletin->valid_bitmap |= 1 << MAC_ADDR_VALID;
  2809. memcpy(bulletin->mac, mac, ETH_ALEN);
  2810. /* Post update on VF's bulletin board */
  2811. rc = bnx2x_post_vf_bulletin(bp, vfidx);
  2812. if (rc) {
  2813. BNX2X_ERR("failed to update VF[%d] bulletin\n", vfidx);
  2814. return rc;
  2815. }
  2816. q_logical_state =
  2817. bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj));
  2818. if (vf->state == VF_ENABLED &&
  2819. q_logical_state == BNX2X_Q_LOGICAL_STATE_ACTIVE) {
  2820. /* configure the mac in device on this vf's queue */
  2821. unsigned long ramrod_flags = 0;
  2822. struct bnx2x_vlan_mac_obj *mac_obj =
  2823. &bnx2x_leading_vfq(vf, mac_obj);
  2824. rc = validate_vlan_mac(bp, &bnx2x_leading_vfq(vf, mac_obj));
  2825. if (rc)
  2826. return rc;
  2827. /* must lock vfpf channel to protect against vf flows */
  2828. bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC);
  2829. /* remove existing eth macs */
  2830. rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_ETH_MAC, true);
  2831. if (rc) {
  2832. BNX2X_ERR("failed to delete eth macs\n");
  2833. return -EINVAL;
  2834. }
  2835. /* remove existing uc list macs */
  2836. rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, true);
  2837. if (rc) {
  2838. BNX2X_ERR("failed to delete uc_list macs\n");
  2839. return -EINVAL;
  2840. }
  2841. /* configure the new mac to device */
  2842. __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
  2843. bnx2x_set_mac_one(bp, (u8 *)&bulletin->mac, mac_obj, true,
  2844. BNX2X_ETH_MAC, &ramrod_flags);
  2845. bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC);
  2846. }
  2847. return 0;
  2848. }
  2849. int bnx2x_set_vf_vlan(struct net_device *dev, int vfidx, u16 vlan, u8 qos)
  2850. {
  2851. struct bnx2x *bp = netdev_priv(dev);
  2852. int rc, q_logical_state;
  2853. struct bnx2x_virtf *vf = NULL;
  2854. struct pf_vf_bulletin_content *bulletin = NULL;
  2855. /* sanity and init */
  2856. rc = bnx2x_vf_ndo_prep(bp, vfidx, &vf, &bulletin);
  2857. if (rc)
  2858. return rc;
  2859. if (vlan > 4095) {
  2860. BNX2X_ERR("illegal vlan value %d\n", vlan);
  2861. return -EINVAL;
  2862. }
  2863. DP(BNX2X_MSG_IOV, "configuring VF %d with VLAN %d qos %d\n",
  2864. vfidx, vlan, 0);
  2865. /* update PF's copy of the VF's bulletin. No point in posting the vlan
  2866. * to the VF since it doesn't have anything to do with it. But it useful
  2867. * to store it here in case the VF is not up yet and we can only
  2868. * configure the vlan later when it does.
  2869. */
  2870. bulletin->valid_bitmap |= 1 << VLAN_VALID;
  2871. bulletin->vlan = vlan;
  2872. /* is vf initialized and queue set up? */
  2873. q_logical_state =
  2874. bnx2x_get_q_logical_state(bp, &bnx2x_leading_vfq(vf, sp_obj));
  2875. if (vf->state == VF_ENABLED &&
  2876. q_logical_state == BNX2X_Q_LOGICAL_STATE_ACTIVE) {
  2877. /* configure the vlan in device on this vf's queue */
  2878. unsigned long ramrod_flags = 0;
  2879. unsigned long vlan_mac_flags = 0;
  2880. struct bnx2x_vlan_mac_obj *vlan_obj =
  2881. &bnx2x_leading_vfq(vf, vlan_obj);
  2882. struct bnx2x_vlan_mac_ramrod_params ramrod_param;
  2883. struct bnx2x_queue_state_params q_params = {NULL};
  2884. struct bnx2x_queue_update_params *update_params;
  2885. rc = validate_vlan_mac(bp, &bnx2x_leading_vfq(vf, mac_obj));
  2886. if (rc)
  2887. return rc;
  2888. memset(&ramrod_param, 0, sizeof(ramrod_param));
  2889. /* must lock vfpf channel to protect against vf flows */
  2890. bnx2x_lock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN);
  2891. /* remove existing vlans */
  2892. __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
  2893. rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_mac_flags,
  2894. &ramrod_flags);
  2895. if (rc) {
  2896. BNX2X_ERR("failed to delete vlans\n");
  2897. return -EINVAL;
  2898. }
  2899. /* send queue update ramrod to configure default vlan and silent
  2900. * vlan removal
  2901. */
  2902. __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
  2903. q_params.cmd = BNX2X_Q_CMD_UPDATE;
  2904. q_params.q_obj = &bnx2x_leading_vfq(vf, sp_obj);
  2905. update_params = &q_params.params.update;
  2906. __set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG,
  2907. &update_params->update_flags);
  2908. __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
  2909. &update_params->update_flags);
  2910. if (vlan == 0) {
  2911. /* if vlan is 0 then we want to leave the VF traffic
  2912. * untagged, and leave the incoming traffic untouched
  2913. * (i.e. do not remove any vlan tags).
  2914. */
  2915. __clear_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN,
  2916. &update_params->update_flags);
  2917. __clear_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
  2918. &update_params->update_flags);
  2919. } else {
  2920. /* configure the new vlan to device */
  2921. __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
  2922. ramrod_param.vlan_mac_obj = vlan_obj;
  2923. ramrod_param.ramrod_flags = ramrod_flags;
  2924. ramrod_param.user_req.u.vlan.vlan = vlan;
  2925. ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
  2926. rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
  2927. if (rc) {
  2928. BNX2X_ERR("failed to configure vlan\n");
  2929. return -EINVAL;
  2930. }
  2931. /* configure default vlan to vf queue and set silent
  2932. * vlan removal (the vf remains unaware of this vlan).
  2933. */
  2934. update_params = &q_params.params.update;
  2935. __set_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN,
  2936. &update_params->update_flags);
  2937. __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
  2938. &update_params->update_flags);
  2939. update_params->def_vlan = vlan;
  2940. }
  2941. /* Update the Queue state */
  2942. rc = bnx2x_queue_state_change(bp, &q_params);
  2943. if (rc) {
  2944. BNX2X_ERR("Failed to configure default VLAN\n");
  2945. return rc;
  2946. }
  2947. /* clear the flag indicating that this VF needs its vlan
  2948. * (will only be set if the HV configured th Vlan before vf was
  2949. * and we were called because the VF came up later
  2950. */
  2951. vf->cfg_flags &= ~VF_CFG_VLAN;
  2952. bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN);
  2953. }
  2954. return 0;
  2955. }
  2956. /* crc is the first field in the bulletin board. Compute the crc over the
  2957. * entire bulletin board excluding the crc field itself. Use the length field
  2958. * as the Bulletin Board was posted by a PF with possibly a different version
  2959. * from the vf which will sample it. Therefore, the length is computed by the
  2960. * PF and the used blindly by the VF.
  2961. */
  2962. u32 bnx2x_crc_vf_bulletin(struct bnx2x *bp,
  2963. struct pf_vf_bulletin_content *bulletin)
  2964. {
  2965. return crc32(BULLETIN_CRC_SEED,
  2966. ((u8 *)bulletin) + sizeof(bulletin->crc),
  2967. bulletin->length - sizeof(bulletin->crc));
  2968. }
  2969. /* Check for new posts on the bulletin board */
  2970. enum sample_bulletin_result bnx2x_sample_bulletin(struct bnx2x *bp)
  2971. {
  2972. struct pf_vf_bulletin_content bulletin = bp->pf2vf_bulletin->content;
  2973. int attempts;
  2974. /* bulletin board hasn't changed since last sample */
  2975. if (bp->old_bulletin.version == bulletin.version)
  2976. return PFVF_BULLETIN_UNCHANGED;
  2977. /* validate crc of new bulletin board */
  2978. if (bp->old_bulletin.version != bp->pf2vf_bulletin->content.version) {
  2979. /* sampling structure in mid post may result with corrupted data
  2980. * validate crc to ensure coherency.
  2981. */
  2982. for (attempts = 0; attempts < BULLETIN_ATTEMPTS; attempts++) {
  2983. bulletin = bp->pf2vf_bulletin->content;
  2984. if (bulletin.crc == bnx2x_crc_vf_bulletin(bp,
  2985. &bulletin))
  2986. break;
  2987. BNX2X_ERR("bad crc on bulletin board. Contained %x computed %x\n",
  2988. bulletin.crc,
  2989. bnx2x_crc_vf_bulletin(bp, &bulletin));
  2990. }
  2991. if (attempts >= BULLETIN_ATTEMPTS) {
  2992. BNX2X_ERR("pf to vf bulletin board crc was wrong %d consecutive times. Aborting\n",
  2993. attempts);
  2994. return PFVF_BULLETIN_CRC_ERR;
  2995. }
  2996. }
  2997. /* the mac address in bulletin board is valid and is new */
  2998. if (bulletin.valid_bitmap & 1 << MAC_ADDR_VALID &&
  2999. memcmp(bulletin.mac, bp->old_bulletin.mac, ETH_ALEN)) {
  3000. /* update new mac to net device */
  3001. memcpy(bp->dev->dev_addr, bulletin.mac, ETH_ALEN);
  3002. }
  3003. /* the vlan in bulletin board is valid and is new */
  3004. if (bulletin.valid_bitmap & 1 << VLAN_VALID)
  3005. memcpy(&bulletin.vlan, &bp->old_bulletin.vlan, VLAN_HLEN);
  3006. /* copy new bulletin board to bp */
  3007. bp->old_bulletin = bulletin;
  3008. return PFVF_BULLETIN_UPDATED;
  3009. }
  3010. void bnx2x_timer_sriov(struct bnx2x *bp)
  3011. {
  3012. bnx2x_sample_bulletin(bp);
  3013. /* if channel is down we need to self destruct */
  3014. if (bp->old_bulletin.valid_bitmap & 1 << CHANNEL_DOWN) {
  3015. smp_mb__before_clear_bit();
  3016. set_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
  3017. &bp->sp_rtnl_state);
  3018. smp_mb__after_clear_bit();
  3019. schedule_delayed_work(&bp->sp_rtnl_task, 0);
  3020. }
  3021. }
  3022. void __iomem *bnx2x_vf_doorbells(struct bnx2x *bp)
  3023. {
  3024. /* vf doorbells are embedded within the regview */
  3025. return bp->regview + PXP_VF_ADDR_DB_START;
  3026. }
  3027. int bnx2x_vf_pci_alloc(struct bnx2x *bp)
  3028. {
  3029. mutex_init(&bp->vf2pf_mutex);
  3030. /* allocate vf2pf mailbox for vf to pf channel */
  3031. BNX2X_PCI_ALLOC(bp->vf2pf_mbox, &bp->vf2pf_mbox_mapping,
  3032. sizeof(struct bnx2x_vf_mbx_msg));
  3033. /* allocate pf 2 vf bulletin board */
  3034. BNX2X_PCI_ALLOC(bp->pf2vf_bulletin, &bp->pf2vf_bulletin_mapping,
  3035. sizeof(union pf_vf_bulletin));
  3036. return 0;
  3037. alloc_mem_err:
  3038. BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->vf2pf_mbox_mapping,
  3039. sizeof(struct bnx2x_vf_mbx_msg));
  3040. BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->pf2vf_bulletin_mapping,
  3041. sizeof(union pf_vf_bulletin));
  3042. return -ENOMEM;
  3043. }
  3044. int bnx2x_open_epilog(struct bnx2x *bp)
  3045. {
  3046. /* Enable sriov via delayed work. This must be done via delayed work
  3047. * because it causes the probe of the vf devices to be run, which invoke
  3048. * register_netdevice which must have rtnl lock taken. As we are holding
  3049. * the lock right now, that could only work if the probe would not take
  3050. * the lock. However, as the probe of the vf may be called from other
  3051. * contexts as well (such as passthrough to vm fails) it can't assume
  3052. * the lock is being held for it. Using delayed work here allows the
  3053. * probe code to simply take the lock (i.e. wait for it to be released
  3054. * if it is being held). We only want to do this if the number of VFs
  3055. * was set before PF driver was loaded.
  3056. */
  3057. if (IS_SRIOV(bp) && BNX2X_NR_VIRTFN(bp)) {
  3058. smp_mb__before_clear_bit();
  3059. set_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, &bp->sp_rtnl_state);
  3060. smp_mb__after_clear_bit();
  3061. schedule_delayed_work(&bp->sp_rtnl_task, 0);
  3062. }
  3063. return 0;
  3064. }
  3065. void bnx2x_iov_channel_down(struct bnx2x *bp)
  3066. {
  3067. int vf_idx;
  3068. struct pf_vf_bulletin_content *bulletin;
  3069. if (!IS_SRIOV(bp))
  3070. return;
  3071. for_each_vf(bp, vf_idx) {
  3072. /* locate this VFs bulletin board and update the channel down
  3073. * bit
  3074. */
  3075. bulletin = BP_VF_BULLETIN(bp, vf_idx);
  3076. bulletin->valid_bitmap |= 1 << CHANNEL_DOWN;
  3077. /* update vf bulletin board */
  3078. bnx2x_post_vf_bulletin(bp, vf_idx);
  3079. }
  3080. }