sdhci-pxav3.c 11 KB

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  1. /*
  2. * Copyright (C) 2010 Marvell International Ltd.
  3. * Zhangfei Gao <zhangfei.gao@marvell.com>
  4. * Kevin Wang <dwang4@marvell.com>
  5. * Mingwei Wang <mwwang@marvell.com>
  6. * Philip Rakity <prakity@marvell.com>
  7. * Mark Brown <markb@marvell.com>
  8. *
  9. * This software is licensed under the terms of the GNU General Public
  10. * License version 2, as published by the Free Software Foundation, and
  11. * may be copied, distributed, and modified under those terms.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. */
  19. #include <linux/err.h>
  20. #include <linux/init.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/clk.h>
  23. #include <linux/io.h>
  24. #include <linux/gpio.h>
  25. #include <linux/mmc/card.h>
  26. #include <linux/mmc/host.h>
  27. #include <linux/mmc/slot-gpio.h>
  28. #include <linux/platform_data/pxa_sdhci.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include <linux/module.h>
  32. #include <linux/of.h>
  33. #include <linux/of_device.h>
  34. #include <linux/of_gpio.h>
  35. #include <linux/pm.h>
  36. #include <linux/pm_runtime.h>
  37. #include "sdhci.h"
  38. #include "sdhci-pltfm.h"
  39. #define PXAV3_RPM_DELAY_MS 50
  40. #define SD_CLOCK_BURST_SIZE_SETUP 0x10A
  41. #define SDCLK_SEL 0x100
  42. #define SDCLK_DELAY_SHIFT 9
  43. #define SDCLK_DELAY_MASK 0x1f
  44. #define SD_CFG_FIFO_PARAM 0x100
  45. #define SDCFG_GEN_PAD_CLK_ON (1<<6)
  46. #define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF
  47. #define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24
  48. #define SD_SPI_MODE 0x108
  49. #define SD_CE_ATA_1 0x10C
  50. #define SD_CE_ATA_2 0x10E
  51. #define SDCE_MISC_INT (1<<2)
  52. #define SDCE_MISC_INT_EN (1<<1)
  53. static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask)
  54. {
  55. struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
  56. struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
  57. if (mask == SDHCI_RESET_ALL) {
  58. /*
  59. * tune timing of read data/command when crc error happen
  60. * no performance impact
  61. */
  62. if (pdata && 0 != pdata->clk_delay_cycles) {
  63. u16 tmp;
  64. tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
  65. tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
  66. << SDCLK_DELAY_SHIFT;
  67. tmp |= SDCLK_SEL;
  68. writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
  69. }
  70. }
  71. }
  72. #define MAX_WAIT_COUNT 5
  73. static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
  74. {
  75. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  76. struct sdhci_pxa *pxa = pltfm_host->priv;
  77. u16 tmp;
  78. int count;
  79. if (pxa->power_mode == MMC_POWER_UP
  80. && power_mode == MMC_POWER_ON) {
  81. dev_dbg(mmc_dev(host->mmc),
  82. "%s: slot->power_mode = %d,"
  83. "ios->power_mode = %d\n",
  84. __func__,
  85. pxa->power_mode,
  86. power_mode);
  87. /* set we want notice of when 74 clocks are sent */
  88. tmp = readw(host->ioaddr + SD_CE_ATA_2);
  89. tmp |= SDCE_MISC_INT_EN;
  90. writew(tmp, host->ioaddr + SD_CE_ATA_2);
  91. /* start sending the 74 clocks */
  92. tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
  93. tmp |= SDCFG_GEN_PAD_CLK_ON;
  94. writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
  95. /* slowest speed is about 100KHz or 10usec per clock */
  96. udelay(740);
  97. count = 0;
  98. while (count++ < MAX_WAIT_COUNT) {
  99. if ((readw(host->ioaddr + SD_CE_ATA_2)
  100. & SDCE_MISC_INT) == 0)
  101. break;
  102. udelay(10);
  103. }
  104. if (count == MAX_WAIT_COUNT)
  105. dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
  106. /* clear the interrupt bit if posted */
  107. tmp = readw(host->ioaddr + SD_CE_ATA_2);
  108. tmp |= SDCE_MISC_INT;
  109. writew(tmp, host->ioaddr + SD_CE_ATA_2);
  110. }
  111. pxa->power_mode = power_mode;
  112. }
  113. static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
  114. {
  115. u16 ctrl_2;
  116. /*
  117. * Set V18_EN -- UHS modes do not work without this.
  118. * does not change signaling voltage
  119. */
  120. ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  121. /* Select Bus Speed Mode for host */
  122. ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
  123. switch (uhs) {
  124. case MMC_TIMING_UHS_SDR12:
  125. ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
  126. break;
  127. case MMC_TIMING_UHS_SDR25:
  128. ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
  129. break;
  130. case MMC_TIMING_UHS_SDR50:
  131. ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
  132. break;
  133. case MMC_TIMING_UHS_SDR104:
  134. ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
  135. break;
  136. case MMC_TIMING_UHS_DDR50:
  137. ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
  138. break;
  139. }
  140. sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
  141. dev_dbg(mmc_dev(host->mmc),
  142. "%s uhs = %d, ctrl_2 = %04X\n",
  143. __func__, uhs, ctrl_2);
  144. return 0;
  145. }
  146. static const struct sdhci_ops pxav3_sdhci_ops = {
  147. .platform_reset_exit = pxav3_set_private_registers,
  148. .set_uhs_signaling = pxav3_set_uhs_signaling,
  149. .platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
  150. .get_max_clock = sdhci_pltfm_clk_get_max_clock,
  151. };
  152. static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
  153. .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
  154. | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
  155. | SDHCI_QUIRK_32BIT_ADMA_SIZE
  156. | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
  157. .ops = &pxav3_sdhci_ops,
  158. };
  159. #ifdef CONFIG_OF
  160. static const struct of_device_id sdhci_pxav3_of_match[] = {
  161. {
  162. .compatible = "mrvl,pxav3-mmc",
  163. },
  164. {},
  165. };
  166. MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
  167. static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
  168. {
  169. struct sdhci_pxa_platdata *pdata;
  170. struct device_node *np = dev->of_node;
  171. u32 clk_delay_cycles;
  172. pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
  173. if (!pdata)
  174. return NULL;
  175. of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
  176. if (clk_delay_cycles > 0)
  177. pdata->clk_delay_cycles = clk_delay_cycles;
  178. return pdata;
  179. }
  180. #else
  181. static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
  182. {
  183. return NULL;
  184. }
  185. #endif
  186. static int sdhci_pxav3_probe(struct platform_device *pdev)
  187. {
  188. struct sdhci_pltfm_host *pltfm_host;
  189. struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
  190. struct device *dev = &pdev->dev;
  191. struct sdhci_host *host = NULL;
  192. struct sdhci_pxa *pxa = NULL;
  193. const struct of_device_id *match;
  194. int ret;
  195. struct clk *clk;
  196. pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
  197. if (!pxa)
  198. return -ENOMEM;
  199. host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
  200. if (IS_ERR(host)) {
  201. kfree(pxa);
  202. return PTR_ERR(host);
  203. }
  204. pltfm_host = sdhci_priv(host);
  205. pltfm_host->priv = pxa;
  206. clk = clk_get(dev, NULL);
  207. if (IS_ERR(clk)) {
  208. dev_err(dev, "failed to get io clock\n");
  209. ret = PTR_ERR(clk);
  210. goto err_clk_get;
  211. }
  212. pltfm_host->clk = clk;
  213. clk_prepare_enable(clk);
  214. /* enable 1/8V DDR capable */
  215. host->mmc->caps |= MMC_CAP_1_8V_DDR;
  216. match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
  217. if (match) {
  218. ret = mmc_of_parse(host->mmc);
  219. if (ret)
  220. goto err_of_parse;
  221. sdhci_get_of_property(pdev);
  222. pdata = pxav3_get_mmc_pdata(dev);
  223. } else if (pdata) {
  224. /* on-chip device */
  225. if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
  226. host->mmc->caps |= MMC_CAP_NONREMOVABLE;
  227. /* If slot design supports 8 bit data, indicate this to MMC. */
  228. if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
  229. host->mmc->caps |= MMC_CAP_8_BIT_DATA;
  230. if (pdata->quirks)
  231. host->quirks |= pdata->quirks;
  232. if (pdata->quirks2)
  233. host->quirks2 |= pdata->quirks2;
  234. if (pdata->host_caps)
  235. host->mmc->caps |= pdata->host_caps;
  236. if (pdata->host_caps2)
  237. host->mmc->caps2 |= pdata->host_caps2;
  238. if (pdata->pm_caps)
  239. host->mmc->pm_caps |= pdata->pm_caps;
  240. if (gpio_is_valid(pdata->ext_cd_gpio)) {
  241. ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio,
  242. 0);
  243. if (ret) {
  244. dev_err(mmc_dev(host->mmc),
  245. "failed to allocate card detect gpio\n");
  246. goto err_cd_req;
  247. }
  248. }
  249. }
  250. pm_runtime_enable(&pdev->dev);
  251. pm_runtime_get_sync(&pdev->dev);
  252. pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
  253. pm_runtime_use_autosuspend(&pdev->dev);
  254. pm_suspend_ignore_children(&pdev->dev, 1);
  255. ret = sdhci_add_host(host);
  256. if (ret) {
  257. dev_err(&pdev->dev, "failed to add host\n");
  258. goto err_add_host;
  259. }
  260. platform_set_drvdata(pdev, host);
  261. if (host->mmc->pm_caps & MMC_PM_KEEP_POWER) {
  262. device_init_wakeup(&pdev->dev, 1);
  263. host->mmc->pm_flags |= MMC_PM_WAKE_SDIO_IRQ;
  264. } else {
  265. device_init_wakeup(&pdev->dev, 0);
  266. }
  267. pm_runtime_put_autosuspend(&pdev->dev);
  268. return 0;
  269. err_of_parse:
  270. err_cd_req:
  271. err_add_host:
  272. pm_runtime_put_sync(&pdev->dev);
  273. pm_runtime_disable(&pdev->dev);
  274. clk_disable_unprepare(clk);
  275. clk_put(clk);
  276. err_clk_get:
  277. sdhci_pltfm_free(pdev);
  278. kfree(pxa);
  279. return ret;
  280. }
  281. static int sdhci_pxav3_remove(struct platform_device *pdev)
  282. {
  283. struct sdhci_host *host = platform_get_drvdata(pdev);
  284. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  285. struct sdhci_pxa *pxa = pltfm_host->priv;
  286. pm_runtime_get_sync(&pdev->dev);
  287. sdhci_remove_host(host, 1);
  288. pm_runtime_disable(&pdev->dev);
  289. clk_disable_unprepare(pltfm_host->clk);
  290. clk_put(pltfm_host->clk);
  291. sdhci_pltfm_free(pdev);
  292. kfree(pxa);
  293. return 0;
  294. }
  295. #ifdef CONFIG_PM_SLEEP
  296. static int sdhci_pxav3_suspend(struct device *dev)
  297. {
  298. int ret;
  299. struct sdhci_host *host = dev_get_drvdata(dev);
  300. pm_runtime_get_sync(dev);
  301. ret = sdhci_suspend_host(host);
  302. pm_runtime_mark_last_busy(dev);
  303. pm_runtime_put_autosuspend(dev);
  304. return ret;
  305. }
  306. static int sdhci_pxav3_resume(struct device *dev)
  307. {
  308. int ret;
  309. struct sdhci_host *host = dev_get_drvdata(dev);
  310. pm_runtime_get_sync(dev);
  311. ret = sdhci_resume_host(host);
  312. pm_runtime_mark_last_busy(dev);
  313. pm_runtime_put_autosuspend(dev);
  314. return ret;
  315. }
  316. #endif
  317. #ifdef CONFIG_PM_RUNTIME
  318. static int sdhci_pxav3_runtime_suspend(struct device *dev)
  319. {
  320. struct sdhci_host *host = dev_get_drvdata(dev);
  321. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  322. unsigned long flags;
  323. if (pltfm_host->clk) {
  324. spin_lock_irqsave(&host->lock, flags);
  325. host->runtime_suspended = true;
  326. spin_unlock_irqrestore(&host->lock, flags);
  327. clk_disable_unprepare(pltfm_host->clk);
  328. }
  329. return 0;
  330. }
  331. static int sdhci_pxav3_runtime_resume(struct device *dev)
  332. {
  333. struct sdhci_host *host = dev_get_drvdata(dev);
  334. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  335. unsigned long flags;
  336. if (pltfm_host->clk) {
  337. clk_prepare_enable(pltfm_host->clk);
  338. spin_lock_irqsave(&host->lock, flags);
  339. host->runtime_suspended = false;
  340. spin_unlock_irqrestore(&host->lock, flags);
  341. }
  342. return 0;
  343. }
  344. #endif
  345. #ifdef CONFIG_PM
  346. static const struct dev_pm_ops sdhci_pxav3_pmops = {
  347. SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
  348. SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
  349. sdhci_pxav3_runtime_resume, NULL)
  350. };
  351. #define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)
  352. #else
  353. #define SDHCI_PXAV3_PMOPS NULL
  354. #endif
  355. static struct platform_driver sdhci_pxav3_driver = {
  356. .driver = {
  357. .name = "sdhci-pxav3",
  358. #ifdef CONFIG_OF
  359. .of_match_table = sdhci_pxav3_of_match,
  360. #endif
  361. .owner = THIS_MODULE,
  362. .pm = SDHCI_PXAV3_PMOPS,
  363. },
  364. .probe = sdhci_pxav3_probe,
  365. .remove = sdhci_pxav3_remove,
  366. };
  367. module_platform_driver(sdhci_pxav3_driver);
  368. MODULE_DESCRIPTION("SDHCI driver for pxav3");
  369. MODULE_AUTHOR("Marvell International Ltd.");
  370. MODULE_LICENSE("GPL v2");