rts5249.c 8.7 KB

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  1. /* Driver for Realtek PCI-Express card reader
  2. *
  3. * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2, or (at your option) any
  8. * later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along
  16. * with this program; if not, see <http://www.gnu.org/licenses/>.
  17. *
  18. * Author:
  19. * Wei WANG <wei_wang@realsil.com.cn>
  20. */
  21. #include <linux/module.h>
  22. #include <linux/delay.h>
  23. #include <linux/mfd/rtsx_pci.h>
  24. #include "rtsx_pcr.h"
  25. static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
  26. {
  27. u8 val;
  28. rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  29. return val & 0x0F;
  30. }
  31. static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  32. {
  33. u8 driving_3v3[4][3] = {
  34. {0x11, 0x11, 0x11},
  35. {0x55, 0x55, 0x5C},
  36. {0x99, 0x99, 0x92},
  37. {0x99, 0x99, 0x92},
  38. };
  39. u8 driving_1v8[4][3] = {
  40. {0x3C, 0x3C, 0x3C},
  41. {0xB3, 0xB3, 0xB3},
  42. {0xFE, 0xFE, 0xFE},
  43. {0xC4, 0xC4, 0xC4},
  44. };
  45. u8 (*driving)[3], drive_sel;
  46. if (voltage == OUTPUT_3V3) {
  47. driving = driving_3v3;
  48. drive_sel = pcr->sd30_drive_sel_3v3;
  49. } else {
  50. driving = driving_1v8;
  51. drive_sel = pcr->sd30_drive_sel_1v8;
  52. }
  53. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
  54. 0xFF, driving[drive_sel][0]);
  55. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
  56. 0xFF, driving[drive_sel][1]);
  57. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
  58. 0xFF, driving[drive_sel][2]);
  59. }
  60. static void rts5249_fetch_vendor_settings(struct rtsx_pcr *pcr)
  61. {
  62. u32 reg;
  63. rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
  64. dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  65. if (!rtsx_vendor_setting_valid(reg))
  66. return;
  67. pcr->aspm_en = rtsx_reg_to_aspm(reg);
  68. pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  69. pcr->card_drive_sel &= 0x3F;
  70. pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  71. rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
  72. dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  73. pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  74. if (rtsx_reg_check_reverse_socket(reg))
  75. pcr->flags |= PCR_REVERSE_SOCKET;
  76. }
  77. static void rts5249_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
  78. {
  79. /* Set relink_time to 0 */
  80. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
  81. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
  82. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
  83. if (pm_state == HOST_ENTER_S3)
  84. rtsx_pci_write_register(pcr, PM_CTRL3, 0x10, 0x10);
  85. rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
  86. }
  87. static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
  88. {
  89. rtsx_pci_init_cmd(pcr);
  90. /* Configure GPIO as output */
  91. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
  92. /* Reset ASPM state to default value */
  93. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
  94. /* Switch LDO3318 source from DV33 to card_3v3 */
  95. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
  96. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
  97. /* LED shine disabled, set initial shine cycle period */
  98. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
  99. /* Configure driving */
  100. rts5249_fill_driving(pcr, OUTPUT_3V3);
  101. if (pcr->flags & PCR_REVERSE_SOCKET)
  102. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  103. AUTOLOAD_CFG_BASE + 3, 0xB0, 0xB0);
  104. else
  105. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  106. AUTOLOAD_CFG_BASE + 3, 0xB0, 0x80);
  107. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00);
  108. return rtsx_pci_send_cmd(pcr, 100);
  109. }
  110. static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
  111. {
  112. int err;
  113. err = rtsx_pci_write_phy_register(pcr, PHY_REG_REV, 0xFE46);
  114. if (err < 0)
  115. return err;
  116. msleep(1);
  117. return rtsx_pci_write_phy_register(pcr, PHY_BPCR, 0x05C0);
  118. }
  119. static int rts5249_turn_on_led(struct rtsx_pcr *pcr)
  120. {
  121. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
  122. }
  123. static int rts5249_turn_off_led(struct rtsx_pcr *pcr)
  124. {
  125. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
  126. }
  127. static int rts5249_enable_auto_blink(struct rtsx_pcr *pcr)
  128. {
  129. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
  130. }
  131. static int rts5249_disable_auto_blink(struct rtsx_pcr *pcr)
  132. {
  133. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
  134. }
  135. static int rts5249_card_power_on(struct rtsx_pcr *pcr, int card)
  136. {
  137. int err;
  138. rtsx_pci_init_cmd(pcr);
  139. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  140. SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
  141. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  142. LDO3318_PWR_MASK, 0x02);
  143. err = rtsx_pci_send_cmd(pcr, 100);
  144. if (err < 0)
  145. return err;
  146. msleep(5);
  147. rtsx_pci_init_cmd(pcr);
  148. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  149. SD_POWER_MASK, SD_VCC_POWER_ON);
  150. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  151. LDO3318_PWR_MASK, 0x06);
  152. err = rtsx_pci_send_cmd(pcr, 100);
  153. if (err < 0)
  154. return err;
  155. return 0;
  156. }
  157. static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
  158. {
  159. rtsx_pci_init_cmd(pcr);
  160. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  161. SD_POWER_MASK, SD_POWER_OFF);
  162. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  163. LDO3318_PWR_MASK, 0x00);
  164. return rtsx_pci_send_cmd(pcr, 100);
  165. }
  166. static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  167. {
  168. int err;
  169. if (voltage == OUTPUT_3V3) {
  170. err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4FC0 | 0x24);
  171. if (err < 0)
  172. return err;
  173. } else if (voltage == OUTPUT_1V8) {
  174. err = rtsx_pci_write_phy_register(pcr, PHY_BACR, 0x3C02);
  175. if (err < 0)
  176. return err;
  177. err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4C40 | 0x24);
  178. if (err < 0)
  179. return err;
  180. } else {
  181. return -EINVAL;
  182. }
  183. /* set pad drive */
  184. rtsx_pci_init_cmd(pcr);
  185. rts5249_fill_driving(pcr, voltage);
  186. return rtsx_pci_send_cmd(pcr, 100);
  187. }
  188. static const struct pcr_ops rts5249_pcr_ops = {
  189. .fetch_vendor_settings = rts5249_fetch_vendor_settings,
  190. .extra_init_hw = rts5249_extra_init_hw,
  191. .optimize_phy = rts5249_optimize_phy,
  192. .turn_on_led = rts5249_turn_on_led,
  193. .turn_off_led = rts5249_turn_off_led,
  194. .enable_auto_blink = rts5249_enable_auto_blink,
  195. .disable_auto_blink = rts5249_disable_auto_blink,
  196. .card_power_on = rts5249_card_power_on,
  197. .card_power_off = rts5249_card_power_off,
  198. .switch_output_voltage = rts5249_switch_output_voltage,
  199. .force_power_down = rts5249_force_power_down,
  200. };
  201. /* SD Pull Control Enable:
  202. * SD_DAT[3:0] ==> pull up
  203. * SD_CD ==> pull up
  204. * SD_WP ==> pull up
  205. * SD_CMD ==> pull up
  206. * SD_CLK ==> pull down
  207. */
  208. static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
  209. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
  210. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  211. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
  212. RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
  213. 0,
  214. };
  215. /* SD Pull Control Disable:
  216. * SD_DAT[3:0] ==> pull down
  217. * SD_CD ==> pull up
  218. * SD_WP ==> pull down
  219. * SD_CMD ==> pull down
  220. * SD_CLK ==> pull down
  221. */
  222. static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
  223. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
  224. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  225. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
  226. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
  227. 0,
  228. };
  229. /* MS Pull Control Enable:
  230. * MS CD ==> pull up
  231. * others ==> pull down
  232. */
  233. static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
  234. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
  235. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  236. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  237. 0,
  238. };
  239. /* MS Pull Control Disable:
  240. * MS CD ==> pull up
  241. * others ==> pull down
  242. */
  243. static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
  244. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
  245. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  246. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  247. 0,
  248. };
  249. void rts5249_init_params(struct rtsx_pcr *pcr)
  250. {
  251. pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
  252. pcr->num_slots = 2;
  253. pcr->ops = &rts5249_pcr_ops;
  254. pcr->flags = 0;
  255. pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
  256. pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_C;
  257. pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
  258. pcr->aspm_en = ASPM_L1_EN;
  259. pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
  260. pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
  261. pcr->ic_version = rts5249_get_ic_version(pcr);
  262. pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
  263. pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
  264. pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
  265. pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
  266. }